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1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __AMDGPU_DM_H__
27#define __AMDGPU_DM_H__
28
29#include <drm/drm_atomic.h>
30#include <drm/drm_connector.h>
31#include <drm/drm_crtc.h>
32#include <drm/drm_dp_mst_helper.h>
33#include <drm/drm_plane.h>
34
35/*
36 * This file contains the definition for amdgpu_display_manager
37 * and its API for amdgpu driver's use.
38 * This component provides all the display related functionality
39 * and this is the only component that calls DAL API.
40 * The API contained here intended for amdgpu driver use.
41 * The API that is called directly from KMS framework is located
42 * in amdgpu_dm_kms.h file
43 */
44
45#define AMDGPU_DM_MAX_DISPLAY_INDEX 31
46
47#define AMDGPU_DM_MAX_CRTC 6
48
49/*
50#include "include/amdgpu_dal_power_if.h"
51#include "amdgpu_dm_irq.h"
52*/
53
54#include "irq_types.h"
55#include "signal_types.h"
56#include "amdgpu_dm_crc.h"
57
58/* Forward declarations */
59struct amdgpu_device;
60struct drm_device;
61struct amdgpu_dm_irq_handler_data;
62struct dc;
63struct amdgpu_bo;
64struct dmub_srv;
65
66struct common_irq_params {
67 struct amdgpu_device *adev;
68 enum dc_irq_source irq_src;
69};
70
71/**
72 * struct irq_list_head - Linked-list for low context IRQ handlers.
73 *
74 * @head: The list_head within &struct handler_data
75 * @work: A work_struct containing the deferred handler work
76 */
77struct irq_list_head {
78 struct list_head head;
79 /* In case this interrupt needs post-processing, 'work' will be queued*/
80 struct work_struct work;
81};
82
83/**
84 * struct dm_compressor_info - Buffer info used by frame buffer compression
85 * @cpu_addr: MMIO cpu addr
86 * @bo_ptr: Pointer to the buffer object
87 * @gpu_addr: MMIO gpu addr
88 */
89struct dm_comressor_info {
90 void *cpu_addr;
91 struct amdgpu_bo *bo_ptr;
92 uint64_t gpu_addr;
93};
94
95/**
96 * struct amdgpu_dm_backlight_caps - Information about backlight
97 *
98 * Describe the backlight support for ACPI or eDP AUX.
99 */
100struct amdgpu_dm_backlight_caps {
101 /**
102 * @ext_caps: Keep the data struct with all the information about the
103 * display support for HDR.
104 */
105 union dpcd_sink_ext_caps *ext_caps;
106 /**
107 * @aux_min_input_signal: Min brightness value supported by the display
108 */
109 u32 aux_min_input_signal;
110 /**
111 * @aux_max_input_signal: Max brightness value supported by the display
112 * in nits.
113 */
114 u32 aux_max_input_signal;
115 /**
116 * @min_input_signal: minimum possible input in range 0-255.
117 */
118 int min_input_signal;
119 /**
120 * @max_input_signal: maximum possible input in range 0-255.
121 */
122 int max_input_signal;
123 /**
124 * @caps_valid: true if these values are from the ACPI interface.
125 */
126 bool caps_valid;
127 /**
128 * @aux_support: Describes if the display supports AUX backlight.
129 */
130 bool aux_support;
131};
132
133/**
134 * struct amdgpu_display_manager - Central amdgpu display manager device
135 *
136 * @dc: Display Core control structure
137 * @adev: AMDGPU base driver structure
138 * @ddev: DRM base driver structure
139 * @display_indexes_num: Max number of display streams supported
140 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables
141 * @backlight_dev: Backlight control device
142 * @backlight_link: Link on which to control backlight
143 * @backlight_caps: Capabilities of the backlight device
144 * @freesync_module: Module handling freesync calculations
145 * @hdcp_workqueue: AMDGPU content protection queue
146 * @fw_dmcu: Reference to DMCU firmware
147 * @dmcu_fw_version: Version of the DMCU firmware
148 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW
149 * @cached_state: Caches device atomic state for suspend/resume
150 * @cached_dc_state: Cached state of content streams
151 * @compressor: Frame buffer compression buffer. See &struct dm_comressor_info
152 */
153struct amdgpu_display_manager {
154
155 struct dc *dc;
156
157 /**
158 * @dmub_srv:
159 *
160 * DMUB service, used for controlling the DMUB on hardware
161 * that supports it. The pointer to the dmub_srv will be
162 * NULL on hardware that does not support it.
163 */
164 struct dmub_srv *dmub_srv;
165
166 /**
167 * @dmub_fb_info:
168 *
169 * Framebuffer regions for the DMUB.
170 */
171 struct dmub_srv_fb_info *dmub_fb_info;
172
173 /**
174 * @dmub_fw:
175 *
176 * DMUB firmware, required on hardware that has DMUB support.
177 */
178 const struct firmware *dmub_fw;
179
180 /**
181 * @dmub_bo:
182 *
183 * Buffer object for the DMUB.
184 */
185 struct amdgpu_bo *dmub_bo;
186
187 /**
188 * @dmub_bo_gpu_addr:
189 *
190 * GPU virtual address for the DMUB buffer object.
191 */
192 u64 dmub_bo_gpu_addr;
193
194 /**
195 * @dmub_bo_cpu_addr:
196 *
197 * CPU address for the DMUB buffer object.
198 */
199 void *dmub_bo_cpu_addr;
200
201 /**
202 * @dmcub_fw_version:
203 *
204 * DMCUB firmware version.
205 */
206 uint32_t dmcub_fw_version;
207
208 /**
209 * @cgs_device:
210 *
211 * The Common Graphics Services device. It provides an interface for
212 * accessing registers.
213 */
214 struct cgs_device *cgs_device;
215
216 struct amdgpu_device *adev;
217 struct drm_device *ddev;
218 u16 display_indexes_num;
219
220 /**
221 * @atomic_obj:
222 *
223 * In combination with &dm_atomic_state it helps manage
224 * global atomic state that doesn't map cleanly into existing
225 * drm resources, like &dc_context.
226 */
227 struct drm_private_obj atomic_obj;
228
229 /**
230 * @dc_lock:
231 *
232 * Guards access to DC functions that can issue register write
233 * sequences.
234 */
235 struct mutex dc_lock;
236
237 /**
238 * @audio_lock:
239 *
240 * Guards access to audio instance changes.
241 */
242 struct mutex audio_lock;
243
244 /**
245 * @audio_component:
246 *
247 * Used to notify ELD changes to sound driver.
248 */
249 struct drm_audio_component *audio_component;
250
251 /**
252 * @audio_registered:
253 *
254 * True if the audio component has been registered
255 * successfully, false otherwise.
256 */
257 bool audio_registered;
258
259 /**
260 * @irq_handler_list_low_tab:
261 *
262 * Low priority IRQ handler table.
263 *
264 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ
265 * source. Low priority IRQ handlers are deferred to a workqueue to be
266 * processed. Hence, they can sleep.
267 *
268 * Note that handlers are called in the same order as they were
269 * registered (FIFO).
270 */
271 struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
272
273 /**
274 * @irq_handler_list_high_tab:
275 *
276 * High priority IRQ handler table.
277 *
278 * It is a n*m table, same as &irq_handler_list_low_tab. However,
279 * handlers in this table are not deferred and are called immediately.
280 */
281 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];
282
283 /**
284 * @pflip_params:
285 *
286 * Page flip IRQ parameters, passed to registered handlers when
287 * triggered.
288 */
289 struct common_irq_params
290 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];
291
292 /**
293 * @vblank_params:
294 *
295 * Vertical blanking IRQ parameters, passed to registered handlers when
296 * triggered.
297 */
298 struct common_irq_params
299 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];
300
301 /**
302 * @vupdate_params:
303 *
304 * Vertical update IRQ parameters, passed to registered handlers when
305 * triggered.
306 */
307 struct common_irq_params
308 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1];
309
310 spinlock_t irq_handler_list_table_lock;
311
312 struct backlight_device *backlight_dev;
313
314 const struct dc_link *backlight_link;
315 struct amdgpu_dm_backlight_caps backlight_caps;
316
317 struct mod_freesync *freesync_module;
318#ifdef CONFIG_DRM_AMD_DC_HDCP
319 struct hdcp_workqueue *hdcp_workqueue;
320#endif
321
322 struct drm_atomic_state *cached_state;
323 struct dc_state *cached_dc_state;
324
325 struct dm_comressor_info compressor;
326
327 const struct firmware *fw_dmcu;
328 uint32_t dmcu_fw_version;
329 /**
330 * @soc_bounding_box:
331 *
332 * gpu_info FW provided soc bounding box struct or 0 if not
333 * available in FW
334 */
335 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
336
337 /**
338 * @mst_encoders:
339 *
340 * fake encoders used for DP MST.
341 */
342 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC];
343};
344
345struct amdgpu_dm_connector {
346
347 struct drm_connector base;
348 uint32_t connector_id;
349
350 /* we need to mind the EDID between detect
351 and get modes due to analog/digital/tvencoder */
352 struct edid *edid;
353
354 /* shared with amdgpu */
355 struct amdgpu_hpd hpd;
356
357 /* number of modes generated from EDID at 'dc_sink' */
358 int num_modes;
359
360 /* The 'old' sink - before an HPD.
361 * The 'current' sink is in dc_link->sink. */
362 struct dc_sink *dc_sink;
363 struct dc_link *dc_link;
364 struct dc_sink *dc_em_sink;
365
366 /* DM only */
367 struct drm_dp_mst_topology_mgr mst_mgr;
368 struct amdgpu_dm_dp_aux dm_dp_aux;
369 struct drm_dp_mst_port *port;
370 struct amdgpu_dm_connector *mst_port;
371 struct drm_dp_aux *dsc_aux;
372
373 /* TODO see if we can merge with ddc_bus or make a dm_connector */
374 struct amdgpu_i2c_adapter *i2c;
375
376 /* Monitor range limits */
377 int min_vfreq ;
378 int max_vfreq ;
379 int pixel_clock_mhz;
380
381 /* Audio instance - protected by audio_lock. */
382 int audio_inst;
383
384 struct mutex hpd_lock;
385
386 bool fake_enable;
387#ifdef CONFIG_DEBUG_FS
388 uint32_t debugfs_dpcd_address;
389 uint32_t debugfs_dpcd_size;
390#endif
391 bool force_yuv420_output;
392};
393
394#define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)
395
396extern const struct amdgpu_ip_block_version dm_ip_block;
397
398struct amdgpu_framebuffer;
399struct amdgpu_display_manager;
400struct dc_validation_set;
401struct dc_plane_state;
402
403struct dm_plane_state {
404 struct drm_plane_state base;
405 struct dc_plane_state *dc_state;
406};
407
408struct dm_crtc_state {
409 struct drm_crtc_state base;
410 struct dc_stream_state *stream;
411
412 bool cm_has_degamma;
413 bool cm_is_degamma_srgb;
414
415 int update_type;
416 int active_planes;
417
418 int crc_skip_count;
419 enum amdgpu_dm_pipe_crc_source crc_src;
420
421 bool freesync_timing_changed;
422 bool freesync_vrr_info_changed;
423
424 bool vrr_supported;
425 struct mod_freesync_config freesync_config;
426 struct mod_vrr_params vrr_params;
427 struct dc_info_packet vrr_infopacket;
428
429 int abm_level;
430};
431
432#define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
433
434struct dm_atomic_state {
435 struct drm_private_state base;
436
437 struct dc_state *context;
438};
439
440#define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)
441
442struct dm_connector_state {
443 struct drm_connector_state base;
444
445 enum amdgpu_rmx_type scaling;
446 uint8_t underscan_vborder;
447 uint8_t underscan_hborder;
448 bool underscan_enable;
449 bool freesync_capable;
450 uint8_t abm_level;
451 int vcpi_slots;
452 uint64_t pbn;
453};
454
455#define to_dm_connector_state(x)\
456 container_of((x), struct dm_connector_state, base)
457
458void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);
459struct drm_connector_state *
460amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector);
461int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
462 struct drm_connector_state *state,
463 struct drm_property *property,
464 uint64_t val);
465
466int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
467 const struct drm_connector_state *state,
468 struct drm_property *property,
469 uint64_t *val);
470
471int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev);
472
473void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
474 struct amdgpu_dm_connector *aconnector,
475 int connector_type,
476 struct dc_link *link,
477 int link_index);
478
479enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
480 struct drm_display_mode *mode);
481
482void dm_restore_drm_connector_state(struct drm_device *dev,
483 struct drm_connector *connector);
484
485void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
486 struct edid *edid);
487
488#define MAX_COLOR_LUT_ENTRIES 4096
489/* Legacy gamm LUT users such as X doesn't like large LUT sizes */
490#define MAX_COLOR_LEGACY_LUT_ENTRIES 256
491
492void amdgpu_dm_init_color_mod(void);
493int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc);
494int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
495 struct dc_plane_state *dc_plane_state);
496
497void amdgpu_dm_update_connector_after_detect(
498 struct amdgpu_dm_connector *aconnector);
499
500extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
501
502#endif /* __AMDGPU_DM_H__ */