1/*
  2 * This file is subject to the terms and conditions of the GNU General Public
  3 * License.  See the file "COPYING" in the main directory of this archive
  4 * for more details.
  5 *
  6 * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
  7 */
  8
  9#define pr_fmt(fmt) "mips-gic-timer: " fmt
 10
 11#include <linux/clk.h>
 12#include <linux/clockchips.h>
 13#include <linux/cpu.h>
 14#include <linux/init.h>
 15#include <linux/interrupt.h>
 16#include <linux/notifier.h>
 17#include <linux/of_irq.h>
 18#include <linux/percpu.h>
 19#include <linux/sched_clock.h>
 20#include <linux/smp.h>
 21#include <linux/time.h>
 22#include <asm/mips-cps.h>
 23
 24static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device);
 25static int gic_timer_irq;
 26static unsigned int gic_frequency;
 27static bool __read_mostly gic_clock_unstable;
 28
 29static void gic_clocksource_unstable(char *reason);
 30
 31static u64 notrace gic_read_count_2x32(void)
 32{
 33	unsigned int hi, hi2, lo;
 34
 35	do {
 36		hi = read_gic_counter_32h();
 37		lo = read_gic_counter_32l();
 38		hi2 = read_gic_counter_32h();
 39	} while (hi2 != hi);
 40
 41	return (((u64) hi) << 32) + lo;
 42}
 43
 44static u64 notrace gic_read_count_64(void)
 45{
 46	return read_gic_counter();
 47}
 48
 49static u64 notrace gic_read_count(void)
 50{
 51	if (mips_cm_is64)
 52		return gic_read_count_64();
 53
 54	return gic_read_count_2x32();
 55}
 56
 57static int gic_next_event(unsigned long delta, struct clock_event_device *evt)
 58{
 59	int cpu = cpumask_first(evt->cpumask);
 60	u64 cnt;
 61	int res;
 62
 63	cnt = gic_read_count();
 64	cnt += (u64)delta;
 65	if (cpu == raw_smp_processor_id()) {
 66		write_gic_vl_compare(cnt);
 67	} else {
 68		write_gic_vl_other(mips_cm_vp_id(cpu));
 69		write_gic_vo_compare(cnt);
 70	}
 71	res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0;
 72	return res;
 73}
 74
 75static irqreturn_t gic_compare_interrupt(int irq, void *dev_id)
 76{
 77	struct clock_event_device *cd = dev_id;
 78
 79	write_gic_vl_compare(read_gic_vl_compare());
 80	cd->event_handler(cd);
 81	return IRQ_HANDLED;
 82}
 83
 84static struct irqaction gic_compare_irqaction = {
 85	.handler = gic_compare_interrupt,
 86	.percpu_dev_id = &gic_clockevent_device,
 87	.flags = IRQF_PERCPU | IRQF_TIMER,
 88	.name = "timer",
 89};
 90
 91static void gic_clockevent_cpu_init(unsigned int cpu,
 92				    struct clock_event_device *cd)
 93{
 94	cd->name		= "MIPS GIC";
 95	cd->features		= CLOCK_EVT_FEAT_ONESHOT |
 96				  CLOCK_EVT_FEAT_C3STOP;
 97
 98	cd->rating		= 350;
 99	cd->irq			= gic_timer_irq;
100	cd->cpumask		= cpumask_of(cpu);
101	cd->set_next_event	= gic_next_event;
102
103	clockevents_config_and_register(cd, gic_frequency, 0x300, 0x7fffffff);
104
105	enable_percpu_irq(gic_timer_irq, IRQ_TYPE_NONE);
106}
107
108static void gic_clockevent_cpu_exit(struct clock_event_device *cd)
109{
110	disable_percpu_irq(gic_timer_irq);
111}
112
113static void gic_update_frequency(void *data)
114{
115	unsigned long rate = (unsigned long)data;
116
117	clockevents_update_freq(this_cpu_ptr(&gic_clockevent_device), rate);
118}
119
120static int gic_starting_cpu(unsigned int cpu)
121{
122	gic_clockevent_cpu_init(cpu, this_cpu_ptr(&gic_clockevent_device));
123	return 0;
124}
125
126static int gic_clk_notifier(struct notifier_block *nb, unsigned long action,
127			    void *data)
128{
129	struct clk_notifier_data *cnd = data;
130
131	if (action == POST_RATE_CHANGE) {
132		gic_clocksource_unstable("ref clock rate change");
133		on_each_cpu(gic_update_frequency, (void *)cnd->new_rate, 1);
134	}
135
136	return NOTIFY_OK;
137}
138
139static int gic_dying_cpu(unsigned int cpu)
140{
141	gic_clockevent_cpu_exit(this_cpu_ptr(&gic_clockevent_device));
142	return 0;
143}
144
145static struct notifier_block gic_clk_nb = {
146	.notifier_call = gic_clk_notifier,
147};
148
149static int gic_clockevent_init(void)
150{
151	int ret;
152
153	if (!gic_frequency)
154		return -ENXIO;
155
156	ret = setup_percpu_irq(gic_timer_irq, &gic_compare_irqaction);
157	if (ret < 0) {
158		pr_err("IRQ %d setup failed (%d)\n", gic_timer_irq, ret);
159		return ret;
160	}
161
162	cpuhp_setup_state(CPUHP_AP_MIPS_GIC_TIMER_STARTING,
163			  "clockevents/mips/gic/timer:starting",
164			  gic_starting_cpu, gic_dying_cpu);
165	return 0;
166}
167
168static u64 gic_hpt_read(struct clocksource *cs)
169{
170	return gic_read_count();
171}
172
173static struct clocksource gic_clocksource = {
174	.name			= "GIC",
175	.read			= gic_hpt_read,
176	.flags			= CLOCK_SOURCE_IS_CONTINUOUS,
177	.vdso_clock_mode	= VDSO_CLOCKMODE_GIC,
178};
179
180static void gic_clocksource_unstable(char *reason)
181{
182	if (gic_clock_unstable)
183		return;
184
185	gic_clock_unstable = true;
186
187	pr_info("GIC timer is unstable due to %s\n", reason);
188
189	clocksource_mark_unstable(&gic_clocksource);
190}
191
192static int __init __gic_clocksource_init(void)
193{
194	unsigned int count_width;
195	int ret;
196
197	/* Set clocksource mask. */
198	count_width = read_gic_config() & GIC_CONFIG_COUNTBITS;
199	count_width >>= __ffs(GIC_CONFIG_COUNTBITS);
200	count_width *= 4;
201	count_width += 32;
202	gic_clocksource.mask = CLOCKSOURCE_MASK(count_width);
203
204	/* Calculate a somewhat reasonable rating value. */
205	gic_clocksource.rating = 200 + gic_frequency / 10000000;
206
207	ret = clocksource_register_hz(&gic_clocksource, gic_frequency);
208	if (ret < 0)
209		pr_warn("Unable to register clocksource\n");
210
211	return ret;
212}
213
214static int __init gic_clocksource_of_init(struct device_node *node)
215{
216	struct clk *clk;
217	int ret;
218
219	if (!mips_gic_present() || !node->parent ||
220	    !of_device_is_compatible(node->parent, "mti,gic")) {
221		pr_warn("No DT definition\n");
222		return -ENXIO;
223	}
224
225	clk = of_clk_get(node, 0);
226	if (!IS_ERR(clk)) {
227		ret = clk_prepare_enable(clk);
228		if (ret < 0) {
229			pr_err("Failed to enable clock\n");
230			clk_put(clk);
231			return ret;
232		}
233
234		gic_frequency = clk_get_rate(clk);
235	} else if (of_property_read_u32(node, "clock-frequency",
236					&gic_frequency)) {
237		pr_err("Frequency not specified\n");
238		return -EINVAL;
239	}
240	gic_timer_irq = irq_of_parse_and_map(node, 0);
241	if (!gic_timer_irq) {
242		pr_err("IRQ not specified\n");
243		return -EINVAL;
244	}
245
246	ret = __gic_clocksource_init();
247	if (ret)
248		return ret;
249
250	ret = gic_clockevent_init();
251	if (!ret && !IS_ERR(clk)) {
252		if (clk_notifier_register(clk, &gic_clk_nb) < 0)
253			pr_warn("Unable to register clock notifier\n");
254	}
255
256	/* And finally start the counter */
257	clear_gic_config(GIC_CONFIG_COUNTSTOP);
258
259	/*
260	 * It's safe to use the MIPS GIC timer as a sched clock source only if
261	 * its ticks are stable, which is true on either the platforms with
262	 * stable CPU frequency or on the platforms with CM3 and CPU frequency
263	 * change performed by the CPC core clocks divider.
264	 */
265	if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) {
266		sched_clock_register(mips_cm_is64 ?
267				     gic_read_count_64 : gic_read_count_2x32,
268				     64, gic_frequency);
269	}
270
271	return 0;
272}
273TIMER_OF_DECLARE(mips_gic_timer, "mti,gic-timer",
274		       gic_clocksource_of_init);