1/*
  2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
  3 * reserved.
  4 *
  5 * This software is available to you under a choice of one of two
  6 * licenses.  You may choose to be licensed under the terms of the GNU
  7 * General Public License (GPL) Version 2, available from the file
  8 * COPYING in the main directory of this source tree, or the NetLogic
  9 * license below:
 10 *
 11 * Redistribution and use in source and binary forms, with or without
 12 * modification, are permitted provided that the following conditions
 13 * are met:
 14 *
 15 * 1. Redistributions of source code must retain the above copyright
 16 *    notice, this list of conditions and the following disclaimer.
 17 * 2. Redistributions in binary form must reproduce the above copyright
 18 *    notice, this list of conditions and the following disclaimer in
 19 *    the documentation and/or other materials provided with the
 20 *    distribution.
 21 *
 22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
 31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
 32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 33 */
 34
 35#ifndef _NLM_HAL_XLP_H
 36#define _NLM_HAL_XLP_H
 37
 38#define PIC_UART_0_IRQ			17
 39#define PIC_UART_1_IRQ			18
 40
 41#define PIC_PCIE_LINK_LEGACY_IRQ_BASE	19
 42#define PIC_PCIE_LINK_LEGACY_IRQ(i)	(19 + (i))
 43
 44#define PIC_EHCI_0_IRQ			23
 45#define PIC_EHCI_1_IRQ			24
 46#define PIC_OHCI_0_IRQ			25
 47#define PIC_OHCI_1_IRQ			26
 48#define PIC_OHCI_2_IRQ			27
 49#define PIC_OHCI_3_IRQ			28
 50#define PIC_2XX_XHCI_0_IRQ		23
 51#define PIC_2XX_XHCI_1_IRQ		24
 52#define PIC_2XX_XHCI_2_IRQ		25
 53#define PIC_9XX_XHCI_0_IRQ		23
 54#define PIC_9XX_XHCI_1_IRQ		24
 55#define PIC_9XX_XHCI_2_IRQ		25
 56
 57#define PIC_MMC_IRQ			29
 58#define PIC_I2C_0_IRQ			30
 59#define PIC_I2C_1_IRQ			31
 60#define PIC_I2C_2_IRQ			32
 61#define PIC_I2C_3_IRQ			33
 62#define PIC_SPI_IRQ			34
 63#define PIC_NAND_IRQ			37
 64#define PIC_SATA_IRQ			38
 65#define PIC_GPIO_IRQ			39
 66
 67#define PIC_PCIE_LINK_MSI_IRQ_BASE	44	/* 44 - 47 MSI IRQ */
 68#define PIC_PCIE_LINK_MSI_IRQ(i)	(44 + (i))
 69
 70/* MSI-X with second link-level dispatch */
 71#define PIC_PCIE_MSIX_IRQ_BASE		48	/* 48 - 51 MSI-X IRQ */
 72#define PIC_PCIE_MSIX_IRQ(i)		(48 + (i))
 73
 74/* XLP9xx and XLP8xx has 128 and 32 MSIX vectors respectively */
 75#define NLM_MSIX_VEC_BASE		96	/* 96 - 223 - MSIX mapped */
 76#define NLM_MSI_VEC_BASE		224	/* 224 -351 - MSI mapped */
 77
 78#define NLM_PIC_INDIRECT_VEC_BASE	512
 79#define NLM_GPIO_VEC_BASE		768
 80
 81#define PIC_IRQ_BASE			8
 82#define PIC_IRT_FIRST_IRQ		PIC_IRQ_BASE
 83#define PIC_IRT_LAST_IRQ		63
 84
 85#ifndef __ASSEMBLY__
 86
 87/* SMP support functions */
 88void xlp_boot_core0_siblings(void);
 89void xlp_wakeup_secondary_cpus(void);
 90
 91void xlp_mmu_init(void);
 92void nlm_hal_init(void);
 93int nlm_get_dram_map(int node, uint64_t *dram_map, int nentries);
 94
 95struct pci_dev;
 96int xlp_socdev_to_node(const struct pci_dev *dev);
 97
 98/* Device tree related */
 99void xlp_early_init_devtree(void);
100void *xlp_dt_init(void *fdtp);
101
102static inline int cpu_is_xlpii(void)
103{
104	int chip = read_c0_prid() & PRID_IMP_MASK;
105
106	return chip == PRID_IMP_NETLOGIC_XLP2XX ||
107		chip == PRID_IMP_NETLOGIC_XLP9XX ||
108		chip == PRID_IMP_NETLOGIC_XLP5XX;
109}
110
111static inline int cpu_is_xlp9xx(void)
112{
113	int chip = read_c0_prid() & PRID_IMP_MASK;
114
115	return chip == PRID_IMP_NETLOGIC_XLP9XX ||
116		chip == PRID_IMP_NETLOGIC_XLP5XX;
117}
118#endif /* !__ASSEMBLY__ */
119#endif /* _ASM_NLM_XLP_H */