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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * linux/arch/arm/mm/cache-v6.S
4 *
5 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 *
7 * This is the "shell" of the ARMv6 processor support.
8 */
9#include <linux/linkage.h>
10#include <linux/init.h>
11#include <asm/assembler.h>
12#include <asm/errno.h>
13#include <asm/unwind.h>
14
15#include "proc-macros.S"
16
17#define HARVARD_CACHE
18#define CACHE_LINE_SIZE 32
19#define D_CACHE_LINE_SIZE 32
20#define BTB_FLUSH_SIZE 8
21
22/*
23 * v6_flush_icache_all()
24 *
25 * Flush the whole I-cache.
26 *
27 * ARM1136 erratum 411920 - Invalidate Instruction Cache operation can fail.
28 * This erratum is present in 1136, 1156 and 1176. It does not affect the
29 * MPCore.
30 *
31 * Registers:
32 * r0 - set to 0
33 * r1 - corrupted
34 */
35ENTRY(v6_flush_icache_all)
36 mov r0, #0
37#ifdef CONFIG_ARM_ERRATA_411920
38 mrs r1, cpsr
39 cpsid ifa @ disable interrupts
40 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
41 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
44 msr cpsr_cx, r1 @ restore interrupts
45 .rept 11 @ ARM Ltd recommends at least
46 nop @ 11 NOPs
47 .endr
48#else
49 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
50#endif
51 ret lr
52ENDPROC(v6_flush_icache_all)
53
54/*
55 * v6_flush_cache_all()
56 *
57 * Flush the entire cache.
58 *
59 * It is assumed that:
60 */
61ENTRY(v6_flush_kern_cache_all)
62 mov r0, #0
63#ifdef HARVARD_CACHE
64 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
65#ifndef CONFIG_ARM_ERRATA_411920
66 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
67#else
68 b v6_flush_icache_all
69#endif
70#else
71 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
72#endif
73 ret lr
74
75/*
76 * v6_flush_cache_all()
77 *
78 * Flush all TLB entries in a particular address space
79 *
80 * - mm - mm_struct describing address space
81 */
82ENTRY(v6_flush_user_cache_all)
83 /*FALLTHROUGH*/
84
85/*
86 * v6_flush_cache_range(start, end, flags)
87 *
88 * Flush a range of TLB entries in the specified address space.
89 *
90 * - start - start address (may not be aligned)
91 * - end - end address (exclusive, may not be aligned)
92 * - flags - vm_area_struct flags describing address space
93 *
94 * It is assumed that:
95 * - we have a VIPT cache.
96 */
97ENTRY(v6_flush_user_cache_range)
98 ret lr
99
100/*
101 * v6_coherent_kern_range(start,end)
102 *
103 * Ensure that the I and D caches are coherent within specified
104 * region. This is typically used when code has been written to
105 * a memory region, and will be executed.
106 *
107 * - start - virtual start address of region
108 * - end - virtual end address of region
109 *
110 * It is assumed that:
111 * - the Icache does not read data from the write buffer
112 */
113ENTRY(v6_coherent_kern_range)
114 /* FALLTHROUGH */
115
116/*
117 * v6_coherent_user_range(start,end)
118 *
119 * Ensure that the I and D caches are coherent within specified
120 * region. This is typically used when code has been written to
121 * a memory region, and will be executed.
122 *
123 * - start - virtual start address of region
124 * - end - virtual end address of region
125 *
126 * It is assumed that:
127 * - the Icache does not read data from the write buffer
128 */
129ENTRY(v6_coherent_user_range)
130 UNWIND(.fnstart )
131#ifdef HARVARD_CACHE
132 bic r0, r0, #CACHE_LINE_SIZE - 1
1331:
134 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line
135 add r0, r0, #CACHE_LINE_SIZE
136 cmp r0, r1
137 blo 1b
138#endif
139 mov r0, #0
140#ifdef HARVARD_CACHE
141 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
142#ifndef CONFIG_ARM_ERRATA_411920
143 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
144#else
145 b v6_flush_icache_all
146#endif
147#else
148 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
149#endif
150 ret lr
151
152/*
153 * Fault handling for the cache operation above. If the virtual address in r0
154 * isn't mapped, fail with -EFAULT.
155 */
1569001:
157 mov r0, #-EFAULT
158 ret lr
159 UNWIND(.fnend )
160ENDPROC(v6_coherent_user_range)
161ENDPROC(v6_coherent_kern_range)
162
163/*
164 * v6_flush_kern_dcache_area(void *addr, size_t size)
165 *
166 * Ensure that the data held in the page kaddr is written back
167 * to the page in question.
168 *
169 * - addr - kernel address
170 * - size - region size
171 */
172ENTRY(v6_flush_kern_dcache_area)
173 add r1, r0, r1
174 bic r0, r0, #D_CACHE_LINE_SIZE - 1
1751:
176#ifdef HARVARD_CACHE
177 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
178#else
179 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate unified line
180#endif
181 add r0, r0, #D_CACHE_LINE_SIZE
182 cmp r0, r1
183 blo 1b
184#ifdef HARVARD_CACHE
185 mov r0, #0
186 mcr p15, 0, r0, c7, c10, 4
187#endif
188 ret lr
189
190
191/*
192 * v6_dma_inv_range(start,end)
193 *
194 * Invalidate the data cache within the specified region; we will
195 * be performing a DMA operation in this region and we want to
196 * purge old data in the cache.
197 *
198 * - start - virtual start address of region
199 * - end - virtual end address of region
200 */
201v6_dma_inv_range:
202#ifdef CONFIG_DMA_CACHE_RWFO
203 ldrb r2, [r0] @ read for ownership
204 strb r2, [r0] @ write for ownership
205#endif
206 tst r0, #D_CACHE_LINE_SIZE - 1
207 bic r0, r0, #D_CACHE_LINE_SIZE - 1
208#ifdef HARVARD_CACHE
209 mcrne p15, 0, r0, c7, c10, 1 @ clean D line
210#else
211 mcrne p15, 0, r0, c7, c11, 1 @ clean unified line
212#endif
213 tst r1, #D_CACHE_LINE_SIZE - 1
214#ifdef CONFIG_DMA_CACHE_RWFO
215 ldrbne r2, [r1, #-1] @ read for ownership
216 strbne r2, [r1, #-1] @ write for ownership
217#endif
218 bic r1, r1, #D_CACHE_LINE_SIZE - 1
219#ifdef HARVARD_CACHE
220 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D line
221#else
222 mcrne p15, 0, r1, c7, c15, 1 @ clean & invalidate unified line
223#endif
2241:
225#ifdef HARVARD_CACHE
226 mcr p15, 0, r0, c7, c6, 1 @ invalidate D line
227#else
228 mcr p15, 0, r0, c7, c7, 1 @ invalidate unified line
229#endif
230 add r0, r0, #D_CACHE_LINE_SIZE
231 cmp r0, r1
232#ifdef CONFIG_DMA_CACHE_RWFO
233 ldrlo r2, [r0] @ read for ownership
234 strlo r2, [r0] @ write for ownership
235#endif
236 blo 1b
237 mov r0, #0
238 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
239 ret lr
240
241/*
242 * v6_dma_clean_range(start,end)
243 * - start - virtual start address of region
244 * - end - virtual end address of region
245 */
246v6_dma_clean_range:
247 bic r0, r0, #D_CACHE_LINE_SIZE - 1
2481:
249#ifdef CONFIG_DMA_CACHE_RWFO
250 ldr r2, [r0] @ read for ownership
251#endif
252#ifdef HARVARD_CACHE
253 mcr p15, 0, r0, c7, c10, 1 @ clean D line
254#else
255 mcr p15, 0, r0, c7, c11, 1 @ clean unified line
256#endif
257 add r0, r0, #D_CACHE_LINE_SIZE
258 cmp r0, r1
259 blo 1b
260 mov r0, #0
261 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
262 ret lr
263
264/*
265 * v6_dma_flush_range(start,end)
266 * - start - virtual start address of region
267 * - end - virtual end address of region
268 */
269ENTRY(v6_dma_flush_range)
270#ifdef CONFIG_DMA_CACHE_RWFO
271 ldrb r2, [r0] @ read for ownership
272 strb r2, [r0] @ write for ownership
273#endif
274 bic r0, r0, #D_CACHE_LINE_SIZE - 1
2751:
276#ifdef HARVARD_CACHE
277 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
278#else
279 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate line
280#endif
281 add r0, r0, #D_CACHE_LINE_SIZE
282 cmp r0, r1
283#ifdef CONFIG_DMA_CACHE_RWFO
284 ldrblo r2, [r0] @ read for ownership
285 strblo r2, [r0] @ write for ownership
286#endif
287 blo 1b
288 mov r0, #0
289 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
290 ret lr
291
292/*
293 * dma_map_area(start, size, dir)
294 * - start - kernel virtual start address
295 * - size - size of region
296 * - dir - DMA direction
297 */
298ENTRY(v6_dma_map_area)
299 add r1, r1, r0
300 teq r2, #DMA_FROM_DEVICE
301 beq v6_dma_inv_range
302#ifndef CONFIG_DMA_CACHE_RWFO
303 b v6_dma_clean_range
304#else
305 teq r2, #DMA_TO_DEVICE
306 beq v6_dma_clean_range
307 b v6_dma_flush_range
308#endif
309ENDPROC(v6_dma_map_area)
310
311/*
312 * dma_unmap_area(start, size, dir)
313 * - start - kernel virtual start address
314 * - size - size of region
315 * - dir - DMA direction
316 */
317ENTRY(v6_dma_unmap_area)
318#ifndef CONFIG_DMA_CACHE_RWFO
319 add r1, r1, r0
320 teq r2, #DMA_TO_DEVICE
321 bne v6_dma_inv_range
322#endif
323 ret lr
324ENDPROC(v6_dma_unmap_area)
325
326 .globl v6_flush_kern_cache_louis
327 .equ v6_flush_kern_cache_louis, v6_flush_kern_cache_all
328
329 __INITDATA
330
331 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
332 define_cache_functions v6
1/*
2 * linux/arch/arm/mm/cache-v6.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This is the "shell" of the ARMv6 processor support.
11 */
12#include <linux/linkage.h>
13#include <linux/init.h>
14#include <asm/assembler.h>
15#include <asm/unwind.h>
16
17#include "proc-macros.S"
18
19#define HARVARD_CACHE
20#define CACHE_LINE_SIZE 32
21#define D_CACHE_LINE_SIZE 32
22#define BTB_FLUSH_SIZE 8
23
24/*
25 * v6_flush_icache_all()
26 *
27 * Flush the whole I-cache.
28 *
29 * ARM1136 erratum 411920 - Invalidate Instruction Cache operation can fail.
30 * This erratum is present in 1136, 1156 and 1176. It does not affect the
31 * MPCore.
32 *
33 * Registers:
34 * r0 - set to 0
35 * r1 - corrupted
36 */
37ENTRY(v6_flush_icache_all)
38 mov r0, #0
39#ifdef CONFIG_ARM_ERRATA_411920
40 mrs r1, cpsr
41 cpsid ifa @ disable interrupts
42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
46 msr cpsr_cx, r1 @ restore interrupts
47 .rept 11 @ ARM Ltd recommends at least
48 nop @ 11 NOPs
49 .endr
50#else
51 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
52#endif
53 mov pc, lr
54ENDPROC(v6_flush_icache_all)
55
56/*
57 * v6_flush_cache_all()
58 *
59 * Flush the entire cache.
60 *
61 * It is assumed that:
62 */
63ENTRY(v6_flush_kern_cache_all)
64 mov r0, #0
65#ifdef HARVARD_CACHE
66 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
67#ifndef CONFIG_ARM_ERRATA_411920
68 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
69#else
70 b v6_flush_icache_all
71#endif
72#else
73 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
74#endif
75 mov pc, lr
76
77/*
78 * v6_flush_cache_all()
79 *
80 * Flush all TLB entries in a particular address space
81 *
82 * - mm - mm_struct describing address space
83 */
84ENTRY(v6_flush_user_cache_all)
85 /*FALLTHROUGH*/
86
87/*
88 * v6_flush_cache_range(start, end, flags)
89 *
90 * Flush a range of TLB entries in the specified address space.
91 *
92 * - start - start address (may not be aligned)
93 * - end - end address (exclusive, may not be aligned)
94 * - flags - vm_area_struct flags describing address space
95 *
96 * It is assumed that:
97 * - we have a VIPT cache.
98 */
99ENTRY(v6_flush_user_cache_range)
100 mov pc, lr
101
102/*
103 * v6_coherent_kern_range(start,end)
104 *
105 * Ensure that the I and D caches are coherent within specified
106 * region. This is typically used when code has been written to
107 * a memory region, and will be executed.
108 *
109 * - start - virtual start address of region
110 * - end - virtual end address of region
111 *
112 * It is assumed that:
113 * - the Icache does not read data from the write buffer
114 */
115ENTRY(v6_coherent_kern_range)
116 /* FALLTHROUGH */
117
118/*
119 * v6_coherent_user_range(start,end)
120 *
121 * Ensure that the I and D caches are coherent within specified
122 * region. This is typically used when code has been written to
123 * a memory region, and will be executed.
124 *
125 * - start - virtual start address of region
126 * - end - virtual end address of region
127 *
128 * It is assumed that:
129 * - the Icache does not read data from the write buffer
130 */
131ENTRY(v6_coherent_user_range)
132 UNWIND(.fnstart )
133#ifdef HARVARD_CACHE
134 bic r0, r0, #CACHE_LINE_SIZE - 1
1351:
136 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line
137 add r0, r0, #CACHE_LINE_SIZE
1382:
139 cmp r0, r1
140 blo 1b
141#endif
142 mov r0, #0
143#ifdef HARVARD_CACHE
144 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
145#ifndef CONFIG_ARM_ERRATA_411920
146 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
147#else
148 b v6_flush_icache_all
149#endif
150#else
151 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
152#endif
153 mov pc, lr
154
155/*
156 * Fault handling for the cache operation above. If the virtual address in r0
157 * isn't mapped, just try the next page.
158 */
1599001:
160 mov r0, r0, lsr #12
161 mov r0, r0, lsl #12
162 add r0, r0, #4096
163 b 2b
164 UNWIND(.fnend )
165ENDPROC(v6_coherent_user_range)
166ENDPROC(v6_coherent_kern_range)
167
168/*
169 * v6_flush_kern_dcache_area(void *addr, size_t size)
170 *
171 * Ensure that the data held in the page kaddr is written back
172 * to the page in question.
173 *
174 * - addr - kernel address
175 * - size - region size
176 */
177ENTRY(v6_flush_kern_dcache_area)
178 add r1, r0, r1
179 bic r0, r0, #D_CACHE_LINE_SIZE - 1
1801:
181#ifdef HARVARD_CACHE
182 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
183#else
184 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate unified line
185#endif
186 add r0, r0, #D_CACHE_LINE_SIZE
187 cmp r0, r1
188 blo 1b
189#ifdef HARVARD_CACHE
190 mov r0, #0
191 mcr p15, 0, r0, c7, c10, 4
192#endif
193 mov pc, lr
194
195
196/*
197 * v6_dma_inv_range(start,end)
198 *
199 * Invalidate the data cache within the specified region; we will
200 * be performing a DMA operation in this region and we want to
201 * purge old data in the cache.
202 *
203 * - start - virtual start address of region
204 * - end - virtual end address of region
205 */
206v6_dma_inv_range:
207#ifdef CONFIG_DMA_CACHE_RWFO
208 ldrb r2, [r0] @ read for ownership
209 strb r2, [r0] @ write for ownership
210#endif
211 tst r0, #D_CACHE_LINE_SIZE - 1
212 bic r0, r0, #D_CACHE_LINE_SIZE - 1
213#ifdef HARVARD_CACHE
214 mcrne p15, 0, r0, c7, c10, 1 @ clean D line
215#else
216 mcrne p15, 0, r0, c7, c11, 1 @ clean unified line
217#endif
218 tst r1, #D_CACHE_LINE_SIZE - 1
219#ifdef CONFIG_DMA_CACHE_RWFO
220 ldrneb r2, [r1, #-1] @ read for ownership
221 strneb r2, [r1, #-1] @ write for ownership
222#endif
223 bic r1, r1, #D_CACHE_LINE_SIZE - 1
224#ifdef HARVARD_CACHE
225 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D line
226#else
227 mcrne p15, 0, r1, c7, c15, 1 @ clean & invalidate unified line
228#endif
2291:
230#ifdef HARVARD_CACHE
231 mcr p15, 0, r0, c7, c6, 1 @ invalidate D line
232#else
233 mcr p15, 0, r0, c7, c7, 1 @ invalidate unified line
234#endif
235 add r0, r0, #D_CACHE_LINE_SIZE
236 cmp r0, r1
237#ifdef CONFIG_DMA_CACHE_RWFO
238 ldrlo r2, [r0] @ read for ownership
239 strlo r2, [r0] @ write for ownership
240#endif
241 blo 1b
242 mov r0, #0
243 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
244 mov pc, lr
245
246/*
247 * v6_dma_clean_range(start,end)
248 * - start - virtual start address of region
249 * - end - virtual end address of region
250 */
251v6_dma_clean_range:
252 bic r0, r0, #D_CACHE_LINE_SIZE - 1
2531:
254#ifdef CONFIG_DMA_CACHE_RWFO
255 ldr r2, [r0] @ read for ownership
256#endif
257#ifdef HARVARD_CACHE
258 mcr p15, 0, r0, c7, c10, 1 @ clean D line
259#else
260 mcr p15, 0, r0, c7, c11, 1 @ clean unified line
261#endif
262 add r0, r0, #D_CACHE_LINE_SIZE
263 cmp r0, r1
264 blo 1b
265 mov r0, #0
266 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
267 mov pc, lr
268
269/*
270 * v6_dma_flush_range(start,end)
271 * - start - virtual start address of region
272 * - end - virtual end address of region
273 */
274ENTRY(v6_dma_flush_range)
275#ifdef CONFIG_DMA_CACHE_RWFO
276 ldrb r2, [r0] @ read for ownership
277 strb r2, [r0] @ write for ownership
278#endif
279 bic r0, r0, #D_CACHE_LINE_SIZE - 1
2801:
281#ifdef HARVARD_CACHE
282 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
283#else
284 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate line
285#endif
286 add r0, r0, #D_CACHE_LINE_SIZE
287 cmp r0, r1
288#ifdef CONFIG_DMA_CACHE_RWFO
289 ldrlob r2, [r0] @ read for ownership
290 strlob r2, [r0] @ write for ownership
291#endif
292 blo 1b
293 mov r0, #0
294 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
295 mov pc, lr
296
297/*
298 * dma_map_area(start, size, dir)
299 * - start - kernel virtual start address
300 * - size - size of region
301 * - dir - DMA direction
302 */
303ENTRY(v6_dma_map_area)
304 add r1, r1, r0
305 teq r2, #DMA_FROM_DEVICE
306 beq v6_dma_inv_range
307#ifndef CONFIG_DMA_CACHE_RWFO
308 b v6_dma_clean_range
309#else
310 teq r2, #DMA_TO_DEVICE
311 beq v6_dma_clean_range
312 b v6_dma_flush_range
313#endif
314ENDPROC(v6_dma_map_area)
315
316/*
317 * dma_unmap_area(start, size, dir)
318 * - start - kernel virtual start address
319 * - size - size of region
320 * - dir - DMA direction
321 */
322ENTRY(v6_dma_unmap_area)
323#ifndef CONFIG_DMA_CACHE_RWFO
324 add r1, r1, r0
325 teq r2, #DMA_TO_DEVICE
326 bne v6_dma_inv_range
327#endif
328 mov pc, lr
329ENDPROC(v6_dma_unmap_area)
330
331 __INITDATA
332
333 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
334 define_cache_functions v6