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1// SPDX-License-Identifier: GPL-1.0+
2/*
3 * Device driver for Microgate SyncLink GT serial adapters.
4 *
5 * written by Paul Fulghum for Microgate Corporation
6 * paulkf@microgate.com
7 *
8 * Microgate and SyncLink are trademarks of Microgate Corporation
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
12 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
13 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
14 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
15 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
16 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
17 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
18 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
19 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
20 * OF THE POSSIBILITY OF SUCH DAMAGE.
21 */
22
23/*
24 * DEBUG OUTPUT DEFINITIONS
25 *
26 * uncomment lines below to enable specific types of debug output
27 *
28 * DBGINFO information - most verbose output
29 * DBGERR serious errors
30 * DBGBH bottom half service routine debugging
31 * DBGISR interrupt service routine debugging
32 * DBGDATA output receive and transmit data
33 * DBGTBUF output transmit DMA buffers and registers
34 * DBGRBUF output receive DMA buffers and registers
35 */
36
37#define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
38#define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
39#define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
40#define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
41#define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
42/*#define DBGTBUF(info) dump_tbufs(info)*/
43/*#define DBGRBUF(info) dump_rbufs(info)*/
44
45
46#include <linux/module.h>
47#include <linux/errno.h>
48#include <linux/signal.h>
49#include <linux/sched.h>
50#include <linux/timer.h>
51#include <linux/interrupt.h>
52#include <linux/pci.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
55#include <linux/serial.h>
56#include <linux/major.h>
57#include <linux/string.h>
58#include <linux/fcntl.h>
59#include <linux/ptrace.h>
60#include <linux/ioport.h>
61#include <linux/mm.h>
62#include <linux/seq_file.h>
63#include <linux/slab.h>
64#include <linux/netdevice.h>
65#include <linux/vmalloc.h>
66#include <linux/init.h>
67#include <linux/delay.h>
68#include <linux/ioctl.h>
69#include <linux/termios.h>
70#include <linux/bitops.h>
71#include <linux/workqueue.h>
72#include <linux/hdlc.h>
73#include <linux/synclink.h>
74
75#include <asm/io.h>
76#include <asm/irq.h>
77#include <asm/dma.h>
78#include <asm/types.h>
79#include <linux/uaccess.h>
80
81#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
82#define SYNCLINK_GENERIC_HDLC 1
83#else
84#define SYNCLINK_GENERIC_HDLC 0
85#endif
86
87/*
88 * module identification
89 */
90static char *driver_name = "SyncLink GT";
91static char *slgt_driver_name = "synclink_gt";
92static char *tty_dev_prefix = "ttySLG";
93MODULE_LICENSE("GPL");
94#define MGSL_MAGIC 0x5401
95#define MAX_DEVICES 32
96
97static const struct pci_device_id pci_table[] = {
98 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
99 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
100 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
101 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
102 {0,}, /* terminate list */
103};
104MODULE_DEVICE_TABLE(pci, pci_table);
105
106static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
107static void remove_one(struct pci_dev *dev);
108static struct pci_driver pci_driver = {
109 .name = "synclink_gt",
110 .id_table = pci_table,
111 .probe = init_one,
112 .remove = remove_one,
113};
114
115static bool pci_registered;
116
117/*
118 * module configuration and status
119 */
120static struct slgt_info *slgt_device_list;
121static int slgt_device_count;
122
123static int ttymajor;
124static int debug_level;
125static int maxframe[MAX_DEVICES];
126
127module_param(ttymajor, int, 0);
128module_param(debug_level, int, 0);
129module_param_array(maxframe, int, NULL, 0);
130
131MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
132MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
133MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
134
135/*
136 * tty support and callbacks
137 */
138static struct tty_driver *serial_driver;
139
140static int open(struct tty_struct *tty, struct file * filp);
141static void close(struct tty_struct *tty, struct file * filp);
142static void hangup(struct tty_struct *tty);
143static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
144
145static int write(struct tty_struct *tty, const unsigned char *buf, int count);
146static int put_char(struct tty_struct *tty, unsigned char ch);
147static void send_xchar(struct tty_struct *tty, char ch);
148static void wait_until_sent(struct tty_struct *tty, int timeout);
149static int write_room(struct tty_struct *tty);
150static void flush_chars(struct tty_struct *tty);
151static void flush_buffer(struct tty_struct *tty);
152static void tx_hold(struct tty_struct *tty);
153static void tx_release(struct tty_struct *tty);
154
155static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
156static int chars_in_buffer(struct tty_struct *tty);
157static void throttle(struct tty_struct * tty);
158static void unthrottle(struct tty_struct * tty);
159static int set_break(struct tty_struct *tty, int break_state);
160
161/*
162 * generic HDLC support and callbacks
163 */
164#if SYNCLINK_GENERIC_HDLC
165#define dev_to_port(D) (dev_to_hdlc(D)->priv)
166static void hdlcdev_tx_done(struct slgt_info *info);
167static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
168static int hdlcdev_init(struct slgt_info *info);
169static void hdlcdev_exit(struct slgt_info *info);
170#endif
171
172
173/*
174 * device specific structures, macros and functions
175 */
176
177#define SLGT_MAX_PORTS 4
178#define SLGT_REG_SIZE 256
179
180/*
181 * conditional wait facility
182 */
183struct cond_wait {
184 struct cond_wait *next;
185 wait_queue_head_t q;
186 wait_queue_entry_t wait;
187 unsigned int data;
188};
189static void init_cond_wait(struct cond_wait *w, unsigned int data);
190static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
191static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
192static void flush_cond_wait(struct cond_wait **head);
193
194/*
195 * DMA buffer descriptor and access macros
196 */
197struct slgt_desc
198{
199 __le16 count;
200 __le16 status;
201 __le32 pbuf; /* physical address of data buffer */
202 __le32 next; /* physical address of next descriptor */
203
204 /* driver book keeping */
205 char *buf; /* virtual address of data buffer */
206 unsigned int pdesc; /* physical address of this descriptor */
207 dma_addr_t buf_dma_addr;
208 unsigned short buf_count;
209};
210
211#define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
212#define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
213#define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
214#define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
215#define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
216#define desc_count(a) (le16_to_cpu((a).count))
217#define desc_status(a) (le16_to_cpu((a).status))
218#define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
219#define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
220#define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
221#define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
222#define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
223
224struct _input_signal_events {
225 int ri_up;
226 int ri_down;
227 int dsr_up;
228 int dsr_down;
229 int dcd_up;
230 int dcd_down;
231 int cts_up;
232 int cts_down;
233};
234
235/*
236 * device instance data structure
237 */
238struct slgt_info {
239 void *if_ptr; /* General purpose pointer (used by SPPP) */
240 struct tty_port port;
241
242 struct slgt_info *next_device; /* device list link */
243
244 int magic;
245
246 char device_name[25];
247 struct pci_dev *pdev;
248
249 int port_count; /* count of ports on adapter */
250 int adapter_num; /* adapter instance number */
251 int port_num; /* port instance number */
252
253 /* array of pointers to port contexts on this adapter */
254 struct slgt_info *port_array[SLGT_MAX_PORTS];
255
256 int line; /* tty line instance number */
257
258 struct mgsl_icount icount;
259
260 int timeout;
261 int x_char; /* xon/xoff character */
262 unsigned int read_status_mask;
263 unsigned int ignore_status_mask;
264
265 wait_queue_head_t status_event_wait_q;
266 wait_queue_head_t event_wait_q;
267 struct timer_list tx_timer;
268 struct timer_list rx_timer;
269
270 unsigned int gpio_present;
271 struct cond_wait *gpio_wait_q;
272
273 spinlock_t lock; /* spinlock for synchronizing with ISR */
274
275 struct work_struct task;
276 u32 pending_bh;
277 bool bh_requested;
278 bool bh_running;
279
280 int isr_overflow;
281 bool irq_requested; /* true if IRQ requested */
282 bool irq_occurred; /* for diagnostics use */
283
284 /* device configuration */
285
286 unsigned int bus_type;
287 unsigned int irq_level;
288 unsigned long irq_flags;
289
290 unsigned char __iomem * reg_addr; /* memory mapped registers address */
291 u32 phys_reg_addr;
292 bool reg_addr_requested;
293
294 MGSL_PARAMS params; /* communications parameters */
295 u32 idle_mode;
296 u32 max_frame_size; /* as set by device config */
297
298 unsigned int rbuf_fill_level;
299 unsigned int rx_pio;
300 unsigned int if_mode;
301 unsigned int base_clock;
302 unsigned int xsync;
303 unsigned int xctrl;
304
305 /* device status */
306
307 bool rx_enabled;
308 bool rx_restart;
309
310 bool tx_enabled;
311 bool tx_active;
312
313 unsigned char signals; /* serial signal states */
314 int init_error; /* initialization error */
315
316 unsigned char *tx_buf;
317 int tx_count;
318
319 char *flag_buf;
320 bool drop_rts_on_tx_done;
321 struct _input_signal_events input_signal_events;
322
323 int dcd_chkcount; /* check counts to prevent */
324 int cts_chkcount; /* too many IRQs if a signal */
325 int dsr_chkcount; /* is floating */
326 int ri_chkcount;
327
328 char *bufs; /* virtual address of DMA buffer lists */
329 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
330
331 unsigned int rbuf_count;
332 struct slgt_desc *rbufs;
333 unsigned int rbuf_current;
334 unsigned int rbuf_index;
335 unsigned int rbuf_fill_index;
336 unsigned short rbuf_fill_count;
337
338 unsigned int tbuf_count;
339 struct slgt_desc *tbufs;
340 unsigned int tbuf_current;
341 unsigned int tbuf_start;
342
343 unsigned char *tmp_rbuf;
344 unsigned int tmp_rbuf_count;
345
346 /* SPPP/Cisco HDLC device parts */
347
348 int netcount;
349 spinlock_t netlock;
350#if SYNCLINK_GENERIC_HDLC
351 struct net_device *netdev;
352#endif
353
354};
355
356static MGSL_PARAMS default_params = {
357 .mode = MGSL_MODE_HDLC,
358 .loopback = 0,
359 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
360 .encoding = HDLC_ENCODING_NRZI_SPACE,
361 .clock_speed = 0,
362 .addr_filter = 0xff,
363 .crc_type = HDLC_CRC_16_CCITT,
364 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
365 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
366 .data_rate = 9600,
367 .data_bits = 8,
368 .stop_bits = 1,
369 .parity = ASYNC_PARITY_NONE
370};
371
372
373#define BH_RECEIVE 1
374#define BH_TRANSMIT 2
375#define BH_STATUS 4
376#define IO_PIN_SHUTDOWN_LIMIT 100
377
378#define DMABUFSIZE 256
379#define DESC_LIST_SIZE 4096
380
381#define MASK_PARITY BIT1
382#define MASK_FRAMING BIT0
383#define MASK_BREAK BIT14
384#define MASK_OVERRUN BIT4
385
386#define GSR 0x00 /* global status */
387#define JCR 0x04 /* JTAG control */
388#define IODR 0x08 /* GPIO direction */
389#define IOER 0x0c /* GPIO interrupt enable */
390#define IOVR 0x10 /* GPIO value */
391#define IOSR 0x14 /* GPIO interrupt status */
392#define TDR 0x80 /* tx data */
393#define RDR 0x80 /* rx data */
394#define TCR 0x82 /* tx control */
395#define TIR 0x84 /* tx idle */
396#define TPR 0x85 /* tx preamble */
397#define RCR 0x86 /* rx control */
398#define VCR 0x88 /* V.24 control */
399#define CCR 0x89 /* clock control */
400#define BDR 0x8a /* baud divisor */
401#define SCR 0x8c /* serial control */
402#define SSR 0x8e /* serial status */
403#define RDCSR 0x90 /* rx DMA control/status */
404#define TDCSR 0x94 /* tx DMA control/status */
405#define RDDAR 0x98 /* rx DMA descriptor address */
406#define TDDAR 0x9c /* tx DMA descriptor address */
407#define XSR 0x40 /* extended sync pattern */
408#define XCR 0x44 /* extended control */
409
410#define RXIDLE BIT14
411#define RXBREAK BIT14
412#define IRQ_TXDATA BIT13
413#define IRQ_TXIDLE BIT12
414#define IRQ_TXUNDER BIT11 /* HDLC */
415#define IRQ_RXDATA BIT10
416#define IRQ_RXIDLE BIT9 /* HDLC */
417#define IRQ_RXBREAK BIT9 /* async */
418#define IRQ_RXOVER BIT8
419#define IRQ_DSR BIT7
420#define IRQ_CTS BIT6
421#define IRQ_DCD BIT5
422#define IRQ_RI BIT4
423#define IRQ_ALL 0x3ff0
424#define IRQ_MASTER BIT0
425
426#define slgt_irq_on(info, mask) \
427 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
428#define slgt_irq_off(info, mask) \
429 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
430
431static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
432static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
433static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
434static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
435static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
436static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
437
438static void msc_set_vcr(struct slgt_info *info);
439
440static int startup(struct slgt_info *info);
441static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
442static void shutdown(struct slgt_info *info);
443static void program_hw(struct slgt_info *info);
444static void change_params(struct slgt_info *info);
445
446static int register_test(struct slgt_info *info);
447static int irq_test(struct slgt_info *info);
448static int loopback_test(struct slgt_info *info);
449static int adapter_test(struct slgt_info *info);
450
451static void reset_adapter(struct slgt_info *info);
452static void reset_port(struct slgt_info *info);
453static void async_mode(struct slgt_info *info);
454static void sync_mode(struct slgt_info *info);
455
456static void rx_stop(struct slgt_info *info);
457static void rx_start(struct slgt_info *info);
458static void reset_rbufs(struct slgt_info *info);
459static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
460static void rdma_reset(struct slgt_info *info);
461static bool rx_get_frame(struct slgt_info *info);
462static bool rx_get_buf(struct slgt_info *info);
463
464static void tx_start(struct slgt_info *info);
465static void tx_stop(struct slgt_info *info);
466static void tx_set_idle(struct slgt_info *info);
467static unsigned int free_tbuf_count(struct slgt_info *info);
468static unsigned int tbuf_bytes(struct slgt_info *info);
469static void reset_tbufs(struct slgt_info *info);
470static void tdma_reset(struct slgt_info *info);
471static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
472
473static void get_signals(struct slgt_info *info);
474static void set_signals(struct slgt_info *info);
475static void enable_loopback(struct slgt_info *info);
476static void set_rate(struct slgt_info *info, u32 data_rate);
477
478static int bh_action(struct slgt_info *info);
479static void bh_handler(struct work_struct *work);
480static void bh_transmit(struct slgt_info *info);
481static void isr_serial(struct slgt_info *info);
482static void isr_rdma(struct slgt_info *info);
483static void isr_txeom(struct slgt_info *info, unsigned short status);
484static void isr_tdma(struct slgt_info *info);
485
486static int alloc_dma_bufs(struct slgt_info *info);
487static void free_dma_bufs(struct slgt_info *info);
488static int alloc_desc(struct slgt_info *info);
489static void free_desc(struct slgt_info *info);
490static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
491static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
492
493static int alloc_tmp_rbuf(struct slgt_info *info);
494static void free_tmp_rbuf(struct slgt_info *info);
495
496static void tx_timeout(struct timer_list *t);
497static void rx_timeout(struct timer_list *t);
498
499/*
500 * ioctl handlers
501 */
502static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
503static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
504static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
505static int get_txidle(struct slgt_info *info, int __user *idle_mode);
506static int set_txidle(struct slgt_info *info, int idle_mode);
507static int tx_enable(struct slgt_info *info, int enable);
508static int tx_abort(struct slgt_info *info);
509static int rx_enable(struct slgt_info *info, int enable);
510static int modem_input_wait(struct slgt_info *info,int arg);
511static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
512static int tiocmget(struct tty_struct *tty);
513static int tiocmset(struct tty_struct *tty,
514 unsigned int set, unsigned int clear);
515static int set_break(struct tty_struct *tty, int break_state);
516static int get_interface(struct slgt_info *info, int __user *if_mode);
517static int set_interface(struct slgt_info *info, int if_mode);
518static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
519static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
520static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
521static int get_xsync(struct slgt_info *info, int __user *if_mode);
522static int set_xsync(struct slgt_info *info, int if_mode);
523static int get_xctrl(struct slgt_info *info, int __user *if_mode);
524static int set_xctrl(struct slgt_info *info, int if_mode);
525
526/*
527 * driver functions
528 */
529static void add_device(struct slgt_info *info);
530static void device_init(int adapter_num, struct pci_dev *pdev);
531static int claim_resources(struct slgt_info *info);
532static void release_resources(struct slgt_info *info);
533
534/*
535 * DEBUG OUTPUT CODE
536 */
537#ifndef DBGINFO
538#define DBGINFO(fmt)
539#endif
540#ifndef DBGERR
541#define DBGERR(fmt)
542#endif
543#ifndef DBGBH
544#define DBGBH(fmt)
545#endif
546#ifndef DBGISR
547#define DBGISR(fmt)
548#endif
549
550#ifdef DBGDATA
551static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
552{
553 int i;
554 int linecount;
555 printk("%s %s data:\n",info->device_name, label);
556 while(count) {
557 linecount = (count > 16) ? 16 : count;
558 for(i=0; i < linecount; i++)
559 printk("%02X ",(unsigned char)data[i]);
560 for(;i<17;i++)
561 printk(" ");
562 for(i=0;i<linecount;i++) {
563 if (data[i]>=040 && data[i]<=0176)
564 printk("%c",data[i]);
565 else
566 printk(".");
567 }
568 printk("\n");
569 data += linecount;
570 count -= linecount;
571 }
572}
573#else
574#define DBGDATA(info, buf, size, label)
575#endif
576
577#ifdef DBGTBUF
578static void dump_tbufs(struct slgt_info *info)
579{
580 int i;
581 printk("tbuf_current=%d\n", info->tbuf_current);
582 for (i=0 ; i < info->tbuf_count ; i++) {
583 printk("%d: count=%04X status=%04X\n",
584 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
585 }
586}
587#else
588#define DBGTBUF(info)
589#endif
590
591#ifdef DBGRBUF
592static void dump_rbufs(struct slgt_info *info)
593{
594 int i;
595 printk("rbuf_current=%d\n", info->rbuf_current);
596 for (i=0 ; i < info->rbuf_count ; i++) {
597 printk("%d: count=%04X status=%04X\n",
598 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
599 }
600}
601#else
602#define DBGRBUF(info)
603#endif
604
605static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
606{
607#ifdef SANITY_CHECK
608 if (!info) {
609 printk("null struct slgt_info for (%s) in %s\n", devname, name);
610 return 1;
611 }
612 if (info->magic != MGSL_MAGIC) {
613 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
614 return 1;
615 }
616#else
617 if (!info)
618 return 1;
619#endif
620 return 0;
621}
622
623/**
624 * line discipline callback wrappers
625 *
626 * The wrappers maintain line discipline references
627 * while calling into the line discipline.
628 *
629 * ldisc_receive_buf - pass receive data to line discipline
630 */
631static void ldisc_receive_buf(struct tty_struct *tty,
632 const __u8 *data, char *flags, int count)
633{
634 struct tty_ldisc *ld;
635 if (!tty)
636 return;
637 ld = tty_ldisc_ref(tty);
638 if (ld) {
639 if (ld->ops->receive_buf)
640 ld->ops->receive_buf(tty, data, flags, count);
641 tty_ldisc_deref(ld);
642 }
643}
644
645/* tty callbacks */
646
647static int open(struct tty_struct *tty, struct file *filp)
648{
649 struct slgt_info *info;
650 int retval, line;
651 unsigned long flags;
652
653 line = tty->index;
654 if (line >= slgt_device_count) {
655 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
656 return -ENODEV;
657 }
658
659 info = slgt_device_list;
660 while(info && info->line != line)
661 info = info->next_device;
662 if (sanity_check(info, tty->name, "open"))
663 return -ENODEV;
664 if (info->init_error) {
665 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
666 return -ENODEV;
667 }
668
669 tty->driver_data = info;
670 info->port.tty = tty;
671
672 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
673
674 mutex_lock(&info->port.mutex);
675 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
676
677 spin_lock_irqsave(&info->netlock, flags);
678 if (info->netcount) {
679 retval = -EBUSY;
680 spin_unlock_irqrestore(&info->netlock, flags);
681 mutex_unlock(&info->port.mutex);
682 goto cleanup;
683 }
684 info->port.count++;
685 spin_unlock_irqrestore(&info->netlock, flags);
686
687 if (info->port.count == 1) {
688 /* 1st open on this device, init hardware */
689 retval = startup(info);
690 if (retval < 0) {
691 mutex_unlock(&info->port.mutex);
692 goto cleanup;
693 }
694 }
695 mutex_unlock(&info->port.mutex);
696 retval = block_til_ready(tty, filp, info);
697 if (retval) {
698 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
699 goto cleanup;
700 }
701
702 retval = 0;
703
704cleanup:
705 if (retval) {
706 if (tty->count == 1)
707 info->port.tty = NULL; /* tty layer will release tty struct */
708 if(info->port.count)
709 info->port.count--;
710 }
711
712 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
713 return retval;
714}
715
716static void close(struct tty_struct *tty, struct file *filp)
717{
718 struct slgt_info *info = tty->driver_data;
719
720 if (sanity_check(info, tty->name, "close"))
721 return;
722 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
723
724 if (tty_port_close_start(&info->port, tty, filp) == 0)
725 goto cleanup;
726
727 mutex_lock(&info->port.mutex);
728 if (tty_port_initialized(&info->port))
729 wait_until_sent(tty, info->timeout);
730 flush_buffer(tty);
731 tty_ldisc_flush(tty);
732
733 shutdown(info);
734 mutex_unlock(&info->port.mutex);
735
736 tty_port_close_end(&info->port, tty);
737 info->port.tty = NULL;
738cleanup:
739 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
740}
741
742static void hangup(struct tty_struct *tty)
743{
744 struct slgt_info *info = tty->driver_data;
745 unsigned long flags;
746
747 if (sanity_check(info, tty->name, "hangup"))
748 return;
749 DBGINFO(("%s hangup\n", info->device_name));
750
751 flush_buffer(tty);
752
753 mutex_lock(&info->port.mutex);
754 shutdown(info);
755
756 spin_lock_irqsave(&info->port.lock, flags);
757 info->port.count = 0;
758 info->port.tty = NULL;
759 spin_unlock_irqrestore(&info->port.lock, flags);
760 tty_port_set_active(&info->port, 0);
761 mutex_unlock(&info->port.mutex);
762
763 wake_up_interruptible(&info->port.open_wait);
764}
765
766static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
767{
768 struct slgt_info *info = tty->driver_data;
769 unsigned long flags;
770
771 DBGINFO(("%s set_termios\n", tty->driver->name));
772
773 change_params(info);
774
775 /* Handle transition to B0 status */
776 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
777 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
778 spin_lock_irqsave(&info->lock,flags);
779 set_signals(info);
780 spin_unlock_irqrestore(&info->lock,flags);
781 }
782
783 /* Handle transition away from B0 status */
784 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
785 info->signals |= SerialSignal_DTR;
786 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
787 info->signals |= SerialSignal_RTS;
788 spin_lock_irqsave(&info->lock,flags);
789 set_signals(info);
790 spin_unlock_irqrestore(&info->lock,flags);
791 }
792
793 /* Handle turning off CRTSCTS */
794 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
795 tty->hw_stopped = 0;
796 tx_release(tty);
797 }
798}
799
800static void update_tx_timer(struct slgt_info *info)
801{
802 /*
803 * use worst case speed of 1200bps to calculate transmit timeout
804 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
805 */
806 if (info->params.mode == MGSL_MODE_HDLC) {
807 int timeout = (tbuf_bytes(info) * 7) + 1000;
808 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
809 }
810}
811
812static int write(struct tty_struct *tty,
813 const unsigned char *buf, int count)
814{
815 int ret = 0;
816 struct slgt_info *info = tty->driver_data;
817 unsigned long flags;
818
819 if (sanity_check(info, tty->name, "write"))
820 return -EIO;
821
822 DBGINFO(("%s write count=%d\n", info->device_name, count));
823
824 if (!info->tx_buf || (count > info->max_frame_size))
825 return -EIO;
826
827 if (!count || tty->stopped || tty->hw_stopped)
828 return 0;
829
830 spin_lock_irqsave(&info->lock, flags);
831
832 if (info->tx_count) {
833 /* send accumulated data from send_char() */
834 if (!tx_load(info, info->tx_buf, info->tx_count))
835 goto cleanup;
836 info->tx_count = 0;
837 }
838
839 if (tx_load(info, buf, count))
840 ret = count;
841
842cleanup:
843 spin_unlock_irqrestore(&info->lock, flags);
844 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
845 return ret;
846}
847
848static int put_char(struct tty_struct *tty, unsigned char ch)
849{
850 struct slgt_info *info = tty->driver_data;
851 unsigned long flags;
852 int ret = 0;
853
854 if (sanity_check(info, tty->name, "put_char"))
855 return 0;
856 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
857 if (!info->tx_buf)
858 return 0;
859 spin_lock_irqsave(&info->lock,flags);
860 if (info->tx_count < info->max_frame_size) {
861 info->tx_buf[info->tx_count++] = ch;
862 ret = 1;
863 }
864 spin_unlock_irqrestore(&info->lock,flags);
865 return ret;
866}
867
868static void send_xchar(struct tty_struct *tty, char ch)
869{
870 struct slgt_info *info = tty->driver_data;
871 unsigned long flags;
872
873 if (sanity_check(info, tty->name, "send_xchar"))
874 return;
875 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
876 info->x_char = ch;
877 if (ch) {
878 spin_lock_irqsave(&info->lock,flags);
879 if (!info->tx_enabled)
880 tx_start(info);
881 spin_unlock_irqrestore(&info->lock,flags);
882 }
883}
884
885static void wait_until_sent(struct tty_struct *tty, int timeout)
886{
887 struct slgt_info *info = tty->driver_data;
888 unsigned long orig_jiffies, char_time;
889
890 if (!info )
891 return;
892 if (sanity_check(info, tty->name, "wait_until_sent"))
893 return;
894 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
895 if (!tty_port_initialized(&info->port))
896 goto exit;
897
898 orig_jiffies = jiffies;
899
900 /* Set check interval to 1/5 of estimated time to
901 * send a character, and make it at least 1. The check
902 * interval should also be less than the timeout.
903 * Note: use tight timings here to satisfy the NIST-PCTS.
904 */
905
906 if (info->params.data_rate) {
907 char_time = info->timeout/(32 * 5);
908 if (!char_time)
909 char_time++;
910 } else
911 char_time = 1;
912
913 if (timeout)
914 char_time = min_t(unsigned long, char_time, timeout);
915
916 while (info->tx_active) {
917 msleep_interruptible(jiffies_to_msecs(char_time));
918 if (signal_pending(current))
919 break;
920 if (timeout && time_after(jiffies, orig_jiffies + timeout))
921 break;
922 }
923exit:
924 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
925}
926
927static int write_room(struct tty_struct *tty)
928{
929 struct slgt_info *info = tty->driver_data;
930 int ret;
931
932 if (sanity_check(info, tty->name, "write_room"))
933 return 0;
934 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
935 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
936 return ret;
937}
938
939static void flush_chars(struct tty_struct *tty)
940{
941 struct slgt_info *info = tty->driver_data;
942 unsigned long flags;
943
944 if (sanity_check(info, tty->name, "flush_chars"))
945 return;
946 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
947
948 if (info->tx_count <= 0 || tty->stopped ||
949 tty->hw_stopped || !info->tx_buf)
950 return;
951
952 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
953
954 spin_lock_irqsave(&info->lock,flags);
955 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
956 info->tx_count = 0;
957 spin_unlock_irqrestore(&info->lock,flags);
958}
959
960static void flush_buffer(struct tty_struct *tty)
961{
962 struct slgt_info *info = tty->driver_data;
963 unsigned long flags;
964
965 if (sanity_check(info, tty->name, "flush_buffer"))
966 return;
967 DBGINFO(("%s flush_buffer\n", info->device_name));
968
969 spin_lock_irqsave(&info->lock, flags);
970 info->tx_count = 0;
971 spin_unlock_irqrestore(&info->lock, flags);
972
973 tty_wakeup(tty);
974}
975
976/*
977 * throttle (stop) transmitter
978 */
979static void tx_hold(struct tty_struct *tty)
980{
981 struct slgt_info *info = tty->driver_data;
982 unsigned long flags;
983
984 if (sanity_check(info, tty->name, "tx_hold"))
985 return;
986 DBGINFO(("%s tx_hold\n", info->device_name));
987 spin_lock_irqsave(&info->lock,flags);
988 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
989 tx_stop(info);
990 spin_unlock_irqrestore(&info->lock,flags);
991}
992
993/*
994 * release (start) transmitter
995 */
996static void tx_release(struct tty_struct *tty)
997{
998 struct slgt_info *info = tty->driver_data;
999 unsigned long flags;
1000
1001 if (sanity_check(info, tty->name, "tx_release"))
1002 return;
1003 DBGINFO(("%s tx_release\n", info->device_name));
1004 spin_lock_irqsave(&info->lock, flags);
1005 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
1006 info->tx_count = 0;
1007 spin_unlock_irqrestore(&info->lock, flags);
1008}
1009
1010/*
1011 * Service an IOCTL request
1012 *
1013 * Arguments
1014 *
1015 * tty pointer to tty instance data
1016 * cmd IOCTL command code
1017 * arg command argument/context
1018 *
1019 * Return 0 if success, otherwise error code
1020 */
1021static int ioctl(struct tty_struct *tty,
1022 unsigned int cmd, unsigned long arg)
1023{
1024 struct slgt_info *info = tty->driver_data;
1025 void __user *argp = (void __user *)arg;
1026 int ret;
1027
1028 if (sanity_check(info, tty->name, "ioctl"))
1029 return -ENODEV;
1030 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1031
1032 if (cmd != TIOCMIWAIT) {
1033 if (tty_io_error(tty))
1034 return -EIO;
1035 }
1036
1037 switch (cmd) {
1038 case MGSL_IOCWAITEVENT:
1039 return wait_mgsl_event(info, argp);
1040 case TIOCMIWAIT:
1041 return modem_input_wait(info,(int)arg);
1042 case MGSL_IOCSGPIO:
1043 return set_gpio(info, argp);
1044 case MGSL_IOCGGPIO:
1045 return get_gpio(info, argp);
1046 case MGSL_IOCWAITGPIO:
1047 return wait_gpio(info, argp);
1048 case MGSL_IOCGXSYNC:
1049 return get_xsync(info, argp);
1050 case MGSL_IOCSXSYNC:
1051 return set_xsync(info, (int)arg);
1052 case MGSL_IOCGXCTRL:
1053 return get_xctrl(info, argp);
1054 case MGSL_IOCSXCTRL:
1055 return set_xctrl(info, (int)arg);
1056 }
1057 mutex_lock(&info->port.mutex);
1058 switch (cmd) {
1059 case MGSL_IOCGPARAMS:
1060 ret = get_params(info, argp);
1061 break;
1062 case MGSL_IOCSPARAMS:
1063 ret = set_params(info, argp);
1064 break;
1065 case MGSL_IOCGTXIDLE:
1066 ret = get_txidle(info, argp);
1067 break;
1068 case MGSL_IOCSTXIDLE:
1069 ret = set_txidle(info, (int)arg);
1070 break;
1071 case MGSL_IOCTXENABLE:
1072 ret = tx_enable(info, (int)arg);
1073 break;
1074 case MGSL_IOCRXENABLE:
1075 ret = rx_enable(info, (int)arg);
1076 break;
1077 case MGSL_IOCTXABORT:
1078 ret = tx_abort(info);
1079 break;
1080 case MGSL_IOCGSTATS:
1081 ret = get_stats(info, argp);
1082 break;
1083 case MGSL_IOCGIF:
1084 ret = get_interface(info, argp);
1085 break;
1086 case MGSL_IOCSIF:
1087 ret = set_interface(info,(int)arg);
1088 break;
1089 default:
1090 ret = -ENOIOCTLCMD;
1091 }
1092 mutex_unlock(&info->port.mutex);
1093 return ret;
1094}
1095
1096static int get_icount(struct tty_struct *tty,
1097 struct serial_icounter_struct *icount)
1098
1099{
1100 struct slgt_info *info = tty->driver_data;
1101 struct mgsl_icount cnow; /* kernel counter temps */
1102 unsigned long flags;
1103
1104 spin_lock_irqsave(&info->lock,flags);
1105 cnow = info->icount;
1106 spin_unlock_irqrestore(&info->lock,flags);
1107
1108 icount->cts = cnow.cts;
1109 icount->dsr = cnow.dsr;
1110 icount->rng = cnow.rng;
1111 icount->dcd = cnow.dcd;
1112 icount->rx = cnow.rx;
1113 icount->tx = cnow.tx;
1114 icount->frame = cnow.frame;
1115 icount->overrun = cnow.overrun;
1116 icount->parity = cnow.parity;
1117 icount->brk = cnow.brk;
1118 icount->buf_overrun = cnow.buf_overrun;
1119
1120 return 0;
1121}
1122
1123/*
1124 * support for 32 bit ioctl calls on 64 bit systems
1125 */
1126#ifdef CONFIG_COMPAT
1127static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1128{
1129 struct MGSL_PARAMS32 tmp_params;
1130
1131 DBGINFO(("%s get_params32\n", info->device_name));
1132 memset(&tmp_params, 0, sizeof(tmp_params));
1133 tmp_params.mode = (compat_ulong_t)info->params.mode;
1134 tmp_params.loopback = info->params.loopback;
1135 tmp_params.flags = info->params.flags;
1136 tmp_params.encoding = info->params.encoding;
1137 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1138 tmp_params.addr_filter = info->params.addr_filter;
1139 tmp_params.crc_type = info->params.crc_type;
1140 tmp_params.preamble_length = info->params.preamble_length;
1141 tmp_params.preamble = info->params.preamble;
1142 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1143 tmp_params.data_bits = info->params.data_bits;
1144 tmp_params.stop_bits = info->params.stop_bits;
1145 tmp_params.parity = info->params.parity;
1146 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1147 return -EFAULT;
1148 return 0;
1149}
1150
1151static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1152{
1153 struct MGSL_PARAMS32 tmp_params;
1154
1155 DBGINFO(("%s set_params32\n", info->device_name));
1156 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1157 return -EFAULT;
1158
1159 spin_lock(&info->lock);
1160 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1161 info->base_clock = tmp_params.clock_speed;
1162 } else {
1163 info->params.mode = tmp_params.mode;
1164 info->params.loopback = tmp_params.loopback;
1165 info->params.flags = tmp_params.flags;
1166 info->params.encoding = tmp_params.encoding;
1167 info->params.clock_speed = tmp_params.clock_speed;
1168 info->params.addr_filter = tmp_params.addr_filter;
1169 info->params.crc_type = tmp_params.crc_type;
1170 info->params.preamble_length = tmp_params.preamble_length;
1171 info->params.preamble = tmp_params.preamble;
1172 info->params.data_rate = tmp_params.data_rate;
1173 info->params.data_bits = tmp_params.data_bits;
1174 info->params.stop_bits = tmp_params.stop_bits;
1175 info->params.parity = tmp_params.parity;
1176 }
1177 spin_unlock(&info->lock);
1178
1179 program_hw(info);
1180
1181 return 0;
1182}
1183
1184static long slgt_compat_ioctl(struct tty_struct *tty,
1185 unsigned int cmd, unsigned long arg)
1186{
1187 struct slgt_info *info = tty->driver_data;
1188 int rc;
1189
1190 if (sanity_check(info, tty->name, "compat_ioctl"))
1191 return -ENODEV;
1192 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1193
1194 switch (cmd) {
1195 case MGSL_IOCSPARAMS32:
1196 rc = set_params32(info, compat_ptr(arg));
1197 break;
1198
1199 case MGSL_IOCGPARAMS32:
1200 rc = get_params32(info, compat_ptr(arg));
1201 break;
1202
1203 case MGSL_IOCGPARAMS:
1204 case MGSL_IOCSPARAMS:
1205 case MGSL_IOCGTXIDLE:
1206 case MGSL_IOCGSTATS:
1207 case MGSL_IOCWAITEVENT:
1208 case MGSL_IOCGIF:
1209 case MGSL_IOCSGPIO:
1210 case MGSL_IOCGGPIO:
1211 case MGSL_IOCWAITGPIO:
1212 case MGSL_IOCGXSYNC:
1213 case MGSL_IOCGXCTRL:
1214 rc = ioctl(tty, cmd, (unsigned long)compat_ptr(arg));
1215 break;
1216 default:
1217 rc = ioctl(tty, cmd, arg);
1218 }
1219 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1220 return rc;
1221}
1222#else
1223#define slgt_compat_ioctl NULL
1224#endif /* ifdef CONFIG_COMPAT */
1225
1226/*
1227 * proc fs support
1228 */
1229static inline void line_info(struct seq_file *m, struct slgt_info *info)
1230{
1231 char stat_buf[30];
1232 unsigned long flags;
1233
1234 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1235 info->device_name, info->phys_reg_addr,
1236 info->irq_level, info->max_frame_size);
1237
1238 /* output current serial signal states */
1239 spin_lock_irqsave(&info->lock,flags);
1240 get_signals(info);
1241 spin_unlock_irqrestore(&info->lock,flags);
1242
1243 stat_buf[0] = 0;
1244 stat_buf[1] = 0;
1245 if (info->signals & SerialSignal_RTS)
1246 strcat(stat_buf, "|RTS");
1247 if (info->signals & SerialSignal_CTS)
1248 strcat(stat_buf, "|CTS");
1249 if (info->signals & SerialSignal_DTR)
1250 strcat(stat_buf, "|DTR");
1251 if (info->signals & SerialSignal_DSR)
1252 strcat(stat_buf, "|DSR");
1253 if (info->signals & SerialSignal_DCD)
1254 strcat(stat_buf, "|CD");
1255 if (info->signals & SerialSignal_RI)
1256 strcat(stat_buf, "|RI");
1257
1258 if (info->params.mode != MGSL_MODE_ASYNC) {
1259 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1260 info->icount.txok, info->icount.rxok);
1261 if (info->icount.txunder)
1262 seq_printf(m, " txunder:%d", info->icount.txunder);
1263 if (info->icount.txabort)
1264 seq_printf(m, " txabort:%d", info->icount.txabort);
1265 if (info->icount.rxshort)
1266 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1267 if (info->icount.rxlong)
1268 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1269 if (info->icount.rxover)
1270 seq_printf(m, " rxover:%d", info->icount.rxover);
1271 if (info->icount.rxcrc)
1272 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1273 } else {
1274 seq_printf(m, "\tASYNC tx:%d rx:%d",
1275 info->icount.tx, info->icount.rx);
1276 if (info->icount.frame)
1277 seq_printf(m, " fe:%d", info->icount.frame);
1278 if (info->icount.parity)
1279 seq_printf(m, " pe:%d", info->icount.parity);
1280 if (info->icount.brk)
1281 seq_printf(m, " brk:%d", info->icount.brk);
1282 if (info->icount.overrun)
1283 seq_printf(m, " oe:%d", info->icount.overrun);
1284 }
1285
1286 /* Append serial signal status to end */
1287 seq_printf(m, " %s\n", stat_buf+1);
1288
1289 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1290 info->tx_active,info->bh_requested,info->bh_running,
1291 info->pending_bh);
1292}
1293
1294/* Called to print information about devices
1295 */
1296static int synclink_gt_proc_show(struct seq_file *m, void *v)
1297{
1298 struct slgt_info *info;
1299
1300 seq_puts(m, "synclink_gt driver\n");
1301
1302 info = slgt_device_list;
1303 while( info ) {
1304 line_info(m, info);
1305 info = info->next_device;
1306 }
1307 return 0;
1308}
1309
1310/*
1311 * return count of bytes in transmit buffer
1312 */
1313static int chars_in_buffer(struct tty_struct *tty)
1314{
1315 struct slgt_info *info = tty->driver_data;
1316 int count;
1317 if (sanity_check(info, tty->name, "chars_in_buffer"))
1318 return 0;
1319 count = tbuf_bytes(info);
1320 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1321 return count;
1322}
1323
1324/*
1325 * signal remote device to throttle send data (our receive data)
1326 */
1327static void throttle(struct tty_struct * tty)
1328{
1329 struct slgt_info *info = tty->driver_data;
1330 unsigned long flags;
1331
1332 if (sanity_check(info, tty->name, "throttle"))
1333 return;
1334 DBGINFO(("%s throttle\n", info->device_name));
1335 if (I_IXOFF(tty))
1336 send_xchar(tty, STOP_CHAR(tty));
1337 if (C_CRTSCTS(tty)) {
1338 spin_lock_irqsave(&info->lock,flags);
1339 info->signals &= ~SerialSignal_RTS;
1340 set_signals(info);
1341 spin_unlock_irqrestore(&info->lock,flags);
1342 }
1343}
1344
1345/*
1346 * signal remote device to stop throttling send data (our receive data)
1347 */
1348static void unthrottle(struct tty_struct * tty)
1349{
1350 struct slgt_info *info = tty->driver_data;
1351 unsigned long flags;
1352
1353 if (sanity_check(info, tty->name, "unthrottle"))
1354 return;
1355 DBGINFO(("%s unthrottle\n", info->device_name));
1356 if (I_IXOFF(tty)) {
1357 if (info->x_char)
1358 info->x_char = 0;
1359 else
1360 send_xchar(tty, START_CHAR(tty));
1361 }
1362 if (C_CRTSCTS(tty)) {
1363 spin_lock_irqsave(&info->lock,flags);
1364 info->signals |= SerialSignal_RTS;
1365 set_signals(info);
1366 spin_unlock_irqrestore(&info->lock,flags);
1367 }
1368}
1369
1370/*
1371 * set or clear transmit break condition
1372 * break_state -1=set break condition, 0=clear
1373 */
1374static int set_break(struct tty_struct *tty, int break_state)
1375{
1376 struct slgt_info *info = tty->driver_data;
1377 unsigned short value;
1378 unsigned long flags;
1379
1380 if (sanity_check(info, tty->name, "set_break"))
1381 return -EINVAL;
1382 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1383
1384 spin_lock_irqsave(&info->lock,flags);
1385 value = rd_reg16(info, TCR);
1386 if (break_state == -1)
1387 value |= BIT6;
1388 else
1389 value &= ~BIT6;
1390 wr_reg16(info, TCR, value);
1391 spin_unlock_irqrestore(&info->lock,flags);
1392 return 0;
1393}
1394
1395#if SYNCLINK_GENERIC_HDLC
1396
1397/**
1398 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1399 * set encoding and frame check sequence (FCS) options
1400 *
1401 * dev pointer to network device structure
1402 * encoding serial encoding setting
1403 * parity FCS setting
1404 *
1405 * returns 0 if success, otherwise error code
1406 */
1407static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1408 unsigned short parity)
1409{
1410 struct slgt_info *info = dev_to_port(dev);
1411 unsigned char new_encoding;
1412 unsigned short new_crctype;
1413
1414 /* return error if TTY interface open */
1415 if (info->port.count)
1416 return -EBUSY;
1417
1418 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1419
1420 switch (encoding)
1421 {
1422 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1423 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1424 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1425 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1426 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1427 default: return -EINVAL;
1428 }
1429
1430 switch (parity)
1431 {
1432 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1433 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1434 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1435 default: return -EINVAL;
1436 }
1437
1438 info->params.encoding = new_encoding;
1439 info->params.crc_type = new_crctype;
1440
1441 /* if network interface up, reprogram hardware */
1442 if (info->netcount)
1443 program_hw(info);
1444
1445 return 0;
1446}
1447
1448/**
1449 * called by generic HDLC layer to send frame
1450 *
1451 * skb socket buffer containing HDLC frame
1452 * dev pointer to network device structure
1453 */
1454static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1455 struct net_device *dev)
1456{
1457 struct slgt_info *info = dev_to_port(dev);
1458 unsigned long flags;
1459
1460 DBGINFO(("%s hdlc_xmit\n", dev->name));
1461
1462 if (!skb->len)
1463 return NETDEV_TX_OK;
1464
1465 /* stop sending until this frame completes */
1466 netif_stop_queue(dev);
1467
1468 /* update network statistics */
1469 dev->stats.tx_packets++;
1470 dev->stats.tx_bytes += skb->len;
1471
1472 /* save start time for transmit timeout detection */
1473 netif_trans_update(dev);
1474
1475 spin_lock_irqsave(&info->lock, flags);
1476 tx_load(info, skb->data, skb->len);
1477 spin_unlock_irqrestore(&info->lock, flags);
1478
1479 /* done with socket buffer, so free it */
1480 dev_kfree_skb(skb);
1481
1482 return NETDEV_TX_OK;
1483}
1484
1485/**
1486 * called by network layer when interface enabled
1487 * claim resources and initialize hardware
1488 *
1489 * dev pointer to network device structure
1490 *
1491 * returns 0 if success, otherwise error code
1492 */
1493static int hdlcdev_open(struct net_device *dev)
1494{
1495 struct slgt_info *info = dev_to_port(dev);
1496 int rc;
1497 unsigned long flags;
1498
1499 if (!try_module_get(THIS_MODULE))
1500 return -EBUSY;
1501
1502 DBGINFO(("%s hdlcdev_open\n", dev->name));
1503
1504 /* generic HDLC layer open processing */
1505 rc = hdlc_open(dev);
1506 if (rc)
1507 return rc;
1508
1509 /* arbitrate between network and tty opens */
1510 spin_lock_irqsave(&info->netlock, flags);
1511 if (info->port.count != 0 || info->netcount != 0) {
1512 DBGINFO(("%s hdlc_open busy\n", dev->name));
1513 spin_unlock_irqrestore(&info->netlock, flags);
1514 return -EBUSY;
1515 }
1516 info->netcount=1;
1517 spin_unlock_irqrestore(&info->netlock, flags);
1518
1519 /* claim resources and init adapter */
1520 if ((rc = startup(info)) != 0) {
1521 spin_lock_irqsave(&info->netlock, flags);
1522 info->netcount=0;
1523 spin_unlock_irqrestore(&info->netlock, flags);
1524 return rc;
1525 }
1526
1527 /* assert RTS and DTR, apply hardware settings */
1528 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1529 program_hw(info);
1530
1531 /* enable network layer transmit */
1532 netif_trans_update(dev);
1533 netif_start_queue(dev);
1534
1535 /* inform generic HDLC layer of current DCD status */
1536 spin_lock_irqsave(&info->lock, flags);
1537 get_signals(info);
1538 spin_unlock_irqrestore(&info->lock, flags);
1539 if (info->signals & SerialSignal_DCD)
1540 netif_carrier_on(dev);
1541 else
1542 netif_carrier_off(dev);
1543 return 0;
1544}
1545
1546/**
1547 * called by network layer when interface is disabled
1548 * shutdown hardware and release resources
1549 *
1550 * dev pointer to network device structure
1551 *
1552 * returns 0 if success, otherwise error code
1553 */
1554static int hdlcdev_close(struct net_device *dev)
1555{
1556 struct slgt_info *info = dev_to_port(dev);
1557 unsigned long flags;
1558
1559 DBGINFO(("%s hdlcdev_close\n", dev->name));
1560
1561 netif_stop_queue(dev);
1562
1563 /* shutdown adapter and release resources */
1564 shutdown(info);
1565
1566 hdlc_close(dev);
1567
1568 spin_lock_irqsave(&info->netlock, flags);
1569 info->netcount=0;
1570 spin_unlock_irqrestore(&info->netlock, flags);
1571
1572 module_put(THIS_MODULE);
1573 return 0;
1574}
1575
1576/**
1577 * called by network layer to process IOCTL call to network device
1578 *
1579 * dev pointer to network device structure
1580 * ifr pointer to network interface request structure
1581 * cmd IOCTL command code
1582 *
1583 * returns 0 if success, otherwise error code
1584 */
1585static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1586{
1587 const size_t size = sizeof(sync_serial_settings);
1588 sync_serial_settings new_line;
1589 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1590 struct slgt_info *info = dev_to_port(dev);
1591 unsigned int flags;
1592
1593 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1594
1595 /* return error if TTY interface open */
1596 if (info->port.count)
1597 return -EBUSY;
1598
1599 if (cmd != SIOCWANDEV)
1600 return hdlc_ioctl(dev, ifr, cmd);
1601
1602 memset(&new_line, 0, sizeof(new_line));
1603
1604 switch(ifr->ifr_settings.type) {
1605 case IF_GET_IFACE: /* return current sync_serial_settings */
1606
1607 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1608 if (ifr->ifr_settings.size < size) {
1609 ifr->ifr_settings.size = size; /* data size wanted */
1610 return -ENOBUFS;
1611 }
1612
1613 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1614 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1615 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1616 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1617
1618 switch (flags){
1619 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1620 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1621 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1622 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1623 default: new_line.clock_type = CLOCK_DEFAULT;
1624 }
1625
1626 new_line.clock_rate = info->params.clock_speed;
1627 new_line.loopback = info->params.loopback ? 1:0;
1628
1629 if (copy_to_user(line, &new_line, size))
1630 return -EFAULT;
1631 return 0;
1632
1633 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1634
1635 if(!capable(CAP_NET_ADMIN))
1636 return -EPERM;
1637 if (copy_from_user(&new_line, line, size))
1638 return -EFAULT;
1639
1640 switch (new_line.clock_type)
1641 {
1642 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1643 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1644 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1645 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1646 case CLOCK_DEFAULT: flags = info->params.flags &
1647 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1648 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1649 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1650 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1651 default: return -EINVAL;
1652 }
1653
1654 if (new_line.loopback != 0 && new_line.loopback != 1)
1655 return -EINVAL;
1656
1657 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1658 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1659 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1660 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1661 info->params.flags |= flags;
1662
1663 info->params.loopback = new_line.loopback;
1664
1665 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1666 info->params.clock_speed = new_line.clock_rate;
1667 else
1668 info->params.clock_speed = 0;
1669
1670 /* if network interface up, reprogram hardware */
1671 if (info->netcount)
1672 program_hw(info);
1673 return 0;
1674
1675 default:
1676 return hdlc_ioctl(dev, ifr, cmd);
1677 }
1678}
1679
1680/**
1681 * called by network layer when transmit timeout is detected
1682 *
1683 * dev pointer to network device structure
1684 */
1685static void hdlcdev_tx_timeout(struct net_device *dev, unsigned int txqueue)
1686{
1687 struct slgt_info *info = dev_to_port(dev);
1688 unsigned long flags;
1689
1690 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1691
1692 dev->stats.tx_errors++;
1693 dev->stats.tx_aborted_errors++;
1694
1695 spin_lock_irqsave(&info->lock,flags);
1696 tx_stop(info);
1697 spin_unlock_irqrestore(&info->lock,flags);
1698
1699 netif_wake_queue(dev);
1700}
1701
1702/**
1703 * called by device driver when transmit completes
1704 * reenable network layer transmit if stopped
1705 *
1706 * info pointer to device instance information
1707 */
1708static void hdlcdev_tx_done(struct slgt_info *info)
1709{
1710 if (netif_queue_stopped(info->netdev))
1711 netif_wake_queue(info->netdev);
1712}
1713
1714/**
1715 * called by device driver when frame received
1716 * pass frame to network layer
1717 *
1718 * info pointer to device instance information
1719 * buf pointer to buffer contianing frame data
1720 * size count of data bytes in buf
1721 */
1722static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1723{
1724 struct sk_buff *skb = dev_alloc_skb(size);
1725 struct net_device *dev = info->netdev;
1726
1727 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1728
1729 if (skb == NULL) {
1730 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1731 dev->stats.rx_dropped++;
1732 return;
1733 }
1734
1735 skb_put_data(skb, buf, size);
1736
1737 skb->protocol = hdlc_type_trans(skb, dev);
1738
1739 dev->stats.rx_packets++;
1740 dev->stats.rx_bytes += size;
1741
1742 netif_rx(skb);
1743}
1744
1745static const struct net_device_ops hdlcdev_ops = {
1746 .ndo_open = hdlcdev_open,
1747 .ndo_stop = hdlcdev_close,
1748 .ndo_start_xmit = hdlc_start_xmit,
1749 .ndo_do_ioctl = hdlcdev_ioctl,
1750 .ndo_tx_timeout = hdlcdev_tx_timeout,
1751};
1752
1753/**
1754 * called by device driver when adding device instance
1755 * do generic HDLC initialization
1756 *
1757 * info pointer to device instance information
1758 *
1759 * returns 0 if success, otherwise error code
1760 */
1761static int hdlcdev_init(struct slgt_info *info)
1762{
1763 int rc;
1764 struct net_device *dev;
1765 hdlc_device *hdlc;
1766
1767 /* allocate and initialize network and HDLC layer objects */
1768
1769 dev = alloc_hdlcdev(info);
1770 if (!dev) {
1771 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1772 return -ENOMEM;
1773 }
1774
1775 /* for network layer reporting purposes only */
1776 dev->mem_start = info->phys_reg_addr;
1777 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1778 dev->irq = info->irq_level;
1779
1780 /* network layer callbacks and settings */
1781 dev->netdev_ops = &hdlcdev_ops;
1782 dev->watchdog_timeo = 10 * HZ;
1783 dev->tx_queue_len = 50;
1784
1785 /* generic HDLC layer callbacks and settings */
1786 hdlc = dev_to_hdlc(dev);
1787 hdlc->attach = hdlcdev_attach;
1788 hdlc->xmit = hdlcdev_xmit;
1789
1790 /* register objects with HDLC layer */
1791 rc = register_hdlc_device(dev);
1792 if (rc) {
1793 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1794 free_netdev(dev);
1795 return rc;
1796 }
1797
1798 info->netdev = dev;
1799 return 0;
1800}
1801
1802/**
1803 * called by device driver when removing device instance
1804 * do generic HDLC cleanup
1805 *
1806 * info pointer to device instance information
1807 */
1808static void hdlcdev_exit(struct slgt_info *info)
1809{
1810 unregister_hdlc_device(info->netdev);
1811 free_netdev(info->netdev);
1812 info->netdev = NULL;
1813}
1814
1815#endif /* ifdef CONFIG_HDLC */
1816
1817/*
1818 * get async data from rx DMA buffers
1819 */
1820static void rx_async(struct slgt_info *info)
1821{
1822 struct mgsl_icount *icount = &info->icount;
1823 unsigned int start, end;
1824 unsigned char *p;
1825 unsigned char status;
1826 struct slgt_desc *bufs = info->rbufs;
1827 int i, count;
1828 int chars = 0;
1829 int stat;
1830 unsigned char ch;
1831
1832 start = end = info->rbuf_current;
1833
1834 while(desc_complete(bufs[end])) {
1835 count = desc_count(bufs[end]) - info->rbuf_index;
1836 p = bufs[end].buf + info->rbuf_index;
1837
1838 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1839 DBGDATA(info, p, count, "rx");
1840
1841 for(i=0 ; i < count; i+=2, p+=2) {
1842 ch = *p;
1843 icount->rx++;
1844
1845 stat = 0;
1846
1847 status = *(p + 1) & (BIT1 + BIT0);
1848 if (status) {
1849 if (status & BIT1)
1850 icount->parity++;
1851 else if (status & BIT0)
1852 icount->frame++;
1853 /* discard char if tty control flags say so */
1854 if (status & info->ignore_status_mask)
1855 continue;
1856 if (status & BIT1)
1857 stat = TTY_PARITY;
1858 else if (status & BIT0)
1859 stat = TTY_FRAME;
1860 }
1861 tty_insert_flip_char(&info->port, ch, stat);
1862 chars++;
1863 }
1864
1865 if (i < count) {
1866 /* receive buffer not completed */
1867 info->rbuf_index += i;
1868 mod_timer(&info->rx_timer, jiffies + 1);
1869 break;
1870 }
1871
1872 info->rbuf_index = 0;
1873 free_rbufs(info, end, end);
1874
1875 if (++end == info->rbuf_count)
1876 end = 0;
1877
1878 /* if entire list searched then no frame available */
1879 if (end == start)
1880 break;
1881 }
1882
1883 if (chars)
1884 tty_flip_buffer_push(&info->port);
1885}
1886
1887/*
1888 * return next bottom half action to perform
1889 */
1890static int bh_action(struct slgt_info *info)
1891{
1892 unsigned long flags;
1893 int rc;
1894
1895 spin_lock_irqsave(&info->lock,flags);
1896
1897 if (info->pending_bh & BH_RECEIVE) {
1898 info->pending_bh &= ~BH_RECEIVE;
1899 rc = BH_RECEIVE;
1900 } else if (info->pending_bh & BH_TRANSMIT) {
1901 info->pending_bh &= ~BH_TRANSMIT;
1902 rc = BH_TRANSMIT;
1903 } else if (info->pending_bh & BH_STATUS) {
1904 info->pending_bh &= ~BH_STATUS;
1905 rc = BH_STATUS;
1906 } else {
1907 /* Mark BH routine as complete */
1908 info->bh_running = false;
1909 info->bh_requested = false;
1910 rc = 0;
1911 }
1912
1913 spin_unlock_irqrestore(&info->lock,flags);
1914
1915 return rc;
1916}
1917
1918/*
1919 * perform bottom half processing
1920 */
1921static void bh_handler(struct work_struct *work)
1922{
1923 struct slgt_info *info = container_of(work, struct slgt_info, task);
1924 int action;
1925
1926 info->bh_running = true;
1927
1928 while((action = bh_action(info))) {
1929 switch (action) {
1930 case BH_RECEIVE:
1931 DBGBH(("%s bh receive\n", info->device_name));
1932 switch(info->params.mode) {
1933 case MGSL_MODE_ASYNC:
1934 rx_async(info);
1935 break;
1936 case MGSL_MODE_HDLC:
1937 while(rx_get_frame(info));
1938 break;
1939 case MGSL_MODE_RAW:
1940 case MGSL_MODE_MONOSYNC:
1941 case MGSL_MODE_BISYNC:
1942 case MGSL_MODE_XSYNC:
1943 while(rx_get_buf(info));
1944 break;
1945 }
1946 /* restart receiver if rx DMA buffers exhausted */
1947 if (info->rx_restart)
1948 rx_start(info);
1949 break;
1950 case BH_TRANSMIT:
1951 bh_transmit(info);
1952 break;
1953 case BH_STATUS:
1954 DBGBH(("%s bh status\n", info->device_name));
1955 info->ri_chkcount = 0;
1956 info->dsr_chkcount = 0;
1957 info->dcd_chkcount = 0;
1958 info->cts_chkcount = 0;
1959 break;
1960 default:
1961 DBGBH(("%s unknown action\n", info->device_name));
1962 break;
1963 }
1964 }
1965 DBGBH(("%s bh_handler exit\n", info->device_name));
1966}
1967
1968static void bh_transmit(struct slgt_info *info)
1969{
1970 struct tty_struct *tty = info->port.tty;
1971
1972 DBGBH(("%s bh_transmit\n", info->device_name));
1973 if (tty)
1974 tty_wakeup(tty);
1975}
1976
1977static void dsr_change(struct slgt_info *info, unsigned short status)
1978{
1979 if (status & BIT3) {
1980 info->signals |= SerialSignal_DSR;
1981 info->input_signal_events.dsr_up++;
1982 } else {
1983 info->signals &= ~SerialSignal_DSR;
1984 info->input_signal_events.dsr_down++;
1985 }
1986 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
1987 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1988 slgt_irq_off(info, IRQ_DSR);
1989 return;
1990 }
1991 info->icount.dsr++;
1992 wake_up_interruptible(&info->status_event_wait_q);
1993 wake_up_interruptible(&info->event_wait_q);
1994 info->pending_bh |= BH_STATUS;
1995}
1996
1997static void cts_change(struct slgt_info *info, unsigned short status)
1998{
1999 if (status & BIT2) {
2000 info->signals |= SerialSignal_CTS;
2001 info->input_signal_events.cts_up++;
2002 } else {
2003 info->signals &= ~SerialSignal_CTS;
2004 info->input_signal_events.cts_down++;
2005 }
2006 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2007 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2008 slgt_irq_off(info, IRQ_CTS);
2009 return;
2010 }
2011 info->icount.cts++;
2012 wake_up_interruptible(&info->status_event_wait_q);
2013 wake_up_interruptible(&info->event_wait_q);
2014 info->pending_bh |= BH_STATUS;
2015
2016 if (tty_port_cts_enabled(&info->port)) {
2017 if (info->port.tty) {
2018 if (info->port.tty->hw_stopped) {
2019 if (info->signals & SerialSignal_CTS) {
2020 info->port.tty->hw_stopped = 0;
2021 info->pending_bh |= BH_TRANSMIT;
2022 return;
2023 }
2024 } else {
2025 if (!(info->signals & SerialSignal_CTS))
2026 info->port.tty->hw_stopped = 1;
2027 }
2028 }
2029 }
2030}
2031
2032static void dcd_change(struct slgt_info *info, unsigned short status)
2033{
2034 if (status & BIT1) {
2035 info->signals |= SerialSignal_DCD;
2036 info->input_signal_events.dcd_up++;
2037 } else {
2038 info->signals &= ~SerialSignal_DCD;
2039 info->input_signal_events.dcd_down++;
2040 }
2041 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2042 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2043 slgt_irq_off(info, IRQ_DCD);
2044 return;
2045 }
2046 info->icount.dcd++;
2047#if SYNCLINK_GENERIC_HDLC
2048 if (info->netcount) {
2049 if (info->signals & SerialSignal_DCD)
2050 netif_carrier_on(info->netdev);
2051 else
2052 netif_carrier_off(info->netdev);
2053 }
2054#endif
2055 wake_up_interruptible(&info->status_event_wait_q);
2056 wake_up_interruptible(&info->event_wait_q);
2057 info->pending_bh |= BH_STATUS;
2058
2059 if (tty_port_check_carrier(&info->port)) {
2060 if (info->signals & SerialSignal_DCD)
2061 wake_up_interruptible(&info->port.open_wait);
2062 else {
2063 if (info->port.tty)
2064 tty_hangup(info->port.tty);
2065 }
2066 }
2067}
2068
2069static void ri_change(struct slgt_info *info, unsigned short status)
2070{
2071 if (status & BIT0) {
2072 info->signals |= SerialSignal_RI;
2073 info->input_signal_events.ri_up++;
2074 } else {
2075 info->signals &= ~SerialSignal_RI;
2076 info->input_signal_events.ri_down++;
2077 }
2078 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2079 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2080 slgt_irq_off(info, IRQ_RI);
2081 return;
2082 }
2083 info->icount.rng++;
2084 wake_up_interruptible(&info->status_event_wait_q);
2085 wake_up_interruptible(&info->event_wait_q);
2086 info->pending_bh |= BH_STATUS;
2087}
2088
2089static void isr_rxdata(struct slgt_info *info)
2090{
2091 unsigned int count = info->rbuf_fill_count;
2092 unsigned int i = info->rbuf_fill_index;
2093 unsigned short reg;
2094
2095 while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2096 reg = rd_reg16(info, RDR);
2097 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2098 if (desc_complete(info->rbufs[i])) {
2099 /* all buffers full */
2100 rx_stop(info);
2101 info->rx_restart = true;
2102 continue;
2103 }
2104 info->rbufs[i].buf[count++] = (unsigned char)reg;
2105 /* async mode saves status byte to buffer for each data byte */
2106 if (info->params.mode == MGSL_MODE_ASYNC)
2107 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2108 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2109 /* buffer full or end of frame */
2110 set_desc_count(info->rbufs[i], count);
2111 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2112 info->rbuf_fill_count = count = 0;
2113 if (++i == info->rbuf_count)
2114 i = 0;
2115 info->pending_bh |= BH_RECEIVE;
2116 }
2117 }
2118
2119 info->rbuf_fill_index = i;
2120 info->rbuf_fill_count = count;
2121}
2122
2123static void isr_serial(struct slgt_info *info)
2124{
2125 unsigned short status = rd_reg16(info, SSR);
2126
2127 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2128
2129 wr_reg16(info, SSR, status); /* clear pending */
2130
2131 info->irq_occurred = true;
2132
2133 if (info->params.mode == MGSL_MODE_ASYNC) {
2134 if (status & IRQ_TXIDLE) {
2135 if (info->tx_active)
2136 isr_txeom(info, status);
2137 }
2138 if (info->rx_pio && (status & IRQ_RXDATA))
2139 isr_rxdata(info);
2140 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2141 info->icount.brk++;
2142 /* process break detection if tty control allows */
2143 if (info->port.tty) {
2144 if (!(status & info->ignore_status_mask)) {
2145 if (info->read_status_mask & MASK_BREAK) {
2146 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2147 if (info->port.flags & ASYNC_SAK)
2148 do_SAK(info->port.tty);
2149 }
2150 }
2151 }
2152 }
2153 } else {
2154 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2155 isr_txeom(info, status);
2156 if (info->rx_pio && (status & IRQ_RXDATA))
2157 isr_rxdata(info);
2158 if (status & IRQ_RXIDLE) {
2159 if (status & RXIDLE)
2160 info->icount.rxidle++;
2161 else
2162 info->icount.exithunt++;
2163 wake_up_interruptible(&info->event_wait_q);
2164 }
2165
2166 if (status & IRQ_RXOVER)
2167 rx_start(info);
2168 }
2169
2170 if (status & IRQ_DSR)
2171 dsr_change(info, status);
2172 if (status & IRQ_CTS)
2173 cts_change(info, status);
2174 if (status & IRQ_DCD)
2175 dcd_change(info, status);
2176 if (status & IRQ_RI)
2177 ri_change(info, status);
2178}
2179
2180static void isr_rdma(struct slgt_info *info)
2181{
2182 unsigned int status = rd_reg32(info, RDCSR);
2183
2184 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2185
2186 /* RDCSR (rx DMA control/status)
2187 *
2188 * 31..07 reserved
2189 * 06 save status byte to DMA buffer
2190 * 05 error
2191 * 04 eol (end of list)
2192 * 03 eob (end of buffer)
2193 * 02 IRQ enable
2194 * 01 reset
2195 * 00 enable
2196 */
2197 wr_reg32(info, RDCSR, status); /* clear pending */
2198
2199 if (status & (BIT5 + BIT4)) {
2200 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2201 info->rx_restart = true;
2202 }
2203 info->pending_bh |= BH_RECEIVE;
2204}
2205
2206static void isr_tdma(struct slgt_info *info)
2207{
2208 unsigned int status = rd_reg32(info, TDCSR);
2209
2210 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2211
2212 /* TDCSR (tx DMA control/status)
2213 *
2214 * 31..06 reserved
2215 * 05 error
2216 * 04 eol (end of list)
2217 * 03 eob (end of buffer)
2218 * 02 IRQ enable
2219 * 01 reset
2220 * 00 enable
2221 */
2222 wr_reg32(info, TDCSR, status); /* clear pending */
2223
2224 if (status & (BIT5 + BIT4 + BIT3)) {
2225 // another transmit buffer has completed
2226 // run bottom half to get more send data from user
2227 info->pending_bh |= BH_TRANSMIT;
2228 }
2229}
2230
2231/*
2232 * return true if there are unsent tx DMA buffers, otherwise false
2233 *
2234 * if there are unsent buffers then info->tbuf_start
2235 * is set to index of first unsent buffer
2236 */
2237static bool unsent_tbufs(struct slgt_info *info)
2238{
2239 unsigned int i = info->tbuf_current;
2240 bool rc = false;
2241
2242 /*
2243 * search backwards from last loaded buffer (precedes tbuf_current)
2244 * for first unsent buffer (desc_count > 0)
2245 */
2246
2247 do {
2248 if (i)
2249 i--;
2250 else
2251 i = info->tbuf_count - 1;
2252 if (!desc_count(info->tbufs[i]))
2253 break;
2254 info->tbuf_start = i;
2255 rc = true;
2256 } while (i != info->tbuf_current);
2257
2258 return rc;
2259}
2260
2261static void isr_txeom(struct slgt_info *info, unsigned short status)
2262{
2263 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2264
2265 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2266 tdma_reset(info);
2267 if (status & IRQ_TXUNDER) {
2268 unsigned short val = rd_reg16(info, TCR);
2269 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2270 wr_reg16(info, TCR, val); /* clear reset bit */
2271 }
2272
2273 if (info->tx_active) {
2274 if (info->params.mode != MGSL_MODE_ASYNC) {
2275 if (status & IRQ_TXUNDER)
2276 info->icount.txunder++;
2277 else if (status & IRQ_TXIDLE)
2278 info->icount.txok++;
2279 }
2280
2281 if (unsent_tbufs(info)) {
2282 tx_start(info);
2283 update_tx_timer(info);
2284 return;
2285 }
2286 info->tx_active = false;
2287
2288 del_timer(&info->tx_timer);
2289
2290 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2291 info->signals &= ~SerialSignal_RTS;
2292 info->drop_rts_on_tx_done = false;
2293 set_signals(info);
2294 }
2295
2296#if SYNCLINK_GENERIC_HDLC
2297 if (info->netcount)
2298 hdlcdev_tx_done(info);
2299 else
2300#endif
2301 {
2302 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2303 tx_stop(info);
2304 return;
2305 }
2306 info->pending_bh |= BH_TRANSMIT;
2307 }
2308 }
2309}
2310
2311static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2312{
2313 struct cond_wait *w, *prev;
2314
2315 /* wake processes waiting for specific transitions */
2316 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2317 if (w->data & changed) {
2318 w->data = state;
2319 wake_up_interruptible(&w->q);
2320 if (prev != NULL)
2321 prev->next = w->next;
2322 else
2323 info->gpio_wait_q = w->next;
2324 } else
2325 prev = w;
2326 }
2327}
2328
2329/* interrupt service routine
2330 *
2331 * irq interrupt number
2332 * dev_id device ID supplied during interrupt registration
2333 */
2334static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2335{
2336 struct slgt_info *info = dev_id;
2337 unsigned int gsr;
2338 unsigned int i;
2339
2340 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2341
2342 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2343 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2344 info->irq_occurred = true;
2345 for(i=0; i < info->port_count ; i++) {
2346 if (info->port_array[i] == NULL)
2347 continue;
2348 spin_lock(&info->port_array[i]->lock);
2349 if (gsr & (BIT8 << i))
2350 isr_serial(info->port_array[i]);
2351 if (gsr & (BIT16 << (i*2)))
2352 isr_rdma(info->port_array[i]);
2353 if (gsr & (BIT17 << (i*2)))
2354 isr_tdma(info->port_array[i]);
2355 spin_unlock(&info->port_array[i]->lock);
2356 }
2357 }
2358
2359 if (info->gpio_present) {
2360 unsigned int state;
2361 unsigned int changed;
2362 spin_lock(&info->lock);
2363 while ((changed = rd_reg32(info, IOSR)) != 0) {
2364 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2365 /* read latched state of GPIO signals */
2366 state = rd_reg32(info, IOVR);
2367 /* clear pending GPIO interrupt bits */
2368 wr_reg32(info, IOSR, changed);
2369 for (i=0 ; i < info->port_count ; i++) {
2370 if (info->port_array[i] != NULL)
2371 isr_gpio(info->port_array[i], changed, state);
2372 }
2373 }
2374 spin_unlock(&info->lock);
2375 }
2376
2377 for(i=0; i < info->port_count ; i++) {
2378 struct slgt_info *port = info->port_array[i];
2379 if (port == NULL)
2380 continue;
2381 spin_lock(&port->lock);
2382 if ((port->port.count || port->netcount) &&
2383 port->pending_bh && !port->bh_running &&
2384 !port->bh_requested) {
2385 DBGISR(("%s bh queued\n", port->device_name));
2386 schedule_work(&port->task);
2387 port->bh_requested = true;
2388 }
2389 spin_unlock(&port->lock);
2390 }
2391
2392 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2393 return IRQ_HANDLED;
2394}
2395
2396static int startup(struct slgt_info *info)
2397{
2398 DBGINFO(("%s startup\n", info->device_name));
2399
2400 if (tty_port_initialized(&info->port))
2401 return 0;
2402
2403 if (!info->tx_buf) {
2404 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2405 if (!info->tx_buf) {
2406 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2407 return -ENOMEM;
2408 }
2409 }
2410
2411 info->pending_bh = 0;
2412
2413 memset(&info->icount, 0, sizeof(info->icount));
2414
2415 /* program hardware for current parameters */
2416 change_params(info);
2417
2418 if (info->port.tty)
2419 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2420
2421 tty_port_set_initialized(&info->port, 1);
2422
2423 return 0;
2424}
2425
2426/*
2427 * called by close() and hangup() to shutdown hardware
2428 */
2429static void shutdown(struct slgt_info *info)
2430{
2431 unsigned long flags;
2432
2433 if (!tty_port_initialized(&info->port))
2434 return;
2435
2436 DBGINFO(("%s shutdown\n", info->device_name));
2437
2438 /* clear status wait queue because status changes */
2439 /* can't happen after shutting down the hardware */
2440 wake_up_interruptible(&info->status_event_wait_q);
2441 wake_up_interruptible(&info->event_wait_q);
2442
2443 del_timer_sync(&info->tx_timer);
2444 del_timer_sync(&info->rx_timer);
2445
2446 kfree(info->tx_buf);
2447 info->tx_buf = NULL;
2448
2449 spin_lock_irqsave(&info->lock,flags);
2450
2451 tx_stop(info);
2452 rx_stop(info);
2453
2454 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2455
2456 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2457 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2458 set_signals(info);
2459 }
2460
2461 flush_cond_wait(&info->gpio_wait_q);
2462
2463 spin_unlock_irqrestore(&info->lock,flags);
2464
2465 if (info->port.tty)
2466 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2467
2468 tty_port_set_initialized(&info->port, 0);
2469}
2470
2471static void program_hw(struct slgt_info *info)
2472{
2473 unsigned long flags;
2474
2475 spin_lock_irqsave(&info->lock,flags);
2476
2477 rx_stop(info);
2478 tx_stop(info);
2479
2480 if (info->params.mode != MGSL_MODE_ASYNC ||
2481 info->netcount)
2482 sync_mode(info);
2483 else
2484 async_mode(info);
2485
2486 set_signals(info);
2487
2488 info->dcd_chkcount = 0;
2489 info->cts_chkcount = 0;
2490 info->ri_chkcount = 0;
2491 info->dsr_chkcount = 0;
2492
2493 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2494 get_signals(info);
2495
2496 if (info->netcount ||
2497 (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2498 rx_start(info);
2499
2500 spin_unlock_irqrestore(&info->lock,flags);
2501}
2502
2503/*
2504 * reconfigure adapter based on new parameters
2505 */
2506static void change_params(struct slgt_info *info)
2507{
2508 unsigned cflag;
2509 int bits_per_char;
2510
2511 if (!info->port.tty)
2512 return;
2513 DBGINFO(("%s change_params\n", info->device_name));
2514
2515 cflag = info->port.tty->termios.c_cflag;
2516
2517 /* if B0 rate (hangup) specified then negate RTS and DTR */
2518 /* otherwise assert RTS and DTR */
2519 if (cflag & CBAUD)
2520 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2521 else
2522 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2523
2524 /* byte size and parity */
2525
2526 switch (cflag & CSIZE) {
2527 case CS5: info->params.data_bits = 5; break;
2528 case CS6: info->params.data_bits = 6; break;
2529 case CS7: info->params.data_bits = 7; break;
2530 case CS8: info->params.data_bits = 8; break;
2531 default: info->params.data_bits = 7; break;
2532 }
2533
2534 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2535
2536 if (cflag & PARENB)
2537 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2538 else
2539 info->params.parity = ASYNC_PARITY_NONE;
2540
2541 /* calculate number of jiffies to transmit a full
2542 * FIFO (32 bytes) at specified data rate
2543 */
2544 bits_per_char = info->params.data_bits +
2545 info->params.stop_bits + 1;
2546
2547 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2548
2549 if (info->params.data_rate) {
2550 info->timeout = (32*HZ*bits_per_char) /
2551 info->params.data_rate;
2552 }
2553 info->timeout += HZ/50; /* Add .02 seconds of slop */
2554
2555 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2556 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2557
2558 /* process tty input control flags */
2559
2560 info->read_status_mask = IRQ_RXOVER;
2561 if (I_INPCK(info->port.tty))
2562 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2563 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2564 info->read_status_mask |= MASK_BREAK;
2565 if (I_IGNPAR(info->port.tty))
2566 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2567 if (I_IGNBRK(info->port.tty)) {
2568 info->ignore_status_mask |= MASK_BREAK;
2569 /* If ignoring parity and break indicators, ignore
2570 * overruns too. (For real raw support).
2571 */
2572 if (I_IGNPAR(info->port.tty))
2573 info->ignore_status_mask |= MASK_OVERRUN;
2574 }
2575
2576 program_hw(info);
2577}
2578
2579static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2580{
2581 DBGINFO(("%s get_stats\n", info->device_name));
2582 if (!user_icount) {
2583 memset(&info->icount, 0, sizeof(info->icount));
2584 } else {
2585 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2586 return -EFAULT;
2587 }
2588 return 0;
2589}
2590
2591static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2592{
2593 DBGINFO(("%s get_params\n", info->device_name));
2594 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2595 return -EFAULT;
2596 return 0;
2597}
2598
2599static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2600{
2601 unsigned long flags;
2602 MGSL_PARAMS tmp_params;
2603
2604 DBGINFO(("%s set_params\n", info->device_name));
2605 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2606 return -EFAULT;
2607
2608 spin_lock_irqsave(&info->lock, flags);
2609 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2610 info->base_clock = tmp_params.clock_speed;
2611 else
2612 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2613 spin_unlock_irqrestore(&info->lock, flags);
2614
2615 program_hw(info);
2616
2617 return 0;
2618}
2619
2620static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2621{
2622 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2623 if (put_user(info->idle_mode, idle_mode))
2624 return -EFAULT;
2625 return 0;
2626}
2627
2628static int set_txidle(struct slgt_info *info, int idle_mode)
2629{
2630 unsigned long flags;
2631 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2632 spin_lock_irqsave(&info->lock,flags);
2633 info->idle_mode = idle_mode;
2634 if (info->params.mode != MGSL_MODE_ASYNC)
2635 tx_set_idle(info);
2636 spin_unlock_irqrestore(&info->lock,flags);
2637 return 0;
2638}
2639
2640static int tx_enable(struct slgt_info *info, int enable)
2641{
2642 unsigned long flags;
2643 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2644 spin_lock_irqsave(&info->lock,flags);
2645 if (enable) {
2646 if (!info->tx_enabled)
2647 tx_start(info);
2648 } else {
2649 if (info->tx_enabled)
2650 tx_stop(info);
2651 }
2652 spin_unlock_irqrestore(&info->lock,flags);
2653 return 0;
2654}
2655
2656/*
2657 * abort transmit HDLC frame
2658 */
2659static int tx_abort(struct slgt_info *info)
2660{
2661 unsigned long flags;
2662 DBGINFO(("%s tx_abort\n", info->device_name));
2663 spin_lock_irqsave(&info->lock,flags);
2664 tdma_reset(info);
2665 spin_unlock_irqrestore(&info->lock,flags);
2666 return 0;
2667}
2668
2669static int rx_enable(struct slgt_info *info, int enable)
2670{
2671 unsigned long flags;
2672 unsigned int rbuf_fill_level;
2673 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2674 spin_lock_irqsave(&info->lock,flags);
2675 /*
2676 * enable[31..16] = receive DMA buffer fill level
2677 * 0 = noop (leave fill level unchanged)
2678 * fill level must be multiple of 4 and <= buffer size
2679 */
2680 rbuf_fill_level = ((unsigned int)enable) >> 16;
2681 if (rbuf_fill_level) {
2682 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2683 spin_unlock_irqrestore(&info->lock, flags);
2684 return -EINVAL;
2685 }
2686 info->rbuf_fill_level = rbuf_fill_level;
2687 if (rbuf_fill_level < 128)
2688 info->rx_pio = 1; /* PIO mode */
2689 else
2690 info->rx_pio = 0; /* DMA mode */
2691 rx_stop(info); /* restart receiver to use new fill level */
2692 }
2693
2694 /*
2695 * enable[1..0] = receiver enable command
2696 * 0 = disable
2697 * 1 = enable
2698 * 2 = enable or force hunt mode if already enabled
2699 */
2700 enable &= 3;
2701 if (enable) {
2702 if (!info->rx_enabled)
2703 rx_start(info);
2704 else if (enable == 2) {
2705 /* force hunt mode (write 1 to RCR[3]) */
2706 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2707 }
2708 } else {
2709 if (info->rx_enabled)
2710 rx_stop(info);
2711 }
2712 spin_unlock_irqrestore(&info->lock,flags);
2713 return 0;
2714}
2715
2716/*
2717 * wait for specified event to occur
2718 */
2719static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2720{
2721 unsigned long flags;
2722 int s;
2723 int rc=0;
2724 struct mgsl_icount cprev, cnow;
2725 int events;
2726 int mask;
2727 struct _input_signal_events oldsigs, newsigs;
2728 DECLARE_WAITQUEUE(wait, current);
2729
2730 if (get_user(mask, mask_ptr))
2731 return -EFAULT;
2732
2733 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2734
2735 spin_lock_irqsave(&info->lock,flags);
2736
2737 /* return immediately if state matches requested events */
2738 get_signals(info);
2739 s = info->signals;
2740
2741 events = mask &
2742 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2743 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2744 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2745 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2746 if (events) {
2747 spin_unlock_irqrestore(&info->lock,flags);
2748 goto exit;
2749 }
2750
2751 /* save current irq counts */
2752 cprev = info->icount;
2753 oldsigs = info->input_signal_events;
2754
2755 /* enable hunt and idle irqs if needed */
2756 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2757 unsigned short val = rd_reg16(info, SCR);
2758 if (!(val & IRQ_RXIDLE))
2759 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2760 }
2761
2762 set_current_state(TASK_INTERRUPTIBLE);
2763 add_wait_queue(&info->event_wait_q, &wait);
2764
2765 spin_unlock_irqrestore(&info->lock,flags);
2766
2767 for(;;) {
2768 schedule();
2769 if (signal_pending(current)) {
2770 rc = -ERESTARTSYS;
2771 break;
2772 }
2773
2774 /* get current irq counts */
2775 spin_lock_irqsave(&info->lock,flags);
2776 cnow = info->icount;
2777 newsigs = info->input_signal_events;
2778 set_current_state(TASK_INTERRUPTIBLE);
2779 spin_unlock_irqrestore(&info->lock,flags);
2780
2781 /* if no change, wait aborted for some reason */
2782 if (newsigs.dsr_up == oldsigs.dsr_up &&
2783 newsigs.dsr_down == oldsigs.dsr_down &&
2784 newsigs.dcd_up == oldsigs.dcd_up &&
2785 newsigs.dcd_down == oldsigs.dcd_down &&
2786 newsigs.cts_up == oldsigs.cts_up &&
2787 newsigs.cts_down == oldsigs.cts_down &&
2788 newsigs.ri_up == oldsigs.ri_up &&
2789 newsigs.ri_down == oldsigs.ri_down &&
2790 cnow.exithunt == cprev.exithunt &&
2791 cnow.rxidle == cprev.rxidle) {
2792 rc = -EIO;
2793 break;
2794 }
2795
2796 events = mask &
2797 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2798 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2799 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2800 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2801 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2802 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2803 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2804 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2805 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2806 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2807 if (events)
2808 break;
2809
2810 cprev = cnow;
2811 oldsigs = newsigs;
2812 }
2813
2814 remove_wait_queue(&info->event_wait_q, &wait);
2815 set_current_state(TASK_RUNNING);
2816
2817
2818 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2819 spin_lock_irqsave(&info->lock,flags);
2820 if (!waitqueue_active(&info->event_wait_q)) {
2821 /* disable enable exit hunt mode/idle rcvd IRQs */
2822 wr_reg16(info, SCR,
2823 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2824 }
2825 spin_unlock_irqrestore(&info->lock,flags);
2826 }
2827exit:
2828 if (rc == 0)
2829 rc = put_user(events, mask_ptr);
2830 return rc;
2831}
2832
2833static int get_interface(struct slgt_info *info, int __user *if_mode)
2834{
2835 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2836 if (put_user(info->if_mode, if_mode))
2837 return -EFAULT;
2838 return 0;
2839}
2840
2841static int set_interface(struct slgt_info *info, int if_mode)
2842{
2843 unsigned long flags;
2844 unsigned short val;
2845
2846 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2847 spin_lock_irqsave(&info->lock,flags);
2848 info->if_mode = if_mode;
2849
2850 msc_set_vcr(info);
2851
2852 /* TCR (tx control) 07 1=RTS driver control */
2853 val = rd_reg16(info, TCR);
2854 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2855 val |= BIT7;
2856 else
2857 val &= ~BIT7;
2858 wr_reg16(info, TCR, val);
2859
2860 spin_unlock_irqrestore(&info->lock,flags);
2861 return 0;
2862}
2863
2864static int get_xsync(struct slgt_info *info, int __user *xsync)
2865{
2866 DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2867 if (put_user(info->xsync, xsync))
2868 return -EFAULT;
2869 return 0;
2870}
2871
2872/*
2873 * set extended sync pattern (1 to 4 bytes) for extended sync mode
2874 *
2875 * sync pattern is contained in least significant bytes of value
2876 * most significant byte of sync pattern is oldest (1st sent/detected)
2877 */
2878static int set_xsync(struct slgt_info *info, int xsync)
2879{
2880 unsigned long flags;
2881
2882 DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2883 spin_lock_irqsave(&info->lock, flags);
2884 info->xsync = xsync;
2885 wr_reg32(info, XSR, xsync);
2886 spin_unlock_irqrestore(&info->lock, flags);
2887 return 0;
2888}
2889
2890static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2891{
2892 DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2893 if (put_user(info->xctrl, xctrl))
2894 return -EFAULT;
2895 return 0;
2896}
2897
2898/*
2899 * set extended control options
2900 *
2901 * xctrl[31:19] reserved, must be zero
2902 * xctrl[18:17] extended sync pattern length in bytes
2903 * 00 = 1 byte in xsr[7:0]
2904 * 01 = 2 bytes in xsr[15:0]
2905 * 10 = 3 bytes in xsr[23:0]
2906 * 11 = 4 bytes in xsr[31:0]
2907 * xctrl[16] 1 = enable terminal count, 0=disabled
2908 * xctrl[15:0] receive terminal count for fixed length packets
2909 * value is count minus one (0 = 1 byte packet)
2910 * when terminal count is reached, receiver
2911 * automatically returns to hunt mode and receive
2912 * FIFO contents are flushed to DMA buffers with
2913 * end of frame (EOF) status
2914 */
2915static int set_xctrl(struct slgt_info *info, int xctrl)
2916{
2917 unsigned long flags;
2918
2919 DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2920 spin_lock_irqsave(&info->lock, flags);
2921 info->xctrl = xctrl;
2922 wr_reg32(info, XCR, xctrl);
2923 spin_unlock_irqrestore(&info->lock, flags);
2924 return 0;
2925}
2926
2927/*
2928 * set general purpose IO pin state and direction
2929 *
2930 * user_gpio fields:
2931 * state each bit indicates a pin state
2932 * smask set bit indicates pin state to set
2933 * dir each bit indicates a pin direction (0=input, 1=output)
2934 * dmask set bit indicates pin direction to set
2935 */
2936static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2937{
2938 unsigned long flags;
2939 struct gpio_desc gpio;
2940 __u32 data;
2941
2942 if (!info->gpio_present)
2943 return -EINVAL;
2944 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2945 return -EFAULT;
2946 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2947 info->device_name, gpio.state, gpio.smask,
2948 gpio.dir, gpio.dmask));
2949
2950 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2951 if (gpio.dmask) {
2952 data = rd_reg32(info, IODR);
2953 data |= gpio.dmask & gpio.dir;
2954 data &= ~(gpio.dmask & ~gpio.dir);
2955 wr_reg32(info, IODR, data);
2956 }
2957 if (gpio.smask) {
2958 data = rd_reg32(info, IOVR);
2959 data |= gpio.smask & gpio.state;
2960 data &= ~(gpio.smask & ~gpio.state);
2961 wr_reg32(info, IOVR, data);
2962 }
2963 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
2964
2965 return 0;
2966}
2967
2968/*
2969 * get general purpose IO pin state and direction
2970 */
2971static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2972{
2973 struct gpio_desc gpio;
2974 if (!info->gpio_present)
2975 return -EINVAL;
2976 gpio.state = rd_reg32(info, IOVR);
2977 gpio.smask = 0xffffffff;
2978 gpio.dir = rd_reg32(info, IODR);
2979 gpio.dmask = 0xffffffff;
2980 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2981 return -EFAULT;
2982 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2983 info->device_name, gpio.state, gpio.dir));
2984 return 0;
2985}
2986
2987/*
2988 * conditional wait facility
2989 */
2990static void init_cond_wait(struct cond_wait *w, unsigned int data)
2991{
2992 init_waitqueue_head(&w->q);
2993 init_waitqueue_entry(&w->wait, current);
2994 w->data = data;
2995}
2996
2997static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2998{
2999 set_current_state(TASK_INTERRUPTIBLE);
3000 add_wait_queue(&w->q, &w->wait);
3001 w->next = *head;
3002 *head = w;
3003}
3004
3005static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
3006{
3007 struct cond_wait *w, *prev;
3008 remove_wait_queue(&cw->q, &cw->wait);
3009 set_current_state(TASK_RUNNING);
3010 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
3011 if (w == cw) {
3012 if (prev != NULL)
3013 prev->next = w->next;
3014 else
3015 *head = w->next;
3016 break;
3017 }
3018 }
3019}
3020
3021static void flush_cond_wait(struct cond_wait **head)
3022{
3023 while (*head != NULL) {
3024 wake_up_interruptible(&(*head)->q);
3025 *head = (*head)->next;
3026 }
3027}
3028
3029/*
3030 * wait for general purpose I/O pin(s) to enter specified state
3031 *
3032 * user_gpio fields:
3033 * state - bit indicates target pin state
3034 * smask - set bit indicates watched pin
3035 *
3036 * The wait ends when at least one watched pin enters the specified
3037 * state. When 0 (no error) is returned, user_gpio->state is set to the
3038 * state of all GPIO pins when the wait ends.
3039 *
3040 * Note: Each pin may be a dedicated input, dedicated output, or
3041 * configurable input/output. The number and configuration of pins
3042 * varies with the specific adapter model. Only input pins (dedicated
3043 * or configured) can be monitored with this function.
3044 */
3045static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3046{
3047 unsigned long flags;
3048 int rc = 0;
3049 struct gpio_desc gpio;
3050 struct cond_wait wait;
3051 u32 state;
3052
3053 if (!info->gpio_present)
3054 return -EINVAL;
3055 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3056 return -EFAULT;
3057 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3058 info->device_name, gpio.state, gpio.smask));
3059 /* ignore output pins identified by set IODR bit */
3060 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3061 return -EINVAL;
3062 init_cond_wait(&wait, gpio.smask);
3063
3064 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3065 /* enable interrupts for watched pins */
3066 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3067 /* get current pin states */
3068 state = rd_reg32(info, IOVR);
3069
3070 if (gpio.smask & ~(state ^ gpio.state)) {
3071 /* already in target state */
3072 gpio.state = state;
3073 } else {
3074 /* wait for target state */
3075 add_cond_wait(&info->gpio_wait_q, &wait);
3076 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3077 schedule();
3078 if (signal_pending(current))
3079 rc = -ERESTARTSYS;
3080 else
3081 gpio.state = wait.data;
3082 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3083 remove_cond_wait(&info->gpio_wait_q, &wait);
3084 }
3085
3086 /* disable all GPIO interrupts if no waiting processes */
3087 if (info->gpio_wait_q == NULL)
3088 wr_reg32(info, IOER, 0);
3089 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3090
3091 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3092 rc = -EFAULT;
3093 return rc;
3094}
3095
3096static int modem_input_wait(struct slgt_info *info,int arg)
3097{
3098 unsigned long flags;
3099 int rc;
3100 struct mgsl_icount cprev, cnow;
3101 DECLARE_WAITQUEUE(wait, current);
3102
3103 /* save current irq counts */
3104 spin_lock_irqsave(&info->lock,flags);
3105 cprev = info->icount;
3106 add_wait_queue(&info->status_event_wait_q, &wait);
3107 set_current_state(TASK_INTERRUPTIBLE);
3108 spin_unlock_irqrestore(&info->lock,flags);
3109
3110 for(;;) {
3111 schedule();
3112 if (signal_pending(current)) {
3113 rc = -ERESTARTSYS;
3114 break;
3115 }
3116
3117 /* get new irq counts */
3118 spin_lock_irqsave(&info->lock,flags);
3119 cnow = info->icount;
3120 set_current_state(TASK_INTERRUPTIBLE);
3121 spin_unlock_irqrestore(&info->lock,flags);
3122
3123 /* if no change, wait aborted for some reason */
3124 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3125 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3126 rc = -EIO;
3127 break;
3128 }
3129
3130 /* check for change in caller specified modem input */
3131 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3132 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3133 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3134 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3135 rc = 0;
3136 break;
3137 }
3138
3139 cprev = cnow;
3140 }
3141 remove_wait_queue(&info->status_event_wait_q, &wait);
3142 set_current_state(TASK_RUNNING);
3143 return rc;
3144}
3145
3146/*
3147 * return state of serial control and status signals
3148 */
3149static int tiocmget(struct tty_struct *tty)
3150{
3151 struct slgt_info *info = tty->driver_data;
3152 unsigned int result;
3153 unsigned long flags;
3154
3155 spin_lock_irqsave(&info->lock,flags);
3156 get_signals(info);
3157 spin_unlock_irqrestore(&info->lock,flags);
3158
3159 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3160 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3161 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3162 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3163 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3164 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3165
3166 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3167 return result;
3168}
3169
3170/*
3171 * set modem control signals (DTR/RTS)
3172 *
3173 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3174 * TIOCMSET = set/clear signal values
3175 * value bit mask for command
3176 */
3177static int tiocmset(struct tty_struct *tty,
3178 unsigned int set, unsigned int clear)
3179{
3180 struct slgt_info *info = tty->driver_data;
3181 unsigned long flags;
3182
3183 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3184
3185 if (set & TIOCM_RTS)
3186 info->signals |= SerialSignal_RTS;
3187 if (set & TIOCM_DTR)
3188 info->signals |= SerialSignal_DTR;
3189 if (clear & TIOCM_RTS)
3190 info->signals &= ~SerialSignal_RTS;
3191 if (clear & TIOCM_DTR)
3192 info->signals &= ~SerialSignal_DTR;
3193
3194 spin_lock_irqsave(&info->lock,flags);
3195 set_signals(info);
3196 spin_unlock_irqrestore(&info->lock,flags);
3197 return 0;
3198}
3199
3200static int carrier_raised(struct tty_port *port)
3201{
3202 unsigned long flags;
3203 struct slgt_info *info = container_of(port, struct slgt_info, port);
3204
3205 spin_lock_irqsave(&info->lock,flags);
3206 get_signals(info);
3207 spin_unlock_irqrestore(&info->lock,flags);
3208 return (info->signals & SerialSignal_DCD) ? 1 : 0;
3209}
3210
3211static void dtr_rts(struct tty_port *port, int on)
3212{
3213 unsigned long flags;
3214 struct slgt_info *info = container_of(port, struct slgt_info, port);
3215
3216 spin_lock_irqsave(&info->lock,flags);
3217 if (on)
3218 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3219 else
3220 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3221 set_signals(info);
3222 spin_unlock_irqrestore(&info->lock,flags);
3223}
3224
3225
3226/*
3227 * block current process until the device is ready to open
3228 */
3229static int block_til_ready(struct tty_struct *tty, struct file *filp,
3230 struct slgt_info *info)
3231{
3232 DECLARE_WAITQUEUE(wait, current);
3233 int retval;
3234 bool do_clocal = false;
3235 unsigned long flags;
3236 int cd;
3237 struct tty_port *port = &info->port;
3238
3239 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3240
3241 if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3242 /* nonblock mode is set or port is not enabled */
3243 tty_port_set_active(port, 1);
3244 return 0;
3245 }
3246
3247 if (C_CLOCAL(tty))
3248 do_clocal = true;
3249
3250 /* Wait for carrier detect and the line to become
3251 * free (i.e., not in use by the callout). While we are in
3252 * this loop, port->count is dropped by one, so that
3253 * close() knows when to free things. We restore it upon
3254 * exit, either normal or abnormal.
3255 */
3256
3257 retval = 0;
3258 add_wait_queue(&port->open_wait, &wait);
3259
3260 spin_lock_irqsave(&info->lock, flags);
3261 port->count--;
3262 spin_unlock_irqrestore(&info->lock, flags);
3263 port->blocked_open++;
3264
3265 while (1) {
3266 if (C_BAUD(tty) && tty_port_initialized(port))
3267 tty_port_raise_dtr_rts(port);
3268
3269 set_current_state(TASK_INTERRUPTIBLE);
3270
3271 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3272 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3273 -EAGAIN : -ERESTARTSYS;
3274 break;
3275 }
3276
3277 cd = tty_port_carrier_raised(port);
3278 if (do_clocal || cd)
3279 break;
3280
3281 if (signal_pending(current)) {
3282 retval = -ERESTARTSYS;
3283 break;
3284 }
3285
3286 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3287 tty_unlock(tty);
3288 schedule();
3289 tty_lock(tty);
3290 }
3291
3292 set_current_state(TASK_RUNNING);
3293 remove_wait_queue(&port->open_wait, &wait);
3294
3295 if (!tty_hung_up_p(filp))
3296 port->count++;
3297 port->blocked_open--;
3298
3299 if (!retval)
3300 tty_port_set_active(port, 1);
3301
3302 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3303 return retval;
3304}
3305
3306/*
3307 * allocate buffers used for calling line discipline receive_buf
3308 * directly in synchronous mode
3309 * note: add 5 bytes to max frame size to allow appending
3310 * 32-bit CRC and status byte when configured to do so
3311 */
3312static int alloc_tmp_rbuf(struct slgt_info *info)
3313{
3314 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3315 if (info->tmp_rbuf == NULL)
3316 return -ENOMEM;
3317 /* unused flag buffer to satisfy receive_buf calling interface */
3318 info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
3319 if (!info->flag_buf) {
3320 kfree(info->tmp_rbuf);
3321 info->tmp_rbuf = NULL;
3322 return -ENOMEM;
3323 }
3324 return 0;
3325}
3326
3327static void free_tmp_rbuf(struct slgt_info *info)
3328{
3329 kfree(info->tmp_rbuf);
3330 info->tmp_rbuf = NULL;
3331 kfree(info->flag_buf);
3332 info->flag_buf = NULL;
3333}
3334
3335/*
3336 * allocate DMA descriptor lists.
3337 */
3338static int alloc_desc(struct slgt_info *info)
3339{
3340 unsigned int i;
3341 unsigned int pbufs;
3342
3343 /* allocate memory to hold descriptor lists */
3344 info->bufs = pci_zalloc_consistent(info->pdev, DESC_LIST_SIZE,
3345 &info->bufs_dma_addr);
3346 if (info->bufs == NULL)
3347 return -ENOMEM;
3348
3349 info->rbufs = (struct slgt_desc*)info->bufs;
3350 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3351
3352 pbufs = (unsigned int)info->bufs_dma_addr;
3353
3354 /*
3355 * Build circular lists of descriptors
3356 */
3357
3358 for (i=0; i < info->rbuf_count; i++) {
3359 /* physical address of this descriptor */
3360 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3361
3362 /* physical address of next descriptor */
3363 if (i == info->rbuf_count - 1)
3364 info->rbufs[i].next = cpu_to_le32(pbufs);
3365 else
3366 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3367 set_desc_count(info->rbufs[i], DMABUFSIZE);
3368 }
3369
3370 for (i=0; i < info->tbuf_count; i++) {
3371 /* physical address of this descriptor */
3372 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3373
3374 /* physical address of next descriptor */
3375 if (i == info->tbuf_count - 1)
3376 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3377 else
3378 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3379 }
3380
3381 return 0;
3382}
3383
3384static void free_desc(struct slgt_info *info)
3385{
3386 if (info->bufs != NULL) {
3387 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3388 info->bufs = NULL;
3389 info->rbufs = NULL;
3390 info->tbufs = NULL;
3391 }
3392}
3393
3394static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3395{
3396 int i;
3397 for (i=0; i < count; i++) {
3398 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3399 return -ENOMEM;
3400 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3401 }
3402 return 0;
3403}
3404
3405static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3406{
3407 int i;
3408 for (i=0; i < count; i++) {
3409 if (bufs[i].buf == NULL)
3410 continue;
3411 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3412 bufs[i].buf = NULL;
3413 }
3414}
3415
3416static int alloc_dma_bufs(struct slgt_info *info)
3417{
3418 info->rbuf_count = 32;
3419 info->tbuf_count = 32;
3420
3421 if (alloc_desc(info) < 0 ||
3422 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3423 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3424 alloc_tmp_rbuf(info) < 0) {
3425 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3426 return -ENOMEM;
3427 }
3428 reset_rbufs(info);
3429 return 0;
3430}
3431
3432static void free_dma_bufs(struct slgt_info *info)
3433{
3434 if (info->bufs) {
3435 free_bufs(info, info->rbufs, info->rbuf_count);
3436 free_bufs(info, info->tbufs, info->tbuf_count);
3437 free_desc(info);
3438 }
3439 free_tmp_rbuf(info);
3440}
3441
3442static int claim_resources(struct slgt_info *info)
3443{
3444 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3445 DBGERR(("%s reg addr conflict, addr=%08X\n",
3446 info->device_name, info->phys_reg_addr));
3447 info->init_error = DiagStatus_AddressConflict;
3448 goto errout;
3449 }
3450 else
3451 info->reg_addr_requested = true;
3452
3453 info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE);
3454 if (!info->reg_addr) {
3455 DBGERR(("%s can't map device registers, addr=%08X\n",
3456 info->device_name, info->phys_reg_addr));
3457 info->init_error = DiagStatus_CantAssignPciResources;
3458 goto errout;
3459 }
3460 return 0;
3461
3462errout:
3463 release_resources(info);
3464 return -ENODEV;
3465}
3466
3467static void release_resources(struct slgt_info *info)
3468{
3469 if (info->irq_requested) {
3470 free_irq(info->irq_level, info);
3471 info->irq_requested = false;
3472 }
3473
3474 if (info->reg_addr_requested) {
3475 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3476 info->reg_addr_requested = false;
3477 }
3478
3479 if (info->reg_addr) {
3480 iounmap(info->reg_addr);
3481 info->reg_addr = NULL;
3482 }
3483}
3484
3485/* Add the specified device instance data structure to the
3486 * global linked list of devices and increment the device count.
3487 */
3488static void add_device(struct slgt_info *info)
3489{
3490 char *devstr;
3491
3492 info->next_device = NULL;
3493 info->line = slgt_device_count;
3494 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3495
3496 if (info->line < MAX_DEVICES) {
3497 if (maxframe[info->line])
3498 info->max_frame_size = maxframe[info->line];
3499 }
3500
3501 slgt_device_count++;
3502
3503 if (!slgt_device_list)
3504 slgt_device_list = info;
3505 else {
3506 struct slgt_info *current_dev = slgt_device_list;
3507 while(current_dev->next_device)
3508 current_dev = current_dev->next_device;
3509 current_dev->next_device = info;
3510 }
3511
3512 if (info->max_frame_size < 4096)
3513 info->max_frame_size = 4096;
3514 else if (info->max_frame_size > 65535)
3515 info->max_frame_size = 65535;
3516
3517 switch(info->pdev->device) {
3518 case SYNCLINK_GT_DEVICE_ID:
3519 devstr = "GT";
3520 break;
3521 case SYNCLINK_GT2_DEVICE_ID:
3522 devstr = "GT2";
3523 break;
3524 case SYNCLINK_GT4_DEVICE_ID:
3525 devstr = "GT4";
3526 break;
3527 case SYNCLINK_AC_DEVICE_ID:
3528 devstr = "AC";
3529 info->params.mode = MGSL_MODE_ASYNC;
3530 break;
3531 default:
3532 devstr = "(unknown model)";
3533 }
3534 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3535 devstr, info->device_name, info->phys_reg_addr,
3536 info->irq_level, info->max_frame_size);
3537
3538#if SYNCLINK_GENERIC_HDLC
3539 hdlcdev_init(info);
3540#endif
3541}
3542
3543static const struct tty_port_operations slgt_port_ops = {
3544 .carrier_raised = carrier_raised,
3545 .dtr_rts = dtr_rts,
3546};
3547
3548/*
3549 * allocate device instance structure, return NULL on failure
3550 */
3551static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3552{
3553 struct slgt_info *info;
3554
3555 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3556
3557 if (!info) {
3558 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3559 driver_name, adapter_num, port_num));
3560 } else {
3561 tty_port_init(&info->port);
3562 info->port.ops = &slgt_port_ops;
3563 info->magic = MGSL_MAGIC;
3564 INIT_WORK(&info->task, bh_handler);
3565 info->max_frame_size = 4096;
3566 info->base_clock = 14745600;
3567 info->rbuf_fill_level = DMABUFSIZE;
3568 info->port.close_delay = 5*HZ/10;
3569 info->port.closing_wait = 30*HZ;
3570 init_waitqueue_head(&info->status_event_wait_q);
3571 init_waitqueue_head(&info->event_wait_q);
3572 spin_lock_init(&info->netlock);
3573 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3574 info->idle_mode = HDLC_TXIDLE_FLAGS;
3575 info->adapter_num = adapter_num;
3576 info->port_num = port_num;
3577
3578 timer_setup(&info->tx_timer, tx_timeout, 0);
3579 timer_setup(&info->rx_timer, rx_timeout, 0);
3580
3581 /* Copy configuration info to device instance data */
3582 info->pdev = pdev;
3583 info->irq_level = pdev->irq;
3584 info->phys_reg_addr = pci_resource_start(pdev,0);
3585
3586 info->bus_type = MGSL_BUS_TYPE_PCI;
3587 info->irq_flags = IRQF_SHARED;
3588
3589 info->init_error = -1; /* assume error, set to 0 on successful init */
3590 }
3591
3592 return info;
3593}
3594
3595static void device_init(int adapter_num, struct pci_dev *pdev)
3596{
3597 struct slgt_info *port_array[SLGT_MAX_PORTS];
3598 int i;
3599 int port_count = 1;
3600
3601 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3602 port_count = 2;
3603 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3604 port_count = 4;
3605
3606 /* allocate device instances for all ports */
3607 for (i=0; i < port_count; ++i) {
3608 port_array[i] = alloc_dev(adapter_num, i, pdev);
3609 if (port_array[i] == NULL) {
3610 for (--i; i >= 0; --i) {
3611 tty_port_destroy(&port_array[i]->port);
3612 kfree(port_array[i]);
3613 }
3614 return;
3615 }
3616 }
3617
3618 /* give copy of port_array to all ports and add to device list */
3619 for (i=0; i < port_count; ++i) {
3620 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3621 add_device(port_array[i]);
3622 port_array[i]->port_count = port_count;
3623 spin_lock_init(&port_array[i]->lock);
3624 }
3625
3626 /* Allocate and claim adapter resources */
3627 if (!claim_resources(port_array[0])) {
3628
3629 alloc_dma_bufs(port_array[0]);
3630
3631 /* copy resource information from first port to others */
3632 for (i = 1; i < port_count; ++i) {
3633 port_array[i]->irq_level = port_array[0]->irq_level;
3634 port_array[i]->reg_addr = port_array[0]->reg_addr;
3635 alloc_dma_bufs(port_array[i]);
3636 }
3637
3638 if (request_irq(port_array[0]->irq_level,
3639 slgt_interrupt,
3640 port_array[0]->irq_flags,
3641 port_array[0]->device_name,
3642 port_array[0]) < 0) {
3643 DBGERR(("%s request_irq failed IRQ=%d\n",
3644 port_array[0]->device_name,
3645 port_array[0]->irq_level));
3646 } else {
3647 port_array[0]->irq_requested = true;
3648 adapter_test(port_array[0]);
3649 for (i=1 ; i < port_count ; i++) {
3650 port_array[i]->init_error = port_array[0]->init_error;
3651 port_array[i]->gpio_present = port_array[0]->gpio_present;
3652 }
3653 }
3654 }
3655
3656 for (i = 0; i < port_count; ++i) {
3657 struct slgt_info *info = port_array[i];
3658 tty_port_register_device(&info->port, serial_driver, info->line,
3659 &info->pdev->dev);
3660 }
3661}
3662
3663static int init_one(struct pci_dev *dev,
3664 const struct pci_device_id *ent)
3665{
3666 if (pci_enable_device(dev)) {
3667 printk("error enabling pci device %p\n", dev);
3668 return -EIO;
3669 }
3670 pci_set_master(dev);
3671 device_init(slgt_device_count, dev);
3672 return 0;
3673}
3674
3675static void remove_one(struct pci_dev *dev)
3676{
3677}
3678
3679static const struct tty_operations ops = {
3680 .open = open,
3681 .close = close,
3682 .write = write,
3683 .put_char = put_char,
3684 .flush_chars = flush_chars,
3685 .write_room = write_room,
3686 .chars_in_buffer = chars_in_buffer,
3687 .flush_buffer = flush_buffer,
3688 .ioctl = ioctl,
3689 .compat_ioctl = slgt_compat_ioctl,
3690 .throttle = throttle,
3691 .unthrottle = unthrottle,
3692 .send_xchar = send_xchar,
3693 .break_ctl = set_break,
3694 .wait_until_sent = wait_until_sent,
3695 .set_termios = set_termios,
3696 .stop = tx_hold,
3697 .start = tx_release,
3698 .hangup = hangup,
3699 .tiocmget = tiocmget,
3700 .tiocmset = tiocmset,
3701 .get_icount = get_icount,
3702 .proc_show = synclink_gt_proc_show,
3703};
3704
3705static void slgt_cleanup(void)
3706{
3707 int rc;
3708 struct slgt_info *info;
3709 struct slgt_info *tmp;
3710
3711 printk(KERN_INFO "unload %s\n", driver_name);
3712
3713 if (serial_driver) {
3714 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3715 tty_unregister_device(serial_driver, info->line);
3716 rc = tty_unregister_driver(serial_driver);
3717 if (rc)
3718 DBGERR(("tty_unregister_driver error=%d\n", rc));
3719 put_tty_driver(serial_driver);
3720 }
3721
3722 /* reset devices */
3723 info = slgt_device_list;
3724 while(info) {
3725 reset_port(info);
3726 info = info->next_device;
3727 }
3728
3729 /* release devices */
3730 info = slgt_device_list;
3731 while(info) {
3732#if SYNCLINK_GENERIC_HDLC
3733 hdlcdev_exit(info);
3734#endif
3735 free_dma_bufs(info);
3736 free_tmp_rbuf(info);
3737 if (info->port_num == 0)
3738 release_resources(info);
3739 tmp = info;
3740 info = info->next_device;
3741 tty_port_destroy(&tmp->port);
3742 kfree(tmp);
3743 }
3744
3745 if (pci_registered)
3746 pci_unregister_driver(&pci_driver);
3747}
3748
3749/*
3750 * Driver initialization entry point.
3751 */
3752static int __init slgt_init(void)
3753{
3754 int rc;
3755
3756 printk(KERN_INFO "%s\n", driver_name);
3757
3758 serial_driver = alloc_tty_driver(MAX_DEVICES);
3759 if (!serial_driver) {
3760 printk("%s can't allocate tty driver\n", driver_name);
3761 return -ENOMEM;
3762 }
3763
3764 /* Initialize the tty_driver structure */
3765
3766 serial_driver->driver_name = slgt_driver_name;
3767 serial_driver->name = tty_dev_prefix;
3768 serial_driver->major = ttymajor;
3769 serial_driver->minor_start = 64;
3770 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3771 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3772 serial_driver->init_termios = tty_std_termios;
3773 serial_driver->init_termios.c_cflag =
3774 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3775 serial_driver->init_termios.c_ispeed = 9600;
3776 serial_driver->init_termios.c_ospeed = 9600;
3777 serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3778 tty_set_operations(serial_driver, &ops);
3779 if ((rc = tty_register_driver(serial_driver)) < 0) {
3780 DBGERR(("%s can't register serial driver\n", driver_name));
3781 put_tty_driver(serial_driver);
3782 serial_driver = NULL;
3783 goto error;
3784 }
3785
3786 printk(KERN_INFO "%s, tty major#%d\n",
3787 driver_name, serial_driver->major);
3788
3789 slgt_device_count = 0;
3790 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3791 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3792 goto error;
3793 }
3794 pci_registered = true;
3795
3796 if (!slgt_device_list)
3797 printk("%s no devices found\n",driver_name);
3798
3799 return 0;
3800
3801error:
3802 slgt_cleanup();
3803 return rc;
3804}
3805
3806static void __exit slgt_exit(void)
3807{
3808 slgt_cleanup();
3809}
3810
3811module_init(slgt_init);
3812module_exit(slgt_exit);
3813
3814/*
3815 * register access routines
3816 */
3817
3818#define CALC_REGADDR() \
3819 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3820 if (addr >= 0x80) \
3821 reg_addr += (info->port_num) * 32; \
3822 else if (addr >= 0x40) \
3823 reg_addr += (info->port_num) * 16;
3824
3825static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3826{
3827 CALC_REGADDR();
3828 return readb((void __iomem *)reg_addr);
3829}
3830
3831static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3832{
3833 CALC_REGADDR();
3834 writeb(value, (void __iomem *)reg_addr);
3835}
3836
3837static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3838{
3839 CALC_REGADDR();
3840 return readw((void __iomem *)reg_addr);
3841}
3842
3843static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3844{
3845 CALC_REGADDR();
3846 writew(value, (void __iomem *)reg_addr);
3847}
3848
3849static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3850{
3851 CALC_REGADDR();
3852 return readl((void __iomem *)reg_addr);
3853}
3854
3855static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3856{
3857 CALC_REGADDR();
3858 writel(value, (void __iomem *)reg_addr);
3859}
3860
3861static void rdma_reset(struct slgt_info *info)
3862{
3863 unsigned int i;
3864
3865 /* set reset bit */
3866 wr_reg32(info, RDCSR, BIT1);
3867
3868 /* wait for enable bit cleared */
3869 for(i=0 ; i < 1000 ; i++)
3870 if (!(rd_reg32(info, RDCSR) & BIT0))
3871 break;
3872}
3873
3874static void tdma_reset(struct slgt_info *info)
3875{
3876 unsigned int i;
3877
3878 /* set reset bit */
3879 wr_reg32(info, TDCSR, BIT1);
3880
3881 /* wait for enable bit cleared */
3882 for(i=0 ; i < 1000 ; i++)
3883 if (!(rd_reg32(info, TDCSR) & BIT0))
3884 break;
3885}
3886
3887/*
3888 * enable internal loopback
3889 * TxCLK and RxCLK are generated from BRG
3890 * and TxD is looped back to RxD internally.
3891 */
3892static void enable_loopback(struct slgt_info *info)
3893{
3894 /* SCR (serial control) BIT2=loopback enable */
3895 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3896
3897 if (info->params.mode != MGSL_MODE_ASYNC) {
3898 /* CCR (clock control)
3899 * 07..05 tx clock source (010 = BRG)
3900 * 04..02 rx clock source (010 = BRG)
3901 * 01 auxclk enable (0 = disable)
3902 * 00 BRG enable (1 = enable)
3903 *
3904 * 0100 1001
3905 */
3906 wr_reg8(info, CCR, 0x49);
3907
3908 /* set speed if available, otherwise use default */
3909 if (info->params.clock_speed)
3910 set_rate(info, info->params.clock_speed);
3911 else
3912 set_rate(info, 3686400);
3913 }
3914}
3915
3916/*
3917 * set baud rate generator to specified rate
3918 */
3919static void set_rate(struct slgt_info *info, u32 rate)
3920{
3921 unsigned int div;
3922 unsigned int osc = info->base_clock;
3923
3924 /* div = osc/rate - 1
3925 *
3926 * Round div up if osc/rate is not integer to
3927 * force to next slowest rate.
3928 */
3929
3930 if (rate) {
3931 div = osc/rate;
3932 if (!(osc % rate) && div)
3933 div--;
3934 wr_reg16(info, BDR, (unsigned short)div);
3935 }
3936}
3937
3938static void rx_stop(struct slgt_info *info)
3939{
3940 unsigned short val;
3941
3942 /* disable and reset receiver */
3943 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3944 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3945 wr_reg16(info, RCR, val); /* clear reset bit */
3946
3947 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3948
3949 /* clear pending rx interrupts */
3950 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3951
3952 rdma_reset(info);
3953
3954 info->rx_enabled = false;
3955 info->rx_restart = false;
3956}
3957
3958static void rx_start(struct slgt_info *info)
3959{
3960 unsigned short val;
3961
3962 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3963
3964 /* clear pending rx overrun IRQ */
3965 wr_reg16(info, SSR, IRQ_RXOVER);
3966
3967 /* reset and disable receiver */
3968 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3969 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3970 wr_reg16(info, RCR, val); /* clear reset bit */
3971
3972 rdma_reset(info);
3973 reset_rbufs(info);
3974
3975 if (info->rx_pio) {
3976 /* rx request when rx FIFO not empty */
3977 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
3978 slgt_irq_on(info, IRQ_RXDATA);
3979 if (info->params.mode == MGSL_MODE_ASYNC) {
3980 /* enable saving of rx status */
3981 wr_reg32(info, RDCSR, BIT6);
3982 }
3983 } else {
3984 /* rx request when rx FIFO half full */
3985 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
3986 /* set 1st descriptor address */
3987 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3988
3989 if (info->params.mode != MGSL_MODE_ASYNC) {
3990 /* enable rx DMA and DMA interrupt */
3991 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3992 } else {
3993 /* enable saving of rx status, rx DMA and DMA interrupt */
3994 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3995 }
3996 }
3997
3998 slgt_irq_on(info, IRQ_RXOVER);
3999
4000 /* enable receiver */
4001 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
4002
4003 info->rx_restart = false;
4004 info->rx_enabled = true;
4005}
4006
4007static void tx_start(struct slgt_info *info)
4008{
4009 if (!info->tx_enabled) {
4010 wr_reg16(info, TCR,
4011 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
4012 info->tx_enabled = true;
4013 }
4014
4015 if (desc_count(info->tbufs[info->tbuf_start])) {
4016 info->drop_rts_on_tx_done = false;
4017
4018 if (info->params.mode != MGSL_MODE_ASYNC) {
4019 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
4020 get_signals(info);
4021 if (!(info->signals & SerialSignal_RTS)) {
4022 info->signals |= SerialSignal_RTS;
4023 set_signals(info);
4024 info->drop_rts_on_tx_done = true;
4025 }
4026 }
4027
4028 slgt_irq_off(info, IRQ_TXDATA);
4029 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
4030 /* clear tx idle and underrun status bits */
4031 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4032 } else {
4033 slgt_irq_off(info, IRQ_TXDATA);
4034 slgt_irq_on(info, IRQ_TXIDLE);
4035 /* clear tx idle status bit */
4036 wr_reg16(info, SSR, IRQ_TXIDLE);
4037 }
4038 /* set 1st descriptor address and start DMA */
4039 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
4040 wr_reg32(info, TDCSR, BIT2 + BIT0);
4041 info->tx_active = true;
4042 }
4043}
4044
4045static void tx_stop(struct slgt_info *info)
4046{
4047 unsigned short val;
4048
4049 del_timer(&info->tx_timer);
4050
4051 tdma_reset(info);
4052
4053 /* reset and disable transmitter */
4054 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
4055 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
4056
4057 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
4058
4059 /* clear tx idle and underrun status bit */
4060 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4061
4062 reset_tbufs(info);
4063
4064 info->tx_enabled = false;
4065 info->tx_active = false;
4066}
4067
4068static void reset_port(struct slgt_info *info)
4069{
4070 if (!info->reg_addr)
4071 return;
4072
4073 tx_stop(info);
4074 rx_stop(info);
4075
4076 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4077 set_signals(info);
4078
4079 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4080}
4081
4082static void reset_adapter(struct slgt_info *info)
4083{
4084 int i;
4085 for (i=0; i < info->port_count; ++i) {
4086 if (info->port_array[i])
4087 reset_port(info->port_array[i]);
4088 }
4089}
4090
4091static void async_mode(struct slgt_info *info)
4092{
4093 unsigned short val;
4094
4095 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4096 tx_stop(info);
4097 rx_stop(info);
4098
4099 /* TCR (tx control)
4100 *
4101 * 15..13 mode, 010=async
4102 * 12..10 encoding, 000=NRZ
4103 * 09 parity enable
4104 * 08 1=odd parity, 0=even parity
4105 * 07 1=RTS driver control
4106 * 06 1=break enable
4107 * 05..04 character length
4108 * 00=5 bits
4109 * 01=6 bits
4110 * 10=7 bits
4111 * 11=8 bits
4112 * 03 0=1 stop bit, 1=2 stop bits
4113 * 02 reset
4114 * 01 enable
4115 * 00 auto-CTS enable
4116 */
4117 val = 0x4000;
4118
4119 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4120 val |= BIT7;
4121
4122 if (info->params.parity != ASYNC_PARITY_NONE) {
4123 val |= BIT9;
4124 if (info->params.parity == ASYNC_PARITY_ODD)
4125 val |= BIT8;
4126 }
4127
4128 switch (info->params.data_bits)
4129 {
4130 case 6: val |= BIT4; break;
4131 case 7: val |= BIT5; break;
4132 case 8: val |= BIT5 + BIT4; break;
4133 }
4134
4135 if (info->params.stop_bits != 1)
4136 val |= BIT3;
4137
4138 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4139 val |= BIT0;
4140
4141 wr_reg16(info, TCR, val);
4142
4143 /* RCR (rx control)
4144 *
4145 * 15..13 mode, 010=async
4146 * 12..10 encoding, 000=NRZ
4147 * 09 parity enable
4148 * 08 1=odd parity, 0=even parity
4149 * 07..06 reserved, must be 0
4150 * 05..04 character length
4151 * 00=5 bits
4152 * 01=6 bits
4153 * 10=7 bits
4154 * 11=8 bits
4155 * 03 reserved, must be zero
4156 * 02 reset
4157 * 01 enable
4158 * 00 auto-DCD enable
4159 */
4160 val = 0x4000;
4161
4162 if (info->params.parity != ASYNC_PARITY_NONE) {
4163 val |= BIT9;
4164 if (info->params.parity == ASYNC_PARITY_ODD)
4165 val |= BIT8;
4166 }
4167
4168 switch (info->params.data_bits)
4169 {
4170 case 6: val |= BIT4; break;
4171 case 7: val |= BIT5; break;
4172 case 8: val |= BIT5 + BIT4; break;
4173 }
4174
4175 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4176 val |= BIT0;
4177
4178 wr_reg16(info, RCR, val);
4179
4180 /* CCR (clock control)
4181 *
4182 * 07..05 011 = tx clock source is BRG/16
4183 * 04..02 010 = rx clock source is BRG
4184 * 01 0 = auxclk disabled
4185 * 00 1 = BRG enabled
4186 *
4187 * 0110 1001
4188 */
4189 wr_reg8(info, CCR, 0x69);
4190
4191 msc_set_vcr(info);
4192
4193 /* SCR (serial control)
4194 *
4195 * 15 1=tx req on FIFO half empty
4196 * 14 1=rx req on FIFO half full
4197 * 13 tx data IRQ enable
4198 * 12 tx idle IRQ enable
4199 * 11 rx break on IRQ enable
4200 * 10 rx data IRQ enable
4201 * 09 rx break off IRQ enable
4202 * 08 overrun IRQ enable
4203 * 07 DSR IRQ enable
4204 * 06 CTS IRQ enable
4205 * 05 DCD IRQ enable
4206 * 04 RI IRQ enable
4207 * 03 0=16x sampling, 1=8x sampling
4208 * 02 1=txd->rxd internal loopback enable
4209 * 01 reserved, must be zero
4210 * 00 1=master IRQ enable
4211 */
4212 val = BIT15 + BIT14 + BIT0;
4213 /* JCR[8] : 1 = x8 async mode feature available */
4214 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4215 ((info->base_clock < (info->params.data_rate * 16)) ||
4216 (info->base_clock % (info->params.data_rate * 16)))) {
4217 /* use 8x sampling */
4218 val |= BIT3;
4219 set_rate(info, info->params.data_rate * 8);
4220 } else {
4221 /* use 16x sampling */
4222 set_rate(info, info->params.data_rate * 16);
4223 }
4224 wr_reg16(info, SCR, val);
4225
4226 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4227
4228 if (info->params.loopback)
4229 enable_loopback(info);
4230}
4231
4232static void sync_mode(struct slgt_info *info)
4233{
4234 unsigned short val;
4235
4236 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4237 tx_stop(info);
4238 rx_stop(info);
4239
4240 /* TCR (tx control)
4241 *
4242 * 15..13 mode
4243 * 000=HDLC/SDLC
4244 * 001=raw bit synchronous
4245 * 010=asynchronous/isochronous
4246 * 011=monosync byte synchronous
4247 * 100=bisync byte synchronous
4248 * 101=xsync byte synchronous
4249 * 12..10 encoding
4250 * 09 CRC enable
4251 * 08 CRC32
4252 * 07 1=RTS driver control
4253 * 06 preamble enable
4254 * 05..04 preamble length
4255 * 03 share open/close flag
4256 * 02 reset
4257 * 01 enable
4258 * 00 auto-CTS enable
4259 */
4260 val = BIT2;
4261
4262 switch(info->params.mode) {
4263 case MGSL_MODE_XSYNC:
4264 val |= BIT15 + BIT13;
4265 break;
4266 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4267 case MGSL_MODE_BISYNC: val |= BIT15; break;
4268 case MGSL_MODE_RAW: val |= BIT13; break;
4269 }
4270 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4271 val |= BIT7;
4272
4273 switch(info->params.encoding)
4274 {
4275 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4276 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4277 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4278 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4279 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4280 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4281 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4282 }
4283
4284 switch (info->params.crc_type & HDLC_CRC_MASK)
4285 {
4286 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4287 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4288 }
4289
4290 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4291 val |= BIT6;
4292
4293 switch (info->params.preamble_length)
4294 {
4295 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4296 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4297 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4298 }
4299
4300 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4301 val |= BIT0;
4302
4303 wr_reg16(info, TCR, val);
4304
4305 /* TPR (transmit preamble) */
4306
4307 switch (info->params.preamble)
4308 {
4309 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4310 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4311 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4312 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4313 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4314 default: val = 0x7e; break;
4315 }
4316 wr_reg8(info, TPR, (unsigned char)val);
4317
4318 /* RCR (rx control)
4319 *
4320 * 15..13 mode
4321 * 000=HDLC/SDLC
4322 * 001=raw bit synchronous
4323 * 010=asynchronous/isochronous
4324 * 011=monosync byte synchronous
4325 * 100=bisync byte synchronous
4326 * 101=xsync byte synchronous
4327 * 12..10 encoding
4328 * 09 CRC enable
4329 * 08 CRC32
4330 * 07..03 reserved, must be 0
4331 * 02 reset
4332 * 01 enable
4333 * 00 auto-DCD enable
4334 */
4335 val = 0;
4336
4337 switch(info->params.mode) {
4338 case MGSL_MODE_XSYNC:
4339 val |= BIT15 + BIT13;
4340 break;
4341 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4342 case MGSL_MODE_BISYNC: val |= BIT15; break;
4343 case MGSL_MODE_RAW: val |= BIT13; break;
4344 }
4345
4346 switch(info->params.encoding)
4347 {
4348 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4349 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4350 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4351 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4352 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4353 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4354 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4355 }
4356
4357 switch (info->params.crc_type & HDLC_CRC_MASK)
4358 {
4359 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4360 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4361 }
4362
4363 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4364 val |= BIT0;
4365
4366 wr_reg16(info, RCR, val);
4367
4368 /* CCR (clock control)
4369 *
4370 * 07..05 tx clock source
4371 * 04..02 rx clock source
4372 * 01 auxclk enable
4373 * 00 BRG enable
4374 */
4375 val = 0;
4376
4377 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4378 {
4379 // when RxC source is DPLL, BRG generates 16X DPLL
4380 // reference clock, so take TxC from BRG/16 to get
4381 // transmit clock at actual data rate
4382 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4383 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4384 else
4385 val |= BIT6; /* 010, txclk = BRG */
4386 }
4387 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4388 val |= BIT7; /* 100, txclk = DPLL Input */
4389 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4390 val |= BIT5; /* 001, txclk = RXC Input */
4391
4392 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4393 val |= BIT3; /* 010, rxclk = BRG */
4394 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4395 val |= BIT4; /* 100, rxclk = DPLL */
4396 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4397 val |= BIT2; /* 001, rxclk = TXC Input */
4398
4399 if (info->params.clock_speed)
4400 val |= BIT1 + BIT0;
4401
4402 wr_reg8(info, CCR, (unsigned char)val);
4403
4404 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4405 {
4406 // program DPLL mode
4407 switch(info->params.encoding)
4408 {
4409 case HDLC_ENCODING_BIPHASE_MARK:
4410 case HDLC_ENCODING_BIPHASE_SPACE:
4411 val = BIT7; break;
4412 case HDLC_ENCODING_BIPHASE_LEVEL:
4413 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4414 val = BIT7 + BIT6; break;
4415 default: val = BIT6; // NRZ encodings
4416 }
4417 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4418
4419 // DPLL requires a 16X reference clock from BRG
4420 set_rate(info, info->params.clock_speed * 16);
4421 }
4422 else
4423 set_rate(info, info->params.clock_speed);
4424
4425 tx_set_idle(info);
4426
4427 msc_set_vcr(info);
4428
4429 /* SCR (serial control)
4430 *
4431 * 15 1=tx req on FIFO half empty
4432 * 14 1=rx req on FIFO half full
4433 * 13 tx data IRQ enable
4434 * 12 tx idle IRQ enable
4435 * 11 underrun IRQ enable
4436 * 10 rx data IRQ enable
4437 * 09 rx idle IRQ enable
4438 * 08 overrun IRQ enable
4439 * 07 DSR IRQ enable
4440 * 06 CTS IRQ enable
4441 * 05 DCD IRQ enable
4442 * 04 RI IRQ enable
4443 * 03 reserved, must be zero
4444 * 02 1=txd->rxd internal loopback enable
4445 * 01 reserved, must be zero
4446 * 00 1=master IRQ enable
4447 */
4448 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4449
4450 if (info->params.loopback)
4451 enable_loopback(info);
4452}
4453
4454/*
4455 * set transmit idle mode
4456 */
4457static void tx_set_idle(struct slgt_info *info)
4458{
4459 unsigned char val;
4460 unsigned short tcr;
4461
4462 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4463 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4464 */
4465 tcr = rd_reg16(info, TCR);
4466 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4467 /* disable preamble, set idle size to 16 bits */
4468 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4469 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4470 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4471 } else if (!(tcr & BIT6)) {
4472 /* preamble is disabled, set idle size to 8 bits */
4473 tcr &= ~(BIT5 + BIT4);
4474 }
4475 wr_reg16(info, TCR, tcr);
4476
4477 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4478 /* LSB of custom tx idle specified in tx idle register */
4479 val = (unsigned char)(info->idle_mode & 0xff);
4480 } else {
4481 /* standard 8 bit idle patterns */
4482 switch(info->idle_mode)
4483 {
4484 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4485 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4486 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4487 case HDLC_TXIDLE_ZEROS:
4488 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4489 default: val = 0xff;
4490 }
4491 }
4492
4493 wr_reg8(info, TIR, val);
4494}
4495
4496/*
4497 * get state of V24 status (input) signals
4498 */
4499static void get_signals(struct slgt_info *info)
4500{
4501 unsigned short status = rd_reg16(info, SSR);
4502
4503 /* clear all serial signals except RTS and DTR */
4504 info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4505
4506 if (status & BIT3)
4507 info->signals |= SerialSignal_DSR;
4508 if (status & BIT2)
4509 info->signals |= SerialSignal_CTS;
4510 if (status & BIT1)
4511 info->signals |= SerialSignal_DCD;
4512 if (status & BIT0)
4513 info->signals |= SerialSignal_RI;
4514}
4515
4516/*
4517 * set V.24 Control Register based on current configuration
4518 */
4519static void msc_set_vcr(struct slgt_info *info)
4520{
4521 unsigned char val = 0;
4522
4523 /* VCR (V.24 control)
4524 *
4525 * 07..04 serial IF select
4526 * 03 DTR
4527 * 02 RTS
4528 * 01 LL
4529 * 00 RL
4530 */
4531
4532 switch(info->if_mode & MGSL_INTERFACE_MASK)
4533 {
4534 case MGSL_INTERFACE_RS232:
4535 val |= BIT5; /* 0010 */
4536 break;
4537 case MGSL_INTERFACE_V35:
4538 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4539 break;
4540 case MGSL_INTERFACE_RS422:
4541 val |= BIT6; /* 0100 */
4542 break;
4543 }
4544
4545 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4546 val |= BIT4;
4547 if (info->signals & SerialSignal_DTR)
4548 val |= BIT3;
4549 if (info->signals & SerialSignal_RTS)
4550 val |= BIT2;
4551 if (info->if_mode & MGSL_INTERFACE_LL)
4552 val |= BIT1;
4553 if (info->if_mode & MGSL_INTERFACE_RL)
4554 val |= BIT0;
4555 wr_reg8(info, VCR, val);
4556}
4557
4558/*
4559 * set state of V24 control (output) signals
4560 */
4561static void set_signals(struct slgt_info *info)
4562{
4563 unsigned char val = rd_reg8(info, VCR);
4564 if (info->signals & SerialSignal_DTR)
4565 val |= BIT3;
4566 else
4567 val &= ~BIT3;
4568 if (info->signals & SerialSignal_RTS)
4569 val |= BIT2;
4570 else
4571 val &= ~BIT2;
4572 wr_reg8(info, VCR, val);
4573}
4574
4575/*
4576 * free range of receive DMA buffers (i to last)
4577 */
4578static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4579{
4580 int done = 0;
4581
4582 while(!done) {
4583 /* reset current buffer for reuse */
4584 info->rbufs[i].status = 0;
4585 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4586 if (i == last)
4587 done = 1;
4588 if (++i == info->rbuf_count)
4589 i = 0;
4590 }
4591 info->rbuf_current = i;
4592}
4593
4594/*
4595 * mark all receive DMA buffers as free
4596 */
4597static void reset_rbufs(struct slgt_info *info)
4598{
4599 free_rbufs(info, 0, info->rbuf_count - 1);
4600 info->rbuf_fill_index = 0;
4601 info->rbuf_fill_count = 0;
4602}
4603
4604/*
4605 * pass receive HDLC frame to upper layer
4606 *
4607 * return true if frame available, otherwise false
4608 */
4609static bool rx_get_frame(struct slgt_info *info)
4610{
4611 unsigned int start, end;
4612 unsigned short status;
4613 unsigned int framesize = 0;
4614 unsigned long flags;
4615 struct tty_struct *tty = info->port.tty;
4616 unsigned char addr_field = 0xff;
4617 unsigned int crc_size = 0;
4618
4619 switch (info->params.crc_type & HDLC_CRC_MASK) {
4620 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4621 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4622 }
4623
4624check_again:
4625
4626 framesize = 0;
4627 addr_field = 0xff;
4628 start = end = info->rbuf_current;
4629
4630 for (;;) {
4631 if (!desc_complete(info->rbufs[end]))
4632 goto cleanup;
4633
4634 if (framesize == 0 && info->params.addr_filter != 0xff)
4635 addr_field = info->rbufs[end].buf[0];
4636
4637 framesize += desc_count(info->rbufs[end]);
4638
4639 if (desc_eof(info->rbufs[end]))
4640 break;
4641
4642 if (++end == info->rbuf_count)
4643 end = 0;
4644
4645 if (end == info->rbuf_current) {
4646 if (info->rx_enabled){
4647 spin_lock_irqsave(&info->lock,flags);
4648 rx_start(info);
4649 spin_unlock_irqrestore(&info->lock,flags);
4650 }
4651 goto cleanup;
4652 }
4653 }
4654
4655 /* status
4656 *
4657 * 15 buffer complete
4658 * 14..06 reserved
4659 * 05..04 residue
4660 * 02 eof (end of frame)
4661 * 01 CRC error
4662 * 00 abort
4663 */
4664 status = desc_status(info->rbufs[end]);
4665
4666 /* ignore CRC bit if not using CRC (bit is undefined) */
4667 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4668 status &= ~BIT1;
4669
4670 if (framesize == 0 ||
4671 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4672 free_rbufs(info, start, end);
4673 goto check_again;
4674 }
4675
4676 if (framesize < (2 + crc_size) || status & BIT0) {
4677 info->icount.rxshort++;
4678 framesize = 0;
4679 } else if (status & BIT1) {
4680 info->icount.rxcrc++;
4681 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4682 framesize = 0;
4683 }
4684
4685#if SYNCLINK_GENERIC_HDLC
4686 if (framesize == 0) {
4687 info->netdev->stats.rx_errors++;
4688 info->netdev->stats.rx_frame_errors++;
4689 }
4690#endif
4691
4692 DBGBH(("%s rx frame status=%04X size=%d\n",
4693 info->device_name, status, framesize));
4694 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4695
4696 if (framesize) {
4697 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4698 framesize -= crc_size;
4699 crc_size = 0;
4700 }
4701
4702 if (framesize > info->max_frame_size + crc_size)
4703 info->icount.rxlong++;
4704 else {
4705 /* copy dma buffer(s) to contiguous temp buffer */
4706 int copy_count = framesize;
4707 int i = start;
4708 unsigned char *p = info->tmp_rbuf;
4709 info->tmp_rbuf_count = framesize;
4710
4711 info->icount.rxok++;
4712
4713 while(copy_count) {
4714 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4715 memcpy(p, info->rbufs[i].buf, partial_count);
4716 p += partial_count;
4717 copy_count -= partial_count;
4718 if (++i == info->rbuf_count)
4719 i = 0;
4720 }
4721
4722 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4723 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4724 framesize++;
4725 }
4726
4727#if SYNCLINK_GENERIC_HDLC
4728 if (info->netcount)
4729 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4730 else
4731#endif
4732 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4733 }
4734 }
4735 free_rbufs(info, start, end);
4736 return true;
4737
4738cleanup:
4739 return false;
4740}
4741
4742/*
4743 * pass receive buffer (RAW synchronous mode) to tty layer
4744 * return true if buffer available, otherwise false
4745 */
4746static bool rx_get_buf(struct slgt_info *info)
4747{
4748 unsigned int i = info->rbuf_current;
4749 unsigned int count;
4750
4751 if (!desc_complete(info->rbufs[i]))
4752 return false;
4753 count = desc_count(info->rbufs[i]);
4754 switch(info->params.mode) {
4755 case MGSL_MODE_MONOSYNC:
4756 case MGSL_MODE_BISYNC:
4757 case MGSL_MODE_XSYNC:
4758 /* ignore residue in byte synchronous modes */
4759 if (desc_residue(info->rbufs[i]))
4760 count--;
4761 break;
4762 }
4763 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4764 DBGINFO(("rx_get_buf size=%d\n", count));
4765 if (count)
4766 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4767 info->flag_buf, count);
4768 free_rbufs(info, i, i);
4769 return true;
4770}
4771
4772static void reset_tbufs(struct slgt_info *info)
4773{
4774 unsigned int i;
4775 info->tbuf_current = 0;
4776 for (i=0 ; i < info->tbuf_count ; i++) {
4777 info->tbufs[i].status = 0;
4778 info->tbufs[i].count = 0;
4779 }
4780}
4781
4782/*
4783 * return number of free transmit DMA buffers
4784 */
4785static unsigned int free_tbuf_count(struct slgt_info *info)
4786{
4787 unsigned int count = 0;
4788 unsigned int i = info->tbuf_current;
4789
4790 do
4791 {
4792 if (desc_count(info->tbufs[i]))
4793 break; /* buffer in use */
4794 ++count;
4795 if (++i == info->tbuf_count)
4796 i=0;
4797 } while (i != info->tbuf_current);
4798
4799 /* if tx DMA active, last zero count buffer is in use */
4800 if (count && (rd_reg32(info, TDCSR) & BIT0))
4801 --count;
4802
4803 return count;
4804}
4805
4806/*
4807 * return number of bytes in unsent transmit DMA buffers
4808 * and the serial controller tx FIFO
4809 */
4810static unsigned int tbuf_bytes(struct slgt_info *info)
4811{
4812 unsigned int total_count = 0;
4813 unsigned int i = info->tbuf_current;
4814 unsigned int reg_value;
4815 unsigned int count;
4816 unsigned int active_buf_count = 0;
4817
4818 /*
4819 * Add descriptor counts for all tx DMA buffers.
4820 * If count is zero (cleared by DMA controller after read),
4821 * the buffer is complete or is actively being read from.
4822 *
4823 * Record buf_count of last buffer with zero count starting
4824 * from current ring position. buf_count is mirror
4825 * copy of count and is not cleared by serial controller.
4826 * If DMA controller is active, that buffer is actively
4827 * being read so add to total.
4828 */
4829 do {
4830 count = desc_count(info->tbufs[i]);
4831 if (count)
4832 total_count += count;
4833 else if (!total_count)
4834 active_buf_count = info->tbufs[i].buf_count;
4835 if (++i == info->tbuf_count)
4836 i = 0;
4837 } while (i != info->tbuf_current);
4838
4839 /* read tx DMA status register */
4840 reg_value = rd_reg32(info, TDCSR);
4841
4842 /* if tx DMA active, last zero count buffer is in use */
4843 if (reg_value & BIT0)
4844 total_count += active_buf_count;
4845
4846 /* add tx FIFO count = reg_value[15..8] */
4847 total_count += (reg_value >> 8) & 0xff;
4848
4849 /* if transmitter active add one byte for shift register */
4850 if (info->tx_active)
4851 total_count++;
4852
4853 return total_count;
4854}
4855
4856/*
4857 * load data into transmit DMA buffer ring and start transmitter if needed
4858 * return true if data accepted, otherwise false (buffers full)
4859 */
4860static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4861{
4862 unsigned short count;
4863 unsigned int i;
4864 struct slgt_desc *d;
4865
4866 /* check required buffer space */
4867 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4868 return false;
4869
4870 DBGDATA(info, buf, size, "tx");
4871
4872 /*
4873 * copy data to one or more DMA buffers in circular ring
4874 * tbuf_start = first buffer for this data
4875 * tbuf_current = next free buffer
4876 *
4877 * Copy all data before making data visible to DMA controller by
4878 * setting descriptor count of the first buffer.
4879 * This prevents an active DMA controller from reading the first DMA
4880 * buffers of a frame and stopping before the final buffers are filled.
4881 */
4882
4883 info->tbuf_start = i = info->tbuf_current;
4884
4885 while (size) {
4886 d = &info->tbufs[i];
4887
4888 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4889 memcpy(d->buf, buf, count);
4890
4891 size -= count;
4892 buf += count;
4893
4894 /*
4895 * set EOF bit for last buffer of HDLC frame or
4896 * for every buffer in raw mode
4897 */
4898 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4899 info->params.mode == MGSL_MODE_RAW)
4900 set_desc_eof(*d, 1);
4901 else
4902 set_desc_eof(*d, 0);
4903
4904 /* set descriptor count for all but first buffer */
4905 if (i != info->tbuf_start)
4906 set_desc_count(*d, count);
4907 d->buf_count = count;
4908
4909 if (++i == info->tbuf_count)
4910 i = 0;
4911 }
4912
4913 info->tbuf_current = i;
4914
4915 /* set first buffer count to make new data visible to DMA controller */
4916 d = &info->tbufs[info->tbuf_start];
4917 set_desc_count(*d, d->buf_count);
4918
4919 /* start transmitter if needed and update transmit timeout */
4920 if (!info->tx_active)
4921 tx_start(info);
4922 update_tx_timer(info);
4923
4924 return true;
4925}
4926
4927static int register_test(struct slgt_info *info)
4928{
4929 static unsigned short patterns[] =
4930 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4931 static unsigned int count = ARRAY_SIZE(patterns);
4932 unsigned int i;
4933 int rc = 0;
4934
4935 for (i=0 ; i < count ; i++) {
4936 wr_reg16(info, TIR, patterns[i]);
4937 wr_reg16(info, BDR, patterns[(i+1)%count]);
4938 if ((rd_reg16(info, TIR) != patterns[i]) ||
4939 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4940 rc = -ENODEV;
4941 break;
4942 }
4943 }
4944 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4945 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4946 return rc;
4947}
4948
4949static int irq_test(struct slgt_info *info)
4950{
4951 unsigned long timeout;
4952 unsigned long flags;
4953 struct tty_struct *oldtty = info->port.tty;
4954 u32 speed = info->params.data_rate;
4955
4956 info->params.data_rate = 921600;
4957 info->port.tty = NULL;
4958
4959 spin_lock_irqsave(&info->lock, flags);
4960 async_mode(info);
4961 slgt_irq_on(info, IRQ_TXIDLE);
4962
4963 /* enable transmitter */
4964 wr_reg16(info, TCR,
4965 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4966
4967 /* write one byte and wait for tx idle */
4968 wr_reg16(info, TDR, 0);
4969
4970 /* assume failure */
4971 info->init_error = DiagStatus_IrqFailure;
4972 info->irq_occurred = false;
4973
4974 spin_unlock_irqrestore(&info->lock, flags);
4975
4976 timeout=100;
4977 while(timeout-- && !info->irq_occurred)
4978 msleep_interruptible(10);
4979
4980 spin_lock_irqsave(&info->lock,flags);
4981 reset_port(info);
4982 spin_unlock_irqrestore(&info->lock,flags);
4983
4984 info->params.data_rate = speed;
4985 info->port.tty = oldtty;
4986
4987 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4988 return info->irq_occurred ? 0 : -ENODEV;
4989}
4990
4991static int loopback_test_rx(struct slgt_info *info)
4992{
4993 unsigned char *src, *dest;
4994 int count;
4995
4996 if (desc_complete(info->rbufs[0])) {
4997 count = desc_count(info->rbufs[0]);
4998 src = info->rbufs[0].buf;
4999 dest = info->tmp_rbuf;
5000
5001 for( ; count ; count-=2, src+=2) {
5002 /* src=data byte (src+1)=status byte */
5003 if (!(*(src+1) & (BIT9 + BIT8))) {
5004 *dest = *src;
5005 dest++;
5006 info->tmp_rbuf_count++;
5007 }
5008 }
5009 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
5010 return 1;
5011 }
5012 return 0;
5013}
5014
5015static int loopback_test(struct slgt_info *info)
5016{
5017#define TESTFRAMESIZE 20
5018
5019 unsigned long timeout;
5020 u16 count = TESTFRAMESIZE;
5021 unsigned char buf[TESTFRAMESIZE];
5022 int rc = -ENODEV;
5023 unsigned long flags;
5024
5025 struct tty_struct *oldtty = info->port.tty;
5026 MGSL_PARAMS params;
5027
5028 memcpy(¶ms, &info->params, sizeof(params));
5029
5030 info->params.mode = MGSL_MODE_ASYNC;
5031 info->params.data_rate = 921600;
5032 info->params.loopback = 1;
5033 info->port.tty = NULL;
5034
5035 /* build and send transmit frame */
5036 for (count = 0; count < TESTFRAMESIZE; ++count)
5037 buf[count] = (unsigned char)count;
5038
5039 info->tmp_rbuf_count = 0;
5040 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
5041
5042 /* program hardware for HDLC and enabled receiver */
5043 spin_lock_irqsave(&info->lock,flags);
5044 async_mode(info);
5045 rx_start(info);
5046 tx_load(info, buf, count);
5047 spin_unlock_irqrestore(&info->lock, flags);
5048
5049 /* wait for receive complete */
5050 for (timeout = 100; timeout; --timeout) {
5051 msleep_interruptible(10);
5052 if (loopback_test_rx(info)) {
5053 rc = 0;
5054 break;
5055 }
5056 }
5057
5058 /* verify received frame length and contents */
5059 if (!rc && (info->tmp_rbuf_count != count ||
5060 memcmp(buf, info->tmp_rbuf, count))) {
5061 rc = -ENODEV;
5062 }
5063
5064 spin_lock_irqsave(&info->lock,flags);
5065 reset_adapter(info);
5066 spin_unlock_irqrestore(&info->lock,flags);
5067
5068 memcpy(&info->params, ¶ms, sizeof(info->params));
5069 info->port.tty = oldtty;
5070
5071 info->init_error = rc ? DiagStatus_DmaFailure : 0;
5072 return rc;
5073}
5074
5075static int adapter_test(struct slgt_info *info)
5076{
5077 DBGINFO(("testing %s\n", info->device_name));
5078 if (register_test(info) < 0) {
5079 printk("register test failure %s addr=%08X\n",
5080 info->device_name, info->phys_reg_addr);
5081 } else if (irq_test(info) < 0) {
5082 printk("IRQ test failure %s IRQ=%d\n",
5083 info->device_name, info->irq_level);
5084 } else if (loopback_test(info) < 0) {
5085 printk("loopback test failure %s\n", info->device_name);
5086 }
5087 return info->init_error;
5088}
5089
5090/*
5091 * transmit timeout handler
5092 */
5093static void tx_timeout(struct timer_list *t)
5094{
5095 struct slgt_info *info = from_timer(info, t, tx_timer);
5096 unsigned long flags;
5097
5098 DBGINFO(("%s tx_timeout\n", info->device_name));
5099 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5100 info->icount.txtimeout++;
5101 }
5102 spin_lock_irqsave(&info->lock,flags);
5103 tx_stop(info);
5104 spin_unlock_irqrestore(&info->lock,flags);
5105
5106#if SYNCLINK_GENERIC_HDLC
5107 if (info->netcount)
5108 hdlcdev_tx_done(info);
5109 else
5110#endif
5111 bh_transmit(info);
5112}
5113
5114/*
5115 * receive buffer polling timer
5116 */
5117static void rx_timeout(struct timer_list *t)
5118{
5119 struct slgt_info *info = from_timer(info, t, rx_timer);
5120 unsigned long flags;
5121
5122 DBGINFO(("%s rx_timeout\n", info->device_name));
5123 spin_lock_irqsave(&info->lock, flags);
5124 info->pending_bh |= BH_RECEIVE;
5125 spin_unlock_irqrestore(&info->lock, flags);
5126 bh_handler(&info->task);
5127}
5128
1/*
2 * Device driver for Microgate SyncLink GT serial adapters.
3 *
4 * written by Paul Fulghum for Microgate Corporation
5 * paulkf@microgate.com
6 *
7 * Microgate and SyncLink are trademarks of Microgate Corporation
8 *
9 * This code is released under the GNU General Public License (GPL)
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
13 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
14 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
15 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
16 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
17 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
18 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
19 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
20 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
21 * OF THE POSSIBILITY OF SUCH DAMAGE.
22 */
23
24/*
25 * DEBUG OUTPUT DEFINITIONS
26 *
27 * uncomment lines below to enable specific types of debug output
28 *
29 * DBGINFO information - most verbose output
30 * DBGERR serious errors
31 * DBGBH bottom half service routine debugging
32 * DBGISR interrupt service routine debugging
33 * DBGDATA output receive and transmit data
34 * DBGTBUF output transmit DMA buffers and registers
35 * DBGRBUF output receive DMA buffers and registers
36 */
37
38#define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
39#define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
40#define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
41#define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
42#define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
43/*#define DBGTBUF(info) dump_tbufs(info)*/
44/*#define DBGRBUF(info) dump_rbufs(info)*/
45
46
47#include <linux/module.h>
48#include <linux/errno.h>
49#include <linux/signal.h>
50#include <linux/sched.h>
51#include <linux/timer.h>
52#include <linux/interrupt.h>
53#include <linux/pci.h>
54#include <linux/tty.h>
55#include <linux/tty_flip.h>
56#include <linux/serial.h>
57#include <linux/major.h>
58#include <linux/string.h>
59#include <linux/fcntl.h>
60#include <linux/ptrace.h>
61#include <linux/ioport.h>
62#include <linux/mm.h>
63#include <linux/seq_file.h>
64#include <linux/slab.h>
65#include <linux/netdevice.h>
66#include <linux/vmalloc.h>
67#include <linux/init.h>
68#include <linux/delay.h>
69#include <linux/ioctl.h>
70#include <linux/termios.h>
71#include <linux/bitops.h>
72#include <linux/workqueue.h>
73#include <linux/hdlc.h>
74#include <linux/synclink.h>
75
76#include <asm/system.h>
77#include <asm/io.h>
78#include <asm/irq.h>
79#include <asm/dma.h>
80#include <asm/types.h>
81#include <asm/uaccess.h>
82
83#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
84#define SYNCLINK_GENERIC_HDLC 1
85#else
86#define SYNCLINK_GENERIC_HDLC 0
87#endif
88
89/*
90 * module identification
91 */
92static char *driver_name = "SyncLink GT";
93static char *tty_driver_name = "synclink_gt";
94static char *tty_dev_prefix = "ttySLG";
95MODULE_LICENSE("GPL");
96#define MGSL_MAGIC 0x5401
97#define MAX_DEVICES 32
98
99static struct pci_device_id pci_table[] = {
100 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
101 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
102 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
103 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
104 {0,}, /* terminate list */
105};
106MODULE_DEVICE_TABLE(pci, pci_table);
107
108static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
109static void remove_one(struct pci_dev *dev);
110static struct pci_driver pci_driver = {
111 .name = "synclink_gt",
112 .id_table = pci_table,
113 .probe = init_one,
114 .remove = __devexit_p(remove_one),
115};
116
117static bool pci_registered;
118
119/*
120 * module configuration and status
121 */
122static struct slgt_info *slgt_device_list;
123static int slgt_device_count;
124
125static int ttymajor;
126static int debug_level;
127static int maxframe[MAX_DEVICES];
128
129module_param(ttymajor, int, 0);
130module_param(debug_level, int, 0);
131module_param_array(maxframe, int, NULL, 0);
132
133MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
134MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
135MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
136
137/*
138 * tty support and callbacks
139 */
140static struct tty_driver *serial_driver;
141
142static int open(struct tty_struct *tty, struct file * filp);
143static void close(struct tty_struct *tty, struct file * filp);
144static void hangup(struct tty_struct *tty);
145static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
146
147static int write(struct tty_struct *tty, const unsigned char *buf, int count);
148static int put_char(struct tty_struct *tty, unsigned char ch);
149static void send_xchar(struct tty_struct *tty, char ch);
150static void wait_until_sent(struct tty_struct *tty, int timeout);
151static int write_room(struct tty_struct *tty);
152static void flush_chars(struct tty_struct *tty);
153static void flush_buffer(struct tty_struct *tty);
154static void tx_hold(struct tty_struct *tty);
155static void tx_release(struct tty_struct *tty);
156
157static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
158static int chars_in_buffer(struct tty_struct *tty);
159static void throttle(struct tty_struct * tty);
160static void unthrottle(struct tty_struct * tty);
161static int set_break(struct tty_struct *tty, int break_state);
162
163/*
164 * generic HDLC support and callbacks
165 */
166#if SYNCLINK_GENERIC_HDLC
167#define dev_to_port(D) (dev_to_hdlc(D)->priv)
168static void hdlcdev_tx_done(struct slgt_info *info);
169static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
170static int hdlcdev_init(struct slgt_info *info);
171static void hdlcdev_exit(struct slgt_info *info);
172#endif
173
174
175/*
176 * device specific structures, macros and functions
177 */
178
179#define SLGT_MAX_PORTS 4
180#define SLGT_REG_SIZE 256
181
182/*
183 * conditional wait facility
184 */
185struct cond_wait {
186 struct cond_wait *next;
187 wait_queue_head_t q;
188 wait_queue_t wait;
189 unsigned int data;
190};
191static void init_cond_wait(struct cond_wait *w, unsigned int data);
192static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
193static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
194static void flush_cond_wait(struct cond_wait **head);
195
196/*
197 * DMA buffer descriptor and access macros
198 */
199struct slgt_desc
200{
201 __le16 count;
202 __le16 status;
203 __le32 pbuf; /* physical address of data buffer */
204 __le32 next; /* physical address of next descriptor */
205
206 /* driver book keeping */
207 char *buf; /* virtual address of data buffer */
208 unsigned int pdesc; /* physical address of this descriptor */
209 dma_addr_t buf_dma_addr;
210 unsigned short buf_count;
211};
212
213#define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
214#define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
215#define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
216#define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
217#define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
218#define desc_count(a) (le16_to_cpu((a).count))
219#define desc_status(a) (le16_to_cpu((a).status))
220#define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
221#define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
222#define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
223#define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
224#define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
225
226struct _input_signal_events {
227 int ri_up;
228 int ri_down;
229 int dsr_up;
230 int dsr_down;
231 int dcd_up;
232 int dcd_down;
233 int cts_up;
234 int cts_down;
235};
236
237/*
238 * device instance data structure
239 */
240struct slgt_info {
241 void *if_ptr; /* General purpose pointer (used by SPPP) */
242 struct tty_port port;
243
244 struct slgt_info *next_device; /* device list link */
245
246 int magic;
247
248 char device_name[25];
249 struct pci_dev *pdev;
250
251 int port_count; /* count of ports on adapter */
252 int adapter_num; /* adapter instance number */
253 int port_num; /* port instance number */
254
255 /* array of pointers to port contexts on this adapter */
256 struct slgt_info *port_array[SLGT_MAX_PORTS];
257
258 int line; /* tty line instance number */
259
260 struct mgsl_icount icount;
261
262 int timeout;
263 int x_char; /* xon/xoff character */
264 unsigned int read_status_mask;
265 unsigned int ignore_status_mask;
266
267 wait_queue_head_t status_event_wait_q;
268 wait_queue_head_t event_wait_q;
269 struct timer_list tx_timer;
270 struct timer_list rx_timer;
271
272 unsigned int gpio_present;
273 struct cond_wait *gpio_wait_q;
274
275 spinlock_t lock; /* spinlock for synchronizing with ISR */
276
277 struct work_struct task;
278 u32 pending_bh;
279 bool bh_requested;
280 bool bh_running;
281
282 int isr_overflow;
283 bool irq_requested; /* true if IRQ requested */
284 bool irq_occurred; /* for diagnostics use */
285
286 /* device configuration */
287
288 unsigned int bus_type;
289 unsigned int irq_level;
290 unsigned long irq_flags;
291
292 unsigned char __iomem * reg_addr; /* memory mapped registers address */
293 u32 phys_reg_addr;
294 bool reg_addr_requested;
295
296 MGSL_PARAMS params; /* communications parameters */
297 u32 idle_mode;
298 u32 max_frame_size; /* as set by device config */
299
300 unsigned int rbuf_fill_level;
301 unsigned int rx_pio;
302 unsigned int if_mode;
303 unsigned int base_clock;
304 unsigned int xsync;
305 unsigned int xctrl;
306
307 /* device status */
308
309 bool rx_enabled;
310 bool rx_restart;
311
312 bool tx_enabled;
313 bool tx_active;
314
315 unsigned char signals; /* serial signal states */
316 int init_error; /* initialization error */
317
318 unsigned char *tx_buf;
319 int tx_count;
320
321 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
322 char char_buf[MAX_ASYNC_BUFFER_SIZE];
323 bool drop_rts_on_tx_done;
324 struct _input_signal_events input_signal_events;
325
326 int dcd_chkcount; /* check counts to prevent */
327 int cts_chkcount; /* too many IRQs if a signal */
328 int dsr_chkcount; /* is floating */
329 int ri_chkcount;
330
331 char *bufs; /* virtual address of DMA buffer lists */
332 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
333
334 unsigned int rbuf_count;
335 struct slgt_desc *rbufs;
336 unsigned int rbuf_current;
337 unsigned int rbuf_index;
338 unsigned int rbuf_fill_index;
339 unsigned short rbuf_fill_count;
340
341 unsigned int tbuf_count;
342 struct slgt_desc *tbufs;
343 unsigned int tbuf_current;
344 unsigned int tbuf_start;
345
346 unsigned char *tmp_rbuf;
347 unsigned int tmp_rbuf_count;
348
349 /* SPPP/Cisco HDLC device parts */
350
351 int netcount;
352 spinlock_t netlock;
353#if SYNCLINK_GENERIC_HDLC
354 struct net_device *netdev;
355#endif
356
357};
358
359static MGSL_PARAMS default_params = {
360 .mode = MGSL_MODE_HDLC,
361 .loopback = 0,
362 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
363 .encoding = HDLC_ENCODING_NRZI_SPACE,
364 .clock_speed = 0,
365 .addr_filter = 0xff,
366 .crc_type = HDLC_CRC_16_CCITT,
367 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
368 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
369 .data_rate = 9600,
370 .data_bits = 8,
371 .stop_bits = 1,
372 .parity = ASYNC_PARITY_NONE
373};
374
375
376#define BH_RECEIVE 1
377#define BH_TRANSMIT 2
378#define BH_STATUS 4
379#define IO_PIN_SHUTDOWN_LIMIT 100
380
381#define DMABUFSIZE 256
382#define DESC_LIST_SIZE 4096
383
384#define MASK_PARITY BIT1
385#define MASK_FRAMING BIT0
386#define MASK_BREAK BIT14
387#define MASK_OVERRUN BIT4
388
389#define GSR 0x00 /* global status */
390#define JCR 0x04 /* JTAG control */
391#define IODR 0x08 /* GPIO direction */
392#define IOER 0x0c /* GPIO interrupt enable */
393#define IOVR 0x10 /* GPIO value */
394#define IOSR 0x14 /* GPIO interrupt status */
395#define TDR 0x80 /* tx data */
396#define RDR 0x80 /* rx data */
397#define TCR 0x82 /* tx control */
398#define TIR 0x84 /* tx idle */
399#define TPR 0x85 /* tx preamble */
400#define RCR 0x86 /* rx control */
401#define VCR 0x88 /* V.24 control */
402#define CCR 0x89 /* clock control */
403#define BDR 0x8a /* baud divisor */
404#define SCR 0x8c /* serial control */
405#define SSR 0x8e /* serial status */
406#define RDCSR 0x90 /* rx DMA control/status */
407#define TDCSR 0x94 /* tx DMA control/status */
408#define RDDAR 0x98 /* rx DMA descriptor address */
409#define TDDAR 0x9c /* tx DMA descriptor address */
410#define XSR 0x40 /* extended sync pattern */
411#define XCR 0x44 /* extended control */
412
413#define RXIDLE BIT14
414#define RXBREAK BIT14
415#define IRQ_TXDATA BIT13
416#define IRQ_TXIDLE BIT12
417#define IRQ_TXUNDER BIT11 /* HDLC */
418#define IRQ_RXDATA BIT10
419#define IRQ_RXIDLE BIT9 /* HDLC */
420#define IRQ_RXBREAK BIT9 /* async */
421#define IRQ_RXOVER BIT8
422#define IRQ_DSR BIT7
423#define IRQ_CTS BIT6
424#define IRQ_DCD BIT5
425#define IRQ_RI BIT4
426#define IRQ_ALL 0x3ff0
427#define IRQ_MASTER BIT0
428
429#define slgt_irq_on(info, mask) \
430 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
431#define slgt_irq_off(info, mask) \
432 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
433
434static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
435static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
436static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
437static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
438static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
439static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
440
441static void msc_set_vcr(struct slgt_info *info);
442
443static int startup(struct slgt_info *info);
444static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
445static void shutdown(struct slgt_info *info);
446static void program_hw(struct slgt_info *info);
447static void change_params(struct slgt_info *info);
448
449static int register_test(struct slgt_info *info);
450static int irq_test(struct slgt_info *info);
451static int loopback_test(struct slgt_info *info);
452static int adapter_test(struct slgt_info *info);
453
454static void reset_adapter(struct slgt_info *info);
455static void reset_port(struct slgt_info *info);
456static void async_mode(struct slgt_info *info);
457static void sync_mode(struct slgt_info *info);
458
459static void rx_stop(struct slgt_info *info);
460static void rx_start(struct slgt_info *info);
461static void reset_rbufs(struct slgt_info *info);
462static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
463static void rdma_reset(struct slgt_info *info);
464static bool rx_get_frame(struct slgt_info *info);
465static bool rx_get_buf(struct slgt_info *info);
466
467static void tx_start(struct slgt_info *info);
468static void tx_stop(struct slgt_info *info);
469static void tx_set_idle(struct slgt_info *info);
470static unsigned int free_tbuf_count(struct slgt_info *info);
471static unsigned int tbuf_bytes(struct slgt_info *info);
472static void reset_tbufs(struct slgt_info *info);
473static void tdma_reset(struct slgt_info *info);
474static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
475
476static void get_signals(struct slgt_info *info);
477static void set_signals(struct slgt_info *info);
478static void enable_loopback(struct slgt_info *info);
479static void set_rate(struct slgt_info *info, u32 data_rate);
480
481static int bh_action(struct slgt_info *info);
482static void bh_handler(struct work_struct *work);
483static void bh_transmit(struct slgt_info *info);
484static void isr_serial(struct slgt_info *info);
485static void isr_rdma(struct slgt_info *info);
486static void isr_txeom(struct slgt_info *info, unsigned short status);
487static void isr_tdma(struct slgt_info *info);
488
489static int alloc_dma_bufs(struct slgt_info *info);
490static void free_dma_bufs(struct slgt_info *info);
491static int alloc_desc(struct slgt_info *info);
492static void free_desc(struct slgt_info *info);
493static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
494static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
495
496static int alloc_tmp_rbuf(struct slgt_info *info);
497static void free_tmp_rbuf(struct slgt_info *info);
498
499static void tx_timeout(unsigned long context);
500static void rx_timeout(unsigned long context);
501
502/*
503 * ioctl handlers
504 */
505static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
506static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
507static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
508static int get_txidle(struct slgt_info *info, int __user *idle_mode);
509static int set_txidle(struct slgt_info *info, int idle_mode);
510static int tx_enable(struct slgt_info *info, int enable);
511static int tx_abort(struct slgt_info *info);
512static int rx_enable(struct slgt_info *info, int enable);
513static int modem_input_wait(struct slgt_info *info,int arg);
514static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
515static int tiocmget(struct tty_struct *tty);
516static int tiocmset(struct tty_struct *tty,
517 unsigned int set, unsigned int clear);
518static int set_break(struct tty_struct *tty, int break_state);
519static int get_interface(struct slgt_info *info, int __user *if_mode);
520static int set_interface(struct slgt_info *info, int if_mode);
521static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
522static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
523static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
524static int get_xsync(struct slgt_info *info, int __user *if_mode);
525static int set_xsync(struct slgt_info *info, int if_mode);
526static int get_xctrl(struct slgt_info *info, int __user *if_mode);
527static int set_xctrl(struct slgt_info *info, int if_mode);
528
529/*
530 * driver functions
531 */
532static void add_device(struct slgt_info *info);
533static void device_init(int adapter_num, struct pci_dev *pdev);
534static int claim_resources(struct slgt_info *info);
535static void release_resources(struct slgt_info *info);
536
537/*
538 * DEBUG OUTPUT CODE
539 */
540#ifndef DBGINFO
541#define DBGINFO(fmt)
542#endif
543#ifndef DBGERR
544#define DBGERR(fmt)
545#endif
546#ifndef DBGBH
547#define DBGBH(fmt)
548#endif
549#ifndef DBGISR
550#define DBGISR(fmt)
551#endif
552
553#ifdef DBGDATA
554static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
555{
556 int i;
557 int linecount;
558 printk("%s %s data:\n",info->device_name, label);
559 while(count) {
560 linecount = (count > 16) ? 16 : count;
561 for(i=0; i < linecount; i++)
562 printk("%02X ",(unsigned char)data[i]);
563 for(;i<17;i++)
564 printk(" ");
565 for(i=0;i<linecount;i++) {
566 if (data[i]>=040 && data[i]<=0176)
567 printk("%c",data[i]);
568 else
569 printk(".");
570 }
571 printk("\n");
572 data += linecount;
573 count -= linecount;
574 }
575}
576#else
577#define DBGDATA(info, buf, size, label)
578#endif
579
580#ifdef DBGTBUF
581static void dump_tbufs(struct slgt_info *info)
582{
583 int i;
584 printk("tbuf_current=%d\n", info->tbuf_current);
585 for (i=0 ; i < info->tbuf_count ; i++) {
586 printk("%d: count=%04X status=%04X\n",
587 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
588 }
589}
590#else
591#define DBGTBUF(info)
592#endif
593
594#ifdef DBGRBUF
595static void dump_rbufs(struct slgt_info *info)
596{
597 int i;
598 printk("rbuf_current=%d\n", info->rbuf_current);
599 for (i=0 ; i < info->rbuf_count ; i++) {
600 printk("%d: count=%04X status=%04X\n",
601 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
602 }
603}
604#else
605#define DBGRBUF(info)
606#endif
607
608static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
609{
610#ifdef SANITY_CHECK
611 if (!info) {
612 printk("null struct slgt_info for (%s) in %s\n", devname, name);
613 return 1;
614 }
615 if (info->magic != MGSL_MAGIC) {
616 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
617 return 1;
618 }
619#else
620 if (!info)
621 return 1;
622#endif
623 return 0;
624}
625
626/**
627 * line discipline callback wrappers
628 *
629 * The wrappers maintain line discipline references
630 * while calling into the line discipline.
631 *
632 * ldisc_receive_buf - pass receive data to line discipline
633 */
634static void ldisc_receive_buf(struct tty_struct *tty,
635 const __u8 *data, char *flags, int count)
636{
637 struct tty_ldisc *ld;
638 if (!tty)
639 return;
640 ld = tty_ldisc_ref(tty);
641 if (ld) {
642 if (ld->ops->receive_buf)
643 ld->ops->receive_buf(tty, data, flags, count);
644 tty_ldisc_deref(ld);
645 }
646}
647
648/* tty callbacks */
649
650static int open(struct tty_struct *tty, struct file *filp)
651{
652 struct slgt_info *info;
653 int retval, line;
654 unsigned long flags;
655
656 line = tty->index;
657 if ((line < 0) || (line >= slgt_device_count)) {
658 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
659 return -ENODEV;
660 }
661
662 info = slgt_device_list;
663 while(info && info->line != line)
664 info = info->next_device;
665 if (sanity_check(info, tty->name, "open"))
666 return -ENODEV;
667 if (info->init_error) {
668 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
669 return -ENODEV;
670 }
671
672 tty->driver_data = info;
673 info->port.tty = tty;
674
675 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
676
677 /* If port is closing, signal caller to try again */
678 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
679 if (info->port.flags & ASYNC_CLOSING)
680 interruptible_sleep_on(&info->port.close_wait);
681 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
682 -EAGAIN : -ERESTARTSYS);
683 goto cleanup;
684 }
685
686 mutex_lock(&info->port.mutex);
687 info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
688
689 spin_lock_irqsave(&info->netlock, flags);
690 if (info->netcount) {
691 retval = -EBUSY;
692 spin_unlock_irqrestore(&info->netlock, flags);
693 mutex_unlock(&info->port.mutex);
694 goto cleanup;
695 }
696 info->port.count++;
697 spin_unlock_irqrestore(&info->netlock, flags);
698
699 if (info->port.count == 1) {
700 /* 1st open on this device, init hardware */
701 retval = startup(info);
702 if (retval < 0) {
703 mutex_unlock(&info->port.mutex);
704 goto cleanup;
705 }
706 }
707 mutex_unlock(&info->port.mutex);
708 retval = block_til_ready(tty, filp, info);
709 if (retval) {
710 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
711 goto cleanup;
712 }
713
714 retval = 0;
715
716cleanup:
717 if (retval) {
718 if (tty->count == 1)
719 info->port.tty = NULL; /* tty layer will release tty struct */
720 if(info->port.count)
721 info->port.count--;
722 }
723
724 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
725 return retval;
726}
727
728static void close(struct tty_struct *tty, struct file *filp)
729{
730 struct slgt_info *info = tty->driver_data;
731
732 if (sanity_check(info, tty->name, "close"))
733 return;
734 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
735
736 if (tty_port_close_start(&info->port, tty, filp) == 0)
737 goto cleanup;
738
739 mutex_lock(&info->port.mutex);
740 if (info->port.flags & ASYNC_INITIALIZED)
741 wait_until_sent(tty, info->timeout);
742 flush_buffer(tty);
743 tty_ldisc_flush(tty);
744
745 shutdown(info);
746 mutex_unlock(&info->port.mutex);
747
748 tty_port_close_end(&info->port, tty);
749 info->port.tty = NULL;
750cleanup:
751 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
752}
753
754static void hangup(struct tty_struct *tty)
755{
756 struct slgt_info *info = tty->driver_data;
757 unsigned long flags;
758
759 if (sanity_check(info, tty->name, "hangup"))
760 return;
761 DBGINFO(("%s hangup\n", info->device_name));
762
763 flush_buffer(tty);
764
765 mutex_lock(&info->port.mutex);
766 shutdown(info);
767
768 spin_lock_irqsave(&info->port.lock, flags);
769 info->port.count = 0;
770 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
771 info->port.tty = NULL;
772 spin_unlock_irqrestore(&info->port.lock, flags);
773 mutex_unlock(&info->port.mutex);
774
775 wake_up_interruptible(&info->port.open_wait);
776}
777
778static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
779{
780 struct slgt_info *info = tty->driver_data;
781 unsigned long flags;
782
783 DBGINFO(("%s set_termios\n", tty->driver->name));
784
785 change_params(info);
786
787 /* Handle transition to B0 status */
788 if (old_termios->c_cflag & CBAUD &&
789 !(tty->termios->c_cflag & CBAUD)) {
790 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
791 spin_lock_irqsave(&info->lock,flags);
792 set_signals(info);
793 spin_unlock_irqrestore(&info->lock,flags);
794 }
795
796 /* Handle transition away from B0 status */
797 if (!(old_termios->c_cflag & CBAUD) &&
798 tty->termios->c_cflag & CBAUD) {
799 info->signals |= SerialSignal_DTR;
800 if (!(tty->termios->c_cflag & CRTSCTS) ||
801 !test_bit(TTY_THROTTLED, &tty->flags)) {
802 info->signals |= SerialSignal_RTS;
803 }
804 spin_lock_irqsave(&info->lock,flags);
805 set_signals(info);
806 spin_unlock_irqrestore(&info->lock,flags);
807 }
808
809 /* Handle turning off CRTSCTS */
810 if (old_termios->c_cflag & CRTSCTS &&
811 !(tty->termios->c_cflag & CRTSCTS)) {
812 tty->hw_stopped = 0;
813 tx_release(tty);
814 }
815}
816
817static void update_tx_timer(struct slgt_info *info)
818{
819 /*
820 * use worst case speed of 1200bps to calculate transmit timeout
821 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
822 */
823 if (info->params.mode == MGSL_MODE_HDLC) {
824 int timeout = (tbuf_bytes(info) * 7) + 1000;
825 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
826 }
827}
828
829static int write(struct tty_struct *tty,
830 const unsigned char *buf, int count)
831{
832 int ret = 0;
833 struct slgt_info *info = tty->driver_data;
834 unsigned long flags;
835
836 if (sanity_check(info, tty->name, "write"))
837 return -EIO;
838
839 DBGINFO(("%s write count=%d\n", info->device_name, count));
840
841 if (!info->tx_buf || (count > info->max_frame_size))
842 return -EIO;
843
844 if (!count || tty->stopped || tty->hw_stopped)
845 return 0;
846
847 spin_lock_irqsave(&info->lock, flags);
848
849 if (info->tx_count) {
850 /* send accumulated data from send_char() */
851 if (!tx_load(info, info->tx_buf, info->tx_count))
852 goto cleanup;
853 info->tx_count = 0;
854 }
855
856 if (tx_load(info, buf, count))
857 ret = count;
858
859cleanup:
860 spin_unlock_irqrestore(&info->lock, flags);
861 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
862 return ret;
863}
864
865static int put_char(struct tty_struct *tty, unsigned char ch)
866{
867 struct slgt_info *info = tty->driver_data;
868 unsigned long flags;
869 int ret = 0;
870
871 if (sanity_check(info, tty->name, "put_char"))
872 return 0;
873 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
874 if (!info->tx_buf)
875 return 0;
876 spin_lock_irqsave(&info->lock,flags);
877 if (info->tx_count < info->max_frame_size) {
878 info->tx_buf[info->tx_count++] = ch;
879 ret = 1;
880 }
881 spin_unlock_irqrestore(&info->lock,flags);
882 return ret;
883}
884
885static void send_xchar(struct tty_struct *tty, char ch)
886{
887 struct slgt_info *info = tty->driver_data;
888 unsigned long flags;
889
890 if (sanity_check(info, tty->name, "send_xchar"))
891 return;
892 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
893 info->x_char = ch;
894 if (ch) {
895 spin_lock_irqsave(&info->lock,flags);
896 if (!info->tx_enabled)
897 tx_start(info);
898 spin_unlock_irqrestore(&info->lock,flags);
899 }
900}
901
902static void wait_until_sent(struct tty_struct *tty, int timeout)
903{
904 struct slgt_info *info = tty->driver_data;
905 unsigned long orig_jiffies, char_time;
906
907 if (!info )
908 return;
909 if (sanity_check(info, tty->name, "wait_until_sent"))
910 return;
911 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
912 if (!(info->port.flags & ASYNC_INITIALIZED))
913 goto exit;
914
915 orig_jiffies = jiffies;
916
917 /* Set check interval to 1/5 of estimated time to
918 * send a character, and make it at least 1. The check
919 * interval should also be less than the timeout.
920 * Note: use tight timings here to satisfy the NIST-PCTS.
921 */
922
923 if (info->params.data_rate) {
924 char_time = info->timeout/(32 * 5);
925 if (!char_time)
926 char_time++;
927 } else
928 char_time = 1;
929
930 if (timeout)
931 char_time = min_t(unsigned long, char_time, timeout);
932
933 while (info->tx_active) {
934 msleep_interruptible(jiffies_to_msecs(char_time));
935 if (signal_pending(current))
936 break;
937 if (timeout && time_after(jiffies, orig_jiffies + timeout))
938 break;
939 }
940exit:
941 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
942}
943
944static int write_room(struct tty_struct *tty)
945{
946 struct slgt_info *info = tty->driver_data;
947 int ret;
948
949 if (sanity_check(info, tty->name, "write_room"))
950 return 0;
951 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
952 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
953 return ret;
954}
955
956static void flush_chars(struct tty_struct *tty)
957{
958 struct slgt_info *info = tty->driver_data;
959 unsigned long flags;
960
961 if (sanity_check(info, tty->name, "flush_chars"))
962 return;
963 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
964
965 if (info->tx_count <= 0 || tty->stopped ||
966 tty->hw_stopped || !info->tx_buf)
967 return;
968
969 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
970
971 spin_lock_irqsave(&info->lock,flags);
972 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
973 info->tx_count = 0;
974 spin_unlock_irqrestore(&info->lock,flags);
975}
976
977static void flush_buffer(struct tty_struct *tty)
978{
979 struct slgt_info *info = tty->driver_data;
980 unsigned long flags;
981
982 if (sanity_check(info, tty->name, "flush_buffer"))
983 return;
984 DBGINFO(("%s flush_buffer\n", info->device_name));
985
986 spin_lock_irqsave(&info->lock, flags);
987 info->tx_count = 0;
988 spin_unlock_irqrestore(&info->lock, flags);
989
990 tty_wakeup(tty);
991}
992
993/*
994 * throttle (stop) transmitter
995 */
996static void tx_hold(struct tty_struct *tty)
997{
998 struct slgt_info *info = tty->driver_data;
999 unsigned long flags;
1000
1001 if (sanity_check(info, tty->name, "tx_hold"))
1002 return;
1003 DBGINFO(("%s tx_hold\n", info->device_name));
1004 spin_lock_irqsave(&info->lock,flags);
1005 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1006 tx_stop(info);
1007 spin_unlock_irqrestore(&info->lock,flags);
1008}
1009
1010/*
1011 * release (start) transmitter
1012 */
1013static void tx_release(struct tty_struct *tty)
1014{
1015 struct slgt_info *info = tty->driver_data;
1016 unsigned long flags;
1017
1018 if (sanity_check(info, tty->name, "tx_release"))
1019 return;
1020 DBGINFO(("%s tx_release\n", info->device_name));
1021 spin_lock_irqsave(&info->lock, flags);
1022 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
1023 info->tx_count = 0;
1024 spin_unlock_irqrestore(&info->lock, flags);
1025}
1026
1027/*
1028 * Service an IOCTL request
1029 *
1030 * Arguments
1031 *
1032 * tty pointer to tty instance data
1033 * cmd IOCTL command code
1034 * arg command argument/context
1035 *
1036 * Return 0 if success, otherwise error code
1037 */
1038static int ioctl(struct tty_struct *tty,
1039 unsigned int cmd, unsigned long arg)
1040{
1041 struct slgt_info *info = tty->driver_data;
1042 void __user *argp = (void __user *)arg;
1043 int ret;
1044
1045 if (sanity_check(info, tty->name, "ioctl"))
1046 return -ENODEV;
1047 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1048
1049 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1050 (cmd != TIOCMIWAIT)) {
1051 if (tty->flags & (1 << TTY_IO_ERROR))
1052 return -EIO;
1053 }
1054
1055 switch (cmd) {
1056 case MGSL_IOCWAITEVENT:
1057 return wait_mgsl_event(info, argp);
1058 case TIOCMIWAIT:
1059 return modem_input_wait(info,(int)arg);
1060 case MGSL_IOCSGPIO:
1061 return set_gpio(info, argp);
1062 case MGSL_IOCGGPIO:
1063 return get_gpio(info, argp);
1064 case MGSL_IOCWAITGPIO:
1065 return wait_gpio(info, argp);
1066 case MGSL_IOCGXSYNC:
1067 return get_xsync(info, argp);
1068 case MGSL_IOCSXSYNC:
1069 return set_xsync(info, (int)arg);
1070 case MGSL_IOCGXCTRL:
1071 return get_xctrl(info, argp);
1072 case MGSL_IOCSXCTRL:
1073 return set_xctrl(info, (int)arg);
1074 }
1075 mutex_lock(&info->port.mutex);
1076 switch (cmd) {
1077 case MGSL_IOCGPARAMS:
1078 ret = get_params(info, argp);
1079 break;
1080 case MGSL_IOCSPARAMS:
1081 ret = set_params(info, argp);
1082 break;
1083 case MGSL_IOCGTXIDLE:
1084 ret = get_txidle(info, argp);
1085 break;
1086 case MGSL_IOCSTXIDLE:
1087 ret = set_txidle(info, (int)arg);
1088 break;
1089 case MGSL_IOCTXENABLE:
1090 ret = tx_enable(info, (int)arg);
1091 break;
1092 case MGSL_IOCRXENABLE:
1093 ret = rx_enable(info, (int)arg);
1094 break;
1095 case MGSL_IOCTXABORT:
1096 ret = tx_abort(info);
1097 break;
1098 case MGSL_IOCGSTATS:
1099 ret = get_stats(info, argp);
1100 break;
1101 case MGSL_IOCGIF:
1102 ret = get_interface(info, argp);
1103 break;
1104 case MGSL_IOCSIF:
1105 ret = set_interface(info,(int)arg);
1106 break;
1107 default:
1108 ret = -ENOIOCTLCMD;
1109 }
1110 mutex_unlock(&info->port.mutex);
1111 return ret;
1112}
1113
1114static int get_icount(struct tty_struct *tty,
1115 struct serial_icounter_struct *icount)
1116
1117{
1118 struct slgt_info *info = tty->driver_data;
1119 struct mgsl_icount cnow; /* kernel counter temps */
1120 unsigned long flags;
1121
1122 spin_lock_irqsave(&info->lock,flags);
1123 cnow = info->icount;
1124 spin_unlock_irqrestore(&info->lock,flags);
1125
1126 icount->cts = cnow.cts;
1127 icount->dsr = cnow.dsr;
1128 icount->rng = cnow.rng;
1129 icount->dcd = cnow.dcd;
1130 icount->rx = cnow.rx;
1131 icount->tx = cnow.tx;
1132 icount->frame = cnow.frame;
1133 icount->overrun = cnow.overrun;
1134 icount->parity = cnow.parity;
1135 icount->brk = cnow.brk;
1136 icount->buf_overrun = cnow.buf_overrun;
1137
1138 return 0;
1139}
1140
1141/*
1142 * support for 32 bit ioctl calls on 64 bit systems
1143 */
1144#ifdef CONFIG_COMPAT
1145static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1146{
1147 struct MGSL_PARAMS32 tmp_params;
1148
1149 DBGINFO(("%s get_params32\n", info->device_name));
1150 memset(&tmp_params, 0, sizeof(tmp_params));
1151 tmp_params.mode = (compat_ulong_t)info->params.mode;
1152 tmp_params.loopback = info->params.loopback;
1153 tmp_params.flags = info->params.flags;
1154 tmp_params.encoding = info->params.encoding;
1155 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1156 tmp_params.addr_filter = info->params.addr_filter;
1157 tmp_params.crc_type = info->params.crc_type;
1158 tmp_params.preamble_length = info->params.preamble_length;
1159 tmp_params.preamble = info->params.preamble;
1160 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1161 tmp_params.data_bits = info->params.data_bits;
1162 tmp_params.stop_bits = info->params.stop_bits;
1163 tmp_params.parity = info->params.parity;
1164 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1165 return -EFAULT;
1166 return 0;
1167}
1168
1169static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1170{
1171 struct MGSL_PARAMS32 tmp_params;
1172
1173 DBGINFO(("%s set_params32\n", info->device_name));
1174 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1175 return -EFAULT;
1176
1177 spin_lock(&info->lock);
1178 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1179 info->base_clock = tmp_params.clock_speed;
1180 } else {
1181 info->params.mode = tmp_params.mode;
1182 info->params.loopback = tmp_params.loopback;
1183 info->params.flags = tmp_params.flags;
1184 info->params.encoding = tmp_params.encoding;
1185 info->params.clock_speed = tmp_params.clock_speed;
1186 info->params.addr_filter = tmp_params.addr_filter;
1187 info->params.crc_type = tmp_params.crc_type;
1188 info->params.preamble_length = tmp_params.preamble_length;
1189 info->params.preamble = tmp_params.preamble;
1190 info->params.data_rate = tmp_params.data_rate;
1191 info->params.data_bits = tmp_params.data_bits;
1192 info->params.stop_bits = tmp_params.stop_bits;
1193 info->params.parity = tmp_params.parity;
1194 }
1195 spin_unlock(&info->lock);
1196
1197 program_hw(info);
1198
1199 return 0;
1200}
1201
1202static long slgt_compat_ioctl(struct tty_struct *tty,
1203 unsigned int cmd, unsigned long arg)
1204{
1205 struct slgt_info *info = tty->driver_data;
1206 int rc = -ENOIOCTLCMD;
1207
1208 if (sanity_check(info, tty->name, "compat_ioctl"))
1209 return -ENODEV;
1210 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1211
1212 switch (cmd) {
1213
1214 case MGSL_IOCSPARAMS32:
1215 rc = set_params32(info, compat_ptr(arg));
1216 break;
1217
1218 case MGSL_IOCGPARAMS32:
1219 rc = get_params32(info, compat_ptr(arg));
1220 break;
1221
1222 case MGSL_IOCGPARAMS:
1223 case MGSL_IOCSPARAMS:
1224 case MGSL_IOCGTXIDLE:
1225 case MGSL_IOCGSTATS:
1226 case MGSL_IOCWAITEVENT:
1227 case MGSL_IOCGIF:
1228 case MGSL_IOCSGPIO:
1229 case MGSL_IOCGGPIO:
1230 case MGSL_IOCWAITGPIO:
1231 case MGSL_IOCGXSYNC:
1232 case MGSL_IOCGXCTRL:
1233 case MGSL_IOCSTXIDLE:
1234 case MGSL_IOCTXENABLE:
1235 case MGSL_IOCRXENABLE:
1236 case MGSL_IOCTXABORT:
1237 case TIOCMIWAIT:
1238 case MGSL_IOCSIF:
1239 case MGSL_IOCSXSYNC:
1240 case MGSL_IOCSXCTRL:
1241 rc = ioctl(tty, cmd, arg);
1242 break;
1243 }
1244
1245 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1246 return rc;
1247}
1248#else
1249#define slgt_compat_ioctl NULL
1250#endif /* ifdef CONFIG_COMPAT */
1251
1252/*
1253 * proc fs support
1254 */
1255static inline void line_info(struct seq_file *m, struct slgt_info *info)
1256{
1257 char stat_buf[30];
1258 unsigned long flags;
1259
1260 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1261 info->device_name, info->phys_reg_addr,
1262 info->irq_level, info->max_frame_size);
1263
1264 /* output current serial signal states */
1265 spin_lock_irqsave(&info->lock,flags);
1266 get_signals(info);
1267 spin_unlock_irqrestore(&info->lock,flags);
1268
1269 stat_buf[0] = 0;
1270 stat_buf[1] = 0;
1271 if (info->signals & SerialSignal_RTS)
1272 strcat(stat_buf, "|RTS");
1273 if (info->signals & SerialSignal_CTS)
1274 strcat(stat_buf, "|CTS");
1275 if (info->signals & SerialSignal_DTR)
1276 strcat(stat_buf, "|DTR");
1277 if (info->signals & SerialSignal_DSR)
1278 strcat(stat_buf, "|DSR");
1279 if (info->signals & SerialSignal_DCD)
1280 strcat(stat_buf, "|CD");
1281 if (info->signals & SerialSignal_RI)
1282 strcat(stat_buf, "|RI");
1283
1284 if (info->params.mode != MGSL_MODE_ASYNC) {
1285 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1286 info->icount.txok, info->icount.rxok);
1287 if (info->icount.txunder)
1288 seq_printf(m, " txunder:%d", info->icount.txunder);
1289 if (info->icount.txabort)
1290 seq_printf(m, " txabort:%d", info->icount.txabort);
1291 if (info->icount.rxshort)
1292 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1293 if (info->icount.rxlong)
1294 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1295 if (info->icount.rxover)
1296 seq_printf(m, " rxover:%d", info->icount.rxover);
1297 if (info->icount.rxcrc)
1298 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1299 } else {
1300 seq_printf(m, "\tASYNC tx:%d rx:%d",
1301 info->icount.tx, info->icount.rx);
1302 if (info->icount.frame)
1303 seq_printf(m, " fe:%d", info->icount.frame);
1304 if (info->icount.parity)
1305 seq_printf(m, " pe:%d", info->icount.parity);
1306 if (info->icount.brk)
1307 seq_printf(m, " brk:%d", info->icount.brk);
1308 if (info->icount.overrun)
1309 seq_printf(m, " oe:%d", info->icount.overrun);
1310 }
1311
1312 /* Append serial signal status to end */
1313 seq_printf(m, " %s\n", stat_buf+1);
1314
1315 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1316 info->tx_active,info->bh_requested,info->bh_running,
1317 info->pending_bh);
1318}
1319
1320/* Called to print information about devices
1321 */
1322static int synclink_gt_proc_show(struct seq_file *m, void *v)
1323{
1324 struct slgt_info *info;
1325
1326 seq_puts(m, "synclink_gt driver\n");
1327
1328 info = slgt_device_list;
1329 while( info ) {
1330 line_info(m, info);
1331 info = info->next_device;
1332 }
1333 return 0;
1334}
1335
1336static int synclink_gt_proc_open(struct inode *inode, struct file *file)
1337{
1338 return single_open(file, synclink_gt_proc_show, NULL);
1339}
1340
1341static const struct file_operations synclink_gt_proc_fops = {
1342 .owner = THIS_MODULE,
1343 .open = synclink_gt_proc_open,
1344 .read = seq_read,
1345 .llseek = seq_lseek,
1346 .release = single_release,
1347};
1348
1349/*
1350 * return count of bytes in transmit buffer
1351 */
1352static int chars_in_buffer(struct tty_struct *tty)
1353{
1354 struct slgt_info *info = tty->driver_data;
1355 int count;
1356 if (sanity_check(info, tty->name, "chars_in_buffer"))
1357 return 0;
1358 count = tbuf_bytes(info);
1359 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1360 return count;
1361}
1362
1363/*
1364 * signal remote device to throttle send data (our receive data)
1365 */
1366static void throttle(struct tty_struct * tty)
1367{
1368 struct slgt_info *info = tty->driver_data;
1369 unsigned long flags;
1370
1371 if (sanity_check(info, tty->name, "throttle"))
1372 return;
1373 DBGINFO(("%s throttle\n", info->device_name));
1374 if (I_IXOFF(tty))
1375 send_xchar(tty, STOP_CHAR(tty));
1376 if (tty->termios->c_cflag & CRTSCTS) {
1377 spin_lock_irqsave(&info->lock,flags);
1378 info->signals &= ~SerialSignal_RTS;
1379 set_signals(info);
1380 spin_unlock_irqrestore(&info->lock,flags);
1381 }
1382}
1383
1384/*
1385 * signal remote device to stop throttling send data (our receive data)
1386 */
1387static void unthrottle(struct tty_struct * tty)
1388{
1389 struct slgt_info *info = tty->driver_data;
1390 unsigned long flags;
1391
1392 if (sanity_check(info, tty->name, "unthrottle"))
1393 return;
1394 DBGINFO(("%s unthrottle\n", info->device_name));
1395 if (I_IXOFF(tty)) {
1396 if (info->x_char)
1397 info->x_char = 0;
1398 else
1399 send_xchar(tty, START_CHAR(tty));
1400 }
1401 if (tty->termios->c_cflag & CRTSCTS) {
1402 spin_lock_irqsave(&info->lock,flags);
1403 info->signals |= SerialSignal_RTS;
1404 set_signals(info);
1405 spin_unlock_irqrestore(&info->lock,flags);
1406 }
1407}
1408
1409/*
1410 * set or clear transmit break condition
1411 * break_state -1=set break condition, 0=clear
1412 */
1413static int set_break(struct tty_struct *tty, int break_state)
1414{
1415 struct slgt_info *info = tty->driver_data;
1416 unsigned short value;
1417 unsigned long flags;
1418
1419 if (sanity_check(info, tty->name, "set_break"))
1420 return -EINVAL;
1421 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1422
1423 spin_lock_irqsave(&info->lock,flags);
1424 value = rd_reg16(info, TCR);
1425 if (break_state == -1)
1426 value |= BIT6;
1427 else
1428 value &= ~BIT6;
1429 wr_reg16(info, TCR, value);
1430 spin_unlock_irqrestore(&info->lock,flags);
1431 return 0;
1432}
1433
1434#if SYNCLINK_GENERIC_HDLC
1435
1436/**
1437 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1438 * set encoding and frame check sequence (FCS) options
1439 *
1440 * dev pointer to network device structure
1441 * encoding serial encoding setting
1442 * parity FCS setting
1443 *
1444 * returns 0 if success, otherwise error code
1445 */
1446static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1447 unsigned short parity)
1448{
1449 struct slgt_info *info = dev_to_port(dev);
1450 unsigned char new_encoding;
1451 unsigned short new_crctype;
1452
1453 /* return error if TTY interface open */
1454 if (info->port.count)
1455 return -EBUSY;
1456
1457 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1458
1459 switch (encoding)
1460 {
1461 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1462 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1463 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1464 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1465 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1466 default: return -EINVAL;
1467 }
1468
1469 switch (parity)
1470 {
1471 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1472 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1473 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1474 default: return -EINVAL;
1475 }
1476
1477 info->params.encoding = new_encoding;
1478 info->params.crc_type = new_crctype;
1479
1480 /* if network interface up, reprogram hardware */
1481 if (info->netcount)
1482 program_hw(info);
1483
1484 return 0;
1485}
1486
1487/**
1488 * called by generic HDLC layer to send frame
1489 *
1490 * skb socket buffer containing HDLC frame
1491 * dev pointer to network device structure
1492 */
1493static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1494 struct net_device *dev)
1495{
1496 struct slgt_info *info = dev_to_port(dev);
1497 unsigned long flags;
1498
1499 DBGINFO(("%s hdlc_xmit\n", dev->name));
1500
1501 if (!skb->len)
1502 return NETDEV_TX_OK;
1503
1504 /* stop sending until this frame completes */
1505 netif_stop_queue(dev);
1506
1507 /* update network statistics */
1508 dev->stats.tx_packets++;
1509 dev->stats.tx_bytes += skb->len;
1510
1511 /* save start time for transmit timeout detection */
1512 dev->trans_start = jiffies;
1513
1514 spin_lock_irqsave(&info->lock, flags);
1515 tx_load(info, skb->data, skb->len);
1516 spin_unlock_irqrestore(&info->lock, flags);
1517
1518 /* done with socket buffer, so free it */
1519 dev_kfree_skb(skb);
1520
1521 return NETDEV_TX_OK;
1522}
1523
1524/**
1525 * called by network layer when interface enabled
1526 * claim resources and initialize hardware
1527 *
1528 * dev pointer to network device structure
1529 *
1530 * returns 0 if success, otherwise error code
1531 */
1532static int hdlcdev_open(struct net_device *dev)
1533{
1534 struct slgt_info *info = dev_to_port(dev);
1535 int rc;
1536 unsigned long flags;
1537
1538 if (!try_module_get(THIS_MODULE))
1539 return -EBUSY;
1540
1541 DBGINFO(("%s hdlcdev_open\n", dev->name));
1542
1543 /* generic HDLC layer open processing */
1544 if ((rc = hdlc_open(dev)))
1545 return rc;
1546
1547 /* arbitrate between network and tty opens */
1548 spin_lock_irqsave(&info->netlock, flags);
1549 if (info->port.count != 0 || info->netcount != 0) {
1550 DBGINFO(("%s hdlc_open busy\n", dev->name));
1551 spin_unlock_irqrestore(&info->netlock, flags);
1552 return -EBUSY;
1553 }
1554 info->netcount=1;
1555 spin_unlock_irqrestore(&info->netlock, flags);
1556
1557 /* claim resources and init adapter */
1558 if ((rc = startup(info)) != 0) {
1559 spin_lock_irqsave(&info->netlock, flags);
1560 info->netcount=0;
1561 spin_unlock_irqrestore(&info->netlock, flags);
1562 return rc;
1563 }
1564
1565 /* assert DTR and RTS, apply hardware settings */
1566 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1567 program_hw(info);
1568
1569 /* enable network layer transmit */
1570 dev->trans_start = jiffies;
1571 netif_start_queue(dev);
1572
1573 /* inform generic HDLC layer of current DCD status */
1574 spin_lock_irqsave(&info->lock, flags);
1575 get_signals(info);
1576 spin_unlock_irqrestore(&info->lock, flags);
1577 if (info->signals & SerialSignal_DCD)
1578 netif_carrier_on(dev);
1579 else
1580 netif_carrier_off(dev);
1581 return 0;
1582}
1583
1584/**
1585 * called by network layer when interface is disabled
1586 * shutdown hardware and release resources
1587 *
1588 * dev pointer to network device structure
1589 *
1590 * returns 0 if success, otherwise error code
1591 */
1592static int hdlcdev_close(struct net_device *dev)
1593{
1594 struct slgt_info *info = dev_to_port(dev);
1595 unsigned long flags;
1596
1597 DBGINFO(("%s hdlcdev_close\n", dev->name));
1598
1599 netif_stop_queue(dev);
1600
1601 /* shutdown adapter and release resources */
1602 shutdown(info);
1603
1604 hdlc_close(dev);
1605
1606 spin_lock_irqsave(&info->netlock, flags);
1607 info->netcount=0;
1608 spin_unlock_irqrestore(&info->netlock, flags);
1609
1610 module_put(THIS_MODULE);
1611 return 0;
1612}
1613
1614/**
1615 * called by network layer to process IOCTL call to network device
1616 *
1617 * dev pointer to network device structure
1618 * ifr pointer to network interface request structure
1619 * cmd IOCTL command code
1620 *
1621 * returns 0 if success, otherwise error code
1622 */
1623static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1624{
1625 const size_t size = sizeof(sync_serial_settings);
1626 sync_serial_settings new_line;
1627 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1628 struct slgt_info *info = dev_to_port(dev);
1629 unsigned int flags;
1630
1631 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1632
1633 /* return error if TTY interface open */
1634 if (info->port.count)
1635 return -EBUSY;
1636
1637 if (cmd != SIOCWANDEV)
1638 return hdlc_ioctl(dev, ifr, cmd);
1639
1640 memset(&new_line, 0, sizeof(new_line));
1641
1642 switch(ifr->ifr_settings.type) {
1643 case IF_GET_IFACE: /* return current sync_serial_settings */
1644
1645 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1646 if (ifr->ifr_settings.size < size) {
1647 ifr->ifr_settings.size = size; /* data size wanted */
1648 return -ENOBUFS;
1649 }
1650
1651 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1652 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1653 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1654 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1655
1656 switch (flags){
1657 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1658 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1659 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1660 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1661 default: new_line.clock_type = CLOCK_DEFAULT;
1662 }
1663
1664 new_line.clock_rate = info->params.clock_speed;
1665 new_line.loopback = info->params.loopback ? 1:0;
1666
1667 if (copy_to_user(line, &new_line, size))
1668 return -EFAULT;
1669 return 0;
1670
1671 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1672
1673 if(!capable(CAP_NET_ADMIN))
1674 return -EPERM;
1675 if (copy_from_user(&new_line, line, size))
1676 return -EFAULT;
1677
1678 switch (new_line.clock_type)
1679 {
1680 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1681 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1682 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1683 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1684 case CLOCK_DEFAULT: flags = info->params.flags &
1685 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1686 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1687 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1688 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1689 default: return -EINVAL;
1690 }
1691
1692 if (new_line.loopback != 0 && new_line.loopback != 1)
1693 return -EINVAL;
1694
1695 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1696 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1697 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1698 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1699 info->params.flags |= flags;
1700
1701 info->params.loopback = new_line.loopback;
1702
1703 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1704 info->params.clock_speed = new_line.clock_rate;
1705 else
1706 info->params.clock_speed = 0;
1707
1708 /* if network interface up, reprogram hardware */
1709 if (info->netcount)
1710 program_hw(info);
1711 return 0;
1712
1713 default:
1714 return hdlc_ioctl(dev, ifr, cmd);
1715 }
1716}
1717
1718/**
1719 * called by network layer when transmit timeout is detected
1720 *
1721 * dev pointer to network device structure
1722 */
1723static void hdlcdev_tx_timeout(struct net_device *dev)
1724{
1725 struct slgt_info *info = dev_to_port(dev);
1726 unsigned long flags;
1727
1728 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1729
1730 dev->stats.tx_errors++;
1731 dev->stats.tx_aborted_errors++;
1732
1733 spin_lock_irqsave(&info->lock,flags);
1734 tx_stop(info);
1735 spin_unlock_irqrestore(&info->lock,flags);
1736
1737 netif_wake_queue(dev);
1738}
1739
1740/**
1741 * called by device driver when transmit completes
1742 * reenable network layer transmit if stopped
1743 *
1744 * info pointer to device instance information
1745 */
1746static void hdlcdev_tx_done(struct slgt_info *info)
1747{
1748 if (netif_queue_stopped(info->netdev))
1749 netif_wake_queue(info->netdev);
1750}
1751
1752/**
1753 * called by device driver when frame received
1754 * pass frame to network layer
1755 *
1756 * info pointer to device instance information
1757 * buf pointer to buffer contianing frame data
1758 * size count of data bytes in buf
1759 */
1760static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1761{
1762 struct sk_buff *skb = dev_alloc_skb(size);
1763 struct net_device *dev = info->netdev;
1764
1765 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1766
1767 if (skb == NULL) {
1768 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1769 dev->stats.rx_dropped++;
1770 return;
1771 }
1772
1773 memcpy(skb_put(skb, size), buf, size);
1774
1775 skb->protocol = hdlc_type_trans(skb, dev);
1776
1777 dev->stats.rx_packets++;
1778 dev->stats.rx_bytes += size;
1779
1780 netif_rx(skb);
1781}
1782
1783static const struct net_device_ops hdlcdev_ops = {
1784 .ndo_open = hdlcdev_open,
1785 .ndo_stop = hdlcdev_close,
1786 .ndo_change_mtu = hdlc_change_mtu,
1787 .ndo_start_xmit = hdlc_start_xmit,
1788 .ndo_do_ioctl = hdlcdev_ioctl,
1789 .ndo_tx_timeout = hdlcdev_tx_timeout,
1790};
1791
1792/**
1793 * called by device driver when adding device instance
1794 * do generic HDLC initialization
1795 *
1796 * info pointer to device instance information
1797 *
1798 * returns 0 if success, otherwise error code
1799 */
1800static int hdlcdev_init(struct slgt_info *info)
1801{
1802 int rc;
1803 struct net_device *dev;
1804 hdlc_device *hdlc;
1805
1806 /* allocate and initialize network and HDLC layer objects */
1807
1808 if (!(dev = alloc_hdlcdev(info))) {
1809 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1810 return -ENOMEM;
1811 }
1812
1813 /* for network layer reporting purposes only */
1814 dev->mem_start = info->phys_reg_addr;
1815 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1816 dev->irq = info->irq_level;
1817
1818 /* network layer callbacks and settings */
1819 dev->netdev_ops = &hdlcdev_ops;
1820 dev->watchdog_timeo = 10 * HZ;
1821 dev->tx_queue_len = 50;
1822
1823 /* generic HDLC layer callbacks and settings */
1824 hdlc = dev_to_hdlc(dev);
1825 hdlc->attach = hdlcdev_attach;
1826 hdlc->xmit = hdlcdev_xmit;
1827
1828 /* register objects with HDLC layer */
1829 if ((rc = register_hdlc_device(dev))) {
1830 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1831 free_netdev(dev);
1832 return rc;
1833 }
1834
1835 info->netdev = dev;
1836 return 0;
1837}
1838
1839/**
1840 * called by device driver when removing device instance
1841 * do generic HDLC cleanup
1842 *
1843 * info pointer to device instance information
1844 */
1845static void hdlcdev_exit(struct slgt_info *info)
1846{
1847 unregister_hdlc_device(info->netdev);
1848 free_netdev(info->netdev);
1849 info->netdev = NULL;
1850}
1851
1852#endif /* ifdef CONFIG_HDLC */
1853
1854/*
1855 * get async data from rx DMA buffers
1856 */
1857static void rx_async(struct slgt_info *info)
1858{
1859 struct tty_struct *tty = info->port.tty;
1860 struct mgsl_icount *icount = &info->icount;
1861 unsigned int start, end;
1862 unsigned char *p;
1863 unsigned char status;
1864 struct slgt_desc *bufs = info->rbufs;
1865 int i, count;
1866 int chars = 0;
1867 int stat;
1868 unsigned char ch;
1869
1870 start = end = info->rbuf_current;
1871
1872 while(desc_complete(bufs[end])) {
1873 count = desc_count(bufs[end]) - info->rbuf_index;
1874 p = bufs[end].buf + info->rbuf_index;
1875
1876 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1877 DBGDATA(info, p, count, "rx");
1878
1879 for(i=0 ; i < count; i+=2, p+=2) {
1880 ch = *p;
1881 icount->rx++;
1882
1883 stat = 0;
1884
1885 if ((status = *(p+1) & (BIT1 + BIT0))) {
1886 if (status & BIT1)
1887 icount->parity++;
1888 else if (status & BIT0)
1889 icount->frame++;
1890 /* discard char if tty control flags say so */
1891 if (status & info->ignore_status_mask)
1892 continue;
1893 if (status & BIT1)
1894 stat = TTY_PARITY;
1895 else if (status & BIT0)
1896 stat = TTY_FRAME;
1897 }
1898 if (tty) {
1899 tty_insert_flip_char(tty, ch, stat);
1900 chars++;
1901 }
1902 }
1903
1904 if (i < count) {
1905 /* receive buffer not completed */
1906 info->rbuf_index += i;
1907 mod_timer(&info->rx_timer, jiffies + 1);
1908 break;
1909 }
1910
1911 info->rbuf_index = 0;
1912 free_rbufs(info, end, end);
1913
1914 if (++end == info->rbuf_count)
1915 end = 0;
1916
1917 /* if entire list searched then no frame available */
1918 if (end == start)
1919 break;
1920 }
1921
1922 if (tty && chars)
1923 tty_flip_buffer_push(tty);
1924}
1925
1926/*
1927 * return next bottom half action to perform
1928 */
1929static int bh_action(struct slgt_info *info)
1930{
1931 unsigned long flags;
1932 int rc;
1933
1934 spin_lock_irqsave(&info->lock,flags);
1935
1936 if (info->pending_bh & BH_RECEIVE) {
1937 info->pending_bh &= ~BH_RECEIVE;
1938 rc = BH_RECEIVE;
1939 } else if (info->pending_bh & BH_TRANSMIT) {
1940 info->pending_bh &= ~BH_TRANSMIT;
1941 rc = BH_TRANSMIT;
1942 } else if (info->pending_bh & BH_STATUS) {
1943 info->pending_bh &= ~BH_STATUS;
1944 rc = BH_STATUS;
1945 } else {
1946 /* Mark BH routine as complete */
1947 info->bh_running = false;
1948 info->bh_requested = false;
1949 rc = 0;
1950 }
1951
1952 spin_unlock_irqrestore(&info->lock,flags);
1953
1954 return rc;
1955}
1956
1957/*
1958 * perform bottom half processing
1959 */
1960static void bh_handler(struct work_struct *work)
1961{
1962 struct slgt_info *info = container_of(work, struct slgt_info, task);
1963 int action;
1964
1965 if (!info)
1966 return;
1967 info->bh_running = true;
1968
1969 while((action = bh_action(info))) {
1970 switch (action) {
1971 case BH_RECEIVE:
1972 DBGBH(("%s bh receive\n", info->device_name));
1973 switch(info->params.mode) {
1974 case MGSL_MODE_ASYNC:
1975 rx_async(info);
1976 break;
1977 case MGSL_MODE_HDLC:
1978 while(rx_get_frame(info));
1979 break;
1980 case MGSL_MODE_RAW:
1981 case MGSL_MODE_MONOSYNC:
1982 case MGSL_MODE_BISYNC:
1983 case MGSL_MODE_XSYNC:
1984 while(rx_get_buf(info));
1985 break;
1986 }
1987 /* restart receiver if rx DMA buffers exhausted */
1988 if (info->rx_restart)
1989 rx_start(info);
1990 break;
1991 case BH_TRANSMIT:
1992 bh_transmit(info);
1993 break;
1994 case BH_STATUS:
1995 DBGBH(("%s bh status\n", info->device_name));
1996 info->ri_chkcount = 0;
1997 info->dsr_chkcount = 0;
1998 info->dcd_chkcount = 0;
1999 info->cts_chkcount = 0;
2000 break;
2001 default:
2002 DBGBH(("%s unknown action\n", info->device_name));
2003 break;
2004 }
2005 }
2006 DBGBH(("%s bh_handler exit\n", info->device_name));
2007}
2008
2009static void bh_transmit(struct slgt_info *info)
2010{
2011 struct tty_struct *tty = info->port.tty;
2012
2013 DBGBH(("%s bh_transmit\n", info->device_name));
2014 if (tty)
2015 tty_wakeup(tty);
2016}
2017
2018static void dsr_change(struct slgt_info *info, unsigned short status)
2019{
2020 if (status & BIT3) {
2021 info->signals |= SerialSignal_DSR;
2022 info->input_signal_events.dsr_up++;
2023 } else {
2024 info->signals &= ~SerialSignal_DSR;
2025 info->input_signal_events.dsr_down++;
2026 }
2027 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2028 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2029 slgt_irq_off(info, IRQ_DSR);
2030 return;
2031 }
2032 info->icount.dsr++;
2033 wake_up_interruptible(&info->status_event_wait_q);
2034 wake_up_interruptible(&info->event_wait_q);
2035 info->pending_bh |= BH_STATUS;
2036}
2037
2038static void cts_change(struct slgt_info *info, unsigned short status)
2039{
2040 if (status & BIT2) {
2041 info->signals |= SerialSignal_CTS;
2042 info->input_signal_events.cts_up++;
2043 } else {
2044 info->signals &= ~SerialSignal_CTS;
2045 info->input_signal_events.cts_down++;
2046 }
2047 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2048 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2049 slgt_irq_off(info, IRQ_CTS);
2050 return;
2051 }
2052 info->icount.cts++;
2053 wake_up_interruptible(&info->status_event_wait_q);
2054 wake_up_interruptible(&info->event_wait_q);
2055 info->pending_bh |= BH_STATUS;
2056
2057 if (info->port.flags & ASYNC_CTS_FLOW) {
2058 if (info->port.tty) {
2059 if (info->port.tty->hw_stopped) {
2060 if (info->signals & SerialSignal_CTS) {
2061 info->port.tty->hw_stopped = 0;
2062 info->pending_bh |= BH_TRANSMIT;
2063 return;
2064 }
2065 } else {
2066 if (!(info->signals & SerialSignal_CTS))
2067 info->port.tty->hw_stopped = 1;
2068 }
2069 }
2070 }
2071}
2072
2073static void dcd_change(struct slgt_info *info, unsigned short status)
2074{
2075 if (status & BIT1) {
2076 info->signals |= SerialSignal_DCD;
2077 info->input_signal_events.dcd_up++;
2078 } else {
2079 info->signals &= ~SerialSignal_DCD;
2080 info->input_signal_events.dcd_down++;
2081 }
2082 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2083 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2084 slgt_irq_off(info, IRQ_DCD);
2085 return;
2086 }
2087 info->icount.dcd++;
2088#if SYNCLINK_GENERIC_HDLC
2089 if (info->netcount) {
2090 if (info->signals & SerialSignal_DCD)
2091 netif_carrier_on(info->netdev);
2092 else
2093 netif_carrier_off(info->netdev);
2094 }
2095#endif
2096 wake_up_interruptible(&info->status_event_wait_q);
2097 wake_up_interruptible(&info->event_wait_q);
2098 info->pending_bh |= BH_STATUS;
2099
2100 if (info->port.flags & ASYNC_CHECK_CD) {
2101 if (info->signals & SerialSignal_DCD)
2102 wake_up_interruptible(&info->port.open_wait);
2103 else {
2104 if (info->port.tty)
2105 tty_hangup(info->port.tty);
2106 }
2107 }
2108}
2109
2110static void ri_change(struct slgt_info *info, unsigned short status)
2111{
2112 if (status & BIT0) {
2113 info->signals |= SerialSignal_RI;
2114 info->input_signal_events.ri_up++;
2115 } else {
2116 info->signals &= ~SerialSignal_RI;
2117 info->input_signal_events.ri_down++;
2118 }
2119 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2120 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2121 slgt_irq_off(info, IRQ_RI);
2122 return;
2123 }
2124 info->icount.rng++;
2125 wake_up_interruptible(&info->status_event_wait_q);
2126 wake_up_interruptible(&info->event_wait_q);
2127 info->pending_bh |= BH_STATUS;
2128}
2129
2130static void isr_rxdata(struct slgt_info *info)
2131{
2132 unsigned int count = info->rbuf_fill_count;
2133 unsigned int i = info->rbuf_fill_index;
2134 unsigned short reg;
2135
2136 while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2137 reg = rd_reg16(info, RDR);
2138 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2139 if (desc_complete(info->rbufs[i])) {
2140 /* all buffers full */
2141 rx_stop(info);
2142 info->rx_restart = 1;
2143 continue;
2144 }
2145 info->rbufs[i].buf[count++] = (unsigned char)reg;
2146 /* async mode saves status byte to buffer for each data byte */
2147 if (info->params.mode == MGSL_MODE_ASYNC)
2148 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2149 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2150 /* buffer full or end of frame */
2151 set_desc_count(info->rbufs[i], count);
2152 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2153 info->rbuf_fill_count = count = 0;
2154 if (++i == info->rbuf_count)
2155 i = 0;
2156 info->pending_bh |= BH_RECEIVE;
2157 }
2158 }
2159
2160 info->rbuf_fill_index = i;
2161 info->rbuf_fill_count = count;
2162}
2163
2164static void isr_serial(struct slgt_info *info)
2165{
2166 unsigned short status = rd_reg16(info, SSR);
2167
2168 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2169
2170 wr_reg16(info, SSR, status); /* clear pending */
2171
2172 info->irq_occurred = true;
2173
2174 if (info->params.mode == MGSL_MODE_ASYNC) {
2175 if (status & IRQ_TXIDLE) {
2176 if (info->tx_active)
2177 isr_txeom(info, status);
2178 }
2179 if (info->rx_pio && (status & IRQ_RXDATA))
2180 isr_rxdata(info);
2181 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2182 info->icount.brk++;
2183 /* process break detection if tty control allows */
2184 if (info->port.tty) {
2185 if (!(status & info->ignore_status_mask)) {
2186 if (info->read_status_mask & MASK_BREAK) {
2187 tty_insert_flip_char(info->port.tty, 0, TTY_BREAK);
2188 if (info->port.flags & ASYNC_SAK)
2189 do_SAK(info->port.tty);
2190 }
2191 }
2192 }
2193 }
2194 } else {
2195 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2196 isr_txeom(info, status);
2197 if (info->rx_pio && (status & IRQ_RXDATA))
2198 isr_rxdata(info);
2199 if (status & IRQ_RXIDLE) {
2200 if (status & RXIDLE)
2201 info->icount.rxidle++;
2202 else
2203 info->icount.exithunt++;
2204 wake_up_interruptible(&info->event_wait_q);
2205 }
2206
2207 if (status & IRQ_RXOVER)
2208 rx_start(info);
2209 }
2210
2211 if (status & IRQ_DSR)
2212 dsr_change(info, status);
2213 if (status & IRQ_CTS)
2214 cts_change(info, status);
2215 if (status & IRQ_DCD)
2216 dcd_change(info, status);
2217 if (status & IRQ_RI)
2218 ri_change(info, status);
2219}
2220
2221static void isr_rdma(struct slgt_info *info)
2222{
2223 unsigned int status = rd_reg32(info, RDCSR);
2224
2225 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2226
2227 /* RDCSR (rx DMA control/status)
2228 *
2229 * 31..07 reserved
2230 * 06 save status byte to DMA buffer
2231 * 05 error
2232 * 04 eol (end of list)
2233 * 03 eob (end of buffer)
2234 * 02 IRQ enable
2235 * 01 reset
2236 * 00 enable
2237 */
2238 wr_reg32(info, RDCSR, status); /* clear pending */
2239
2240 if (status & (BIT5 + BIT4)) {
2241 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2242 info->rx_restart = true;
2243 }
2244 info->pending_bh |= BH_RECEIVE;
2245}
2246
2247static void isr_tdma(struct slgt_info *info)
2248{
2249 unsigned int status = rd_reg32(info, TDCSR);
2250
2251 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2252
2253 /* TDCSR (tx DMA control/status)
2254 *
2255 * 31..06 reserved
2256 * 05 error
2257 * 04 eol (end of list)
2258 * 03 eob (end of buffer)
2259 * 02 IRQ enable
2260 * 01 reset
2261 * 00 enable
2262 */
2263 wr_reg32(info, TDCSR, status); /* clear pending */
2264
2265 if (status & (BIT5 + BIT4 + BIT3)) {
2266 // another transmit buffer has completed
2267 // run bottom half to get more send data from user
2268 info->pending_bh |= BH_TRANSMIT;
2269 }
2270}
2271
2272/*
2273 * return true if there are unsent tx DMA buffers, otherwise false
2274 *
2275 * if there are unsent buffers then info->tbuf_start
2276 * is set to index of first unsent buffer
2277 */
2278static bool unsent_tbufs(struct slgt_info *info)
2279{
2280 unsigned int i = info->tbuf_current;
2281 bool rc = false;
2282
2283 /*
2284 * search backwards from last loaded buffer (precedes tbuf_current)
2285 * for first unsent buffer (desc_count > 0)
2286 */
2287
2288 do {
2289 if (i)
2290 i--;
2291 else
2292 i = info->tbuf_count - 1;
2293 if (!desc_count(info->tbufs[i]))
2294 break;
2295 info->tbuf_start = i;
2296 rc = true;
2297 } while (i != info->tbuf_current);
2298
2299 return rc;
2300}
2301
2302static void isr_txeom(struct slgt_info *info, unsigned short status)
2303{
2304 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2305
2306 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2307 tdma_reset(info);
2308 if (status & IRQ_TXUNDER) {
2309 unsigned short val = rd_reg16(info, TCR);
2310 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2311 wr_reg16(info, TCR, val); /* clear reset bit */
2312 }
2313
2314 if (info->tx_active) {
2315 if (info->params.mode != MGSL_MODE_ASYNC) {
2316 if (status & IRQ_TXUNDER)
2317 info->icount.txunder++;
2318 else if (status & IRQ_TXIDLE)
2319 info->icount.txok++;
2320 }
2321
2322 if (unsent_tbufs(info)) {
2323 tx_start(info);
2324 update_tx_timer(info);
2325 return;
2326 }
2327 info->tx_active = false;
2328
2329 del_timer(&info->tx_timer);
2330
2331 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2332 info->signals &= ~SerialSignal_RTS;
2333 info->drop_rts_on_tx_done = false;
2334 set_signals(info);
2335 }
2336
2337#if SYNCLINK_GENERIC_HDLC
2338 if (info->netcount)
2339 hdlcdev_tx_done(info);
2340 else
2341#endif
2342 {
2343 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2344 tx_stop(info);
2345 return;
2346 }
2347 info->pending_bh |= BH_TRANSMIT;
2348 }
2349 }
2350}
2351
2352static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2353{
2354 struct cond_wait *w, *prev;
2355
2356 /* wake processes waiting for specific transitions */
2357 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2358 if (w->data & changed) {
2359 w->data = state;
2360 wake_up_interruptible(&w->q);
2361 if (prev != NULL)
2362 prev->next = w->next;
2363 else
2364 info->gpio_wait_q = w->next;
2365 } else
2366 prev = w;
2367 }
2368}
2369
2370/* interrupt service routine
2371 *
2372 * irq interrupt number
2373 * dev_id device ID supplied during interrupt registration
2374 */
2375static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2376{
2377 struct slgt_info *info = dev_id;
2378 unsigned int gsr;
2379 unsigned int i;
2380
2381 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2382
2383 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2384 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2385 info->irq_occurred = true;
2386 for(i=0; i < info->port_count ; i++) {
2387 if (info->port_array[i] == NULL)
2388 continue;
2389 spin_lock(&info->port_array[i]->lock);
2390 if (gsr & (BIT8 << i))
2391 isr_serial(info->port_array[i]);
2392 if (gsr & (BIT16 << (i*2)))
2393 isr_rdma(info->port_array[i]);
2394 if (gsr & (BIT17 << (i*2)))
2395 isr_tdma(info->port_array[i]);
2396 spin_unlock(&info->port_array[i]->lock);
2397 }
2398 }
2399
2400 if (info->gpio_present) {
2401 unsigned int state;
2402 unsigned int changed;
2403 spin_lock(&info->lock);
2404 while ((changed = rd_reg32(info, IOSR)) != 0) {
2405 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2406 /* read latched state of GPIO signals */
2407 state = rd_reg32(info, IOVR);
2408 /* clear pending GPIO interrupt bits */
2409 wr_reg32(info, IOSR, changed);
2410 for (i=0 ; i < info->port_count ; i++) {
2411 if (info->port_array[i] != NULL)
2412 isr_gpio(info->port_array[i], changed, state);
2413 }
2414 }
2415 spin_unlock(&info->lock);
2416 }
2417
2418 for(i=0; i < info->port_count ; i++) {
2419 struct slgt_info *port = info->port_array[i];
2420 if (port == NULL)
2421 continue;
2422 spin_lock(&port->lock);
2423 if ((port->port.count || port->netcount) &&
2424 port->pending_bh && !port->bh_running &&
2425 !port->bh_requested) {
2426 DBGISR(("%s bh queued\n", port->device_name));
2427 schedule_work(&port->task);
2428 port->bh_requested = true;
2429 }
2430 spin_unlock(&port->lock);
2431 }
2432
2433 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2434 return IRQ_HANDLED;
2435}
2436
2437static int startup(struct slgt_info *info)
2438{
2439 DBGINFO(("%s startup\n", info->device_name));
2440
2441 if (info->port.flags & ASYNC_INITIALIZED)
2442 return 0;
2443
2444 if (!info->tx_buf) {
2445 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2446 if (!info->tx_buf) {
2447 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2448 return -ENOMEM;
2449 }
2450 }
2451
2452 info->pending_bh = 0;
2453
2454 memset(&info->icount, 0, sizeof(info->icount));
2455
2456 /* program hardware for current parameters */
2457 change_params(info);
2458
2459 if (info->port.tty)
2460 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2461
2462 info->port.flags |= ASYNC_INITIALIZED;
2463
2464 return 0;
2465}
2466
2467/*
2468 * called by close() and hangup() to shutdown hardware
2469 */
2470static void shutdown(struct slgt_info *info)
2471{
2472 unsigned long flags;
2473
2474 if (!(info->port.flags & ASYNC_INITIALIZED))
2475 return;
2476
2477 DBGINFO(("%s shutdown\n", info->device_name));
2478
2479 /* clear status wait queue because status changes */
2480 /* can't happen after shutting down the hardware */
2481 wake_up_interruptible(&info->status_event_wait_q);
2482 wake_up_interruptible(&info->event_wait_q);
2483
2484 del_timer_sync(&info->tx_timer);
2485 del_timer_sync(&info->rx_timer);
2486
2487 kfree(info->tx_buf);
2488 info->tx_buf = NULL;
2489
2490 spin_lock_irqsave(&info->lock,flags);
2491
2492 tx_stop(info);
2493 rx_stop(info);
2494
2495 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2496
2497 if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2498 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2499 set_signals(info);
2500 }
2501
2502 flush_cond_wait(&info->gpio_wait_q);
2503
2504 spin_unlock_irqrestore(&info->lock,flags);
2505
2506 if (info->port.tty)
2507 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2508
2509 info->port.flags &= ~ASYNC_INITIALIZED;
2510}
2511
2512static void program_hw(struct slgt_info *info)
2513{
2514 unsigned long flags;
2515
2516 spin_lock_irqsave(&info->lock,flags);
2517
2518 rx_stop(info);
2519 tx_stop(info);
2520
2521 if (info->params.mode != MGSL_MODE_ASYNC ||
2522 info->netcount)
2523 sync_mode(info);
2524 else
2525 async_mode(info);
2526
2527 set_signals(info);
2528
2529 info->dcd_chkcount = 0;
2530 info->cts_chkcount = 0;
2531 info->ri_chkcount = 0;
2532 info->dsr_chkcount = 0;
2533
2534 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2535 get_signals(info);
2536
2537 if (info->netcount ||
2538 (info->port.tty && info->port.tty->termios->c_cflag & CREAD))
2539 rx_start(info);
2540
2541 spin_unlock_irqrestore(&info->lock,flags);
2542}
2543
2544/*
2545 * reconfigure adapter based on new parameters
2546 */
2547static void change_params(struct slgt_info *info)
2548{
2549 unsigned cflag;
2550 int bits_per_char;
2551
2552 if (!info->port.tty || !info->port.tty->termios)
2553 return;
2554 DBGINFO(("%s change_params\n", info->device_name));
2555
2556 cflag = info->port.tty->termios->c_cflag;
2557
2558 /* if B0 rate (hangup) specified then negate DTR and RTS */
2559 /* otherwise assert DTR and RTS */
2560 if (cflag & CBAUD)
2561 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2562 else
2563 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2564
2565 /* byte size and parity */
2566
2567 switch (cflag & CSIZE) {
2568 case CS5: info->params.data_bits = 5; break;
2569 case CS6: info->params.data_bits = 6; break;
2570 case CS7: info->params.data_bits = 7; break;
2571 case CS8: info->params.data_bits = 8; break;
2572 default: info->params.data_bits = 7; break;
2573 }
2574
2575 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2576
2577 if (cflag & PARENB)
2578 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2579 else
2580 info->params.parity = ASYNC_PARITY_NONE;
2581
2582 /* calculate number of jiffies to transmit a full
2583 * FIFO (32 bytes) at specified data rate
2584 */
2585 bits_per_char = info->params.data_bits +
2586 info->params.stop_bits + 1;
2587
2588 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2589
2590 if (info->params.data_rate) {
2591 info->timeout = (32*HZ*bits_per_char) /
2592 info->params.data_rate;
2593 }
2594 info->timeout += HZ/50; /* Add .02 seconds of slop */
2595
2596 if (cflag & CRTSCTS)
2597 info->port.flags |= ASYNC_CTS_FLOW;
2598 else
2599 info->port.flags &= ~ASYNC_CTS_FLOW;
2600
2601 if (cflag & CLOCAL)
2602 info->port.flags &= ~ASYNC_CHECK_CD;
2603 else
2604 info->port.flags |= ASYNC_CHECK_CD;
2605
2606 /* process tty input control flags */
2607
2608 info->read_status_mask = IRQ_RXOVER;
2609 if (I_INPCK(info->port.tty))
2610 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2611 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2612 info->read_status_mask |= MASK_BREAK;
2613 if (I_IGNPAR(info->port.tty))
2614 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2615 if (I_IGNBRK(info->port.tty)) {
2616 info->ignore_status_mask |= MASK_BREAK;
2617 /* If ignoring parity and break indicators, ignore
2618 * overruns too. (For real raw support).
2619 */
2620 if (I_IGNPAR(info->port.tty))
2621 info->ignore_status_mask |= MASK_OVERRUN;
2622 }
2623
2624 program_hw(info);
2625}
2626
2627static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2628{
2629 DBGINFO(("%s get_stats\n", info->device_name));
2630 if (!user_icount) {
2631 memset(&info->icount, 0, sizeof(info->icount));
2632 } else {
2633 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2634 return -EFAULT;
2635 }
2636 return 0;
2637}
2638
2639static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2640{
2641 DBGINFO(("%s get_params\n", info->device_name));
2642 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2643 return -EFAULT;
2644 return 0;
2645}
2646
2647static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2648{
2649 unsigned long flags;
2650 MGSL_PARAMS tmp_params;
2651
2652 DBGINFO(("%s set_params\n", info->device_name));
2653 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2654 return -EFAULT;
2655
2656 spin_lock_irqsave(&info->lock, flags);
2657 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2658 info->base_clock = tmp_params.clock_speed;
2659 else
2660 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2661 spin_unlock_irqrestore(&info->lock, flags);
2662
2663 program_hw(info);
2664
2665 return 0;
2666}
2667
2668static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2669{
2670 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2671 if (put_user(info->idle_mode, idle_mode))
2672 return -EFAULT;
2673 return 0;
2674}
2675
2676static int set_txidle(struct slgt_info *info, int idle_mode)
2677{
2678 unsigned long flags;
2679 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2680 spin_lock_irqsave(&info->lock,flags);
2681 info->idle_mode = idle_mode;
2682 if (info->params.mode != MGSL_MODE_ASYNC)
2683 tx_set_idle(info);
2684 spin_unlock_irqrestore(&info->lock,flags);
2685 return 0;
2686}
2687
2688static int tx_enable(struct slgt_info *info, int enable)
2689{
2690 unsigned long flags;
2691 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2692 spin_lock_irqsave(&info->lock,flags);
2693 if (enable) {
2694 if (!info->tx_enabled)
2695 tx_start(info);
2696 } else {
2697 if (info->tx_enabled)
2698 tx_stop(info);
2699 }
2700 spin_unlock_irqrestore(&info->lock,flags);
2701 return 0;
2702}
2703
2704/*
2705 * abort transmit HDLC frame
2706 */
2707static int tx_abort(struct slgt_info *info)
2708{
2709 unsigned long flags;
2710 DBGINFO(("%s tx_abort\n", info->device_name));
2711 spin_lock_irqsave(&info->lock,flags);
2712 tdma_reset(info);
2713 spin_unlock_irqrestore(&info->lock,flags);
2714 return 0;
2715}
2716
2717static int rx_enable(struct slgt_info *info, int enable)
2718{
2719 unsigned long flags;
2720 unsigned int rbuf_fill_level;
2721 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2722 spin_lock_irqsave(&info->lock,flags);
2723 /*
2724 * enable[31..16] = receive DMA buffer fill level
2725 * 0 = noop (leave fill level unchanged)
2726 * fill level must be multiple of 4 and <= buffer size
2727 */
2728 rbuf_fill_level = ((unsigned int)enable) >> 16;
2729 if (rbuf_fill_level) {
2730 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2731 spin_unlock_irqrestore(&info->lock, flags);
2732 return -EINVAL;
2733 }
2734 info->rbuf_fill_level = rbuf_fill_level;
2735 if (rbuf_fill_level < 128)
2736 info->rx_pio = 1; /* PIO mode */
2737 else
2738 info->rx_pio = 0; /* DMA mode */
2739 rx_stop(info); /* restart receiver to use new fill level */
2740 }
2741
2742 /*
2743 * enable[1..0] = receiver enable command
2744 * 0 = disable
2745 * 1 = enable
2746 * 2 = enable or force hunt mode if already enabled
2747 */
2748 enable &= 3;
2749 if (enable) {
2750 if (!info->rx_enabled)
2751 rx_start(info);
2752 else if (enable == 2) {
2753 /* force hunt mode (write 1 to RCR[3]) */
2754 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2755 }
2756 } else {
2757 if (info->rx_enabled)
2758 rx_stop(info);
2759 }
2760 spin_unlock_irqrestore(&info->lock,flags);
2761 return 0;
2762}
2763
2764/*
2765 * wait for specified event to occur
2766 */
2767static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2768{
2769 unsigned long flags;
2770 int s;
2771 int rc=0;
2772 struct mgsl_icount cprev, cnow;
2773 int events;
2774 int mask;
2775 struct _input_signal_events oldsigs, newsigs;
2776 DECLARE_WAITQUEUE(wait, current);
2777
2778 if (get_user(mask, mask_ptr))
2779 return -EFAULT;
2780
2781 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2782
2783 spin_lock_irqsave(&info->lock,flags);
2784
2785 /* return immediately if state matches requested events */
2786 get_signals(info);
2787 s = info->signals;
2788
2789 events = mask &
2790 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2791 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2792 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2793 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2794 if (events) {
2795 spin_unlock_irqrestore(&info->lock,flags);
2796 goto exit;
2797 }
2798
2799 /* save current irq counts */
2800 cprev = info->icount;
2801 oldsigs = info->input_signal_events;
2802
2803 /* enable hunt and idle irqs if needed */
2804 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2805 unsigned short val = rd_reg16(info, SCR);
2806 if (!(val & IRQ_RXIDLE))
2807 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2808 }
2809
2810 set_current_state(TASK_INTERRUPTIBLE);
2811 add_wait_queue(&info->event_wait_q, &wait);
2812
2813 spin_unlock_irqrestore(&info->lock,flags);
2814
2815 for(;;) {
2816 schedule();
2817 if (signal_pending(current)) {
2818 rc = -ERESTARTSYS;
2819 break;
2820 }
2821
2822 /* get current irq counts */
2823 spin_lock_irqsave(&info->lock,flags);
2824 cnow = info->icount;
2825 newsigs = info->input_signal_events;
2826 set_current_state(TASK_INTERRUPTIBLE);
2827 spin_unlock_irqrestore(&info->lock,flags);
2828
2829 /* if no change, wait aborted for some reason */
2830 if (newsigs.dsr_up == oldsigs.dsr_up &&
2831 newsigs.dsr_down == oldsigs.dsr_down &&
2832 newsigs.dcd_up == oldsigs.dcd_up &&
2833 newsigs.dcd_down == oldsigs.dcd_down &&
2834 newsigs.cts_up == oldsigs.cts_up &&
2835 newsigs.cts_down == oldsigs.cts_down &&
2836 newsigs.ri_up == oldsigs.ri_up &&
2837 newsigs.ri_down == oldsigs.ri_down &&
2838 cnow.exithunt == cprev.exithunt &&
2839 cnow.rxidle == cprev.rxidle) {
2840 rc = -EIO;
2841 break;
2842 }
2843
2844 events = mask &
2845 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2846 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2847 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2848 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2849 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2850 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2851 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2852 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2853 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2854 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2855 if (events)
2856 break;
2857
2858 cprev = cnow;
2859 oldsigs = newsigs;
2860 }
2861
2862 remove_wait_queue(&info->event_wait_q, &wait);
2863 set_current_state(TASK_RUNNING);
2864
2865
2866 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2867 spin_lock_irqsave(&info->lock,flags);
2868 if (!waitqueue_active(&info->event_wait_q)) {
2869 /* disable enable exit hunt mode/idle rcvd IRQs */
2870 wr_reg16(info, SCR,
2871 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2872 }
2873 spin_unlock_irqrestore(&info->lock,flags);
2874 }
2875exit:
2876 if (rc == 0)
2877 rc = put_user(events, mask_ptr);
2878 return rc;
2879}
2880
2881static int get_interface(struct slgt_info *info, int __user *if_mode)
2882{
2883 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2884 if (put_user(info->if_mode, if_mode))
2885 return -EFAULT;
2886 return 0;
2887}
2888
2889static int set_interface(struct slgt_info *info, int if_mode)
2890{
2891 unsigned long flags;
2892 unsigned short val;
2893
2894 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2895 spin_lock_irqsave(&info->lock,flags);
2896 info->if_mode = if_mode;
2897
2898 msc_set_vcr(info);
2899
2900 /* TCR (tx control) 07 1=RTS driver control */
2901 val = rd_reg16(info, TCR);
2902 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2903 val |= BIT7;
2904 else
2905 val &= ~BIT7;
2906 wr_reg16(info, TCR, val);
2907
2908 spin_unlock_irqrestore(&info->lock,flags);
2909 return 0;
2910}
2911
2912static int get_xsync(struct slgt_info *info, int __user *xsync)
2913{
2914 DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2915 if (put_user(info->xsync, xsync))
2916 return -EFAULT;
2917 return 0;
2918}
2919
2920/*
2921 * set extended sync pattern (1 to 4 bytes) for extended sync mode
2922 *
2923 * sync pattern is contained in least significant bytes of value
2924 * most significant byte of sync pattern is oldest (1st sent/detected)
2925 */
2926static int set_xsync(struct slgt_info *info, int xsync)
2927{
2928 unsigned long flags;
2929
2930 DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2931 spin_lock_irqsave(&info->lock, flags);
2932 info->xsync = xsync;
2933 wr_reg32(info, XSR, xsync);
2934 spin_unlock_irqrestore(&info->lock, flags);
2935 return 0;
2936}
2937
2938static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2939{
2940 DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2941 if (put_user(info->xctrl, xctrl))
2942 return -EFAULT;
2943 return 0;
2944}
2945
2946/*
2947 * set extended control options
2948 *
2949 * xctrl[31:19] reserved, must be zero
2950 * xctrl[18:17] extended sync pattern length in bytes
2951 * 00 = 1 byte in xsr[7:0]
2952 * 01 = 2 bytes in xsr[15:0]
2953 * 10 = 3 bytes in xsr[23:0]
2954 * 11 = 4 bytes in xsr[31:0]
2955 * xctrl[16] 1 = enable terminal count, 0=disabled
2956 * xctrl[15:0] receive terminal count for fixed length packets
2957 * value is count minus one (0 = 1 byte packet)
2958 * when terminal count is reached, receiver
2959 * automatically returns to hunt mode and receive
2960 * FIFO contents are flushed to DMA buffers with
2961 * end of frame (EOF) status
2962 */
2963static int set_xctrl(struct slgt_info *info, int xctrl)
2964{
2965 unsigned long flags;
2966
2967 DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2968 spin_lock_irqsave(&info->lock, flags);
2969 info->xctrl = xctrl;
2970 wr_reg32(info, XCR, xctrl);
2971 spin_unlock_irqrestore(&info->lock, flags);
2972 return 0;
2973}
2974
2975/*
2976 * set general purpose IO pin state and direction
2977 *
2978 * user_gpio fields:
2979 * state each bit indicates a pin state
2980 * smask set bit indicates pin state to set
2981 * dir each bit indicates a pin direction (0=input, 1=output)
2982 * dmask set bit indicates pin direction to set
2983 */
2984static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2985{
2986 unsigned long flags;
2987 struct gpio_desc gpio;
2988 __u32 data;
2989
2990 if (!info->gpio_present)
2991 return -EINVAL;
2992 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2993 return -EFAULT;
2994 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2995 info->device_name, gpio.state, gpio.smask,
2996 gpio.dir, gpio.dmask));
2997
2998 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2999 if (gpio.dmask) {
3000 data = rd_reg32(info, IODR);
3001 data |= gpio.dmask & gpio.dir;
3002 data &= ~(gpio.dmask & ~gpio.dir);
3003 wr_reg32(info, IODR, data);
3004 }
3005 if (gpio.smask) {
3006 data = rd_reg32(info, IOVR);
3007 data |= gpio.smask & gpio.state;
3008 data &= ~(gpio.smask & ~gpio.state);
3009 wr_reg32(info, IOVR, data);
3010 }
3011 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3012
3013 return 0;
3014}
3015
3016/*
3017 * get general purpose IO pin state and direction
3018 */
3019static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3020{
3021 struct gpio_desc gpio;
3022 if (!info->gpio_present)
3023 return -EINVAL;
3024 gpio.state = rd_reg32(info, IOVR);
3025 gpio.smask = 0xffffffff;
3026 gpio.dir = rd_reg32(info, IODR);
3027 gpio.dmask = 0xffffffff;
3028 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3029 return -EFAULT;
3030 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
3031 info->device_name, gpio.state, gpio.dir));
3032 return 0;
3033}
3034
3035/*
3036 * conditional wait facility
3037 */
3038static void init_cond_wait(struct cond_wait *w, unsigned int data)
3039{
3040 init_waitqueue_head(&w->q);
3041 init_waitqueue_entry(&w->wait, current);
3042 w->data = data;
3043}
3044
3045static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
3046{
3047 set_current_state(TASK_INTERRUPTIBLE);
3048 add_wait_queue(&w->q, &w->wait);
3049 w->next = *head;
3050 *head = w;
3051}
3052
3053static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
3054{
3055 struct cond_wait *w, *prev;
3056 remove_wait_queue(&cw->q, &cw->wait);
3057 set_current_state(TASK_RUNNING);
3058 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
3059 if (w == cw) {
3060 if (prev != NULL)
3061 prev->next = w->next;
3062 else
3063 *head = w->next;
3064 break;
3065 }
3066 }
3067}
3068
3069static void flush_cond_wait(struct cond_wait **head)
3070{
3071 while (*head != NULL) {
3072 wake_up_interruptible(&(*head)->q);
3073 *head = (*head)->next;
3074 }
3075}
3076
3077/*
3078 * wait for general purpose I/O pin(s) to enter specified state
3079 *
3080 * user_gpio fields:
3081 * state - bit indicates target pin state
3082 * smask - set bit indicates watched pin
3083 *
3084 * The wait ends when at least one watched pin enters the specified
3085 * state. When 0 (no error) is returned, user_gpio->state is set to the
3086 * state of all GPIO pins when the wait ends.
3087 *
3088 * Note: Each pin may be a dedicated input, dedicated output, or
3089 * configurable input/output. The number and configuration of pins
3090 * varies with the specific adapter model. Only input pins (dedicated
3091 * or configured) can be monitored with this function.
3092 */
3093static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3094{
3095 unsigned long flags;
3096 int rc = 0;
3097 struct gpio_desc gpio;
3098 struct cond_wait wait;
3099 u32 state;
3100
3101 if (!info->gpio_present)
3102 return -EINVAL;
3103 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3104 return -EFAULT;
3105 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3106 info->device_name, gpio.state, gpio.smask));
3107 /* ignore output pins identified by set IODR bit */
3108 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3109 return -EINVAL;
3110 init_cond_wait(&wait, gpio.smask);
3111
3112 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3113 /* enable interrupts for watched pins */
3114 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3115 /* get current pin states */
3116 state = rd_reg32(info, IOVR);
3117
3118 if (gpio.smask & ~(state ^ gpio.state)) {
3119 /* already in target state */
3120 gpio.state = state;
3121 } else {
3122 /* wait for target state */
3123 add_cond_wait(&info->gpio_wait_q, &wait);
3124 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3125 schedule();
3126 if (signal_pending(current))
3127 rc = -ERESTARTSYS;
3128 else
3129 gpio.state = wait.data;
3130 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3131 remove_cond_wait(&info->gpio_wait_q, &wait);
3132 }
3133
3134 /* disable all GPIO interrupts if no waiting processes */
3135 if (info->gpio_wait_q == NULL)
3136 wr_reg32(info, IOER, 0);
3137 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3138
3139 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3140 rc = -EFAULT;
3141 return rc;
3142}
3143
3144static int modem_input_wait(struct slgt_info *info,int arg)
3145{
3146 unsigned long flags;
3147 int rc;
3148 struct mgsl_icount cprev, cnow;
3149 DECLARE_WAITQUEUE(wait, current);
3150
3151 /* save current irq counts */
3152 spin_lock_irqsave(&info->lock,flags);
3153 cprev = info->icount;
3154 add_wait_queue(&info->status_event_wait_q, &wait);
3155 set_current_state(TASK_INTERRUPTIBLE);
3156 spin_unlock_irqrestore(&info->lock,flags);
3157
3158 for(;;) {
3159 schedule();
3160 if (signal_pending(current)) {
3161 rc = -ERESTARTSYS;
3162 break;
3163 }
3164
3165 /* get new irq counts */
3166 spin_lock_irqsave(&info->lock,flags);
3167 cnow = info->icount;
3168 set_current_state(TASK_INTERRUPTIBLE);
3169 spin_unlock_irqrestore(&info->lock,flags);
3170
3171 /* if no change, wait aborted for some reason */
3172 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3173 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3174 rc = -EIO;
3175 break;
3176 }
3177
3178 /* check for change in caller specified modem input */
3179 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3180 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3181 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3182 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3183 rc = 0;
3184 break;
3185 }
3186
3187 cprev = cnow;
3188 }
3189 remove_wait_queue(&info->status_event_wait_q, &wait);
3190 set_current_state(TASK_RUNNING);
3191 return rc;
3192}
3193
3194/*
3195 * return state of serial control and status signals
3196 */
3197static int tiocmget(struct tty_struct *tty)
3198{
3199 struct slgt_info *info = tty->driver_data;
3200 unsigned int result;
3201 unsigned long flags;
3202
3203 spin_lock_irqsave(&info->lock,flags);
3204 get_signals(info);
3205 spin_unlock_irqrestore(&info->lock,flags);
3206
3207 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3208 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3209 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3210 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3211 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3212 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3213
3214 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3215 return result;
3216}
3217
3218/*
3219 * set modem control signals (DTR/RTS)
3220 *
3221 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3222 * TIOCMSET = set/clear signal values
3223 * value bit mask for command
3224 */
3225static int tiocmset(struct tty_struct *tty,
3226 unsigned int set, unsigned int clear)
3227{
3228 struct slgt_info *info = tty->driver_data;
3229 unsigned long flags;
3230
3231 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3232
3233 if (set & TIOCM_RTS)
3234 info->signals |= SerialSignal_RTS;
3235 if (set & TIOCM_DTR)
3236 info->signals |= SerialSignal_DTR;
3237 if (clear & TIOCM_RTS)
3238 info->signals &= ~SerialSignal_RTS;
3239 if (clear & TIOCM_DTR)
3240 info->signals &= ~SerialSignal_DTR;
3241
3242 spin_lock_irqsave(&info->lock,flags);
3243 set_signals(info);
3244 spin_unlock_irqrestore(&info->lock,flags);
3245 return 0;
3246}
3247
3248static int carrier_raised(struct tty_port *port)
3249{
3250 unsigned long flags;
3251 struct slgt_info *info = container_of(port, struct slgt_info, port);
3252
3253 spin_lock_irqsave(&info->lock,flags);
3254 get_signals(info);
3255 spin_unlock_irqrestore(&info->lock,flags);
3256 return (info->signals & SerialSignal_DCD) ? 1 : 0;
3257}
3258
3259static void dtr_rts(struct tty_port *port, int on)
3260{
3261 unsigned long flags;
3262 struct slgt_info *info = container_of(port, struct slgt_info, port);
3263
3264 spin_lock_irqsave(&info->lock,flags);
3265 if (on)
3266 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3267 else
3268 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3269 set_signals(info);
3270 spin_unlock_irqrestore(&info->lock,flags);
3271}
3272
3273
3274/*
3275 * block current process until the device is ready to open
3276 */
3277static int block_til_ready(struct tty_struct *tty, struct file *filp,
3278 struct slgt_info *info)
3279{
3280 DECLARE_WAITQUEUE(wait, current);
3281 int retval;
3282 bool do_clocal = false;
3283 bool extra_count = false;
3284 unsigned long flags;
3285 int cd;
3286 struct tty_port *port = &info->port;
3287
3288 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3289
3290 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3291 /* nonblock mode is set or port is not enabled */
3292 port->flags |= ASYNC_NORMAL_ACTIVE;
3293 return 0;
3294 }
3295
3296 if (tty->termios->c_cflag & CLOCAL)
3297 do_clocal = true;
3298
3299 /* Wait for carrier detect and the line to become
3300 * free (i.e., not in use by the callout). While we are in
3301 * this loop, port->count is dropped by one, so that
3302 * close() knows when to free things. We restore it upon
3303 * exit, either normal or abnormal.
3304 */
3305
3306 retval = 0;
3307 add_wait_queue(&port->open_wait, &wait);
3308
3309 spin_lock_irqsave(&info->lock, flags);
3310 if (!tty_hung_up_p(filp)) {
3311 extra_count = true;
3312 port->count--;
3313 }
3314 spin_unlock_irqrestore(&info->lock, flags);
3315 port->blocked_open++;
3316
3317 while (1) {
3318 if ((tty->termios->c_cflag & CBAUD))
3319 tty_port_raise_dtr_rts(port);
3320
3321 set_current_state(TASK_INTERRUPTIBLE);
3322
3323 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3324 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3325 -EAGAIN : -ERESTARTSYS;
3326 break;
3327 }
3328
3329 cd = tty_port_carrier_raised(port);
3330
3331 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd ))
3332 break;
3333
3334 if (signal_pending(current)) {
3335 retval = -ERESTARTSYS;
3336 break;
3337 }
3338
3339 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3340 tty_unlock();
3341 schedule();
3342 tty_lock();
3343 }
3344
3345 set_current_state(TASK_RUNNING);
3346 remove_wait_queue(&port->open_wait, &wait);
3347
3348 if (extra_count)
3349 port->count++;
3350 port->blocked_open--;
3351
3352 if (!retval)
3353 port->flags |= ASYNC_NORMAL_ACTIVE;
3354
3355 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3356 return retval;
3357}
3358
3359static int alloc_tmp_rbuf(struct slgt_info *info)
3360{
3361 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3362 if (info->tmp_rbuf == NULL)
3363 return -ENOMEM;
3364 return 0;
3365}
3366
3367static void free_tmp_rbuf(struct slgt_info *info)
3368{
3369 kfree(info->tmp_rbuf);
3370 info->tmp_rbuf = NULL;
3371}
3372
3373/*
3374 * allocate DMA descriptor lists.
3375 */
3376static int alloc_desc(struct slgt_info *info)
3377{
3378 unsigned int i;
3379 unsigned int pbufs;
3380
3381 /* allocate memory to hold descriptor lists */
3382 info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3383 if (info->bufs == NULL)
3384 return -ENOMEM;
3385
3386 memset(info->bufs, 0, DESC_LIST_SIZE);
3387
3388 info->rbufs = (struct slgt_desc*)info->bufs;
3389 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3390
3391 pbufs = (unsigned int)info->bufs_dma_addr;
3392
3393 /*
3394 * Build circular lists of descriptors
3395 */
3396
3397 for (i=0; i < info->rbuf_count; i++) {
3398 /* physical address of this descriptor */
3399 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3400
3401 /* physical address of next descriptor */
3402 if (i == info->rbuf_count - 1)
3403 info->rbufs[i].next = cpu_to_le32(pbufs);
3404 else
3405 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3406 set_desc_count(info->rbufs[i], DMABUFSIZE);
3407 }
3408
3409 for (i=0; i < info->tbuf_count; i++) {
3410 /* physical address of this descriptor */
3411 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3412
3413 /* physical address of next descriptor */
3414 if (i == info->tbuf_count - 1)
3415 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3416 else
3417 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3418 }
3419
3420 return 0;
3421}
3422
3423static void free_desc(struct slgt_info *info)
3424{
3425 if (info->bufs != NULL) {
3426 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3427 info->bufs = NULL;
3428 info->rbufs = NULL;
3429 info->tbufs = NULL;
3430 }
3431}
3432
3433static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3434{
3435 int i;
3436 for (i=0; i < count; i++) {
3437 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3438 return -ENOMEM;
3439 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3440 }
3441 return 0;
3442}
3443
3444static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3445{
3446 int i;
3447 for (i=0; i < count; i++) {
3448 if (bufs[i].buf == NULL)
3449 continue;
3450 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3451 bufs[i].buf = NULL;
3452 }
3453}
3454
3455static int alloc_dma_bufs(struct slgt_info *info)
3456{
3457 info->rbuf_count = 32;
3458 info->tbuf_count = 32;
3459
3460 if (alloc_desc(info) < 0 ||
3461 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3462 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3463 alloc_tmp_rbuf(info) < 0) {
3464 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3465 return -ENOMEM;
3466 }
3467 reset_rbufs(info);
3468 return 0;
3469}
3470
3471static void free_dma_bufs(struct slgt_info *info)
3472{
3473 if (info->bufs) {
3474 free_bufs(info, info->rbufs, info->rbuf_count);
3475 free_bufs(info, info->tbufs, info->tbuf_count);
3476 free_desc(info);
3477 }
3478 free_tmp_rbuf(info);
3479}
3480
3481static int claim_resources(struct slgt_info *info)
3482{
3483 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3484 DBGERR(("%s reg addr conflict, addr=%08X\n",
3485 info->device_name, info->phys_reg_addr));
3486 info->init_error = DiagStatus_AddressConflict;
3487 goto errout;
3488 }
3489 else
3490 info->reg_addr_requested = true;
3491
3492 info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3493 if (!info->reg_addr) {
3494 DBGERR(("%s can't map device registers, addr=%08X\n",
3495 info->device_name, info->phys_reg_addr));
3496 info->init_error = DiagStatus_CantAssignPciResources;
3497 goto errout;
3498 }
3499 return 0;
3500
3501errout:
3502 release_resources(info);
3503 return -ENODEV;
3504}
3505
3506static void release_resources(struct slgt_info *info)
3507{
3508 if (info->irq_requested) {
3509 free_irq(info->irq_level, info);
3510 info->irq_requested = false;
3511 }
3512
3513 if (info->reg_addr_requested) {
3514 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3515 info->reg_addr_requested = false;
3516 }
3517
3518 if (info->reg_addr) {
3519 iounmap(info->reg_addr);
3520 info->reg_addr = NULL;
3521 }
3522}
3523
3524/* Add the specified device instance data structure to the
3525 * global linked list of devices and increment the device count.
3526 */
3527static void add_device(struct slgt_info *info)
3528{
3529 char *devstr;
3530
3531 info->next_device = NULL;
3532 info->line = slgt_device_count;
3533 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3534
3535 if (info->line < MAX_DEVICES) {
3536 if (maxframe[info->line])
3537 info->max_frame_size = maxframe[info->line];
3538 }
3539
3540 slgt_device_count++;
3541
3542 if (!slgt_device_list)
3543 slgt_device_list = info;
3544 else {
3545 struct slgt_info *current_dev = slgt_device_list;
3546 while(current_dev->next_device)
3547 current_dev = current_dev->next_device;
3548 current_dev->next_device = info;
3549 }
3550
3551 if (info->max_frame_size < 4096)
3552 info->max_frame_size = 4096;
3553 else if (info->max_frame_size > 65535)
3554 info->max_frame_size = 65535;
3555
3556 switch(info->pdev->device) {
3557 case SYNCLINK_GT_DEVICE_ID:
3558 devstr = "GT";
3559 break;
3560 case SYNCLINK_GT2_DEVICE_ID:
3561 devstr = "GT2";
3562 break;
3563 case SYNCLINK_GT4_DEVICE_ID:
3564 devstr = "GT4";
3565 break;
3566 case SYNCLINK_AC_DEVICE_ID:
3567 devstr = "AC";
3568 info->params.mode = MGSL_MODE_ASYNC;
3569 break;
3570 default:
3571 devstr = "(unknown model)";
3572 }
3573 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3574 devstr, info->device_name, info->phys_reg_addr,
3575 info->irq_level, info->max_frame_size);
3576
3577#if SYNCLINK_GENERIC_HDLC
3578 hdlcdev_init(info);
3579#endif
3580}
3581
3582static const struct tty_port_operations slgt_port_ops = {
3583 .carrier_raised = carrier_raised,
3584 .dtr_rts = dtr_rts,
3585};
3586
3587/*
3588 * allocate device instance structure, return NULL on failure
3589 */
3590static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3591{
3592 struct slgt_info *info;
3593
3594 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3595
3596 if (!info) {
3597 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3598 driver_name, adapter_num, port_num));
3599 } else {
3600 tty_port_init(&info->port);
3601 info->port.ops = &slgt_port_ops;
3602 info->magic = MGSL_MAGIC;
3603 INIT_WORK(&info->task, bh_handler);
3604 info->max_frame_size = 4096;
3605 info->base_clock = 14745600;
3606 info->rbuf_fill_level = DMABUFSIZE;
3607 info->port.close_delay = 5*HZ/10;
3608 info->port.closing_wait = 30*HZ;
3609 init_waitqueue_head(&info->status_event_wait_q);
3610 init_waitqueue_head(&info->event_wait_q);
3611 spin_lock_init(&info->netlock);
3612 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3613 info->idle_mode = HDLC_TXIDLE_FLAGS;
3614 info->adapter_num = adapter_num;
3615 info->port_num = port_num;
3616
3617 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3618 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3619
3620 /* Copy configuration info to device instance data */
3621 info->pdev = pdev;
3622 info->irq_level = pdev->irq;
3623 info->phys_reg_addr = pci_resource_start(pdev,0);
3624
3625 info->bus_type = MGSL_BUS_TYPE_PCI;
3626 info->irq_flags = IRQF_SHARED;
3627
3628 info->init_error = -1; /* assume error, set to 0 on successful init */
3629 }
3630
3631 return info;
3632}
3633
3634static void device_init(int adapter_num, struct pci_dev *pdev)
3635{
3636 struct slgt_info *port_array[SLGT_MAX_PORTS];
3637 int i;
3638 int port_count = 1;
3639
3640 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3641 port_count = 2;
3642 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3643 port_count = 4;
3644
3645 /* allocate device instances for all ports */
3646 for (i=0; i < port_count; ++i) {
3647 port_array[i] = alloc_dev(adapter_num, i, pdev);
3648 if (port_array[i] == NULL) {
3649 for (--i; i >= 0; --i)
3650 kfree(port_array[i]);
3651 return;
3652 }
3653 }
3654
3655 /* give copy of port_array to all ports and add to device list */
3656 for (i=0; i < port_count; ++i) {
3657 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3658 add_device(port_array[i]);
3659 port_array[i]->port_count = port_count;
3660 spin_lock_init(&port_array[i]->lock);
3661 }
3662
3663 /* Allocate and claim adapter resources */
3664 if (!claim_resources(port_array[0])) {
3665
3666 alloc_dma_bufs(port_array[0]);
3667
3668 /* copy resource information from first port to others */
3669 for (i = 1; i < port_count; ++i) {
3670 port_array[i]->irq_level = port_array[0]->irq_level;
3671 port_array[i]->reg_addr = port_array[0]->reg_addr;
3672 alloc_dma_bufs(port_array[i]);
3673 }
3674
3675 if (request_irq(port_array[0]->irq_level,
3676 slgt_interrupt,
3677 port_array[0]->irq_flags,
3678 port_array[0]->device_name,
3679 port_array[0]) < 0) {
3680 DBGERR(("%s request_irq failed IRQ=%d\n",
3681 port_array[0]->device_name,
3682 port_array[0]->irq_level));
3683 } else {
3684 port_array[0]->irq_requested = true;
3685 adapter_test(port_array[0]);
3686 for (i=1 ; i < port_count ; i++) {
3687 port_array[i]->init_error = port_array[0]->init_error;
3688 port_array[i]->gpio_present = port_array[0]->gpio_present;
3689 }
3690 }
3691 }
3692
3693 for (i=0; i < port_count; ++i)
3694 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
3695}
3696
3697static int __devinit init_one(struct pci_dev *dev,
3698 const struct pci_device_id *ent)
3699{
3700 if (pci_enable_device(dev)) {
3701 printk("error enabling pci device %p\n", dev);
3702 return -EIO;
3703 }
3704 pci_set_master(dev);
3705 device_init(slgt_device_count, dev);
3706 return 0;
3707}
3708
3709static void __devexit remove_one(struct pci_dev *dev)
3710{
3711}
3712
3713static const struct tty_operations ops = {
3714 .open = open,
3715 .close = close,
3716 .write = write,
3717 .put_char = put_char,
3718 .flush_chars = flush_chars,
3719 .write_room = write_room,
3720 .chars_in_buffer = chars_in_buffer,
3721 .flush_buffer = flush_buffer,
3722 .ioctl = ioctl,
3723 .compat_ioctl = slgt_compat_ioctl,
3724 .throttle = throttle,
3725 .unthrottle = unthrottle,
3726 .send_xchar = send_xchar,
3727 .break_ctl = set_break,
3728 .wait_until_sent = wait_until_sent,
3729 .set_termios = set_termios,
3730 .stop = tx_hold,
3731 .start = tx_release,
3732 .hangup = hangup,
3733 .tiocmget = tiocmget,
3734 .tiocmset = tiocmset,
3735 .get_icount = get_icount,
3736 .proc_fops = &synclink_gt_proc_fops,
3737};
3738
3739static void slgt_cleanup(void)
3740{
3741 int rc;
3742 struct slgt_info *info;
3743 struct slgt_info *tmp;
3744
3745 printk(KERN_INFO "unload %s\n", driver_name);
3746
3747 if (serial_driver) {
3748 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3749 tty_unregister_device(serial_driver, info->line);
3750 if ((rc = tty_unregister_driver(serial_driver)))
3751 DBGERR(("tty_unregister_driver error=%d\n", rc));
3752 put_tty_driver(serial_driver);
3753 }
3754
3755 /* reset devices */
3756 info = slgt_device_list;
3757 while(info) {
3758 reset_port(info);
3759 info = info->next_device;
3760 }
3761
3762 /* release devices */
3763 info = slgt_device_list;
3764 while(info) {
3765#if SYNCLINK_GENERIC_HDLC
3766 hdlcdev_exit(info);
3767#endif
3768 free_dma_bufs(info);
3769 free_tmp_rbuf(info);
3770 if (info->port_num == 0)
3771 release_resources(info);
3772 tmp = info;
3773 info = info->next_device;
3774 kfree(tmp);
3775 }
3776
3777 if (pci_registered)
3778 pci_unregister_driver(&pci_driver);
3779}
3780
3781/*
3782 * Driver initialization entry point.
3783 */
3784static int __init slgt_init(void)
3785{
3786 int rc;
3787
3788 printk(KERN_INFO "%s\n", driver_name);
3789
3790 serial_driver = alloc_tty_driver(MAX_DEVICES);
3791 if (!serial_driver) {
3792 printk("%s can't allocate tty driver\n", driver_name);
3793 return -ENOMEM;
3794 }
3795
3796 /* Initialize the tty_driver structure */
3797
3798 serial_driver->owner = THIS_MODULE;
3799 serial_driver->driver_name = tty_driver_name;
3800 serial_driver->name = tty_dev_prefix;
3801 serial_driver->major = ttymajor;
3802 serial_driver->minor_start = 64;
3803 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3804 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3805 serial_driver->init_termios = tty_std_termios;
3806 serial_driver->init_termios.c_cflag =
3807 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3808 serial_driver->init_termios.c_ispeed = 9600;
3809 serial_driver->init_termios.c_ospeed = 9600;
3810 serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3811 tty_set_operations(serial_driver, &ops);
3812 if ((rc = tty_register_driver(serial_driver)) < 0) {
3813 DBGERR(("%s can't register serial driver\n", driver_name));
3814 put_tty_driver(serial_driver);
3815 serial_driver = NULL;
3816 goto error;
3817 }
3818
3819 printk(KERN_INFO "%s, tty major#%d\n",
3820 driver_name, serial_driver->major);
3821
3822 slgt_device_count = 0;
3823 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3824 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3825 goto error;
3826 }
3827 pci_registered = true;
3828
3829 if (!slgt_device_list)
3830 printk("%s no devices found\n",driver_name);
3831
3832 return 0;
3833
3834error:
3835 slgt_cleanup();
3836 return rc;
3837}
3838
3839static void __exit slgt_exit(void)
3840{
3841 slgt_cleanup();
3842}
3843
3844module_init(slgt_init);
3845module_exit(slgt_exit);
3846
3847/*
3848 * register access routines
3849 */
3850
3851#define CALC_REGADDR() \
3852 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3853 if (addr >= 0x80) \
3854 reg_addr += (info->port_num) * 32; \
3855 else if (addr >= 0x40) \
3856 reg_addr += (info->port_num) * 16;
3857
3858static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3859{
3860 CALC_REGADDR();
3861 return readb((void __iomem *)reg_addr);
3862}
3863
3864static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3865{
3866 CALC_REGADDR();
3867 writeb(value, (void __iomem *)reg_addr);
3868}
3869
3870static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3871{
3872 CALC_REGADDR();
3873 return readw((void __iomem *)reg_addr);
3874}
3875
3876static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3877{
3878 CALC_REGADDR();
3879 writew(value, (void __iomem *)reg_addr);
3880}
3881
3882static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3883{
3884 CALC_REGADDR();
3885 return readl((void __iomem *)reg_addr);
3886}
3887
3888static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3889{
3890 CALC_REGADDR();
3891 writel(value, (void __iomem *)reg_addr);
3892}
3893
3894static void rdma_reset(struct slgt_info *info)
3895{
3896 unsigned int i;
3897
3898 /* set reset bit */
3899 wr_reg32(info, RDCSR, BIT1);
3900
3901 /* wait for enable bit cleared */
3902 for(i=0 ; i < 1000 ; i++)
3903 if (!(rd_reg32(info, RDCSR) & BIT0))
3904 break;
3905}
3906
3907static void tdma_reset(struct slgt_info *info)
3908{
3909 unsigned int i;
3910
3911 /* set reset bit */
3912 wr_reg32(info, TDCSR, BIT1);
3913
3914 /* wait for enable bit cleared */
3915 for(i=0 ; i < 1000 ; i++)
3916 if (!(rd_reg32(info, TDCSR) & BIT0))
3917 break;
3918}
3919
3920/*
3921 * enable internal loopback
3922 * TxCLK and RxCLK are generated from BRG
3923 * and TxD is looped back to RxD internally.
3924 */
3925static void enable_loopback(struct slgt_info *info)
3926{
3927 /* SCR (serial control) BIT2=looopback enable */
3928 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3929
3930 if (info->params.mode != MGSL_MODE_ASYNC) {
3931 /* CCR (clock control)
3932 * 07..05 tx clock source (010 = BRG)
3933 * 04..02 rx clock source (010 = BRG)
3934 * 01 auxclk enable (0 = disable)
3935 * 00 BRG enable (1 = enable)
3936 *
3937 * 0100 1001
3938 */
3939 wr_reg8(info, CCR, 0x49);
3940
3941 /* set speed if available, otherwise use default */
3942 if (info->params.clock_speed)
3943 set_rate(info, info->params.clock_speed);
3944 else
3945 set_rate(info, 3686400);
3946 }
3947}
3948
3949/*
3950 * set baud rate generator to specified rate
3951 */
3952static void set_rate(struct slgt_info *info, u32 rate)
3953{
3954 unsigned int div;
3955 unsigned int osc = info->base_clock;
3956
3957 /* div = osc/rate - 1
3958 *
3959 * Round div up if osc/rate is not integer to
3960 * force to next slowest rate.
3961 */
3962
3963 if (rate) {
3964 div = osc/rate;
3965 if (!(osc % rate) && div)
3966 div--;
3967 wr_reg16(info, BDR, (unsigned short)div);
3968 }
3969}
3970
3971static void rx_stop(struct slgt_info *info)
3972{
3973 unsigned short val;
3974
3975 /* disable and reset receiver */
3976 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3977 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3978 wr_reg16(info, RCR, val); /* clear reset bit */
3979
3980 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3981
3982 /* clear pending rx interrupts */
3983 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3984
3985 rdma_reset(info);
3986
3987 info->rx_enabled = false;
3988 info->rx_restart = false;
3989}
3990
3991static void rx_start(struct slgt_info *info)
3992{
3993 unsigned short val;
3994
3995 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3996
3997 /* clear pending rx overrun IRQ */
3998 wr_reg16(info, SSR, IRQ_RXOVER);
3999
4000 /* reset and disable receiver */
4001 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
4002 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
4003 wr_reg16(info, RCR, val); /* clear reset bit */
4004
4005 rdma_reset(info);
4006 reset_rbufs(info);
4007
4008 if (info->rx_pio) {
4009 /* rx request when rx FIFO not empty */
4010 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
4011 slgt_irq_on(info, IRQ_RXDATA);
4012 if (info->params.mode == MGSL_MODE_ASYNC) {
4013 /* enable saving of rx status */
4014 wr_reg32(info, RDCSR, BIT6);
4015 }
4016 } else {
4017 /* rx request when rx FIFO half full */
4018 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
4019 /* set 1st descriptor address */
4020 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
4021
4022 if (info->params.mode != MGSL_MODE_ASYNC) {
4023 /* enable rx DMA and DMA interrupt */
4024 wr_reg32(info, RDCSR, (BIT2 + BIT0));
4025 } else {
4026 /* enable saving of rx status, rx DMA and DMA interrupt */
4027 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
4028 }
4029 }
4030
4031 slgt_irq_on(info, IRQ_RXOVER);
4032
4033 /* enable receiver */
4034 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
4035
4036 info->rx_restart = false;
4037 info->rx_enabled = true;
4038}
4039
4040static void tx_start(struct slgt_info *info)
4041{
4042 if (!info->tx_enabled) {
4043 wr_reg16(info, TCR,
4044 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
4045 info->tx_enabled = true;
4046 }
4047
4048 if (desc_count(info->tbufs[info->tbuf_start])) {
4049 info->drop_rts_on_tx_done = false;
4050
4051 if (info->params.mode != MGSL_MODE_ASYNC) {
4052 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
4053 get_signals(info);
4054 if (!(info->signals & SerialSignal_RTS)) {
4055 info->signals |= SerialSignal_RTS;
4056 set_signals(info);
4057 info->drop_rts_on_tx_done = true;
4058 }
4059 }
4060
4061 slgt_irq_off(info, IRQ_TXDATA);
4062 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
4063 /* clear tx idle and underrun status bits */
4064 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4065 } else {
4066 slgt_irq_off(info, IRQ_TXDATA);
4067 slgt_irq_on(info, IRQ_TXIDLE);
4068 /* clear tx idle status bit */
4069 wr_reg16(info, SSR, IRQ_TXIDLE);
4070 }
4071 /* set 1st descriptor address and start DMA */
4072 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
4073 wr_reg32(info, TDCSR, BIT2 + BIT0);
4074 info->tx_active = true;
4075 }
4076}
4077
4078static void tx_stop(struct slgt_info *info)
4079{
4080 unsigned short val;
4081
4082 del_timer(&info->tx_timer);
4083
4084 tdma_reset(info);
4085
4086 /* reset and disable transmitter */
4087 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
4088 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
4089
4090 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
4091
4092 /* clear tx idle and underrun status bit */
4093 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4094
4095 reset_tbufs(info);
4096
4097 info->tx_enabled = false;
4098 info->tx_active = false;
4099}
4100
4101static void reset_port(struct slgt_info *info)
4102{
4103 if (!info->reg_addr)
4104 return;
4105
4106 tx_stop(info);
4107 rx_stop(info);
4108
4109 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4110 set_signals(info);
4111
4112 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4113}
4114
4115static void reset_adapter(struct slgt_info *info)
4116{
4117 int i;
4118 for (i=0; i < info->port_count; ++i) {
4119 if (info->port_array[i])
4120 reset_port(info->port_array[i]);
4121 }
4122}
4123
4124static void async_mode(struct slgt_info *info)
4125{
4126 unsigned short val;
4127
4128 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4129 tx_stop(info);
4130 rx_stop(info);
4131
4132 /* TCR (tx control)
4133 *
4134 * 15..13 mode, 010=async
4135 * 12..10 encoding, 000=NRZ
4136 * 09 parity enable
4137 * 08 1=odd parity, 0=even parity
4138 * 07 1=RTS driver control
4139 * 06 1=break enable
4140 * 05..04 character length
4141 * 00=5 bits
4142 * 01=6 bits
4143 * 10=7 bits
4144 * 11=8 bits
4145 * 03 0=1 stop bit, 1=2 stop bits
4146 * 02 reset
4147 * 01 enable
4148 * 00 auto-CTS enable
4149 */
4150 val = 0x4000;
4151
4152 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4153 val |= BIT7;
4154
4155 if (info->params.parity != ASYNC_PARITY_NONE) {
4156 val |= BIT9;
4157 if (info->params.parity == ASYNC_PARITY_ODD)
4158 val |= BIT8;
4159 }
4160
4161 switch (info->params.data_bits)
4162 {
4163 case 6: val |= BIT4; break;
4164 case 7: val |= BIT5; break;
4165 case 8: val |= BIT5 + BIT4; break;
4166 }
4167
4168 if (info->params.stop_bits != 1)
4169 val |= BIT3;
4170
4171 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4172 val |= BIT0;
4173
4174 wr_reg16(info, TCR, val);
4175
4176 /* RCR (rx control)
4177 *
4178 * 15..13 mode, 010=async
4179 * 12..10 encoding, 000=NRZ
4180 * 09 parity enable
4181 * 08 1=odd parity, 0=even parity
4182 * 07..06 reserved, must be 0
4183 * 05..04 character length
4184 * 00=5 bits
4185 * 01=6 bits
4186 * 10=7 bits
4187 * 11=8 bits
4188 * 03 reserved, must be zero
4189 * 02 reset
4190 * 01 enable
4191 * 00 auto-DCD enable
4192 */
4193 val = 0x4000;
4194
4195 if (info->params.parity != ASYNC_PARITY_NONE) {
4196 val |= BIT9;
4197 if (info->params.parity == ASYNC_PARITY_ODD)
4198 val |= BIT8;
4199 }
4200
4201 switch (info->params.data_bits)
4202 {
4203 case 6: val |= BIT4; break;
4204 case 7: val |= BIT5; break;
4205 case 8: val |= BIT5 + BIT4; break;
4206 }
4207
4208 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4209 val |= BIT0;
4210
4211 wr_reg16(info, RCR, val);
4212
4213 /* CCR (clock control)
4214 *
4215 * 07..05 011 = tx clock source is BRG/16
4216 * 04..02 010 = rx clock source is BRG
4217 * 01 0 = auxclk disabled
4218 * 00 1 = BRG enabled
4219 *
4220 * 0110 1001
4221 */
4222 wr_reg8(info, CCR, 0x69);
4223
4224 msc_set_vcr(info);
4225
4226 /* SCR (serial control)
4227 *
4228 * 15 1=tx req on FIFO half empty
4229 * 14 1=rx req on FIFO half full
4230 * 13 tx data IRQ enable
4231 * 12 tx idle IRQ enable
4232 * 11 rx break on IRQ enable
4233 * 10 rx data IRQ enable
4234 * 09 rx break off IRQ enable
4235 * 08 overrun IRQ enable
4236 * 07 DSR IRQ enable
4237 * 06 CTS IRQ enable
4238 * 05 DCD IRQ enable
4239 * 04 RI IRQ enable
4240 * 03 0=16x sampling, 1=8x sampling
4241 * 02 1=txd->rxd internal loopback enable
4242 * 01 reserved, must be zero
4243 * 00 1=master IRQ enable
4244 */
4245 val = BIT15 + BIT14 + BIT0;
4246 /* JCR[8] : 1 = x8 async mode feature available */
4247 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4248 ((info->base_clock < (info->params.data_rate * 16)) ||
4249 (info->base_clock % (info->params.data_rate * 16)))) {
4250 /* use 8x sampling */
4251 val |= BIT3;
4252 set_rate(info, info->params.data_rate * 8);
4253 } else {
4254 /* use 16x sampling */
4255 set_rate(info, info->params.data_rate * 16);
4256 }
4257 wr_reg16(info, SCR, val);
4258
4259 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4260
4261 if (info->params.loopback)
4262 enable_loopback(info);
4263}
4264
4265static void sync_mode(struct slgt_info *info)
4266{
4267 unsigned short val;
4268
4269 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4270 tx_stop(info);
4271 rx_stop(info);
4272
4273 /* TCR (tx control)
4274 *
4275 * 15..13 mode
4276 * 000=HDLC/SDLC
4277 * 001=raw bit synchronous
4278 * 010=asynchronous/isochronous
4279 * 011=monosync byte synchronous
4280 * 100=bisync byte synchronous
4281 * 101=xsync byte synchronous
4282 * 12..10 encoding
4283 * 09 CRC enable
4284 * 08 CRC32
4285 * 07 1=RTS driver control
4286 * 06 preamble enable
4287 * 05..04 preamble length
4288 * 03 share open/close flag
4289 * 02 reset
4290 * 01 enable
4291 * 00 auto-CTS enable
4292 */
4293 val = BIT2;
4294
4295 switch(info->params.mode) {
4296 case MGSL_MODE_XSYNC:
4297 val |= BIT15 + BIT13;
4298 break;
4299 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4300 case MGSL_MODE_BISYNC: val |= BIT15; break;
4301 case MGSL_MODE_RAW: val |= BIT13; break;
4302 }
4303 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4304 val |= BIT7;
4305
4306 switch(info->params.encoding)
4307 {
4308 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4309 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4310 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4311 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4312 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4313 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4314 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4315 }
4316
4317 switch (info->params.crc_type & HDLC_CRC_MASK)
4318 {
4319 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4320 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4321 }
4322
4323 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4324 val |= BIT6;
4325
4326 switch (info->params.preamble_length)
4327 {
4328 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4329 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4330 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4331 }
4332
4333 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4334 val |= BIT0;
4335
4336 wr_reg16(info, TCR, val);
4337
4338 /* TPR (transmit preamble) */
4339
4340 switch (info->params.preamble)
4341 {
4342 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4343 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4344 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4345 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4346 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4347 default: val = 0x7e; break;
4348 }
4349 wr_reg8(info, TPR, (unsigned char)val);
4350
4351 /* RCR (rx control)
4352 *
4353 * 15..13 mode
4354 * 000=HDLC/SDLC
4355 * 001=raw bit synchronous
4356 * 010=asynchronous/isochronous
4357 * 011=monosync byte synchronous
4358 * 100=bisync byte synchronous
4359 * 101=xsync byte synchronous
4360 * 12..10 encoding
4361 * 09 CRC enable
4362 * 08 CRC32
4363 * 07..03 reserved, must be 0
4364 * 02 reset
4365 * 01 enable
4366 * 00 auto-DCD enable
4367 */
4368 val = 0;
4369
4370 switch(info->params.mode) {
4371 case MGSL_MODE_XSYNC:
4372 val |= BIT15 + BIT13;
4373 break;
4374 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4375 case MGSL_MODE_BISYNC: val |= BIT15; break;
4376 case MGSL_MODE_RAW: val |= BIT13; break;
4377 }
4378
4379 switch(info->params.encoding)
4380 {
4381 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4382 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4383 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4384 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4385 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4386 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4387 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4388 }
4389
4390 switch (info->params.crc_type & HDLC_CRC_MASK)
4391 {
4392 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4393 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4394 }
4395
4396 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4397 val |= BIT0;
4398
4399 wr_reg16(info, RCR, val);
4400
4401 /* CCR (clock control)
4402 *
4403 * 07..05 tx clock source
4404 * 04..02 rx clock source
4405 * 01 auxclk enable
4406 * 00 BRG enable
4407 */
4408 val = 0;
4409
4410 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4411 {
4412 // when RxC source is DPLL, BRG generates 16X DPLL
4413 // reference clock, so take TxC from BRG/16 to get
4414 // transmit clock at actual data rate
4415 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4416 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4417 else
4418 val |= BIT6; /* 010, txclk = BRG */
4419 }
4420 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4421 val |= BIT7; /* 100, txclk = DPLL Input */
4422 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4423 val |= BIT5; /* 001, txclk = RXC Input */
4424
4425 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4426 val |= BIT3; /* 010, rxclk = BRG */
4427 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4428 val |= BIT4; /* 100, rxclk = DPLL */
4429 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4430 val |= BIT2; /* 001, rxclk = TXC Input */
4431
4432 if (info->params.clock_speed)
4433 val |= BIT1 + BIT0;
4434
4435 wr_reg8(info, CCR, (unsigned char)val);
4436
4437 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4438 {
4439 // program DPLL mode
4440 switch(info->params.encoding)
4441 {
4442 case HDLC_ENCODING_BIPHASE_MARK:
4443 case HDLC_ENCODING_BIPHASE_SPACE:
4444 val = BIT7; break;
4445 case HDLC_ENCODING_BIPHASE_LEVEL:
4446 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4447 val = BIT7 + BIT6; break;
4448 default: val = BIT6; // NRZ encodings
4449 }
4450 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4451
4452 // DPLL requires a 16X reference clock from BRG
4453 set_rate(info, info->params.clock_speed * 16);
4454 }
4455 else
4456 set_rate(info, info->params.clock_speed);
4457
4458 tx_set_idle(info);
4459
4460 msc_set_vcr(info);
4461
4462 /* SCR (serial control)
4463 *
4464 * 15 1=tx req on FIFO half empty
4465 * 14 1=rx req on FIFO half full
4466 * 13 tx data IRQ enable
4467 * 12 tx idle IRQ enable
4468 * 11 underrun IRQ enable
4469 * 10 rx data IRQ enable
4470 * 09 rx idle IRQ enable
4471 * 08 overrun IRQ enable
4472 * 07 DSR IRQ enable
4473 * 06 CTS IRQ enable
4474 * 05 DCD IRQ enable
4475 * 04 RI IRQ enable
4476 * 03 reserved, must be zero
4477 * 02 1=txd->rxd internal loopback enable
4478 * 01 reserved, must be zero
4479 * 00 1=master IRQ enable
4480 */
4481 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4482
4483 if (info->params.loopback)
4484 enable_loopback(info);
4485}
4486
4487/*
4488 * set transmit idle mode
4489 */
4490static void tx_set_idle(struct slgt_info *info)
4491{
4492 unsigned char val;
4493 unsigned short tcr;
4494
4495 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4496 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4497 */
4498 tcr = rd_reg16(info, TCR);
4499 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4500 /* disable preamble, set idle size to 16 bits */
4501 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4502 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4503 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4504 } else if (!(tcr & BIT6)) {
4505 /* preamble is disabled, set idle size to 8 bits */
4506 tcr &= ~(BIT5 + BIT4);
4507 }
4508 wr_reg16(info, TCR, tcr);
4509
4510 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4511 /* LSB of custom tx idle specified in tx idle register */
4512 val = (unsigned char)(info->idle_mode & 0xff);
4513 } else {
4514 /* standard 8 bit idle patterns */
4515 switch(info->idle_mode)
4516 {
4517 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4518 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4519 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4520 case HDLC_TXIDLE_ZEROS:
4521 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4522 default: val = 0xff;
4523 }
4524 }
4525
4526 wr_reg8(info, TIR, val);
4527}
4528
4529/*
4530 * get state of V24 status (input) signals
4531 */
4532static void get_signals(struct slgt_info *info)
4533{
4534 unsigned short status = rd_reg16(info, SSR);
4535
4536 /* clear all serial signals except DTR and RTS */
4537 info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4538
4539 if (status & BIT3)
4540 info->signals |= SerialSignal_DSR;
4541 if (status & BIT2)
4542 info->signals |= SerialSignal_CTS;
4543 if (status & BIT1)
4544 info->signals |= SerialSignal_DCD;
4545 if (status & BIT0)
4546 info->signals |= SerialSignal_RI;
4547}
4548
4549/*
4550 * set V.24 Control Register based on current configuration
4551 */
4552static void msc_set_vcr(struct slgt_info *info)
4553{
4554 unsigned char val = 0;
4555
4556 /* VCR (V.24 control)
4557 *
4558 * 07..04 serial IF select
4559 * 03 DTR
4560 * 02 RTS
4561 * 01 LL
4562 * 00 RL
4563 */
4564
4565 switch(info->if_mode & MGSL_INTERFACE_MASK)
4566 {
4567 case MGSL_INTERFACE_RS232:
4568 val |= BIT5; /* 0010 */
4569 break;
4570 case MGSL_INTERFACE_V35:
4571 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4572 break;
4573 case MGSL_INTERFACE_RS422:
4574 val |= BIT6; /* 0100 */
4575 break;
4576 }
4577
4578 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4579 val |= BIT4;
4580 if (info->signals & SerialSignal_DTR)
4581 val |= BIT3;
4582 if (info->signals & SerialSignal_RTS)
4583 val |= BIT2;
4584 if (info->if_mode & MGSL_INTERFACE_LL)
4585 val |= BIT1;
4586 if (info->if_mode & MGSL_INTERFACE_RL)
4587 val |= BIT0;
4588 wr_reg8(info, VCR, val);
4589}
4590
4591/*
4592 * set state of V24 control (output) signals
4593 */
4594static void set_signals(struct slgt_info *info)
4595{
4596 unsigned char val = rd_reg8(info, VCR);
4597 if (info->signals & SerialSignal_DTR)
4598 val |= BIT3;
4599 else
4600 val &= ~BIT3;
4601 if (info->signals & SerialSignal_RTS)
4602 val |= BIT2;
4603 else
4604 val &= ~BIT2;
4605 wr_reg8(info, VCR, val);
4606}
4607
4608/*
4609 * free range of receive DMA buffers (i to last)
4610 */
4611static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4612{
4613 int done = 0;
4614
4615 while(!done) {
4616 /* reset current buffer for reuse */
4617 info->rbufs[i].status = 0;
4618 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4619 if (i == last)
4620 done = 1;
4621 if (++i == info->rbuf_count)
4622 i = 0;
4623 }
4624 info->rbuf_current = i;
4625}
4626
4627/*
4628 * mark all receive DMA buffers as free
4629 */
4630static void reset_rbufs(struct slgt_info *info)
4631{
4632 free_rbufs(info, 0, info->rbuf_count - 1);
4633 info->rbuf_fill_index = 0;
4634 info->rbuf_fill_count = 0;
4635}
4636
4637/*
4638 * pass receive HDLC frame to upper layer
4639 *
4640 * return true if frame available, otherwise false
4641 */
4642static bool rx_get_frame(struct slgt_info *info)
4643{
4644 unsigned int start, end;
4645 unsigned short status;
4646 unsigned int framesize = 0;
4647 unsigned long flags;
4648 struct tty_struct *tty = info->port.tty;
4649 unsigned char addr_field = 0xff;
4650 unsigned int crc_size = 0;
4651
4652 switch (info->params.crc_type & HDLC_CRC_MASK) {
4653 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4654 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4655 }
4656
4657check_again:
4658
4659 framesize = 0;
4660 addr_field = 0xff;
4661 start = end = info->rbuf_current;
4662
4663 for (;;) {
4664 if (!desc_complete(info->rbufs[end]))
4665 goto cleanup;
4666
4667 if (framesize == 0 && info->params.addr_filter != 0xff)
4668 addr_field = info->rbufs[end].buf[0];
4669
4670 framesize += desc_count(info->rbufs[end]);
4671
4672 if (desc_eof(info->rbufs[end]))
4673 break;
4674
4675 if (++end == info->rbuf_count)
4676 end = 0;
4677
4678 if (end == info->rbuf_current) {
4679 if (info->rx_enabled){
4680 spin_lock_irqsave(&info->lock,flags);
4681 rx_start(info);
4682 spin_unlock_irqrestore(&info->lock,flags);
4683 }
4684 goto cleanup;
4685 }
4686 }
4687
4688 /* status
4689 *
4690 * 15 buffer complete
4691 * 14..06 reserved
4692 * 05..04 residue
4693 * 02 eof (end of frame)
4694 * 01 CRC error
4695 * 00 abort
4696 */
4697 status = desc_status(info->rbufs[end]);
4698
4699 /* ignore CRC bit if not using CRC (bit is undefined) */
4700 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4701 status &= ~BIT1;
4702
4703 if (framesize == 0 ||
4704 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4705 free_rbufs(info, start, end);
4706 goto check_again;
4707 }
4708
4709 if (framesize < (2 + crc_size) || status & BIT0) {
4710 info->icount.rxshort++;
4711 framesize = 0;
4712 } else if (status & BIT1) {
4713 info->icount.rxcrc++;
4714 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4715 framesize = 0;
4716 }
4717
4718#if SYNCLINK_GENERIC_HDLC
4719 if (framesize == 0) {
4720 info->netdev->stats.rx_errors++;
4721 info->netdev->stats.rx_frame_errors++;
4722 }
4723#endif
4724
4725 DBGBH(("%s rx frame status=%04X size=%d\n",
4726 info->device_name, status, framesize));
4727 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4728
4729 if (framesize) {
4730 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4731 framesize -= crc_size;
4732 crc_size = 0;
4733 }
4734
4735 if (framesize > info->max_frame_size + crc_size)
4736 info->icount.rxlong++;
4737 else {
4738 /* copy dma buffer(s) to contiguous temp buffer */
4739 int copy_count = framesize;
4740 int i = start;
4741 unsigned char *p = info->tmp_rbuf;
4742 info->tmp_rbuf_count = framesize;
4743
4744 info->icount.rxok++;
4745
4746 while(copy_count) {
4747 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4748 memcpy(p, info->rbufs[i].buf, partial_count);
4749 p += partial_count;
4750 copy_count -= partial_count;
4751 if (++i == info->rbuf_count)
4752 i = 0;
4753 }
4754
4755 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4756 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4757 framesize++;
4758 }
4759
4760#if SYNCLINK_GENERIC_HDLC
4761 if (info->netcount)
4762 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4763 else
4764#endif
4765 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4766 }
4767 }
4768 free_rbufs(info, start, end);
4769 return true;
4770
4771cleanup:
4772 return false;
4773}
4774
4775/*
4776 * pass receive buffer (RAW synchronous mode) to tty layer
4777 * return true if buffer available, otherwise false
4778 */
4779static bool rx_get_buf(struct slgt_info *info)
4780{
4781 unsigned int i = info->rbuf_current;
4782 unsigned int count;
4783
4784 if (!desc_complete(info->rbufs[i]))
4785 return false;
4786 count = desc_count(info->rbufs[i]);
4787 switch(info->params.mode) {
4788 case MGSL_MODE_MONOSYNC:
4789 case MGSL_MODE_BISYNC:
4790 case MGSL_MODE_XSYNC:
4791 /* ignore residue in byte synchronous modes */
4792 if (desc_residue(info->rbufs[i]))
4793 count--;
4794 break;
4795 }
4796 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4797 DBGINFO(("rx_get_buf size=%d\n", count));
4798 if (count)
4799 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4800 info->flag_buf, count);
4801 free_rbufs(info, i, i);
4802 return true;
4803}
4804
4805static void reset_tbufs(struct slgt_info *info)
4806{
4807 unsigned int i;
4808 info->tbuf_current = 0;
4809 for (i=0 ; i < info->tbuf_count ; i++) {
4810 info->tbufs[i].status = 0;
4811 info->tbufs[i].count = 0;
4812 }
4813}
4814
4815/*
4816 * return number of free transmit DMA buffers
4817 */
4818static unsigned int free_tbuf_count(struct slgt_info *info)
4819{
4820 unsigned int count = 0;
4821 unsigned int i = info->tbuf_current;
4822
4823 do
4824 {
4825 if (desc_count(info->tbufs[i]))
4826 break; /* buffer in use */
4827 ++count;
4828 if (++i == info->tbuf_count)
4829 i=0;
4830 } while (i != info->tbuf_current);
4831
4832 /* if tx DMA active, last zero count buffer is in use */
4833 if (count && (rd_reg32(info, TDCSR) & BIT0))
4834 --count;
4835
4836 return count;
4837}
4838
4839/*
4840 * return number of bytes in unsent transmit DMA buffers
4841 * and the serial controller tx FIFO
4842 */
4843static unsigned int tbuf_bytes(struct slgt_info *info)
4844{
4845 unsigned int total_count = 0;
4846 unsigned int i = info->tbuf_current;
4847 unsigned int reg_value;
4848 unsigned int count;
4849 unsigned int active_buf_count = 0;
4850
4851 /*
4852 * Add descriptor counts for all tx DMA buffers.
4853 * If count is zero (cleared by DMA controller after read),
4854 * the buffer is complete or is actively being read from.
4855 *
4856 * Record buf_count of last buffer with zero count starting
4857 * from current ring position. buf_count is mirror
4858 * copy of count and is not cleared by serial controller.
4859 * If DMA controller is active, that buffer is actively
4860 * being read so add to total.
4861 */
4862 do {
4863 count = desc_count(info->tbufs[i]);
4864 if (count)
4865 total_count += count;
4866 else if (!total_count)
4867 active_buf_count = info->tbufs[i].buf_count;
4868 if (++i == info->tbuf_count)
4869 i = 0;
4870 } while (i != info->tbuf_current);
4871
4872 /* read tx DMA status register */
4873 reg_value = rd_reg32(info, TDCSR);
4874
4875 /* if tx DMA active, last zero count buffer is in use */
4876 if (reg_value & BIT0)
4877 total_count += active_buf_count;
4878
4879 /* add tx FIFO count = reg_value[15..8] */
4880 total_count += (reg_value >> 8) & 0xff;
4881
4882 /* if transmitter active add one byte for shift register */
4883 if (info->tx_active)
4884 total_count++;
4885
4886 return total_count;
4887}
4888
4889/*
4890 * load data into transmit DMA buffer ring and start transmitter if needed
4891 * return true if data accepted, otherwise false (buffers full)
4892 */
4893static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4894{
4895 unsigned short count;
4896 unsigned int i;
4897 struct slgt_desc *d;
4898
4899 /* check required buffer space */
4900 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4901 return false;
4902
4903 DBGDATA(info, buf, size, "tx");
4904
4905 /*
4906 * copy data to one or more DMA buffers in circular ring
4907 * tbuf_start = first buffer for this data
4908 * tbuf_current = next free buffer
4909 *
4910 * Copy all data before making data visible to DMA controller by
4911 * setting descriptor count of the first buffer.
4912 * This prevents an active DMA controller from reading the first DMA
4913 * buffers of a frame and stopping before the final buffers are filled.
4914 */
4915
4916 info->tbuf_start = i = info->tbuf_current;
4917
4918 while (size) {
4919 d = &info->tbufs[i];
4920
4921 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4922 memcpy(d->buf, buf, count);
4923
4924 size -= count;
4925 buf += count;
4926
4927 /*
4928 * set EOF bit for last buffer of HDLC frame or
4929 * for every buffer in raw mode
4930 */
4931 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4932 info->params.mode == MGSL_MODE_RAW)
4933 set_desc_eof(*d, 1);
4934 else
4935 set_desc_eof(*d, 0);
4936
4937 /* set descriptor count for all but first buffer */
4938 if (i != info->tbuf_start)
4939 set_desc_count(*d, count);
4940 d->buf_count = count;
4941
4942 if (++i == info->tbuf_count)
4943 i = 0;
4944 }
4945
4946 info->tbuf_current = i;
4947
4948 /* set first buffer count to make new data visible to DMA controller */
4949 d = &info->tbufs[info->tbuf_start];
4950 set_desc_count(*d, d->buf_count);
4951
4952 /* start transmitter if needed and update transmit timeout */
4953 if (!info->tx_active)
4954 tx_start(info);
4955 update_tx_timer(info);
4956
4957 return true;
4958}
4959
4960static int register_test(struct slgt_info *info)
4961{
4962 static unsigned short patterns[] =
4963 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4964 static unsigned int count = ARRAY_SIZE(patterns);
4965 unsigned int i;
4966 int rc = 0;
4967
4968 for (i=0 ; i < count ; i++) {
4969 wr_reg16(info, TIR, patterns[i]);
4970 wr_reg16(info, BDR, patterns[(i+1)%count]);
4971 if ((rd_reg16(info, TIR) != patterns[i]) ||
4972 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4973 rc = -ENODEV;
4974 break;
4975 }
4976 }
4977 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4978 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4979 return rc;
4980}
4981
4982static int irq_test(struct slgt_info *info)
4983{
4984 unsigned long timeout;
4985 unsigned long flags;
4986 struct tty_struct *oldtty = info->port.tty;
4987 u32 speed = info->params.data_rate;
4988
4989 info->params.data_rate = 921600;
4990 info->port.tty = NULL;
4991
4992 spin_lock_irqsave(&info->lock, flags);
4993 async_mode(info);
4994 slgt_irq_on(info, IRQ_TXIDLE);
4995
4996 /* enable transmitter */
4997 wr_reg16(info, TCR,
4998 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4999
5000 /* write one byte and wait for tx idle */
5001 wr_reg16(info, TDR, 0);
5002
5003 /* assume failure */
5004 info->init_error = DiagStatus_IrqFailure;
5005 info->irq_occurred = false;
5006
5007 spin_unlock_irqrestore(&info->lock, flags);
5008
5009 timeout=100;
5010 while(timeout-- && !info->irq_occurred)
5011 msleep_interruptible(10);
5012
5013 spin_lock_irqsave(&info->lock,flags);
5014 reset_port(info);
5015 spin_unlock_irqrestore(&info->lock,flags);
5016
5017 info->params.data_rate = speed;
5018 info->port.tty = oldtty;
5019
5020 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
5021 return info->irq_occurred ? 0 : -ENODEV;
5022}
5023
5024static int loopback_test_rx(struct slgt_info *info)
5025{
5026 unsigned char *src, *dest;
5027 int count;
5028
5029 if (desc_complete(info->rbufs[0])) {
5030 count = desc_count(info->rbufs[0]);
5031 src = info->rbufs[0].buf;
5032 dest = info->tmp_rbuf;
5033
5034 for( ; count ; count-=2, src+=2) {
5035 /* src=data byte (src+1)=status byte */
5036 if (!(*(src+1) & (BIT9 + BIT8))) {
5037 *dest = *src;
5038 dest++;
5039 info->tmp_rbuf_count++;
5040 }
5041 }
5042 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
5043 return 1;
5044 }
5045 return 0;
5046}
5047
5048static int loopback_test(struct slgt_info *info)
5049{
5050#define TESTFRAMESIZE 20
5051
5052 unsigned long timeout;
5053 u16 count = TESTFRAMESIZE;
5054 unsigned char buf[TESTFRAMESIZE];
5055 int rc = -ENODEV;
5056 unsigned long flags;
5057
5058 struct tty_struct *oldtty = info->port.tty;
5059 MGSL_PARAMS params;
5060
5061 memcpy(¶ms, &info->params, sizeof(params));
5062
5063 info->params.mode = MGSL_MODE_ASYNC;
5064 info->params.data_rate = 921600;
5065 info->params.loopback = 1;
5066 info->port.tty = NULL;
5067
5068 /* build and send transmit frame */
5069 for (count = 0; count < TESTFRAMESIZE; ++count)
5070 buf[count] = (unsigned char)count;
5071
5072 info->tmp_rbuf_count = 0;
5073 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
5074
5075 /* program hardware for HDLC and enabled receiver */
5076 spin_lock_irqsave(&info->lock,flags);
5077 async_mode(info);
5078 rx_start(info);
5079 tx_load(info, buf, count);
5080 spin_unlock_irqrestore(&info->lock, flags);
5081
5082 /* wait for receive complete */
5083 for (timeout = 100; timeout; --timeout) {
5084 msleep_interruptible(10);
5085 if (loopback_test_rx(info)) {
5086 rc = 0;
5087 break;
5088 }
5089 }
5090
5091 /* verify received frame length and contents */
5092 if (!rc && (info->tmp_rbuf_count != count ||
5093 memcmp(buf, info->tmp_rbuf, count))) {
5094 rc = -ENODEV;
5095 }
5096
5097 spin_lock_irqsave(&info->lock,flags);
5098 reset_adapter(info);
5099 spin_unlock_irqrestore(&info->lock,flags);
5100
5101 memcpy(&info->params, ¶ms, sizeof(info->params));
5102 info->port.tty = oldtty;
5103
5104 info->init_error = rc ? DiagStatus_DmaFailure : 0;
5105 return rc;
5106}
5107
5108static int adapter_test(struct slgt_info *info)
5109{
5110 DBGINFO(("testing %s\n", info->device_name));
5111 if (register_test(info) < 0) {
5112 printk("register test failure %s addr=%08X\n",
5113 info->device_name, info->phys_reg_addr);
5114 } else if (irq_test(info) < 0) {
5115 printk("IRQ test failure %s IRQ=%d\n",
5116 info->device_name, info->irq_level);
5117 } else if (loopback_test(info) < 0) {
5118 printk("loopback test failure %s\n", info->device_name);
5119 }
5120 return info->init_error;
5121}
5122
5123/*
5124 * transmit timeout handler
5125 */
5126static void tx_timeout(unsigned long context)
5127{
5128 struct slgt_info *info = (struct slgt_info*)context;
5129 unsigned long flags;
5130
5131 DBGINFO(("%s tx_timeout\n", info->device_name));
5132 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5133 info->icount.txtimeout++;
5134 }
5135 spin_lock_irqsave(&info->lock,flags);
5136 tx_stop(info);
5137 spin_unlock_irqrestore(&info->lock,flags);
5138
5139#if SYNCLINK_GENERIC_HDLC
5140 if (info->netcount)
5141 hdlcdev_tx_done(info);
5142 else
5143#endif
5144 bh_transmit(info);
5145}
5146
5147/*
5148 * receive buffer polling timer
5149 */
5150static void rx_timeout(unsigned long context)
5151{
5152 struct slgt_info *info = (struct slgt_info*)context;
5153 unsigned long flags;
5154
5155 DBGINFO(("%s rx_timeout\n", info->device_name));
5156 spin_lock_irqsave(&info->lock, flags);
5157 info->pending_bh |= BH_RECEIVE;
5158 spin_unlock_irqrestore(&info->lock, flags);
5159 bh_handler(&info->task);
5160}
5161