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1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27#include <drm/drm_edid.h>
28#include <drm/drm_fb_helper.h>
29#include <drm/drm_probe_helper.h>
30#include <drm/amdgpu_drm.h>
31#include "amdgpu.h"
32#include "atom.h"
33#include "atombios_encoders.h"
34#include "atombios_dp.h"
35#include "amdgpu_connectors.h"
36#include "amdgpu_i2c.h"
37#include "amdgpu_display.h"
38
39#include <linux/pm_runtime.h>
40
41void amdgpu_connector_hotplug(struct drm_connector *connector)
42{
43 struct drm_device *dev = connector->dev;
44 struct amdgpu_device *adev = dev->dev_private;
45 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
46
47 /* bail if the connector does not have hpd pin, e.g.,
48 * VGA, TV, etc.
49 */
50 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE)
51 return;
52
53 amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
54
55 /* if the connector is already off, don't turn it back on */
56 if (connector->dpms != DRM_MODE_DPMS_ON)
57 return;
58
59 /* just deal with DP (not eDP) here. */
60 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
61 struct amdgpu_connector_atom_dig *dig_connector =
62 amdgpu_connector->con_priv;
63
64 /* if existing sink type was not DP no need to retrain */
65 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT)
66 return;
67
68 /* first get sink type as it may be reset after (un)plug */
69 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
70 /* don't do anything if sink is not display port, i.e.,
71 * passive dp->(dvi|hdmi) adaptor
72 */
73 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
74 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) &&
75 amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
76 /* Don't start link training before we have the DPCD */
77 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
78 return;
79
80 /* Turn the connector off and back on immediately, which
81 * will trigger link training
82 */
83 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
84 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
85 }
86 }
87}
88
89static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder)
90{
91 struct drm_crtc *crtc = encoder->crtc;
92
93 if (crtc && crtc->enabled) {
94 drm_crtc_helper_set_mode(crtc, &crtc->mode,
95 crtc->x, crtc->y, crtc->primary->fb);
96 }
97}
98
99int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector)
100{
101 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
102 struct amdgpu_connector_atom_dig *dig_connector;
103 int bpc = 8;
104 unsigned mode_clock, max_tmds_clock;
105
106 switch (connector->connector_type) {
107 case DRM_MODE_CONNECTOR_DVII:
108 case DRM_MODE_CONNECTOR_HDMIB:
109 if (amdgpu_connector->use_digital) {
110 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
111 if (connector->display_info.bpc)
112 bpc = connector->display_info.bpc;
113 }
114 }
115 break;
116 case DRM_MODE_CONNECTOR_DVID:
117 case DRM_MODE_CONNECTOR_HDMIA:
118 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
119 if (connector->display_info.bpc)
120 bpc = connector->display_info.bpc;
121 }
122 break;
123 case DRM_MODE_CONNECTOR_DisplayPort:
124 dig_connector = amdgpu_connector->con_priv;
125 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
126 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
127 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
128 if (connector->display_info.bpc)
129 bpc = connector->display_info.bpc;
130 }
131 break;
132 case DRM_MODE_CONNECTOR_eDP:
133 case DRM_MODE_CONNECTOR_LVDS:
134 if (connector->display_info.bpc)
135 bpc = connector->display_info.bpc;
136 else {
137 const struct drm_connector_helper_funcs *connector_funcs =
138 connector->helper_private;
139 struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
140 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
141 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
142
143 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR)
144 bpc = 6;
145 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR)
146 bpc = 8;
147 }
148 break;
149 }
150
151 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
152 /*
153 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make
154 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at
155 * 12 bpc is always supported on hdmi deep color sinks, as this is
156 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum.
157 */
158 if (bpc > 12) {
159 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n",
160 connector->name, bpc);
161 bpc = 12;
162 }
163
164 /* Any defined maximum tmds clock limit we must not exceed? */
165 if (connector->display_info.max_tmds_clock > 0) {
166 /* mode_clock is clock in kHz for mode to be modeset on this connector */
167 mode_clock = amdgpu_connector->pixelclock_for_modeset;
168
169 /* Maximum allowable input clock in kHz */
170 max_tmds_clock = connector->display_info.max_tmds_clock;
171
172 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n",
173 connector->name, mode_clock, max_tmds_clock);
174
175 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */
176 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
177 if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) &&
178 (mode_clock * 5/4 <= max_tmds_clock))
179 bpc = 10;
180 else
181 bpc = 8;
182
183 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n",
184 connector->name, bpc);
185 }
186
187 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
188 bpc = 8;
189 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
190 connector->name, bpc);
191 }
192 } else if (bpc > 8) {
193 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
194 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
195 connector->name);
196 bpc = 8;
197 }
198 }
199
200 if ((amdgpu_deep_color == 0) && (bpc > 8)) {
201 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n",
202 connector->name);
203 bpc = 8;
204 }
205
206 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
207 connector->name, connector->display_info.bpc, bpc);
208
209 return bpc;
210}
211
212static void
213amdgpu_connector_update_scratch_regs(struct drm_connector *connector,
214 enum drm_connector_status status)
215{
216 struct drm_encoder *best_encoder;
217 struct drm_encoder *encoder;
218 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
219 bool connected;
220
221 best_encoder = connector_funcs->best_encoder(connector);
222
223 drm_connector_for_each_possible_encoder(connector, encoder) {
224 if ((encoder == best_encoder) && (status == connector_status_connected))
225 connected = true;
226 else
227 connected = false;
228
229 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected);
230 }
231}
232
233static struct drm_encoder *
234amdgpu_connector_find_encoder(struct drm_connector *connector,
235 int encoder_type)
236{
237 struct drm_encoder *encoder;
238
239 drm_connector_for_each_possible_encoder(connector, encoder) {
240 if (encoder->encoder_type == encoder_type)
241 return encoder;
242 }
243
244 return NULL;
245}
246
247struct edid *amdgpu_connector_edid(struct drm_connector *connector)
248{
249 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
250 struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
251
252 if (amdgpu_connector->edid) {
253 return amdgpu_connector->edid;
254 } else if (edid_blob) {
255 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL);
256 if (edid)
257 amdgpu_connector->edid = edid;
258 }
259 return amdgpu_connector->edid;
260}
261
262static struct edid *
263amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)
264{
265 struct edid *edid;
266
267 if (adev->mode_info.bios_hardcoded_edid) {
268 edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
269 if (edid) {
270 memcpy((unsigned char *)edid,
271 (unsigned char *)adev->mode_info.bios_hardcoded_edid,
272 adev->mode_info.bios_hardcoded_edid_size);
273 return edid;
274 }
275 }
276 return NULL;
277}
278
279static void amdgpu_connector_get_edid(struct drm_connector *connector)
280{
281 struct drm_device *dev = connector->dev;
282 struct amdgpu_device *adev = dev->dev_private;
283 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
284
285 if (amdgpu_connector->edid)
286 return;
287
288 /* on hw with routers, select right port */
289 if (amdgpu_connector->router.ddc_valid)
290 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
291
292 if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
293 ENCODER_OBJECT_ID_NONE) &&
294 amdgpu_connector->ddc_bus->has_aux) {
295 amdgpu_connector->edid = drm_get_edid(connector,
296 &amdgpu_connector->ddc_bus->aux.ddc);
297 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
298 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
299 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
300
301 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
302 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
303 amdgpu_connector->ddc_bus->has_aux)
304 amdgpu_connector->edid = drm_get_edid(connector,
305 &amdgpu_connector->ddc_bus->aux.ddc);
306 else if (amdgpu_connector->ddc_bus)
307 amdgpu_connector->edid = drm_get_edid(connector,
308 &amdgpu_connector->ddc_bus->adapter);
309 } else if (amdgpu_connector->ddc_bus) {
310 amdgpu_connector->edid = drm_get_edid(connector,
311 &amdgpu_connector->ddc_bus->adapter);
312 }
313
314 if (!amdgpu_connector->edid) {
315 /* some laptops provide a hardcoded edid in rom for LCDs */
316 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
317 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)))
318 amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev);
319 }
320}
321
322static void amdgpu_connector_free_edid(struct drm_connector *connector)
323{
324 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
325
326 kfree(amdgpu_connector->edid);
327 amdgpu_connector->edid = NULL;
328}
329
330static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
331{
332 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
333 int ret;
334
335 if (amdgpu_connector->edid) {
336 drm_connector_update_edid_property(connector, amdgpu_connector->edid);
337 ret = drm_add_edid_modes(connector, amdgpu_connector->edid);
338 return ret;
339 }
340 drm_connector_update_edid_property(connector, NULL);
341 return 0;
342}
343
344static struct drm_encoder *
345amdgpu_connector_best_single_encoder(struct drm_connector *connector)
346{
347 struct drm_encoder *encoder;
348
349 /* pick the first one */
350 drm_connector_for_each_possible_encoder(connector, encoder)
351 return encoder;
352
353 return NULL;
354}
355
356static void amdgpu_get_native_mode(struct drm_connector *connector)
357{
358 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
359 struct amdgpu_encoder *amdgpu_encoder;
360
361 if (encoder == NULL)
362 return;
363
364 amdgpu_encoder = to_amdgpu_encoder(encoder);
365
366 if (!list_empty(&connector->probed_modes)) {
367 struct drm_display_mode *preferred_mode =
368 list_first_entry(&connector->probed_modes,
369 struct drm_display_mode, head);
370
371 amdgpu_encoder->native_mode = *preferred_mode;
372 } else {
373 amdgpu_encoder->native_mode.clock = 0;
374 }
375}
376
377static struct drm_display_mode *
378amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder)
379{
380 struct drm_device *dev = encoder->dev;
381 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
382 struct drm_display_mode *mode = NULL;
383 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
384
385 if (native_mode->hdisplay != 0 &&
386 native_mode->vdisplay != 0 &&
387 native_mode->clock != 0) {
388 mode = drm_mode_duplicate(dev, native_mode);
389 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
390 drm_mode_set_name(mode);
391
392 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
393 } else if (native_mode->hdisplay != 0 &&
394 native_mode->vdisplay != 0) {
395 /* mac laptops without an edid */
396 /* Note that this is not necessarily the exact panel mode,
397 * but an approximation based on the cvt formula. For these
398 * systems we should ideally read the mode info out of the
399 * registers or add a mode table, but this works and is much
400 * simpler.
401 */
402 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
403 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
404 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
405 }
406 return mode;
407}
408
409static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,
410 struct drm_connector *connector)
411{
412 struct drm_device *dev = encoder->dev;
413 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
414 struct drm_display_mode *mode = NULL;
415 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
416 int i;
417 static const struct mode_size {
418 int w;
419 int h;
420 } common_modes[17] = {
421 { 640, 480},
422 { 720, 480},
423 { 800, 600},
424 { 848, 480},
425 {1024, 768},
426 {1152, 768},
427 {1280, 720},
428 {1280, 800},
429 {1280, 854},
430 {1280, 960},
431 {1280, 1024},
432 {1440, 900},
433 {1400, 1050},
434 {1680, 1050},
435 {1600, 1200},
436 {1920, 1080},
437 {1920, 1200}
438 };
439
440 for (i = 0; i < 17; i++) {
441 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
442 if (common_modes[i].w > 1024 ||
443 common_modes[i].h > 768)
444 continue;
445 }
446 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
447 if (common_modes[i].w > native_mode->hdisplay ||
448 common_modes[i].h > native_mode->vdisplay ||
449 (common_modes[i].w == native_mode->hdisplay &&
450 common_modes[i].h == native_mode->vdisplay))
451 continue;
452 }
453 if (common_modes[i].w < 320 || common_modes[i].h < 200)
454 continue;
455
456 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
457 drm_mode_probed_add(connector, mode);
458 }
459}
460
461static int amdgpu_connector_set_property(struct drm_connector *connector,
462 struct drm_property *property,
463 uint64_t val)
464{
465 struct drm_device *dev = connector->dev;
466 struct amdgpu_device *adev = dev->dev_private;
467 struct drm_encoder *encoder;
468 struct amdgpu_encoder *amdgpu_encoder;
469
470 if (property == adev->mode_info.coherent_mode_property) {
471 struct amdgpu_encoder_atom_dig *dig;
472 bool new_coherent_mode;
473
474 /* need to find digital encoder on connector */
475 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
476 if (!encoder)
477 return 0;
478
479 amdgpu_encoder = to_amdgpu_encoder(encoder);
480
481 if (!amdgpu_encoder->enc_priv)
482 return 0;
483
484 dig = amdgpu_encoder->enc_priv;
485 new_coherent_mode = val ? true : false;
486 if (dig->coherent_mode != new_coherent_mode) {
487 dig->coherent_mode = new_coherent_mode;
488 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
489 }
490 }
491
492 if (property == adev->mode_info.audio_property) {
493 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
494 /* need to find digital encoder on connector */
495 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
496 if (!encoder)
497 return 0;
498
499 amdgpu_encoder = to_amdgpu_encoder(encoder);
500
501 if (amdgpu_connector->audio != val) {
502 amdgpu_connector->audio = val;
503 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
504 }
505 }
506
507 if (property == adev->mode_info.dither_property) {
508 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
509 /* need to find digital encoder on connector */
510 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
511 if (!encoder)
512 return 0;
513
514 amdgpu_encoder = to_amdgpu_encoder(encoder);
515
516 if (amdgpu_connector->dither != val) {
517 amdgpu_connector->dither = val;
518 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
519 }
520 }
521
522 if (property == adev->mode_info.underscan_property) {
523 /* need to find digital encoder on connector */
524 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
525 if (!encoder)
526 return 0;
527
528 amdgpu_encoder = to_amdgpu_encoder(encoder);
529
530 if (amdgpu_encoder->underscan_type != val) {
531 amdgpu_encoder->underscan_type = val;
532 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
533 }
534 }
535
536 if (property == adev->mode_info.underscan_hborder_property) {
537 /* need to find digital encoder on connector */
538 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
539 if (!encoder)
540 return 0;
541
542 amdgpu_encoder = to_amdgpu_encoder(encoder);
543
544 if (amdgpu_encoder->underscan_hborder != val) {
545 amdgpu_encoder->underscan_hborder = val;
546 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
547 }
548 }
549
550 if (property == adev->mode_info.underscan_vborder_property) {
551 /* need to find digital encoder on connector */
552 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
553 if (!encoder)
554 return 0;
555
556 amdgpu_encoder = to_amdgpu_encoder(encoder);
557
558 if (amdgpu_encoder->underscan_vborder != val) {
559 amdgpu_encoder->underscan_vborder = val;
560 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
561 }
562 }
563
564 if (property == adev->mode_info.load_detect_property) {
565 struct amdgpu_connector *amdgpu_connector =
566 to_amdgpu_connector(connector);
567
568 if (val == 0)
569 amdgpu_connector->dac_load_detect = false;
570 else
571 amdgpu_connector->dac_load_detect = true;
572 }
573
574 if (property == dev->mode_config.scaling_mode_property) {
575 enum amdgpu_rmx_type rmx_type;
576
577 if (connector->encoder) {
578 amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
579 } else {
580 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
581 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
582 }
583
584 switch (val) {
585 default:
586 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
587 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
588 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
589 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
590 }
591 if (amdgpu_encoder->rmx_type == rmx_type)
592 return 0;
593
594 if ((rmx_type != DRM_MODE_SCALE_NONE) &&
595 (amdgpu_encoder->native_mode.clock == 0))
596 return 0;
597
598 amdgpu_encoder->rmx_type = rmx_type;
599
600 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
601 }
602
603 return 0;
604}
605
606static void
607amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder,
608 struct drm_connector *connector)
609{
610 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
611 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
612 struct drm_display_mode *t, *mode;
613
614 /* If the EDID preferred mode doesn't match the native mode, use it */
615 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
616 if (mode->type & DRM_MODE_TYPE_PREFERRED) {
617 if (mode->hdisplay != native_mode->hdisplay ||
618 mode->vdisplay != native_mode->vdisplay)
619 memcpy(native_mode, mode, sizeof(*mode));
620 }
621 }
622
623 /* Try to get native mode details from EDID if necessary */
624 if (!native_mode->clock) {
625 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
626 if (mode->hdisplay == native_mode->hdisplay &&
627 mode->vdisplay == native_mode->vdisplay) {
628 *native_mode = *mode;
629 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
630 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
631 break;
632 }
633 }
634 }
635
636 if (!native_mode->clock) {
637 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
638 amdgpu_encoder->rmx_type = RMX_OFF;
639 }
640}
641
642static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector)
643{
644 struct drm_encoder *encoder;
645 int ret = 0;
646 struct drm_display_mode *mode;
647
648 amdgpu_connector_get_edid(connector);
649 ret = amdgpu_connector_ddc_get_modes(connector);
650 if (ret > 0) {
651 encoder = amdgpu_connector_best_single_encoder(connector);
652 if (encoder) {
653 amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
654 /* add scaled modes */
655 amdgpu_connector_add_common_modes(encoder, connector);
656 }
657 return ret;
658 }
659
660 encoder = amdgpu_connector_best_single_encoder(connector);
661 if (!encoder)
662 return 0;
663
664 /* we have no EDID modes */
665 mode = amdgpu_connector_lcd_native_mode(encoder);
666 if (mode) {
667 ret = 1;
668 drm_mode_probed_add(connector, mode);
669 /* add the width/height from vbios tables if available */
670 connector->display_info.width_mm = mode->width_mm;
671 connector->display_info.height_mm = mode->height_mm;
672 /* add scaled modes */
673 amdgpu_connector_add_common_modes(encoder, connector);
674 }
675
676 return ret;
677}
678
679static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector,
680 struct drm_display_mode *mode)
681{
682 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
683
684 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
685 return MODE_PANEL;
686
687 if (encoder) {
688 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
689 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
690
691 /* AVIVO hardware supports downscaling modes larger than the panel
692 * to the panel size, but I'm not sure this is desirable.
693 */
694 if ((mode->hdisplay > native_mode->hdisplay) ||
695 (mode->vdisplay > native_mode->vdisplay))
696 return MODE_PANEL;
697
698 /* if scaling is disabled, block non-native modes */
699 if (amdgpu_encoder->rmx_type == RMX_OFF) {
700 if ((mode->hdisplay != native_mode->hdisplay) ||
701 (mode->vdisplay != native_mode->vdisplay))
702 return MODE_PANEL;
703 }
704 }
705
706 return MODE_OK;
707}
708
709static enum drm_connector_status
710amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
711{
712 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
713 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
714 enum drm_connector_status ret = connector_status_disconnected;
715 int r;
716
717 if (!drm_kms_helper_is_poll_worker()) {
718 r = pm_runtime_get_sync(connector->dev->dev);
719 if (r < 0) {
720 pm_runtime_put_autosuspend(connector->dev->dev);
721 return connector_status_disconnected;
722 }
723 }
724
725 if (encoder) {
726 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
727 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
728
729 /* check if panel is valid */
730 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
731 ret = connector_status_connected;
732
733 }
734
735 /* check for edid as well */
736 amdgpu_connector_get_edid(connector);
737 if (amdgpu_connector->edid)
738 ret = connector_status_connected;
739 /* check acpi lid status ??? */
740
741 amdgpu_connector_update_scratch_regs(connector, ret);
742
743 if (!drm_kms_helper_is_poll_worker()) {
744 pm_runtime_mark_last_busy(connector->dev->dev);
745 pm_runtime_put_autosuspend(connector->dev->dev);
746 }
747
748 return ret;
749}
750
751static void amdgpu_connector_unregister(struct drm_connector *connector)
752{
753 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
754
755 if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) {
756 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux);
757 amdgpu_connector->ddc_bus->has_aux = false;
758 }
759}
760
761static void amdgpu_connector_destroy(struct drm_connector *connector)
762{
763 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
764
765 amdgpu_connector_free_edid(connector);
766 kfree(amdgpu_connector->con_priv);
767 drm_connector_unregister(connector);
768 drm_connector_cleanup(connector);
769 kfree(connector);
770}
771
772static int amdgpu_connector_set_lcd_property(struct drm_connector *connector,
773 struct drm_property *property,
774 uint64_t value)
775{
776 struct drm_device *dev = connector->dev;
777 struct amdgpu_encoder *amdgpu_encoder;
778 enum amdgpu_rmx_type rmx_type;
779
780 DRM_DEBUG_KMS("\n");
781 if (property != dev->mode_config.scaling_mode_property)
782 return 0;
783
784 if (connector->encoder)
785 amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
786 else {
787 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
788 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
789 }
790
791 switch (value) {
792 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
793 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
794 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
795 default:
796 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
797 }
798 if (amdgpu_encoder->rmx_type == rmx_type)
799 return 0;
800
801 amdgpu_encoder->rmx_type = rmx_type;
802
803 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
804 return 0;
805}
806
807
808static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = {
809 .get_modes = amdgpu_connector_lvds_get_modes,
810 .mode_valid = amdgpu_connector_lvds_mode_valid,
811 .best_encoder = amdgpu_connector_best_single_encoder,
812};
813
814static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = {
815 .dpms = drm_helper_connector_dpms,
816 .detect = amdgpu_connector_lvds_detect,
817 .fill_modes = drm_helper_probe_single_connector_modes,
818 .early_unregister = amdgpu_connector_unregister,
819 .destroy = amdgpu_connector_destroy,
820 .set_property = amdgpu_connector_set_lcd_property,
821};
822
823static int amdgpu_connector_vga_get_modes(struct drm_connector *connector)
824{
825 int ret;
826
827 amdgpu_connector_get_edid(connector);
828 ret = amdgpu_connector_ddc_get_modes(connector);
829
830 return ret;
831}
832
833static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector,
834 struct drm_display_mode *mode)
835{
836 struct drm_device *dev = connector->dev;
837 struct amdgpu_device *adev = dev->dev_private;
838
839 /* XXX check mode bandwidth */
840
841 if ((mode->clock / 10) > adev->clock.max_pixel_clock)
842 return MODE_CLOCK_HIGH;
843
844 return MODE_OK;
845}
846
847static enum drm_connector_status
848amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
849{
850 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
851 struct drm_encoder *encoder;
852 const struct drm_encoder_helper_funcs *encoder_funcs;
853 bool dret = false;
854 enum drm_connector_status ret = connector_status_disconnected;
855 int r;
856
857 if (!drm_kms_helper_is_poll_worker()) {
858 r = pm_runtime_get_sync(connector->dev->dev);
859 if (r < 0) {
860 pm_runtime_put_autosuspend(connector->dev->dev);
861 return connector_status_disconnected;
862 }
863 }
864
865 encoder = amdgpu_connector_best_single_encoder(connector);
866 if (!encoder)
867 ret = connector_status_disconnected;
868
869 if (amdgpu_connector->ddc_bus)
870 dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
871 if (dret) {
872 amdgpu_connector->detected_by_load = false;
873 amdgpu_connector_free_edid(connector);
874 amdgpu_connector_get_edid(connector);
875
876 if (!amdgpu_connector->edid) {
877 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
878 connector->name);
879 ret = connector_status_connected;
880 } else {
881 amdgpu_connector->use_digital =
882 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
883
884 /* some oems have boards with separate digital and analog connectors
885 * with a shared ddc line (often vga + hdmi)
886 */
887 if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) {
888 amdgpu_connector_free_edid(connector);
889 ret = connector_status_disconnected;
890 } else {
891 ret = connector_status_connected;
892 }
893 }
894 } else {
895
896 /* if we aren't forcing don't do destructive polling */
897 if (!force) {
898 /* only return the previous status if we last
899 * detected a monitor via load.
900 */
901 if (amdgpu_connector->detected_by_load)
902 ret = connector->status;
903 goto out;
904 }
905
906 if (amdgpu_connector->dac_load_detect && encoder) {
907 encoder_funcs = encoder->helper_private;
908 ret = encoder_funcs->detect(encoder, connector);
909 if (ret != connector_status_disconnected)
910 amdgpu_connector->detected_by_load = true;
911 }
912 }
913
914 amdgpu_connector_update_scratch_regs(connector, ret);
915
916out:
917 if (!drm_kms_helper_is_poll_worker()) {
918 pm_runtime_mark_last_busy(connector->dev->dev);
919 pm_runtime_put_autosuspend(connector->dev->dev);
920 }
921
922 return ret;
923}
924
925static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = {
926 .get_modes = amdgpu_connector_vga_get_modes,
927 .mode_valid = amdgpu_connector_vga_mode_valid,
928 .best_encoder = amdgpu_connector_best_single_encoder,
929};
930
931static const struct drm_connector_funcs amdgpu_connector_vga_funcs = {
932 .dpms = drm_helper_connector_dpms,
933 .detect = amdgpu_connector_vga_detect,
934 .fill_modes = drm_helper_probe_single_connector_modes,
935 .early_unregister = amdgpu_connector_unregister,
936 .destroy = amdgpu_connector_destroy,
937 .set_property = amdgpu_connector_set_property,
938};
939
940static bool
941amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector)
942{
943 struct drm_device *dev = connector->dev;
944 struct amdgpu_device *adev = dev->dev_private;
945 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
946 enum drm_connector_status status;
947
948 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) {
949 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd))
950 status = connector_status_connected;
951 else
952 status = connector_status_disconnected;
953 if (connector->status == status)
954 return true;
955 }
956
957 return false;
958}
959
960/*
961 * DVI is complicated
962 * Do a DDC probe, if DDC probe passes, get the full EDID so
963 * we can do analog/digital monitor detection at this point.
964 * If the monitor is an analog monitor or we got no DDC,
965 * we need to find the DAC encoder object for this connector.
966 * If we got no DDC, we do load detection on the DAC encoder object.
967 * If we got analog DDC or load detection passes on the DAC encoder
968 * we have to check if this analog encoder is shared with anyone else (TV)
969 * if its shared we have to set the other connector to disconnected.
970 */
971static enum drm_connector_status
972amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
973{
974 struct drm_device *dev = connector->dev;
975 struct amdgpu_device *adev = dev->dev_private;
976 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
977 const struct drm_encoder_helper_funcs *encoder_funcs;
978 int r;
979 enum drm_connector_status ret = connector_status_disconnected;
980 bool dret = false, broken_edid = false;
981
982 if (!drm_kms_helper_is_poll_worker()) {
983 r = pm_runtime_get_sync(connector->dev->dev);
984 if (r < 0) {
985 pm_runtime_put_autosuspend(connector->dev->dev);
986 return connector_status_disconnected;
987 }
988 }
989
990 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
991 ret = connector->status;
992 goto exit;
993 }
994
995 if (amdgpu_connector->ddc_bus)
996 dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
997 if (dret) {
998 amdgpu_connector->detected_by_load = false;
999 amdgpu_connector_free_edid(connector);
1000 amdgpu_connector_get_edid(connector);
1001
1002 if (!amdgpu_connector->edid) {
1003 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
1004 connector->name);
1005 ret = connector_status_connected;
1006 broken_edid = true; /* defer use_digital to later */
1007 } else {
1008 amdgpu_connector->use_digital =
1009 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
1010
1011 /* some oems have boards with separate digital and analog connectors
1012 * with a shared ddc line (often vga + hdmi)
1013 */
1014 if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) {
1015 amdgpu_connector_free_edid(connector);
1016 ret = connector_status_disconnected;
1017 } else {
1018 ret = connector_status_connected;
1019 }
1020
1021 /* This gets complicated. We have boards with VGA + HDMI with a
1022 * shared DDC line and we have boards with DVI-D + HDMI with a shared
1023 * DDC line. The latter is more complex because with DVI<->HDMI adapters
1024 * you don't really know what's connected to which port as both are digital.
1025 */
1026 if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) {
1027 struct drm_connector *list_connector;
1028 struct drm_connector_list_iter iter;
1029 struct amdgpu_connector *list_amdgpu_connector;
1030
1031 drm_connector_list_iter_begin(dev, &iter);
1032 drm_for_each_connector_iter(list_connector,
1033 &iter) {
1034 if (connector == list_connector)
1035 continue;
1036 list_amdgpu_connector = to_amdgpu_connector(list_connector);
1037 if (list_amdgpu_connector->shared_ddc &&
1038 (list_amdgpu_connector->ddc_bus->rec.i2c_id ==
1039 amdgpu_connector->ddc_bus->rec.i2c_id)) {
1040 /* cases where both connectors are digital */
1041 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
1042 /* hpd is our only option in this case */
1043 if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1044 amdgpu_connector_free_edid(connector);
1045 ret = connector_status_disconnected;
1046 }
1047 }
1048 }
1049 }
1050 drm_connector_list_iter_end(&iter);
1051 }
1052 }
1053 }
1054
1055 if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true))
1056 goto out;
1057
1058 /* DVI-D and HDMI-A are digital only */
1059 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) ||
1060 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))
1061 goto out;
1062
1063 /* if we aren't forcing don't do destructive polling */
1064 if (!force) {
1065 /* only return the previous status if we last
1066 * detected a monitor via load.
1067 */
1068 if (amdgpu_connector->detected_by_load)
1069 ret = connector->status;
1070 goto out;
1071 }
1072
1073 /* find analog encoder */
1074 if (amdgpu_connector->dac_load_detect) {
1075 struct drm_encoder *encoder;
1076
1077 drm_connector_for_each_possible_encoder(connector, encoder) {
1078 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
1079 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
1080 continue;
1081
1082 encoder_funcs = encoder->helper_private;
1083 if (encoder_funcs->detect) {
1084 if (!broken_edid) {
1085 if (ret != connector_status_connected) {
1086 /* deal with analog monitors without DDC */
1087 ret = encoder_funcs->detect(encoder, connector);
1088 if (ret == connector_status_connected) {
1089 amdgpu_connector->use_digital = false;
1090 }
1091 if (ret != connector_status_disconnected)
1092 amdgpu_connector->detected_by_load = true;
1093 }
1094 } else {
1095 enum drm_connector_status lret;
1096 /* assume digital unless load detected otherwise */
1097 amdgpu_connector->use_digital = true;
1098 lret = encoder_funcs->detect(encoder, connector);
1099 DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret);
1100 if (lret == connector_status_connected)
1101 amdgpu_connector->use_digital = false;
1102 }
1103 break;
1104 }
1105 }
1106 }
1107
1108out:
1109 /* updated in get modes as well since we need to know if it's analog or digital */
1110 amdgpu_connector_update_scratch_regs(connector, ret);
1111
1112exit:
1113 if (!drm_kms_helper_is_poll_worker()) {
1114 pm_runtime_mark_last_busy(connector->dev->dev);
1115 pm_runtime_put_autosuspend(connector->dev->dev);
1116 }
1117
1118 return ret;
1119}
1120
1121/* okay need to be smart in here about which encoder to pick */
1122static struct drm_encoder *
1123amdgpu_connector_dvi_encoder(struct drm_connector *connector)
1124{
1125 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1126 struct drm_encoder *encoder;
1127
1128 drm_connector_for_each_possible_encoder(connector, encoder) {
1129 if (amdgpu_connector->use_digital == true) {
1130 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1131 return encoder;
1132 } else {
1133 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
1134 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1135 return encoder;
1136 }
1137 }
1138
1139 /* see if we have a default encoder TODO */
1140
1141 /* then check use digitial */
1142 /* pick the first one */
1143 drm_connector_for_each_possible_encoder(connector, encoder)
1144 return encoder;
1145
1146 return NULL;
1147}
1148
1149static void amdgpu_connector_dvi_force(struct drm_connector *connector)
1150{
1151 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1152 if (connector->force == DRM_FORCE_ON)
1153 amdgpu_connector->use_digital = false;
1154 if (connector->force == DRM_FORCE_ON_DIGITAL)
1155 amdgpu_connector->use_digital = true;
1156}
1157
1158static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector,
1159 struct drm_display_mode *mode)
1160{
1161 struct drm_device *dev = connector->dev;
1162 struct amdgpu_device *adev = dev->dev_private;
1163 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1164
1165 /* XXX check mode bandwidth */
1166
1167 if (amdgpu_connector->use_digital && (mode->clock > 165000)) {
1168 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
1169 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
1170 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) {
1171 return MODE_OK;
1172 } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1173 /* HDMI 1.3+ supports max clock of 340 Mhz */
1174 if (mode->clock > 340000)
1175 return MODE_CLOCK_HIGH;
1176 else
1177 return MODE_OK;
1178 } else {
1179 return MODE_CLOCK_HIGH;
1180 }
1181 }
1182
1183 /* check against the max pixel clock */
1184 if ((mode->clock / 10) > adev->clock.max_pixel_clock)
1185 return MODE_CLOCK_HIGH;
1186
1187 return MODE_OK;
1188}
1189
1190static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = {
1191 .get_modes = amdgpu_connector_vga_get_modes,
1192 .mode_valid = amdgpu_connector_dvi_mode_valid,
1193 .best_encoder = amdgpu_connector_dvi_encoder,
1194};
1195
1196static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = {
1197 .dpms = drm_helper_connector_dpms,
1198 .detect = amdgpu_connector_dvi_detect,
1199 .fill_modes = drm_helper_probe_single_connector_modes,
1200 .set_property = amdgpu_connector_set_property,
1201 .early_unregister = amdgpu_connector_unregister,
1202 .destroy = amdgpu_connector_destroy,
1203 .force = amdgpu_connector_dvi_force,
1204};
1205
1206static int amdgpu_connector_dp_get_modes(struct drm_connector *connector)
1207{
1208 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1209 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1210 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1211 int ret;
1212
1213 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1214 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1215 struct drm_display_mode *mode;
1216
1217 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1218 if (!amdgpu_dig_connector->edp_on)
1219 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1220 ATOM_TRANSMITTER_ACTION_POWER_ON);
1221 amdgpu_connector_get_edid(connector);
1222 ret = amdgpu_connector_ddc_get_modes(connector);
1223 if (!amdgpu_dig_connector->edp_on)
1224 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1225 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1226 } else {
1227 /* need to setup ddc on the bridge */
1228 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1229 ENCODER_OBJECT_ID_NONE) {
1230 if (encoder)
1231 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1232 }
1233 amdgpu_connector_get_edid(connector);
1234 ret = amdgpu_connector_ddc_get_modes(connector);
1235 }
1236
1237 if (ret > 0) {
1238 if (encoder) {
1239 amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
1240 /* add scaled modes */
1241 amdgpu_connector_add_common_modes(encoder, connector);
1242 }
1243 return ret;
1244 }
1245
1246 if (!encoder)
1247 return 0;
1248
1249 /* we have no EDID modes */
1250 mode = amdgpu_connector_lcd_native_mode(encoder);
1251 if (mode) {
1252 ret = 1;
1253 drm_mode_probed_add(connector, mode);
1254 /* add the width/height from vbios tables if available */
1255 connector->display_info.width_mm = mode->width_mm;
1256 connector->display_info.height_mm = mode->height_mm;
1257 /* add scaled modes */
1258 amdgpu_connector_add_common_modes(encoder, connector);
1259 }
1260 } else {
1261 /* need to setup ddc on the bridge */
1262 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1263 ENCODER_OBJECT_ID_NONE) {
1264 if (encoder)
1265 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1266 }
1267 amdgpu_connector_get_edid(connector);
1268 ret = amdgpu_connector_ddc_get_modes(connector);
1269
1270 amdgpu_get_native_mode(connector);
1271 }
1272
1273 return ret;
1274}
1275
1276u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
1277{
1278 struct drm_encoder *encoder;
1279 struct amdgpu_encoder *amdgpu_encoder;
1280
1281 drm_connector_for_each_possible_encoder(connector, encoder) {
1282 amdgpu_encoder = to_amdgpu_encoder(encoder);
1283
1284 switch (amdgpu_encoder->encoder_id) {
1285 case ENCODER_OBJECT_ID_TRAVIS:
1286 case ENCODER_OBJECT_ID_NUTMEG:
1287 return amdgpu_encoder->encoder_id;
1288 default:
1289 break;
1290 }
1291 }
1292
1293 return ENCODER_OBJECT_ID_NONE;
1294}
1295
1296static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
1297{
1298 struct drm_encoder *encoder;
1299 struct amdgpu_encoder *amdgpu_encoder;
1300 bool found = false;
1301
1302 drm_connector_for_each_possible_encoder(connector, encoder) {
1303 amdgpu_encoder = to_amdgpu_encoder(encoder);
1304 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
1305 found = true;
1306 }
1307
1308 return found;
1309}
1310
1311bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector)
1312{
1313 struct drm_device *dev = connector->dev;
1314 struct amdgpu_device *adev = dev->dev_private;
1315
1316 if ((adev->clock.default_dispclk >= 53900) &&
1317 amdgpu_connector_encoder_is_hbr2(connector)) {
1318 return true;
1319 }
1320
1321 return false;
1322}
1323
1324static enum drm_connector_status
1325amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
1326{
1327 struct drm_device *dev = connector->dev;
1328 struct amdgpu_device *adev = dev->dev_private;
1329 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1330 enum drm_connector_status ret = connector_status_disconnected;
1331 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1332 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1333 int r;
1334
1335 if (!drm_kms_helper_is_poll_worker()) {
1336 r = pm_runtime_get_sync(connector->dev->dev);
1337 if (r < 0) {
1338 pm_runtime_put_autosuspend(connector->dev->dev);
1339 return connector_status_disconnected;
1340 }
1341 }
1342
1343 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1344 ret = connector->status;
1345 goto out;
1346 }
1347
1348 amdgpu_connector_free_edid(connector);
1349
1350 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1351 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1352 if (encoder) {
1353 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1354 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1355
1356 /* check if panel is valid */
1357 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
1358 ret = connector_status_connected;
1359 }
1360 /* eDP is always DP */
1361 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1362 if (!amdgpu_dig_connector->edp_on)
1363 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1364 ATOM_TRANSMITTER_ACTION_POWER_ON);
1365 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1366 ret = connector_status_connected;
1367 if (!amdgpu_dig_connector->edp_on)
1368 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1369 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1370 } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1371 ENCODER_OBJECT_ID_NONE) {
1372 /* DP bridges are always DP */
1373 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1374 /* get the DPCD from the bridge */
1375 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1376
1377 if (encoder) {
1378 /* setup ddc on the bridge */
1379 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1380 /* bridge chips are always aux */
1381 /* try DDC */
1382 if (amdgpu_display_ddc_probe(amdgpu_connector, true))
1383 ret = connector_status_connected;
1384 else if (amdgpu_connector->dac_load_detect) { /* try load detection */
1385 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1386 ret = encoder_funcs->detect(encoder, connector);
1387 }
1388 }
1389 } else {
1390 amdgpu_dig_connector->dp_sink_type =
1391 amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
1392 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1393 ret = connector_status_connected;
1394 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
1395 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1396 } else {
1397 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
1398 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1399 ret = connector_status_connected;
1400 } else {
1401 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
1402 if (amdgpu_display_ddc_probe(amdgpu_connector,
1403 false))
1404 ret = connector_status_connected;
1405 }
1406 }
1407 }
1408
1409 amdgpu_connector_update_scratch_regs(connector, ret);
1410out:
1411 if (!drm_kms_helper_is_poll_worker()) {
1412 pm_runtime_mark_last_busy(connector->dev->dev);
1413 pm_runtime_put_autosuspend(connector->dev->dev);
1414 }
1415
1416 return ret;
1417}
1418
1419static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector,
1420 struct drm_display_mode *mode)
1421{
1422 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1423 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1424
1425 /* XXX check mode bandwidth */
1426
1427 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1428 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1429 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1430
1431 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
1432 return MODE_PANEL;
1433
1434 if (encoder) {
1435 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1436 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1437
1438 /* AVIVO hardware supports downscaling modes larger than the panel
1439 * to the panel size, but I'm not sure this is desirable.
1440 */
1441 if ((mode->hdisplay > native_mode->hdisplay) ||
1442 (mode->vdisplay > native_mode->vdisplay))
1443 return MODE_PANEL;
1444
1445 /* if scaling is disabled, block non-native modes */
1446 if (amdgpu_encoder->rmx_type == RMX_OFF) {
1447 if ((mode->hdisplay != native_mode->hdisplay) ||
1448 (mode->vdisplay != native_mode->vdisplay))
1449 return MODE_PANEL;
1450 }
1451 }
1452 return MODE_OK;
1453 } else {
1454 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
1455 (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
1456 return amdgpu_atombios_dp_mode_valid_helper(connector, mode);
1457 } else {
1458 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1459 /* HDMI 1.3+ supports max clock of 340 Mhz */
1460 if (mode->clock > 340000)
1461 return MODE_CLOCK_HIGH;
1462 } else {
1463 if (mode->clock > 165000)
1464 return MODE_CLOCK_HIGH;
1465 }
1466 }
1467 }
1468
1469 return MODE_OK;
1470}
1471
1472static int
1473amdgpu_connector_late_register(struct drm_connector *connector)
1474{
1475 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1476 int r = 0;
1477
1478 if (amdgpu_connector->ddc_bus->has_aux) {
1479 amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev;
1480 r = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux);
1481 }
1482
1483 return r;
1484}
1485
1486static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = {
1487 .get_modes = amdgpu_connector_dp_get_modes,
1488 .mode_valid = amdgpu_connector_dp_mode_valid,
1489 .best_encoder = amdgpu_connector_dvi_encoder,
1490};
1491
1492static const struct drm_connector_funcs amdgpu_connector_dp_funcs = {
1493 .dpms = drm_helper_connector_dpms,
1494 .detect = amdgpu_connector_dp_detect,
1495 .fill_modes = drm_helper_probe_single_connector_modes,
1496 .set_property = amdgpu_connector_set_property,
1497 .early_unregister = amdgpu_connector_unregister,
1498 .destroy = amdgpu_connector_destroy,
1499 .force = amdgpu_connector_dvi_force,
1500 .late_register = amdgpu_connector_late_register,
1501};
1502
1503static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
1504 .dpms = drm_helper_connector_dpms,
1505 .detect = amdgpu_connector_dp_detect,
1506 .fill_modes = drm_helper_probe_single_connector_modes,
1507 .set_property = amdgpu_connector_set_lcd_property,
1508 .early_unregister = amdgpu_connector_unregister,
1509 .destroy = amdgpu_connector_destroy,
1510 .force = amdgpu_connector_dvi_force,
1511 .late_register = amdgpu_connector_late_register,
1512};
1513
1514void
1515amdgpu_connector_add(struct amdgpu_device *adev,
1516 uint32_t connector_id,
1517 uint32_t supported_device,
1518 int connector_type,
1519 struct amdgpu_i2c_bus_rec *i2c_bus,
1520 uint16_t connector_object_id,
1521 struct amdgpu_hpd *hpd,
1522 struct amdgpu_router *router)
1523{
1524 struct drm_device *dev = adev->ddev;
1525 struct drm_connector *connector;
1526 struct drm_connector_list_iter iter;
1527 struct amdgpu_connector *amdgpu_connector;
1528 struct amdgpu_connector_atom_dig *amdgpu_dig_connector;
1529 struct drm_encoder *encoder;
1530 struct amdgpu_encoder *amdgpu_encoder;
1531 struct i2c_adapter *ddc = NULL;
1532 uint32_t subpixel_order = SubPixelNone;
1533 bool shared_ddc = false;
1534 bool is_dp_bridge = false;
1535 bool has_aux = false;
1536
1537 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1538 return;
1539
1540 /* see if we already added it */
1541 drm_connector_list_iter_begin(dev, &iter);
1542 drm_for_each_connector_iter(connector, &iter) {
1543 amdgpu_connector = to_amdgpu_connector(connector);
1544 if (amdgpu_connector->connector_id == connector_id) {
1545 amdgpu_connector->devices |= supported_device;
1546 drm_connector_list_iter_end(&iter);
1547 return;
1548 }
1549 if (amdgpu_connector->ddc_bus && i2c_bus->valid) {
1550 if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
1551 amdgpu_connector->shared_ddc = true;
1552 shared_ddc = true;
1553 }
1554 if (amdgpu_connector->router_bus && router->ddc_valid &&
1555 (amdgpu_connector->router.router_id == router->router_id)) {
1556 amdgpu_connector->shared_ddc = false;
1557 shared_ddc = false;
1558 }
1559 }
1560 }
1561 drm_connector_list_iter_end(&iter);
1562
1563 /* check if it's a dp bridge */
1564 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1565 amdgpu_encoder = to_amdgpu_encoder(encoder);
1566 if (amdgpu_encoder->devices & supported_device) {
1567 switch (amdgpu_encoder->encoder_id) {
1568 case ENCODER_OBJECT_ID_TRAVIS:
1569 case ENCODER_OBJECT_ID_NUTMEG:
1570 is_dp_bridge = true;
1571 break;
1572 default:
1573 break;
1574 }
1575 }
1576 }
1577
1578 amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL);
1579 if (!amdgpu_connector)
1580 return;
1581
1582 connector = &amdgpu_connector->base;
1583
1584 amdgpu_connector->connector_id = connector_id;
1585 amdgpu_connector->devices = supported_device;
1586 amdgpu_connector->shared_ddc = shared_ddc;
1587 amdgpu_connector->connector_object_id = connector_object_id;
1588 amdgpu_connector->hpd = *hpd;
1589
1590 amdgpu_connector->router = *router;
1591 if (router->ddc_valid || router->cd_valid) {
1592 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info);
1593 if (!amdgpu_connector->router_bus)
1594 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
1595 }
1596
1597 if (is_dp_bridge) {
1598 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1599 if (!amdgpu_dig_connector)
1600 goto failed;
1601 amdgpu_connector->con_priv = amdgpu_dig_connector;
1602 if (i2c_bus->valid) {
1603 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1604 if (amdgpu_connector->ddc_bus) {
1605 has_aux = true;
1606 ddc = &amdgpu_connector->ddc_bus->adapter;
1607 } else {
1608 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1609 }
1610 }
1611 switch (connector_type) {
1612 case DRM_MODE_CONNECTOR_VGA:
1613 case DRM_MODE_CONNECTOR_DVIA:
1614 default:
1615 drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1616 &amdgpu_connector_dp_funcs,
1617 connector_type,
1618 ddc);
1619 drm_connector_helper_add(&amdgpu_connector->base,
1620 &amdgpu_connector_dp_helper_funcs);
1621 connector->interlace_allowed = true;
1622 connector->doublescan_allowed = true;
1623 amdgpu_connector->dac_load_detect = true;
1624 drm_object_attach_property(&amdgpu_connector->base.base,
1625 adev->mode_info.load_detect_property,
1626 1);
1627 drm_object_attach_property(&amdgpu_connector->base.base,
1628 dev->mode_config.scaling_mode_property,
1629 DRM_MODE_SCALE_NONE);
1630 break;
1631 case DRM_MODE_CONNECTOR_DVII:
1632 case DRM_MODE_CONNECTOR_DVID:
1633 case DRM_MODE_CONNECTOR_HDMIA:
1634 case DRM_MODE_CONNECTOR_HDMIB:
1635 case DRM_MODE_CONNECTOR_DisplayPort:
1636 drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1637 &amdgpu_connector_dp_funcs,
1638 connector_type,
1639 ddc);
1640 drm_connector_helper_add(&amdgpu_connector->base,
1641 &amdgpu_connector_dp_helper_funcs);
1642 drm_object_attach_property(&amdgpu_connector->base.base,
1643 adev->mode_info.underscan_property,
1644 UNDERSCAN_OFF);
1645 drm_object_attach_property(&amdgpu_connector->base.base,
1646 adev->mode_info.underscan_hborder_property,
1647 0);
1648 drm_object_attach_property(&amdgpu_connector->base.base,
1649 adev->mode_info.underscan_vborder_property,
1650 0);
1651
1652 drm_object_attach_property(&amdgpu_connector->base.base,
1653 dev->mode_config.scaling_mode_property,
1654 DRM_MODE_SCALE_NONE);
1655
1656 drm_object_attach_property(&amdgpu_connector->base.base,
1657 adev->mode_info.dither_property,
1658 AMDGPU_FMT_DITHER_DISABLE);
1659
1660 if (amdgpu_audio != 0)
1661 drm_object_attach_property(&amdgpu_connector->base.base,
1662 adev->mode_info.audio_property,
1663 AMDGPU_AUDIO_AUTO);
1664
1665 subpixel_order = SubPixelHorizontalRGB;
1666 connector->interlace_allowed = true;
1667 if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1668 connector->doublescan_allowed = true;
1669 else
1670 connector->doublescan_allowed = false;
1671 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1672 amdgpu_connector->dac_load_detect = true;
1673 drm_object_attach_property(&amdgpu_connector->base.base,
1674 adev->mode_info.load_detect_property,
1675 1);
1676 }
1677 break;
1678 case DRM_MODE_CONNECTOR_LVDS:
1679 case DRM_MODE_CONNECTOR_eDP:
1680 drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1681 &amdgpu_connector_edp_funcs,
1682 connector_type,
1683 ddc);
1684 drm_connector_helper_add(&amdgpu_connector->base,
1685 &amdgpu_connector_dp_helper_funcs);
1686 drm_object_attach_property(&amdgpu_connector->base.base,
1687 dev->mode_config.scaling_mode_property,
1688 DRM_MODE_SCALE_FULLSCREEN);
1689 subpixel_order = SubPixelHorizontalRGB;
1690 connector->interlace_allowed = false;
1691 connector->doublescan_allowed = false;
1692 break;
1693 }
1694 } else {
1695 switch (connector_type) {
1696 case DRM_MODE_CONNECTOR_VGA:
1697 if (i2c_bus->valid) {
1698 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1699 if (!amdgpu_connector->ddc_bus)
1700 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1701 else
1702 ddc = &amdgpu_connector->ddc_bus->adapter;
1703 }
1704 drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1705 &amdgpu_connector_vga_funcs,
1706 connector_type,
1707 ddc);
1708 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1709 amdgpu_connector->dac_load_detect = true;
1710 drm_object_attach_property(&amdgpu_connector->base.base,
1711 adev->mode_info.load_detect_property,
1712 1);
1713 drm_object_attach_property(&amdgpu_connector->base.base,
1714 dev->mode_config.scaling_mode_property,
1715 DRM_MODE_SCALE_NONE);
1716 /* no HPD on analog connectors */
1717 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1718 connector->interlace_allowed = true;
1719 connector->doublescan_allowed = true;
1720 break;
1721 case DRM_MODE_CONNECTOR_DVIA:
1722 if (i2c_bus->valid) {
1723 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1724 if (!amdgpu_connector->ddc_bus)
1725 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1726 else
1727 ddc = &amdgpu_connector->ddc_bus->adapter;
1728 }
1729 drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1730 &amdgpu_connector_vga_funcs,
1731 connector_type,
1732 ddc);
1733 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1734 amdgpu_connector->dac_load_detect = true;
1735 drm_object_attach_property(&amdgpu_connector->base.base,
1736 adev->mode_info.load_detect_property,
1737 1);
1738 drm_object_attach_property(&amdgpu_connector->base.base,
1739 dev->mode_config.scaling_mode_property,
1740 DRM_MODE_SCALE_NONE);
1741 /* no HPD on analog connectors */
1742 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1743 connector->interlace_allowed = true;
1744 connector->doublescan_allowed = true;
1745 break;
1746 case DRM_MODE_CONNECTOR_DVII:
1747 case DRM_MODE_CONNECTOR_DVID:
1748 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1749 if (!amdgpu_dig_connector)
1750 goto failed;
1751 amdgpu_connector->con_priv = amdgpu_dig_connector;
1752 if (i2c_bus->valid) {
1753 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1754 if (!amdgpu_connector->ddc_bus)
1755 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1756 else
1757 ddc = &amdgpu_connector->ddc_bus->adapter;
1758 }
1759 drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1760 &amdgpu_connector_dvi_funcs,
1761 connector_type,
1762 ddc);
1763 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1764 subpixel_order = SubPixelHorizontalRGB;
1765 drm_object_attach_property(&amdgpu_connector->base.base,
1766 adev->mode_info.coherent_mode_property,
1767 1);
1768 drm_object_attach_property(&amdgpu_connector->base.base,
1769 adev->mode_info.underscan_property,
1770 UNDERSCAN_OFF);
1771 drm_object_attach_property(&amdgpu_connector->base.base,
1772 adev->mode_info.underscan_hborder_property,
1773 0);
1774 drm_object_attach_property(&amdgpu_connector->base.base,
1775 adev->mode_info.underscan_vborder_property,
1776 0);
1777 drm_object_attach_property(&amdgpu_connector->base.base,
1778 dev->mode_config.scaling_mode_property,
1779 DRM_MODE_SCALE_NONE);
1780
1781 if (amdgpu_audio != 0) {
1782 drm_object_attach_property(&amdgpu_connector->base.base,
1783 adev->mode_info.audio_property,
1784 AMDGPU_AUDIO_AUTO);
1785 }
1786 drm_object_attach_property(&amdgpu_connector->base.base,
1787 adev->mode_info.dither_property,
1788 AMDGPU_FMT_DITHER_DISABLE);
1789 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1790 amdgpu_connector->dac_load_detect = true;
1791 drm_object_attach_property(&amdgpu_connector->base.base,
1792 adev->mode_info.load_detect_property,
1793 1);
1794 }
1795 connector->interlace_allowed = true;
1796 if (connector_type == DRM_MODE_CONNECTOR_DVII)
1797 connector->doublescan_allowed = true;
1798 else
1799 connector->doublescan_allowed = false;
1800 break;
1801 case DRM_MODE_CONNECTOR_HDMIA:
1802 case DRM_MODE_CONNECTOR_HDMIB:
1803 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1804 if (!amdgpu_dig_connector)
1805 goto failed;
1806 amdgpu_connector->con_priv = amdgpu_dig_connector;
1807 if (i2c_bus->valid) {
1808 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1809 if (!amdgpu_connector->ddc_bus)
1810 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1811 else
1812 ddc = &amdgpu_connector->ddc_bus->adapter;
1813 }
1814 drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1815 &amdgpu_connector_dvi_funcs,
1816 connector_type,
1817 ddc);
1818 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1819 drm_object_attach_property(&amdgpu_connector->base.base,
1820 adev->mode_info.coherent_mode_property,
1821 1);
1822 drm_object_attach_property(&amdgpu_connector->base.base,
1823 adev->mode_info.underscan_property,
1824 UNDERSCAN_OFF);
1825 drm_object_attach_property(&amdgpu_connector->base.base,
1826 adev->mode_info.underscan_hborder_property,
1827 0);
1828 drm_object_attach_property(&amdgpu_connector->base.base,
1829 adev->mode_info.underscan_vborder_property,
1830 0);
1831 drm_object_attach_property(&amdgpu_connector->base.base,
1832 dev->mode_config.scaling_mode_property,
1833 DRM_MODE_SCALE_NONE);
1834 if (amdgpu_audio != 0) {
1835 drm_object_attach_property(&amdgpu_connector->base.base,
1836 adev->mode_info.audio_property,
1837 AMDGPU_AUDIO_AUTO);
1838 }
1839 drm_object_attach_property(&amdgpu_connector->base.base,
1840 adev->mode_info.dither_property,
1841 AMDGPU_FMT_DITHER_DISABLE);
1842 subpixel_order = SubPixelHorizontalRGB;
1843 connector->interlace_allowed = true;
1844 if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1845 connector->doublescan_allowed = true;
1846 else
1847 connector->doublescan_allowed = false;
1848 break;
1849 case DRM_MODE_CONNECTOR_DisplayPort:
1850 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1851 if (!amdgpu_dig_connector)
1852 goto failed;
1853 amdgpu_connector->con_priv = amdgpu_dig_connector;
1854 if (i2c_bus->valid) {
1855 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1856 if (amdgpu_connector->ddc_bus) {
1857 has_aux = true;
1858 ddc = &amdgpu_connector->ddc_bus->adapter;
1859 } else {
1860 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1861 }
1862 }
1863 drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1864 &amdgpu_connector_dp_funcs,
1865 connector_type,
1866 ddc);
1867 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1868 subpixel_order = SubPixelHorizontalRGB;
1869 drm_object_attach_property(&amdgpu_connector->base.base,
1870 adev->mode_info.coherent_mode_property,
1871 1);
1872 drm_object_attach_property(&amdgpu_connector->base.base,
1873 adev->mode_info.underscan_property,
1874 UNDERSCAN_OFF);
1875 drm_object_attach_property(&amdgpu_connector->base.base,
1876 adev->mode_info.underscan_hborder_property,
1877 0);
1878 drm_object_attach_property(&amdgpu_connector->base.base,
1879 adev->mode_info.underscan_vborder_property,
1880 0);
1881 drm_object_attach_property(&amdgpu_connector->base.base,
1882 dev->mode_config.scaling_mode_property,
1883 DRM_MODE_SCALE_NONE);
1884 if (amdgpu_audio != 0) {
1885 drm_object_attach_property(&amdgpu_connector->base.base,
1886 adev->mode_info.audio_property,
1887 AMDGPU_AUDIO_AUTO);
1888 }
1889 drm_object_attach_property(&amdgpu_connector->base.base,
1890 adev->mode_info.dither_property,
1891 AMDGPU_FMT_DITHER_DISABLE);
1892 connector->interlace_allowed = true;
1893 /* in theory with a DP to VGA converter... */
1894 connector->doublescan_allowed = false;
1895 break;
1896 case DRM_MODE_CONNECTOR_eDP:
1897 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1898 if (!amdgpu_dig_connector)
1899 goto failed;
1900 amdgpu_connector->con_priv = amdgpu_dig_connector;
1901 if (i2c_bus->valid) {
1902 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1903 if (amdgpu_connector->ddc_bus) {
1904 has_aux = true;
1905 ddc = &amdgpu_connector->ddc_bus->adapter;
1906 } else {
1907 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1908 }
1909 }
1910 drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1911 &amdgpu_connector_edp_funcs,
1912 connector_type,
1913 ddc);
1914 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1915 drm_object_attach_property(&amdgpu_connector->base.base,
1916 dev->mode_config.scaling_mode_property,
1917 DRM_MODE_SCALE_FULLSCREEN);
1918 subpixel_order = SubPixelHorizontalRGB;
1919 connector->interlace_allowed = false;
1920 connector->doublescan_allowed = false;
1921 break;
1922 case DRM_MODE_CONNECTOR_LVDS:
1923 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1924 if (!amdgpu_dig_connector)
1925 goto failed;
1926 amdgpu_connector->con_priv = amdgpu_dig_connector;
1927 if (i2c_bus->valid) {
1928 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1929 if (!amdgpu_connector->ddc_bus)
1930 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1931 else
1932 ddc = &amdgpu_connector->ddc_bus->adapter;
1933 }
1934 drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1935 &amdgpu_connector_lvds_funcs,
1936 connector_type,
1937 ddc);
1938 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs);
1939 drm_object_attach_property(&amdgpu_connector->base.base,
1940 dev->mode_config.scaling_mode_property,
1941 DRM_MODE_SCALE_FULLSCREEN);
1942 subpixel_order = SubPixelHorizontalRGB;
1943 connector->interlace_allowed = false;
1944 connector->doublescan_allowed = false;
1945 break;
1946 }
1947 }
1948
1949 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) {
1950 if (i2c_bus->valid) {
1951 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1952 DRM_CONNECTOR_POLL_DISCONNECT;
1953 }
1954 } else
1955 connector->polled = DRM_CONNECTOR_POLL_HPD;
1956
1957 connector->display_info.subpixel_order = subpixel_order;
1958
1959 if (has_aux)
1960 amdgpu_atombios_dp_aux_init(amdgpu_connector);
1961
1962 return;
1963
1964failed:
1965 drm_connector_cleanup(connector);
1966 kfree(connector);
1967}