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1/*
2 * Moorestown PCI support
3 * Copyright (c) 2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Moorestown has an interesting PCI implementation:
7 * - configuration space is memory mapped (as defined by MCFG)
8 * - Lincroft devices also have a real, type 1 configuration space
9 * - Early Lincroft silicon has a type 1 access bug that will cause
10 * a hang if non-existent devices are accessed
11 * - some devices have the "fixed BAR" capability, which means
12 * they can't be relocated or modified; check for that during
13 * BAR sizing
14 *
15 * So, we use the MCFG space for all reads and writes, but also send
16 * Lincroft writes to type 1 space. But only read/write if the device
17 * actually exists, otherwise return all 1s for reads and bit bucket
18 * the writes.
19 */
20
21#include <linux/sched.h>
22#include <linux/pci.h>
23#include <linux/ioport.h>
24#include <linux/init.h>
25#include <linux/dmi.h>
26
27#include <asm/acpi.h>
28#include <asm/segment.h>
29#include <asm/io.h>
30#include <asm/smp.h>
31#include <asm/pci_x86.h>
32#include <asm/hw_irq.h>
33#include <asm/io_apic.h>
34
35#define PCIE_CAP_OFFSET 0x100
36
37/* Fixed BAR fields */
38#define PCIE_VNDR_CAP_ID_FIXED_BAR 0x00 /* Fixed BAR (TBD) */
39#define PCI_FIXED_BAR_0_SIZE 0x04
40#define PCI_FIXED_BAR_1_SIZE 0x08
41#define PCI_FIXED_BAR_2_SIZE 0x0c
42#define PCI_FIXED_BAR_3_SIZE 0x10
43#define PCI_FIXED_BAR_4_SIZE 0x14
44#define PCI_FIXED_BAR_5_SIZE 0x1c
45
46/**
47 * fixed_bar_cap - return the offset of the fixed BAR cap if found
48 * @bus: PCI bus
49 * @devfn: device in question
50 *
51 * Look for the fixed BAR cap on @bus and @devfn, returning its offset
52 * if found or 0 otherwise.
53 */
54static int fixed_bar_cap(struct pci_bus *bus, unsigned int devfn)
55{
56 int pos;
57 u32 pcie_cap = 0, cap_data;
58
59 pos = PCIE_CAP_OFFSET;
60
61 if (!raw_pci_ext_ops)
62 return 0;
63
64 while (pos) {
65 if (raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
66 devfn, pos, 4, &pcie_cap))
67 return 0;
68
69 if (PCI_EXT_CAP_ID(pcie_cap) == 0x0000 ||
70 PCI_EXT_CAP_ID(pcie_cap) == 0xffff)
71 break;
72
73 if (PCI_EXT_CAP_ID(pcie_cap) == PCI_EXT_CAP_ID_VNDR) {
74 raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
75 devfn, pos + 4, 4, &cap_data);
76 if ((cap_data & 0xffff) == PCIE_VNDR_CAP_ID_FIXED_BAR)
77 return pos;
78 }
79
80 pos = PCI_EXT_CAP_NEXT(pcie_cap);
81 }
82
83 return 0;
84}
85
86static int pci_device_update_fixed(struct pci_bus *bus, unsigned int devfn,
87 int reg, int len, u32 val, int offset)
88{
89 u32 size;
90 unsigned int domain, busnum;
91 int bar = (reg - PCI_BASE_ADDRESS_0) >> 2;
92
93 domain = pci_domain_nr(bus);
94 busnum = bus->number;
95
96 if (val == ~0 && len == 4) {
97 unsigned long decode;
98
99 raw_pci_ext_ops->read(domain, busnum, devfn,
100 offset + 8 + (bar * 4), 4, &size);
101
102 /* Turn the size into a decode pattern for the sizing code */
103 if (size) {
104 decode = size - 1;
105 decode |= decode >> 1;
106 decode |= decode >> 2;
107 decode |= decode >> 4;
108 decode |= decode >> 8;
109 decode |= decode >> 16;
110 decode++;
111 decode = ~(decode - 1);
112 } else {
113 decode = 0;
114 }
115
116 /*
117 * If val is all ones, the core code is trying to size the reg,
118 * so update the mmconfig space with the real size.
119 *
120 * Note: this assumes the fixed size we got is a power of two.
121 */
122 return raw_pci_ext_ops->write(domain, busnum, devfn, reg, 4,
123 decode);
124 }
125
126 /* This is some other kind of BAR write, so just do it. */
127 return raw_pci_ext_ops->write(domain, busnum, devfn, reg, len, val);
128}
129
130/**
131 * type1_access_ok - check whether to use type 1
132 * @bus: bus number
133 * @devfn: device & function in question
134 *
135 * If the bus is on a Lincroft chip and it exists, or is not on a Lincroft at
136 * all, the we can go ahead with any reads & writes. If it's on a Lincroft,
137 * but doesn't exist, avoid the access altogether to keep the chip from
138 * hanging.
139 */
140static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg)
141{
142 /* This is a workaround for A0 LNC bug where PCI status register does
143 * not have new CAP bit set. can not be written by SW either.
144 *
145 * PCI header type in real LNC indicates a single function device, this
146 * will prevent probing other devices under the same function in PCI
147 * shim. Therefore, use the header type in shim instead.
148 */
149 if (reg >= 0x100 || reg == PCI_STATUS || reg == PCI_HEADER_TYPE)
150 return 0;
151 if (bus == 0 && (devfn == PCI_DEVFN(2, 0) || devfn == PCI_DEVFN(0, 0)))
152 return 1;
153 return 0; /* langwell on others */
154}
155
156static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
157 int size, u32 *value)
158{
159 if (type1_access_ok(bus->number, devfn, where))
160 return pci_direct_conf1.read(pci_domain_nr(bus), bus->number,
161 devfn, where, size, value);
162 return raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
163 devfn, where, size, value);
164}
165
166static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
167 int size, u32 value)
168{
169 int offset;
170
171 /* On MRST, there is no PCI ROM BAR, this will cause a subsequent read
172 * to ROM BAR return 0 then being ignored.
173 */
174 if (where == PCI_ROM_ADDRESS)
175 return 0;
176
177 /*
178 * Devices with fixed BARs need special handling:
179 * - BAR sizing code will save, write ~0, read size, restore
180 * - so writes to fixed BARs need special handling
181 * - other writes to fixed BAR devices should go through mmconfig
182 */
183 offset = fixed_bar_cap(bus, devfn);
184 if (offset &&
185 (where >= PCI_BASE_ADDRESS_0 && where <= PCI_BASE_ADDRESS_5)) {
186 return pci_device_update_fixed(bus, devfn, where, size, value,
187 offset);
188 }
189
190 /*
191 * On Moorestown update both real & mmconfig space
192 * Note: early Lincroft silicon can't handle type 1 accesses to
193 * non-existent devices, so just eat the write in that case.
194 */
195 if (type1_access_ok(bus->number, devfn, where))
196 return pci_direct_conf1.write(pci_domain_nr(bus), bus->number,
197 devfn, where, size, value);
198 return raw_pci_ext_ops->write(pci_domain_nr(bus), bus->number, devfn,
199 where, size, value);
200}
201
202static int mrst_pci_irq_enable(struct pci_dev *dev)
203{
204 u8 pin;
205 struct io_apic_irq_attr irq_attr;
206
207 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
208
209 /* MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to
210 * IOAPIC RTE entries, so we just enable RTE for the device.
211 */
212 irq_attr.ioapic = mp_find_ioapic(dev->irq);
213 irq_attr.ioapic_pin = dev->irq;
214 irq_attr.trigger = 1; /* level */
215 irq_attr.polarity = 1; /* active low */
216 io_apic_set_pci_routing(&dev->dev, dev->irq, &irq_attr);
217
218 return 0;
219}
220
221struct pci_ops pci_mrst_ops = {
222 .read = pci_read,
223 .write = pci_write,
224};
225
226/**
227 * pci_mrst_init - installs pci_mrst_ops
228 *
229 * Moorestown has an interesting PCI implementation (see above).
230 * Called when the early platform detection installs it.
231 */
232int __init pci_mrst_init(void)
233{
234 printk(KERN_INFO "Moorestown platform detected, using MRST PCI ops\n");
235 pci_mmcfg_late_init();
236 pcibios_enable_irq = mrst_pci_irq_enable;
237 pci_root_ops = pci_mrst_ops;
238 /* Continue with standard init */
239 return 1;
240}
241
242/*
243 * Langwell devices reside at fixed offsets, don't try to move them.
244 */
245static void __devinit pci_fixed_bar_fixup(struct pci_dev *dev)
246{
247 unsigned long offset;
248 u32 size;
249 int i;
250
251 /* Must have extended configuration space */
252 if (dev->cfg_size < PCIE_CAP_OFFSET + 4)
253 return;
254
255 /* Fixup the BAR sizes for fixed BAR devices and make them unmoveable */
256 offset = fixed_bar_cap(dev->bus, dev->devfn);
257 if (!offset || PCI_DEVFN(2, 0) == dev->devfn ||
258 PCI_DEVFN(2, 2) == dev->devfn)
259 return;
260
261 for (i = 0; i < PCI_ROM_RESOURCE; i++) {
262 pci_read_config_dword(dev, offset + 8 + (i * 4), &size);
263 dev->resource[i].end = dev->resource[i].start + size - 1;
264 dev->resource[i].flags |= IORESOURCE_PCI_FIXED;
265 }
266}
267DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixed_bar_fixup);