Loading...
1/*
2 * Copyright (C) 1991, 1992 Linus Torvalds
3 * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
4 *
5 * Pentium III FXSR, SSE support
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 */
8
9/*
10 * Handle hardware traps and faults.
11 */
12
13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15#include <linux/context_tracking.h>
16#include <linux/interrupt.h>
17#include <linux/kallsyms.h>
18#include <linux/spinlock.h>
19#include <linux/kprobes.h>
20#include <linux/uaccess.h>
21#include <linux/kdebug.h>
22#include <linux/kgdb.h>
23#include <linux/kernel.h>
24#include <linux/export.h>
25#include <linux/ptrace.h>
26#include <linux/uprobes.h>
27#include <linux/string.h>
28#include <linux/delay.h>
29#include <linux/errno.h>
30#include <linux/kexec.h>
31#include <linux/sched.h>
32#include <linux/sched/task_stack.h>
33#include <linux/timer.h>
34#include <linux/init.h>
35#include <linux/bug.h>
36#include <linux/nmi.h>
37#include <linux/mm.h>
38#include <linux/smp.h>
39#include <linux/io.h>
40#include <linux/hardirq.h>
41#include <linux/atomic.h>
42
43#include <asm/stacktrace.h>
44#include <asm/processor.h>
45#include <asm/debugreg.h>
46#include <asm/text-patching.h>
47#include <asm/ftrace.h>
48#include <asm/traps.h>
49#include <asm/desc.h>
50#include <asm/fpu/internal.h>
51#include <asm/cpu.h>
52#include <asm/cpu_entry_area.h>
53#include <asm/mce.h>
54#include <asm/fixmap.h>
55#include <asm/mach_traps.h>
56#include <asm/alternative.h>
57#include <asm/fpu/xstate.h>
58#include <asm/vm86.h>
59#include <asm/umip.h>
60#include <asm/insn.h>
61#include <asm/insn-eval.h>
62
63#ifdef CONFIG_X86_64
64#include <asm/x86_init.h>
65#include <asm/proto.h>
66#else
67#include <asm/processor-flags.h>
68#include <asm/setup.h>
69#include <asm/proto.h>
70#endif
71
72DECLARE_BITMAP(system_vectors, NR_VECTORS);
73
74static inline void cond_local_irq_enable(struct pt_regs *regs)
75{
76 if (regs->flags & X86_EFLAGS_IF)
77 local_irq_enable();
78}
79
80static inline void cond_local_irq_disable(struct pt_regs *regs)
81{
82 if (regs->flags & X86_EFLAGS_IF)
83 local_irq_disable();
84}
85
86__always_inline int is_valid_bugaddr(unsigned long addr)
87{
88 if (addr < TASK_SIZE_MAX)
89 return 0;
90
91 /*
92 * We got #UD, if the text isn't readable we'd have gotten
93 * a different exception.
94 */
95 return *(unsigned short *)addr == INSN_UD2;
96}
97
98static nokprobe_inline int
99do_trap_no_signal(struct task_struct *tsk, int trapnr, const char *str,
100 struct pt_regs *regs, long error_code)
101{
102 if (v8086_mode(regs)) {
103 /*
104 * Traps 0, 1, 3, 4, and 5 should be forwarded to vm86.
105 * On nmi (interrupt 2), do_trap should not be called.
106 */
107 if (trapnr < X86_TRAP_UD) {
108 if (!handle_vm86_trap((struct kernel_vm86_regs *) regs,
109 error_code, trapnr))
110 return 0;
111 }
112 } else if (!user_mode(regs)) {
113 if (fixup_exception(regs, trapnr, error_code, 0))
114 return 0;
115
116 tsk->thread.error_code = error_code;
117 tsk->thread.trap_nr = trapnr;
118 die(str, regs, error_code);
119 }
120
121 /*
122 * We want error_code and trap_nr set for userspace faults and
123 * kernelspace faults which result in die(), but not
124 * kernelspace faults which are fixed up. die() gives the
125 * process no chance to handle the signal and notice the
126 * kernel fault information, so that won't result in polluting
127 * the information about previously queued, but not yet
128 * delivered, faults. See also exc_general_protection below.
129 */
130 tsk->thread.error_code = error_code;
131 tsk->thread.trap_nr = trapnr;
132
133 return -1;
134}
135
136static void show_signal(struct task_struct *tsk, int signr,
137 const char *type, const char *desc,
138 struct pt_regs *regs, long error_code)
139{
140 if (show_unhandled_signals && unhandled_signal(tsk, signr) &&
141 printk_ratelimit()) {
142 pr_info("%s[%d] %s%s ip:%lx sp:%lx error:%lx",
143 tsk->comm, task_pid_nr(tsk), type, desc,
144 regs->ip, regs->sp, error_code);
145 print_vma_addr(KERN_CONT " in ", regs->ip);
146 pr_cont("\n");
147 }
148}
149
150static void
151do_trap(int trapnr, int signr, char *str, struct pt_regs *regs,
152 long error_code, int sicode, void __user *addr)
153{
154 struct task_struct *tsk = current;
155
156 if (!do_trap_no_signal(tsk, trapnr, str, regs, error_code))
157 return;
158
159 show_signal(tsk, signr, "trap ", str, regs, error_code);
160
161 if (!sicode)
162 force_sig(signr);
163 else
164 force_sig_fault(signr, sicode, addr);
165}
166NOKPROBE_SYMBOL(do_trap);
167
168static void do_error_trap(struct pt_regs *regs, long error_code, char *str,
169 unsigned long trapnr, int signr, int sicode, void __user *addr)
170{
171 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
172
173 if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) !=
174 NOTIFY_STOP) {
175 cond_local_irq_enable(regs);
176 do_trap(trapnr, signr, str, regs, error_code, sicode, addr);
177 cond_local_irq_disable(regs);
178 }
179}
180
181/*
182 * Posix requires to provide the address of the faulting instruction for
183 * SIGILL (#UD) and SIGFPE (#DE) in the si_addr member of siginfo_t.
184 *
185 * This address is usually regs->ip, but when an uprobe moved the code out
186 * of line then regs->ip points to the XOL code which would confuse
187 * anything which analyzes the fault address vs. the unmodified binary. If
188 * a trap happened in XOL code then uprobe maps regs->ip back to the
189 * original instruction address.
190 */
191static __always_inline void __user *error_get_trap_addr(struct pt_regs *regs)
192{
193 return (void __user *)uprobe_get_trap_addr(regs);
194}
195
196DEFINE_IDTENTRY(exc_divide_error)
197{
198 do_error_trap(regs, 0, "divide_error", X86_TRAP_DE, SIGFPE,
199 FPE_INTDIV, error_get_trap_addr(regs));
200}
201
202DEFINE_IDTENTRY(exc_overflow)
203{
204 do_error_trap(regs, 0, "overflow", X86_TRAP_OF, SIGSEGV, 0, NULL);
205}
206
207#ifdef CONFIG_X86_F00F_BUG
208void handle_invalid_op(struct pt_regs *regs)
209#else
210static inline void handle_invalid_op(struct pt_regs *regs)
211#endif
212{
213 do_error_trap(regs, 0, "invalid opcode", X86_TRAP_UD, SIGILL,
214 ILL_ILLOPN, error_get_trap_addr(regs));
215}
216
217static noinstr bool handle_bug(struct pt_regs *regs)
218{
219 bool handled = false;
220
221 if (!is_valid_bugaddr(regs->ip))
222 return handled;
223
224 /*
225 * All lies, just get the WARN/BUG out.
226 */
227 instrumentation_begin();
228 /*
229 * Since we're emulating a CALL with exceptions, restore the interrupt
230 * state to what it was at the exception site.
231 */
232 if (regs->flags & X86_EFLAGS_IF)
233 raw_local_irq_enable();
234 if (report_bug(regs->ip, regs) == BUG_TRAP_TYPE_WARN) {
235 regs->ip += LEN_UD2;
236 handled = true;
237 }
238 if (regs->flags & X86_EFLAGS_IF)
239 raw_local_irq_disable();
240 instrumentation_end();
241
242 return handled;
243}
244
245DEFINE_IDTENTRY_RAW(exc_invalid_op)
246{
247 irqentry_state_t state;
248
249 /*
250 * We use UD2 as a short encoding for 'CALL __WARN', as such
251 * handle it before exception entry to avoid recursive WARN
252 * in case exception entry is the one triggering WARNs.
253 */
254 if (!user_mode(regs) && handle_bug(regs))
255 return;
256
257 state = irqentry_enter(regs);
258 instrumentation_begin();
259 handle_invalid_op(regs);
260 instrumentation_end();
261 irqentry_exit(regs, state);
262}
263
264DEFINE_IDTENTRY(exc_coproc_segment_overrun)
265{
266 do_error_trap(regs, 0, "coprocessor segment overrun",
267 X86_TRAP_OLD_MF, SIGFPE, 0, NULL);
268}
269
270DEFINE_IDTENTRY_ERRORCODE(exc_invalid_tss)
271{
272 do_error_trap(regs, error_code, "invalid TSS", X86_TRAP_TS, SIGSEGV,
273 0, NULL);
274}
275
276DEFINE_IDTENTRY_ERRORCODE(exc_segment_not_present)
277{
278 do_error_trap(regs, error_code, "segment not present", X86_TRAP_NP,
279 SIGBUS, 0, NULL);
280}
281
282DEFINE_IDTENTRY_ERRORCODE(exc_stack_segment)
283{
284 do_error_trap(regs, error_code, "stack segment", X86_TRAP_SS, SIGBUS,
285 0, NULL);
286}
287
288DEFINE_IDTENTRY_ERRORCODE(exc_alignment_check)
289{
290 char *str = "alignment check";
291
292 if (notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_AC, SIGBUS) == NOTIFY_STOP)
293 return;
294
295 if (!user_mode(regs))
296 die("Split lock detected\n", regs, error_code);
297
298 local_irq_enable();
299
300 if (handle_user_split_lock(regs, error_code))
301 return;
302
303 do_trap(X86_TRAP_AC, SIGBUS, "alignment check", regs,
304 error_code, BUS_ADRALN, NULL);
305
306 local_irq_disable();
307}
308
309#ifdef CONFIG_VMAP_STACK
310__visible void __noreturn handle_stack_overflow(const char *message,
311 struct pt_regs *regs,
312 unsigned long fault_address)
313{
314 printk(KERN_EMERG "BUG: stack guard page was hit at %p (stack is %p..%p)\n",
315 (void *)fault_address, current->stack,
316 (char *)current->stack + THREAD_SIZE - 1);
317 die(message, regs, 0);
318
319 /* Be absolutely certain we don't return. */
320 panic("%s", message);
321}
322#endif
323
324/*
325 * Runs on an IST stack for x86_64 and on a special task stack for x86_32.
326 *
327 * On x86_64, this is more or less a normal kernel entry. Notwithstanding the
328 * SDM's warnings about double faults being unrecoverable, returning works as
329 * expected. Presumably what the SDM actually means is that the CPU may get
330 * the register state wrong on entry, so returning could be a bad idea.
331 *
332 * Various CPU engineers have promised that double faults due to an IRET fault
333 * while the stack is read-only are, in fact, recoverable.
334 *
335 * On x86_32, this is entered through a task gate, and regs are synthesized
336 * from the TSS. Returning is, in principle, okay, but changes to regs will
337 * be lost. If, for some reason, we need to return to a context with modified
338 * regs, the shim code could be adjusted to synchronize the registers.
339 *
340 * The 32bit #DF shim provides CR2 already as an argument. On 64bit it needs
341 * to be read before doing anything else.
342 */
343DEFINE_IDTENTRY_DF(exc_double_fault)
344{
345 static const char str[] = "double fault";
346 struct task_struct *tsk = current;
347
348#ifdef CONFIG_VMAP_STACK
349 unsigned long address = read_cr2();
350#endif
351
352#ifdef CONFIG_X86_ESPFIX64
353 extern unsigned char native_irq_return_iret[];
354
355 /*
356 * If IRET takes a non-IST fault on the espfix64 stack, then we
357 * end up promoting it to a doublefault. In that case, take
358 * advantage of the fact that we're not using the normal (TSS.sp0)
359 * stack right now. We can write a fake #GP(0) frame at TSS.sp0
360 * and then modify our own IRET frame so that, when we return,
361 * we land directly at the #GP(0) vector with the stack already
362 * set up according to its expectations.
363 *
364 * The net result is that our #GP handler will think that we
365 * entered from usermode with the bad user context.
366 *
367 * No need for nmi_enter() here because we don't use RCU.
368 */
369 if (((long)regs->sp >> P4D_SHIFT) == ESPFIX_PGD_ENTRY &&
370 regs->cs == __KERNEL_CS &&
371 regs->ip == (unsigned long)native_irq_return_iret)
372 {
373 struct pt_regs *gpregs = (struct pt_regs *)this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1;
374 unsigned long *p = (unsigned long *)regs->sp;
375
376 /*
377 * regs->sp points to the failing IRET frame on the
378 * ESPFIX64 stack. Copy it to the entry stack. This fills
379 * in gpregs->ss through gpregs->ip.
380 *
381 */
382 gpregs->ip = p[0];
383 gpregs->cs = p[1];
384 gpregs->flags = p[2];
385 gpregs->sp = p[3];
386 gpregs->ss = p[4];
387 gpregs->orig_ax = 0; /* Missing (lost) #GP error code */
388
389 /*
390 * Adjust our frame so that we return straight to the #GP
391 * vector with the expected RSP value. This is safe because
392 * we won't enable interupts or schedule before we invoke
393 * general_protection, so nothing will clobber the stack
394 * frame we just set up.
395 *
396 * We will enter general_protection with kernel GSBASE,
397 * which is what the stub expects, given that the faulting
398 * RIP will be the IRET instruction.
399 */
400 regs->ip = (unsigned long)asm_exc_general_protection;
401 regs->sp = (unsigned long)&gpregs->orig_ax;
402
403 return;
404 }
405#endif
406
407 idtentry_enter_nmi(regs);
408 instrumentation_begin();
409 notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV);
410
411 tsk->thread.error_code = error_code;
412 tsk->thread.trap_nr = X86_TRAP_DF;
413
414#ifdef CONFIG_VMAP_STACK
415 /*
416 * If we overflow the stack into a guard page, the CPU will fail
417 * to deliver #PF and will send #DF instead. Similarly, if we
418 * take any non-IST exception while too close to the bottom of
419 * the stack, the processor will get a page fault while
420 * delivering the exception and will generate a double fault.
421 *
422 * According to the SDM (footnote in 6.15 under "Interrupt 14 -
423 * Page-Fault Exception (#PF):
424 *
425 * Processors update CR2 whenever a page fault is detected. If a
426 * second page fault occurs while an earlier page fault is being
427 * delivered, the faulting linear address of the second fault will
428 * overwrite the contents of CR2 (replacing the previous
429 * address). These updates to CR2 occur even if the page fault
430 * results in a double fault or occurs during the delivery of a
431 * double fault.
432 *
433 * The logic below has a small possibility of incorrectly diagnosing
434 * some errors as stack overflows. For example, if the IDT or GDT
435 * gets corrupted such that #GP delivery fails due to a bad descriptor
436 * causing #GP and we hit this condition while CR2 coincidentally
437 * points to the stack guard page, we'll think we overflowed the
438 * stack. Given that we're going to panic one way or another
439 * if this happens, this isn't necessarily worth fixing.
440 *
441 * If necessary, we could improve the test by only diagnosing
442 * a stack overflow if the saved RSP points within 47 bytes of
443 * the bottom of the stack: if RSP == tsk_stack + 48 and we
444 * take an exception, the stack is already aligned and there
445 * will be enough room SS, RSP, RFLAGS, CS, RIP, and a
446 * possible error code, so a stack overflow would *not* double
447 * fault. With any less space left, exception delivery could
448 * fail, and, as a practical matter, we've overflowed the
449 * stack even if the actual trigger for the double fault was
450 * something else.
451 */
452 if ((unsigned long)task_stack_page(tsk) - 1 - address < PAGE_SIZE) {
453 handle_stack_overflow("kernel stack overflow (double-fault)",
454 regs, address);
455 }
456#endif
457
458 pr_emerg("PANIC: double fault, error_code: 0x%lx\n", error_code);
459 die("double fault", regs, error_code);
460 panic("Machine halted.");
461 instrumentation_end();
462}
463
464DEFINE_IDTENTRY(exc_bounds)
465{
466 if (notify_die(DIE_TRAP, "bounds", regs, 0,
467 X86_TRAP_BR, SIGSEGV) == NOTIFY_STOP)
468 return;
469 cond_local_irq_enable(regs);
470
471 if (!user_mode(regs))
472 die("bounds", regs, 0);
473
474 do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, 0, 0, NULL);
475
476 cond_local_irq_disable(regs);
477}
478
479enum kernel_gp_hint {
480 GP_NO_HINT,
481 GP_NON_CANONICAL,
482 GP_CANONICAL
483};
484
485/*
486 * When an uncaught #GP occurs, try to determine the memory address accessed by
487 * the instruction and return that address to the caller. Also, try to figure
488 * out whether any part of the access to that address was non-canonical.
489 */
490static enum kernel_gp_hint get_kernel_gp_address(struct pt_regs *regs,
491 unsigned long *addr)
492{
493 u8 insn_buf[MAX_INSN_SIZE];
494 struct insn insn;
495
496 if (copy_from_kernel_nofault(insn_buf, (void *)regs->ip,
497 MAX_INSN_SIZE))
498 return GP_NO_HINT;
499
500 kernel_insn_init(&insn, insn_buf, MAX_INSN_SIZE);
501 insn_get_modrm(&insn);
502 insn_get_sib(&insn);
503
504 *addr = (unsigned long)insn_get_addr_ref(&insn, regs);
505 if (*addr == -1UL)
506 return GP_NO_HINT;
507
508#ifdef CONFIG_X86_64
509 /*
510 * Check that:
511 * - the operand is not in the kernel half
512 * - the last byte of the operand is not in the user canonical half
513 */
514 if (*addr < ~__VIRTUAL_MASK &&
515 *addr + insn.opnd_bytes - 1 > __VIRTUAL_MASK)
516 return GP_NON_CANONICAL;
517#endif
518
519 return GP_CANONICAL;
520}
521
522#define GPFSTR "general protection fault"
523
524DEFINE_IDTENTRY_ERRORCODE(exc_general_protection)
525{
526 char desc[sizeof(GPFSTR) + 50 + 2*sizeof(unsigned long) + 1] = GPFSTR;
527 enum kernel_gp_hint hint = GP_NO_HINT;
528 struct task_struct *tsk;
529 unsigned long gp_addr;
530 int ret;
531
532 cond_local_irq_enable(regs);
533
534 if (static_cpu_has(X86_FEATURE_UMIP)) {
535 if (user_mode(regs) && fixup_umip_exception(regs))
536 goto exit;
537 }
538
539 if (v8086_mode(regs)) {
540 local_irq_enable();
541 handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code);
542 local_irq_disable();
543 return;
544 }
545
546 tsk = current;
547
548 if (user_mode(regs)) {
549 tsk->thread.error_code = error_code;
550 tsk->thread.trap_nr = X86_TRAP_GP;
551
552 show_signal(tsk, SIGSEGV, "", desc, regs, error_code);
553 force_sig(SIGSEGV);
554 goto exit;
555 }
556
557 if (fixup_exception(regs, X86_TRAP_GP, error_code, 0))
558 goto exit;
559
560 tsk->thread.error_code = error_code;
561 tsk->thread.trap_nr = X86_TRAP_GP;
562
563 /*
564 * To be potentially processing a kprobe fault and to trust the result
565 * from kprobe_running(), we have to be non-preemptible.
566 */
567 if (!preemptible() &&
568 kprobe_running() &&
569 kprobe_fault_handler(regs, X86_TRAP_GP))
570 goto exit;
571
572 ret = notify_die(DIE_GPF, desc, regs, error_code, X86_TRAP_GP, SIGSEGV);
573 if (ret == NOTIFY_STOP)
574 goto exit;
575
576 if (error_code)
577 snprintf(desc, sizeof(desc), "segment-related " GPFSTR);
578 else
579 hint = get_kernel_gp_address(regs, &gp_addr);
580
581 if (hint != GP_NO_HINT)
582 snprintf(desc, sizeof(desc), GPFSTR ", %s 0x%lx",
583 (hint == GP_NON_CANONICAL) ? "probably for non-canonical address"
584 : "maybe for address",
585 gp_addr);
586
587 /*
588 * KASAN is interested only in the non-canonical case, clear it
589 * otherwise.
590 */
591 if (hint != GP_NON_CANONICAL)
592 gp_addr = 0;
593
594 die_addr(desc, regs, error_code, gp_addr);
595
596exit:
597 cond_local_irq_disable(regs);
598}
599
600static bool do_int3(struct pt_regs *regs)
601{
602 int res;
603
604#ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
605 if (kgdb_ll_trap(DIE_INT3, "int3", regs, 0, X86_TRAP_BP,
606 SIGTRAP) == NOTIFY_STOP)
607 return true;
608#endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
609
610#ifdef CONFIG_KPROBES
611 if (kprobe_int3_handler(regs))
612 return true;
613#endif
614 res = notify_die(DIE_INT3, "int3", regs, 0, X86_TRAP_BP, SIGTRAP);
615
616 return res == NOTIFY_STOP;
617}
618
619static void do_int3_user(struct pt_regs *regs)
620{
621 if (do_int3(regs))
622 return;
623
624 cond_local_irq_enable(regs);
625 do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, 0, 0, NULL);
626 cond_local_irq_disable(regs);
627}
628
629DEFINE_IDTENTRY_RAW(exc_int3)
630{
631 /*
632 * poke_int3_handler() is completely self contained code; it does (and
633 * must) *NOT* call out to anything, lest it hits upon yet another
634 * INT3.
635 */
636 if (poke_int3_handler(regs))
637 return;
638
639 /*
640 * irqentry_enter_from_user_mode() uses static_branch_{,un}likely()
641 * and therefore can trigger INT3, hence poke_int3_handler() must
642 * be done before. If the entry came from kernel mode, then use
643 * nmi_enter() because the INT3 could have been hit in any context
644 * including NMI.
645 */
646 if (user_mode(regs)) {
647 irqentry_enter_from_user_mode(regs);
648 instrumentation_begin();
649 do_int3_user(regs);
650 instrumentation_end();
651 irqentry_exit_to_user_mode(regs);
652 } else {
653 bool irq_state = idtentry_enter_nmi(regs);
654 instrumentation_begin();
655 if (!do_int3(regs))
656 die("int3", regs, 0);
657 instrumentation_end();
658 idtentry_exit_nmi(regs, irq_state);
659 }
660}
661
662#ifdef CONFIG_X86_64
663/*
664 * Help handler running on a per-cpu (IST or entry trampoline) stack
665 * to switch to the normal thread stack if the interrupted code was in
666 * user mode. The actual stack switch is done in entry_64.S
667 */
668asmlinkage __visible noinstr struct pt_regs *sync_regs(struct pt_regs *eregs)
669{
670 struct pt_regs *regs = (struct pt_regs *)this_cpu_read(cpu_current_top_of_stack) - 1;
671 if (regs != eregs)
672 *regs = *eregs;
673 return regs;
674}
675
676struct bad_iret_stack {
677 void *error_entry_ret;
678 struct pt_regs regs;
679};
680
681asmlinkage __visible noinstr
682struct bad_iret_stack *fixup_bad_iret(struct bad_iret_stack *s)
683{
684 /*
685 * This is called from entry_64.S early in handling a fault
686 * caused by a bad iret to user mode. To handle the fault
687 * correctly, we want to move our stack frame to where it would
688 * be had we entered directly on the entry stack (rather than
689 * just below the IRET frame) and we want to pretend that the
690 * exception came from the IRET target.
691 */
692 struct bad_iret_stack tmp, *new_stack =
693 (struct bad_iret_stack *)__this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1;
694
695 /* Copy the IRET target to the temporary storage. */
696 __memcpy(&tmp.regs.ip, (void *)s->regs.sp, 5*8);
697
698 /* Copy the remainder of the stack from the current stack. */
699 __memcpy(&tmp, s, offsetof(struct bad_iret_stack, regs.ip));
700
701 /* Update the entry stack */
702 __memcpy(new_stack, &tmp, sizeof(tmp));
703
704 BUG_ON(!user_mode(&new_stack->regs));
705 return new_stack;
706}
707#endif
708
709static bool is_sysenter_singlestep(struct pt_regs *regs)
710{
711 /*
712 * We don't try for precision here. If we're anywhere in the region of
713 * code that can be single-stepped in the SYSENTER entry path, then
714 * assume that this is a useless single-step trap due to SYSENTER
715 * being invoked with TF set. (We don't know in advance exactly
716 * which instructions will be hit because BTF could plausibly
717 * be set.)
718 */
719#ifdef CONFIG_X86_32
720 return (regs->ip - (unsigned long)__begin_SYSENTER_singlestep_region) <
721 (unsigned long)__end_SYSENTER_singlestep_region -
722 (unsigned long)__begin_SYSENTER_singlestep_region;
723#elif defined(CONFIG_IA32_EMULATION)
724 return (regs->ip - (unsigned long)entry_SYSENTER_compat) <
725 (unsigned long)__end_entry_SYSENTER_compat -
726 (unsigned long)entry_SYSENTER_compat;
727#else
728 return false;
729#endif
730}
731
732static __always_inline unsigned long debug_read_clear_dr6(void)
733{
734 unsigned long dr6;
735
736 /*
737 * The Intel SDM says:
738 *
739 * Certain debug exceptions may clear bits 0-3. The remaining
740 * contents of the DR6 register are never cleared by the
741 * processor. To avoid confusion in identifying debug
742 * exceptions, debug handlers should clear the register before
743 * returning to the interrupted task.
744 *
745 * Keep it simple: clear DR6 immediately.
746 */
747 get_debugreg(dr6, 6);
748 set_debugreg(0, 6);
749 /* Filter out all the reserved bits which are preset to 1 */
750 dr6 &= ~DR6_RESERVED;
751
752 return dr6;
753}
754
755/*
756 * Our handling of the processor debug registers is non-trivial.
757 * We do not clear them on entry and exit from the kernel. Therefore
758 * it is possible to get a watchpoint trap here from inside the kernel.
759 * However, the code in ./ptrace.c has ensured that the user can
760 * only set watchpoints on userspace addresses. Therefore the in-kernel
761 * watchpoint trap can only occur in code which is reading/writing
762 * from user space. Such code must not hold kernel locks (since it
763 * can equally take a page fault), therefore it is safe to call
764 * force_sig_info even though that claims and releases locks.
765 *
766 * Code in ./signal.c ensures that the debug control register
767 * is restored before we deliver any signal, and therefore that
768 * user code runs with the correct debug control register even though
769 * we clear it here.
770 *
771 * Being careful here means that we don't have to be as careful in a
772 * lot of more complicated places (task switching can be a bit lazy
773 * about restoring all the debug state, and ptrace doesn't have to
774 * find every occurrence of the TF bit that could be saved away even
775 * by user code)
776 *
777 * May run on IST stack.
778 */
779static void handle_debug(struct pt_regs *regs, unsigned long dr6, bool user)
780{
781 struct task_struct *tsk = current;
782 bool user_icebp;
783 int si_code;
784
785 /*
786 * The SDM says "The processor clears the BTF flag when it
787 * generates a debug exception." Clear TIF_BLOCKSTEP to keep
788 * TIF_BLOCKSTEP in sync with the hardware BTF flag.
789 */
790 clear_thread_flag(TIF_BLOCKSTEP);
791
792 /*
793 * If DR6 is zero, no point in trying to handle it. The kernel is
794 * not using INT1.
795 */
796 if (!user && !dr6)
797 return;
798
799 /*
800 * If dr6 has no reason to give us about the origin of this trap,
801 * then it's very likely the result of an icebp/int01 trap.
802 * User wants a sigtrap for that.
803 */
804 user_icebp = user && !dr6;
805
806 /* Store the virtualized DR6 value */
807 tsk->thread.debugreg6 = dr6;
808
809#ifdef CONFIG_KPROBES
810 if (kprobe_debug_handler(regs)) {
811 return;
812 }
813#endif
814
815 if (notify_die(DIE_DEBUG, "debug", regs, (long)&dr6, 0,
816 SIGTRAP) == NOTIFY_STOP) {
817 return;
818 }
819
820 /* It's safe to allow irq's after DR6 has been saved */
821 cond_local_irq_enable(regs);
822
823 if (v8086_mode(regs)) {
824 handle_vm86_trap((struct kernel_vm86_regs *) regs, 0,
825 X86_TRAP_DB);
826 goto out;
827 }
828
829 if (WARN_ON_ONCE((dr6 & DR_STEP) && !user_mode(regs))) {
830 /*
831 * Historical junk that used to handle SYSENTER single-stepping.
832 * This should be unreachable now. If we survive for a while
833 * without anyone hitting this warning, we'll turn this into
834 * an oops.
835 */
836 tsk->thread.debugreg6 &= ~DR_STEP;
837 set_tsk_thread_flag(tsk, TIF_SINGLESTEP);
838 regs->flags &= ~X86_EFLAGS_TF;
839 }
840
841 si_code = get_si_code(tsk->thread.debugreg6);
842 if (tsk->thread.debugreg6 & (DR_STEP | DR_TRAP_BITS) || user_icebp)
843 send_sigtrap(regs, 0, si_code);
844
845out:
846 cond_local_irq_disable(regs);
847}
848
849static __always_inline void exc_debug_kernel(struct pt_regs *regs,
850 unsigned long dr6)
851{
852 /*
853 * Disable breakpoints during exception handling; recursive exceptions
854 * are exceedingly 'fun'.
855 *
856 * Since this function is NOKPROBE, and that also applies to
857 * HW_BREAKPOINT_X, we can't hit a breakpoint before this (XXX except a
858 * HW_BREAKPOINT_W on our stack)
859 *
860 * Entry text is excluded for HW_BP_X and cpu_entry_area, which
861 * includes the entry stack is excluded for everything.
862 */
863 unsigned long dr7 = local_db_save();
864 bool irq_state = idtentry_enter_nmi(regs);
865 instrumentation_begin();
866
867 /*
868 * If something gets miswired and we end up here for a user mode
869 * #DB, we will malfunction.
870 */
871 WARN_ON_ONCE(user_mode(regs));
872
873 /*
874 * Catch SYSENTER with TF set and clear DR_STEP. If this hit a
875 * watchpoint at the same time then that will still be handled.
876 */
877 if ((dr6 & DR_STEP) && is_sysenter_singlestep(regs))
878 dr6 &= ~DR_STEP;
879
880 handle_debug(regs, dr6, false);
881
882 instrumentation_end();
883 idtentry_exit_nmi(regs, irq_state);
884
885 local_db_restore(dr7);
886}
887
888static __always_inline void exc_debug_user(struct pt_regs *regs,
889 unsigned long dr6)
890{
891 /*
892 * If something gets miswired and we end up here for a kernel mode
893 * #DB, we will malfunction.
894 */
895 WARN_ON_ONCE(!user_mode(regs));
896
897 /*
898 * NB: We can't easily clear DR7 here because
899 * idtentry_exit_to_usermode() can invoke ptrace, schedule, access
900 * user memory, etc. This means that a recursive #DB is possible. If
901 * this happens, that #DB will hit exc_debug_kernel() and clear DR7.
902 * Since we're not on the IST stack right now, everything will be
903 * fine.
904 */
905
906 irqentry_enter_from_user_mode(regs);
907 instrumentation_begin();
908
909 handle_debug(regs, dr6, true);
910
911 instrumentation_end();
912 irqentry_exit_to_user_mode(regs);
913}
914
915#ifdef CONFIG_X86_64
916/* IST stack entry */
917DEFINE_IDTENTRY_DEBUG(exc_debug)
918{
919 exc_debug_kernel(regs, debug_read_clear_dr6());
920}
921
922/* User entry, runs on regular task stack */
923DEFINE_IDTENTRY_DEBUG_USER(exc_debug)
924{
925 exc_debug_user(regs, debug_read_clear_dr6());
926}
927#else
928/* 32 bit does not have separate entry points. */
929DEFINE_IDTENTRY_RAW(exc_debug)
930{
931 unsigned long dr6 = debug_read_clear_dr6();
932
933 if (user_mode(regs))
934 exc_debug_user(regs, dr6);
935 else
936 exc_debug_kernel(regs, dr6);
937}
938#endif
939
940/*
941 * Note that we play around with the 'TS' bit in an attempt to get
942 * the correct behaviour even in the presence of the asynchronous
943 * IRQ13 behaviour
944 */
945static void math_error(struct pt_regs *regs, int trapnr)
946{
947 struct task_struct *task = current;
948 struct fpu *fpu = &task->thread.fpu;
949 int si_code;
950 char *str = (trapnr == X86_TRAP_MF) ? "fpu exception" :
951 "simd exception";
952
953 cond_local_irq_enable(regs);
954
955 if (!user_mode(regs)) {
956 if (fixup_exception(regs, trapnr, 0, 0))
957 goto exit;
958
959 task->thread.error_code = 0;
960 task->thread.trap_nr = trapnr;
961
962 if (notify_die(DIE_TRAP, str, regs, 0, trapnr,
963 SIGFPE) != NOTIFY_STOP)
964 die(str, regs, 0);
965 goto exit;
966 }
967
968 /*
969 * Save the info for the exception handler and clear the error.
970 */
971 fpu__save(fpu);
972
973 task->thread.trap_nr = trapnr;
974 task->thread.error_code = 0;
975
976 si_code = fpu__exception_code(fpu, trapnr);
977 /* Retry when we get spurious exceptions: */
978 if (!si_code)
979 goto exit;
980
981 force_sig_fault(SIGFPE, si_code,
982 (void __user *)uprobe_get_trap_addr(regs));
983exit:
984 cond_local_irq_disable(regs);
985}
986
987DEFINE_IDTENTRY(exc_coprocessor_error)
988{
989 math_error(regs, X86_TRAP_MF);
990}
991
992DEFINE_IDTENTRY(exc_simd_coprocessor_error)
993{
994 if (IS_ENABLED(CONFIG_X86_INVD_BUG)) {
995 /* AMD 486 bug: INVD in CPL 0 raises #XF instead of #GP */
996 if (!static_cpu_has(X86_FEATURE_XMM)) {
997 __exc_general_protection(regs, 0);
998 return;
999 }
1000 }
1001 math_error(regs, X86_TRAP_XF);
1002}
1003
1004DEFINE_IDTENTRY(exc_spurious_interrupt_bug)
1005{
1006 /*
1007 * This addresses a Pentium Pro Erratum:
1008 *
1009 * PROBLEM: If the APIC subsystem is configured in mixed mode with
1010 * Virtual Wire mode implemented through the local APIC, an
1011 * interrupt vector of 0Fh (Intel reserved encoding) may be
1012 * generated by the local APIC (Int 15). This vector may be
1013 * generated upon receipt of a spurious interrupt (an interrupt
1014 * which is removed before the system receives the INTA sequence)
1015 * instead of the programmed 8259 spurious interrupt vector.
1016 *
1017 * IMPLICATION: The spurious interrupt vector programmed in the
1018 * 8259 is normally handled by an operating system's spurious
1019 * interrupt handler. However, a vector of 0Fh is unknown to some
1020 * operating systems, which would crash if this erratum occurred.
1021 *
1022 * In theory this could be limited to 32bit, but the handler is not
1023 * hurting and who knows which other CPUs suffer from this.
1024 */
1025}
1026
1027DEFINE_IDTENTRY(exc_device_not_available)
1028{
1029 unsigned long cr0 = read_cr0();
1030
1031#ifdef CONFIG_MATH_EMULATION
1032 if (!boot_cpu_has(X86_FEATURE_FPU) && (cr0 & X86_CR0_EM)) {
1033 struct math_emu_info info = { };
1034
1035 cond_local_irq_enable(regs);
1036
1037 info.regs = regs;
1038 math_emulate(&info);
1039
1040 cond_local_irq_disable(regs);
1041 return;
1042 }
1043#endif
1044
1045 /* This should not happen. */
1046 if (WARN(cr0 & X86_CR0_TS, "CR0.TS was set")) {
1047 /* Try to fix it up and carry on. */
1048 write_cr0(cr0 & ~X86_CR0_TS);
1049 } else {
1050 /*
1051 * Something terrible happened, and we're better off trying
1052 * to kill the task than getting stuck in a never-ending
1053 * loop of #NM faults.
1054 */
1055 die("unexpected #NM exception", regs, 0);
1056 }
1057}
1058
1059#ifdef CONFIG_X86_32
1060DEFINE_IDTENTRY_SW(iret_error)
1061{
1062 local_irq_enable();
1063 if (notify_die(DIE_TRAP, "iret exception", regs, 0,
1064 X86_TRAP_IRET, SIGILL) != NOTIFY_STOP) {
1065 do_trap(X86_TRAP_IRET, SIGILL, "iret exception", regs, 0,
1066 ILL_BADSTK, (void __user *)NULL);
1067 }
1068 local_irq_disable();
1069}
1070#endif
1071
1072void __init trap_init(void)
1073{
1074 /* Init cpu_entry_area before IST entries are set up */
1075 setup_cpu_entry_areas();
1076
1077 idt_setup_traps();
1078
1079 /*
1080 * Should be a barrier for any external CPU state:
1081 */
1082 cpu_init();
1083
1084 idt_setup_ist_traps();
1085}
1/*
2 * Copyright (C) 1991, 1992 Linus Torvalds
3 * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
4 *
5 * Pentium III FXSR, SSE support
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 */
8
9/*
10 * Handle hardware traps and faults.
11 */
12#include <linux/interrupt.h>
13#include <linux/kallsyms.h>
14#include <linux/spinlock.h>
15#include <linux/kprobes.h>
16#include <linux/uaccess.h>
17#include <linux/kdebug.h>
18#include <linux/kgdb.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/ptrace.h>
22#include <linux/string.h>
23#include <linux/delay.h>
24#include <linux/errno.h>
25#include <linux/kexec.h>
26#include <linux/sched.h>
27#include <linux/timer.h>
28#include <linux/init.h>
29#include <linux/bug.h>
30#include <linux/nmi.h>
31#include <linux/mm.h>
32#include <linux/smp.h>
33#include <linux/io.h>
34
35#ifdef CONFIG_EISA
36#include <linux/ioport.h>
37#include <linux/eisa.h>
38#endif
39
40#ifdef CONFIG_MCA
41#include <linux/mca.h>
42#endif
43
44#if defined(CONFIG_EDAC)
45#include <linux/edac.h>
46#endif
47
48#include <asm/kmemcheck.h>
49#include <asm/stacktrace.h>
50#include <asm/processor.h>
51#include <asm/debugreg.h>
52#include <linux/atomic.h>
53#include <asm/system.h>
54#include <asm/traps.h>
55#include <asm/desc.h>
56#include <asm/i387.h>
57#include <asm/mce.h>
58
59#include <asm/mach_traps.h>
60
61#ifdef CONFIG_X86_64
62#include <asm/x86_init.h>
63#include <asm/pgalloc.h>
64#include <asm/proto.h>
65#else
66#include <asm/processor-flags.h>
67#include <asm/setup.h>
68
69asmlinkage int system_call(void);
70
71/* Do we ignore FPU interrupts ? */
72char ignore_fpu_irq;
73
74/*
75 * The IDT has to be page-aligned to simplify the Pentium
76 * F0 0F bug workaround.
77 */
78gate_desc idt_table[NR_VECTORS] __page_aligned_data = { { { { 0, 0 } } }, };
79#endif
80
81DECLARE_BITMAP(used_vectors, NR_VECTORS);
82EXPORT_SYMBOL_GPL(used_vectors);
83
84static int ignore_nmis;
85
86int unknown_nmi_panic;
87/*
88 * Prevent NMI reason port (0x61) being accessed simultaneously, can
89 * only be used in NMI handler.
90 */
91static DEFINE_RAW_SPINLOCK(nmi_reason_lock);
92
93static inline void conditional_sti(struct pt_regs *regs)
94{
95 if (regs->flags & X86_EFLAGS_IF)
96 local_irq_enable();
97}
98
99static inline void preempt_conditional_sti(struct pt_regs *regs)
100{
101 inc_preempt_count();
102 if (regs->flags & X86_EFLAGS_IF)
103 local_irq_enable();
104}
105
106static inline void conditional_cli(struct pt_regs *regs)
107{
108 if (regs->flags & X86_EFLAGS_IF)
109 local_irq_disable();
110}
111
112static inline void preempt_conditional_cli(struct pt_regs *regs)
113{
114 if (regs->flags & X86_EFLAGS_IF)
115 local_irq_disable();
116 dec_preempt_count();
117}
118
119static void __kprobes
120do_trap(int trapnr, int signr, char *str, struct pt_regs *regs,
121 long error_code, siginfo_t *info)
122{
123 struct task_struct *tsk = current;
124
125#ifdef CONFIG_X86_32
126 if (regs->flags & X86_VM_MASK) {
127 /*
128 * traps 0, 1, 3, 4, and 5 should be forwarded to vm86.
129 * On nmi (interrupt 2), do_trap should not be called.
130 */
131 if (trapnr < 6)
132 goto vm86_trap;
133 goto trap_signal;
134 }
135#endif
136
137 if (!user_mode(regs))
138 goto kernel_trap;
139
140#ifdef CONFIG_X86_32
141trap_signal:
142#endif
143 /*
144 * We want error_code and trap_no set for userspace faults and
145 * kernelspace faults which result in die(), but not
146 * kernelspace faults which are fixed up. die() gives the
147 * process no chance to handle the signal and notice the
148 * kernel fault information, so that won't result in polluting
149 * the information about previously queued, but not yet
150 * delivered, faults. See also do_general_protection below.
151 */
152 tsk->thread.error_code = error_code;
153 tsk->thread.trap_no = trapnr;
154
155#ifdef CONFIG_X86_64
156 if (show_unhandled_signals && unhandled_signal(tsk, signr) &&
157 printk_ratelimit()) {
158 printk(KERN_INFO
159 "%s[%d] trap %s ip:%lx sp:%lx error:%lx",
160 tsk->comm, tsk->pid, str,
161 regs->ip, regs->sp, error_code);
162 print_vma_addr(" in ", regs->ip);
163 printk("\n");
164 }
165#endif
166
167 if (info)
168 force_sig_info(signr, info, tsk);
169 else
170 force_sig(signr, tsk);
171 return;
172
173kernel_trap:
174 if (!fixup_exception(regs)) {
175 tsk->thread.error_code = error_code;
176 tsk->thread.trap_no = trapnr;
177 die(str, regs, error_code);
178 }
179 return;
180
181#ifdef CONFIG_X86_32
182vm86_trap:
183 if (handle_vm86_trap((struct kernel_vm86_regs *) regs,
184 error_code, trapnr))
185 goto trap_signal;
186 return;
187#endif
188}
189
190#define DO_ERROR(trapnr, signr, str, name) \
191dotraplinkage void do_##name(struct pt_regs *regs, long error_code) \
192{ \
193 if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) \
194 == NOTIFY_STOP) \
195 return; \
196 conditional_sti(regs); \
197 do_trap(trapnr, signr, str, regs, error_code, NULL); \
198}
199
200#define DO_ERROR_INFO(trapnr, signr, str, name, sicode, siaddr) \
201dotraplinkage void do_##name(struct pt_regs *regs, long error_code) \
202{ \
203 siginfo_t info; \
204 info.si_signo = signr; \
205 info.si_errno = 0; \
206 info.si_code = sicode; \
207 info.si_addr = (void __user *)siaddr; \
208 if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) \
209 == NOTIFY_STOP) \
210 return; \
211 conditional_sti(regs); \
212 do_trap(trapnr, signr, str, regs, error_code, &info); \
213}
214
215DO_ERROR_INFO(0, SIGFPE, "divide error", divide_error, FPE_INTDIV, regs->ip)
216DO_ERROR(4, SIGSEGV, "overflow", overflow)
217DO_ERROR(5, SIGSEGV, "bounds", bounds)
218DO_ERROR_INFO(6, SIGILL, "invalid opcode", invalid_op, ILL_ILLOPN, regs->ip)
219DO_ERROR(9, SIGFPE, "coprocessor segment overrun", coprocessor_segment_overrun)
220DO_ERROR(10, SIGSEGV, "invalid TSS", invalid_TSS)
221DO_ERROR(11, SIGBUS, "segment not present", segment_not_present)
222#ifdef CONFIG_X86_32
223DO_ERROR(12, SIGBUS, "stack segment", stack_segment)
224#endif
225DO_ERROR_INFO(17, SIGBUS, "alignment check", alignment_check, BUS_ADRALN, 0)
226
227#ifdef CONFIG_X86_64
228/* Runs on IST stack */
229dotraplinkage void do_stack_segment(struct pt_regs *regs, long error_code)
230{
231 if (notify_die(DIE_TRAP, "stack segment", regs, error_code,
232 12, SIGBUS) == NOTIFY_STOP)
233 return;
234 preempt_conditional_sti(regs);
235 do_trap(12, SIGBUS, "stack segment", regs, error_code, NULL);
236 preempt_conditional_cli(regs);
237}
238
239dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code)
240{
241 static const char str[] = "double fault";
242 struct task_struct *tsk = current;
243
244 /* Return not checked because double check cannot be ignored */
245 notify_die(DIE_TRAP, str, regs, error_code, 8, SIGSEGV);
246
247 tsk->thread.error_code = error_code;
248 tsk->thread.trap_no = 8;
249
250 /*
251 * This is always a kernel trap and never fixable (and thus must
252 * never return).
253 */
254 for (;;)
255 die(str, regs, error_code);
256}
257#endif
258
259dotraplinkage void __kprobes
260do_general_protection(struct pt_regs *regs, long error_code)
261{
262 struct task_struct *tsk;
263
264 conditional_sti(regs);
265
266#ifdef CONFIG_X86_32
267 if (regs->flags & X86_VM_MASK)
268 goto gp_in_vm86;
269#endif
270
271 tsk = current;
272 if (!user_mode(regs))
273 goto gp_in_kernel;
274
275 tsk->thread.error_code = error_code;
276 tsk->thread.trap_no = 13;
277
278 if (show_unhandled_signals && unhandled_signal(tsk, SIGSEGV) &&
279 printk_ratelimit()) {
280 printk(KERN_INFO
281 "%s[%d] general protection ip:%lx sp:%lx error:%lx",
282 tsk->comm, task_pid_nr(tsk),
283 regs->ip, regs->sp, error_code);
284 print_vma_addr(" in ", regs->ip);
285 printk("\n");
286 }
287
288 force_sig(SIGSEGV, tsk);
289 return;
290
291#ifdef CONFIG_X86_32
292gp_in_vm86:
293 local_irq_enable();
294 handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code);
295 return;
296#endif
297
298gp_in_kernel:
299 if (fixup_exception(regs))
300 return;
301
302 tsk->thread.error_code = error_code;
303 tsk->thread.trap_no = 13;
304 if (notify_die(DIE_GPF, "general protection fault", regs,
305 error_code, 13, SIGSEGV) == NOTIFY_STOP)
306 return;
307 die("general protection fault", regs, error_code);
308}
309
310static int __init setup_unknown_nmi_panic(char *str)
311{
312 unknown_nmi_panic = 1;
313 return 1;
314}
315__setup("unknown_nmi_panic", setup_unknown_nmi_panic);
316
317static notrace __kprobes void
318pci_serr_error(unsigned char reason, struct pt_regs *regs)
319{
320 pr_emerg("NMI: PCI system error (SERR) for reason %02x on CPU %d.\n",
321 reason, smp_processor_id());
322
323 /*
324 * On some machines, PCI SERR line is used to report memory
325 * errors. EDAC makes use of it.
326 */
327#if defined(CONFIG_EDAC)
328 if (edac_handler_set()) {
329 edac_atomic_assert_error();
330 return;
331 }
332#endif
333
334 if (panic_on_unrecovered_nmi)
335 panic("NMI: Not continuing");
336
337 pr_emerg("Dazed and confused, but trying to continue\n");
338
339 /* Clear and disable the PCI SERR error line. */
340 reason = (reason & NMI_REASON_CLEAR_MASK) | NMI_REASON_CLEAR_SERR;
341 outb(reason, NMI_REASON_PORT);
342}
343
344static notrace __kprobes void
345io_check_error(unsigned char reason, struct pt_regs *regs)
346{
347 unsigned long i;
348
349 pr_emerg(
350 "NMI: IOCK error (debug interrupt?) for reason %02x on CPU %d.\n",
351 reason, smp_processor_id());
352 show_registers(regs);
353
354 if (panic_on_io_nmi)
355 panic("NMI IOCK error: Not continuing");
356
357 /* Re-enable the IOCK line, wait for a few seconds */
358 reason = (reason & NMI_REASON_CLEAR_MASK) | NMI_REASON_CLEAR_IOCHK;
359 outb(reason, NMI_REASON_PORT);
360
361 i = 20000;
362 while (--i) {
363 touch_nmi_watchdog();
364 udelay(100);
365 }
366
367 reason &= ~NMI_REASON_CLEAR_IOCHK;
368 outb(reason, NMI_REASON_PORT);
369}
370
371static notrace __kprobes void
372unknown_nmi_error(unsigned char reason, struct pt_regs *regs)
373{
374 if (notify_die(DIE_NMIUNKNOWN, "nmi", regs, reason, 2, SIGINT) ==
375 NOTIFY_STOP)
376 return;
377#ifdef CONFIG_MCA
378 /*
379 * Might actually be able to figure out what the guilty party
380 * is:
381 */
382 if (MCA_bus) {
383 mca_handle_nmi();
384 return;
385 }
386#endif
387 pr_emerg("Uhhuh. NMI received for unknown reason %02x on CPU %d.\n",
388 reason, smp_processor_id());
389
390 pr_emerg("Do you have a strange power saving mode enabled?\n");
391 if (unknown_nmi_panic || panic_on_unrecovered_nmi)
392 panic("NMI: Not continuing");
393
394 pr_emerg("Dazed and confused, but trying to continue\n");
395}
396
397static notrace __kprobes void default_do_nmi(struct pt_regs *regs)
398{
399 unsigned char reason = 0;
400
401 /*
402 * CPU-specific NMI must be processed before non-CPU-specific
403 * NMI, otherwise we may lose it, because the CPU-specific
404 * NMI can not be detected/processed on other CPUs.
405 */
406 if (notify_die(DIE_NMI, "nmi", regs, 0, 2, SIGINT) == NOTIFY_STOP)
407 return;
408
409 /* Non-CPU-specific NMI: NMI sources can be processed on any CPU */
410 raw_spin_lock(&nmi_reason_lock);
411 reason = get_nmi_reason();
412
413 if (reason & NMI_REASON_MASK) {
414 if (reason & NMI_REASON_SERR)
415 pci_serr_error(reason, regs);
416 else if (reason & NMI_REASON_IOCHK)
417 io_check_error(reason, regs);
418#ifdef CONFIG_X86_32
419 /*
420 * Reassert NMI in case it became active
421 * meanwhile as it's edge-triggered:
422 */
423 reassert_nmi();
424#endif
425 raw_spin_unlock(&nmi_reason_lock);
426 return;
427 }
428 raw_spin_unlock(&nmi_reason_lock);
429
430 unknown_nmi_error(reason, regs);
431}
432
433dotraplinkage notrace __kprobes void
434do_nmi(struct pt_regs *regs, long error_code)
435{
436 nmi_enter();
437
438 inc_irq_stat(__nmi_count);
439
440 if (!ignore_nmis)
441 default_do_nmi(regs);
442
443 nmi_exit();
444}
445
446void stop_nmi(void)
447{
448 ignore_nmis++;
449}
450
451void restart_nmi(void)
452{
453 ignore_nmis--;
454}
455
456/* May run on IST stack. */
457dotraplinkage void __kprobes do_int3(struct pt_regs *regs, long error_code)
458{
459#ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
460 if (kgdb_ll_trap(DIE_INT3, "int3", regs, error_code, 3, SIGTRAP)
461 == NOTIFY_STOP)
462 return;
463#endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
464#ifdef CONFIG_KPROBES
465 if (notify_die(DIE_INT3, "int3", regs, error_code, 3, SIGTRAP)
466 == NOTIFY_STOP)
467 return;
468#else
469 if (notify_die(DIE_TRAP, "int3", regs, error_code, 3, SIGTRAP)
470 == NOTIFY_STOP)
471 return;
472#endif
473
474 preempt_conditional_sti(regs);
475 do_trap(3, SIGTRAP, "int3", regs, error_code, NULL);
476 preempt_conditional_cli(regs);
477}
478
479#ifdef CONFIG_X86_64
480/*
481 * Help handler running on IST stack to switch back to user stack
482 * for scheduling or signal handling. The actual stack switch is done in
483 * entry.S
484 */
485asmlinkage __kprobes struct pt_regs *sync_regs(struct pt_regs *eregs)
486{
487 struct pt_regs *regs = eregs;
488 /* Did already sync */
489 if (eregs == (struct pt_regs *)eregs->sp)
490 ;
491 /* Exception from user space */
492 else if (user_mode(eregs))
493 regs = task_pt_regs(current);
494 /*
495 * Exception from kernel and interrupts are enabled. Move to
496 * kernel process stack.
497 */
498 else if (eregs->flags & X86_EFLAGS_IF)
499 regs = (struct pt_regs *)(eregs->sp -= sizeof(struct pt_regs));
500 if (eregs != regs)
501 *regs = *eregs;
502 return regs;
503}
504#endif
505
506/*
507 * Our handling of the processor debug registers is non-trivial.
508 * We do not clear them on entry and exit from the kernel. Therefore
509 * it is possible to get a watchpoint trap here from inside the kernel.
510 * However, the code in ./ptrace.c has ensured that the user can
511 * only set watchpoints on userspace addresses. Therefore the in-kernel
512 * watchpoint trap can only occur in code which is reading/writing
513 * from user space. Such code must not hold kernel locks (since it
514 * can equally take a page fault), therefore it is safe to call
515 * force_sig_info even though that claims and releases locks.
516 *
517 * Code in ./signal.c ensures that the debug control register
518 * is restored before we deliver any signal, and therefore that
519 * user code runs with the correct debug control register even though
520 * we clear it here.
521 *
522 * Being careful here means that we don't have to be as careful in a
523 * lot of more complicated places (task switching can be a bit lazy
524 * about restoring all the debug state, and ptrace doesn't have to
525 * find every occurrence of the TF bit that could be saved away even
526 * by user code)
527 *
528 * May run on IST stack.
529 */
530dotraplinkage void __kprobes do_debug(struct pt_regs *regs, long error_code)
531{
532 struct task_struct *tsk = current;
533 int user_icebp = 0;
534 unsigned long dr6;
535 int si_code;
536
537 get_debugreg(dr6, 6);
538
539 /* Filter out all the reserved bits which are preset to 1 */
540 dr6 &= ~DR6_RESERVED;
541
542 /*
543 * If dr6 has no reason to give us about the origin of this trap,
544 * then it's very likely the result of an icebp/int01 trap.
545 * User wants a sigtrap for that.
546 */
547 if (!dr6 && user_mode(regs))
548 user_icebp = 1;
549
550 /* Catch kmemcheck conditions first of all! */
551 if ((dr6 & DR_STEP) && kmemcheck_trap(regs))
552 return;
553
554 /* DR6 may or may not be cleared by the CPU */
555 set_debugreg(0, 6);
556
557 /*
558 * The processor cleared BTF, so don't mark that we need it set.
559 */
560 clear_tsk_thread_flag(tsk, TIF_BLOCKSTEP);
561
562 /* Store the virtualized DR6 value */
563 tsk->thread.debugreg6 = dr6;
564
565 if (notify_die(DIE_DEBUG, "debug", regs, PTR_ERR(&dr6), error_code,
566 SIGTRAP) == NOTIFY_STOP)
567 return;
568
569 /* It's safe to allow irq's after DR6 has been saved */
570 preempt_conditional_sti(regs);
571
572 if (regs->flags & X86_VM_MASK) {
573 handle_vm86_trap((struct kernel_vm86_regs *) regs,
574 error_code, 1);
575 preempt_conditional_cli(regs);
576 return;
577 }
578
579 /*
580 * Single-stepping through system calls: ignore any exceptions in
581 * kernel space, but re-enable TF when returning to user mode.
582 *
583 * We already checked v86 mode above, so we can check for kernel mode
584 * by just checking the CPL of CS.
585 */
586 if ((dr6 & DR_STEP) && !user_mode(regs)) {
587 tsk->thread.debugreg6 &= ~DR_STEP;
588 set_tsk_thread_flag(tsk, TIF_SINGLESTEP);
589 regs->flags &= ~X86_EFLAGS_TF;
590 }
591 si_code = get_si_code(tsk->thread.debugreg6);
592 if (tsk->thread.debugreg6 & (DR_STEP | DR_TRAP_BITS) || user_icebp)
593 send_sigtrap(tsk, regs, error_code, si_code);
594 preempt_conditional_cli(regs);
595
596 return;
597}
598
599/*
600 * Note that we play around with the 'TS' bit in an attempt to get
601 * the correct behaviour even in the presence of the asynchronous
602 * IRQ13 behaviour
603 */
604void math_error(struct pt_regs *regs, int error_code, int trapnr)
605{
606 struct task_struct *task = current;
607 siginfo_t info;
608 unsigned short err;
609 char *str = (trapnr == 16) ? "fpu exception" : "simd exception";
610
611 if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, SIGFPE) == NOTIFY_STOP)
612 return;
613 conditional_sti(regs);
614
615 if (!user_mode_vm(regs))
616 {
617 if (!fixup_exception(regs)) {
618 task->thread.error_code = error_code;
619 task->thread.trap_no = trapnr;
620 die(str, regs, error_code);
621 }
622 return;
623 }
624
625 /*
626 * Save the info for the exception handler and clear the error.
627 */
628 save_init_fpu(task);
629 task->thread.trap_no = trapnr;
630 task->thread.error_code = error_code;
631 info.si_signo = SIGFPE;
632 info.si_errno = 0;
633 info.si_addr = (void __user *)regs->ip;
634 if (trapnr == 16) {
635 unsigned short cwd, swd;
636 /*
637 * (~cwd & swd) will mask out exceptions that are not set to unmasked
638 * status. 0x3f is the exception bits in these regs, 0x200 is the
639 * C1 reg you need in case of a stack fault, 0x040 is the stack
640 * fault bit. We should only be taking one exception at a time,
641 * so if this combination doesn't produce any single exception,
642 * then we have a bad program that isn't synchronizing its FPU usage
643 * and it will suffer the consequences since we won't be able to
644 * fully reproduce the context of the exception
645 */
646 cwd = get_fpu_cwd(task);
647 swd = get_fpu_swd(task);
648
649 err = swd & ~cwd;
650 } else {
651 /*
652 * The SIMD FPU exceptions are handled a little differently, as there
653 * is only a single status/control register. Thus, to determine which
654 * unmasked exception was caught we must mask the exception mask bits
655 * at 0x1f80, and then use these to mask the exception bits at 0x3f.
656 */
657 unsigned short mxcsr = get_fpu_mxcsr(task);
658 err = ~(mxcsr >> 7) & mxcsr;
659 }
660
661 if (err & 0x001) { /* Invalid op */
662 /*
663 * swd & 0x240 == 0x040: Stack Underflow
664 * swd & 0x240 == 0x240: Stack Overflow
665 * User must clear the SF bit (0x40) if set
666 */
667 info.si_code = FPE_FLTINV;
668 } else if (err & 0x004) { /* Divide by Zero */
669 info.si_code = FPE_FLTDIV;
670 } else if (err & 0x008) { /* Overflow */
671 info.si_code = FPE_FLTOVF;
672 } else if (err & 0x012) { /* Denormal, Underflow */
673 info.si_code = FPE_FLTUND;
674 } else if (err & 0x020) { /* Precision */
675 info.si_code = FPE_FLTRES;
676 } else {
677 /*
678 * If we're using IRQ 13, or supposedly even some trap 16
679 * implementations, it's possible we get a spurious trap...
680 */
681 return; /* Spurious trap, no error */
682 }
683 force_sig_info(SIGFPE, &info, task);
684}
685
686dotraplinkage void do_coprocessor_error(struct pt_regs *regs, long error_code)
687{
688#ifdef CONFIG_X86_32
689 ignore_fpu_irq = 1;
690#endif
691
692 math_error(regs, error_code, 16);
693}
694
695dotraplinkage void
696do_simd_coprocessor_error(struct pt_regs *regs, long error_code)
697{
698 math_error(regs, error_code, 19);
699}
700
701dotraplinkage void
702do_spurious_interrupt_bug(struct pt_regs *regs, long error_code)
703{
704 conditional_sti(regs);
705#if 0
706 /* No need to warn about this any longer. */
707 printk(KERN_INFO "Ignoring P6 Local APIC Spurious Interrupt Bug...\n");
708#endif
709}
710
711asmlinkage void __attribute__((weak)) smp_thermal_interrupt(void)
712{
713}
714
715asmlinkage void __attribute__((weak)) smp_threshold_interrupt(void)
716{
717}
718
719/*
720 * __math_state_restore assumes that cr0.TS is already clear and the
721 * fpu state is all ready for use. Used during context switch.
722 */
723void __math_state_restore(void)
724{
725 struct thread_info *thread = current_thread_info();
726 struct task_struct *tsk = thread->task;
727
728 /*
729 * Paranoid restore. send a SIGSEGV if we fail to restore the state.
730 */
731 if (unlikely(restore_fpu_checking(tsk))) {
732 stts();
733 force_sig(SIGSEGV, tsk);
734 return;
735 }
736
737 thread->status |= TS_USEDFPU; /* So we fnsave on switch_to() */
738 tsk->fpu_counter++;
739}
740
741/*
742 * 'math_state_restore()' saves the current math information in the
743 * old math state array, and gets the new ones from the current task
744 *
745 * Careful.. There are problems with IBM-designed IRQ13 behaviour.
746 * Don't touch unless you *really* know how it works.
747 *
748 * Must be called with kernel preemption disabled (in this case,
749 * local interrupts are disabled at the call-site in entry.S).
750 */
751asmlinkage void math_state_restore(void)
752{
753 struct thread_info *thread = current_thread_info();
754 struct task_struct *tsk = thread->task;
755
756 if (!tsk_used_math(tsk)) {
757 local_irq_enable();
758 /*
759 * does a slab alloc which can sleep
760 */
761 if (init_fpu(tsk)) {
762 /*
763 * ran out of memory!
764 */
765 do_group_exit(SIGKILL);
766 return;
767 }
768 local_irq_disable();
769 }
770
771 clts(); /* Allow maths ops (or we recurse) */
772
773 __math_state_restore();
774}
775EXPORT_SYMBOL_GPL(math_state_restore);
776
777dotraplinkage void __kprobes
778do_device_not_available(struct pt_regs *regs, long error_code)
779{
780#ifdef CONFIG_MATH_EMULATION
781 if (read_cr0() & X86_CR0_EM) {
782 struct math_emu_info info = { };
783
784 conditional_sti(regs);
785
786 info.regs = regs;
787 math_emulate(&info);
788 return;
789 }
790#endif
791 math_state_restore(); /* interrupts still off */
792#ifdef CONFIG_X86_32
793 conditional_sti(regs);
794#endif
795}
796
797#ifdef CONFIG_X86_32
798dotraplinkage void do_iret_error(struct pt_regs *regs, long error_code)
799{
800 siginfo_t info;
801 local_irq_enable();
802
803 info.si_signo = SIGILL;
804 info.si_errno = 0;
805 info.si_code = ILL_BADSTK;
806 info.si_addr = NULL;
807 if (notify_die(DIE_TRAP, "iret exception",
808 regs, error_code, 32, SIGILL) == NOTIFY_STOP)
809 return;
810 do_trap(32, SIGILL, "iret exception", regs, error_code, &info);
811}
812#endif
813
814/* Set of traps needed for early debugging. */
815void __init early_trap_init(void)
816{
817 set_intr_gate_ist(1, &debug, DEBUG_STACK);
818 /* int3 can be called from all */
819 set_system_intr_gate_ist(3, &int3, DEBUG_STACK);
820 set_intr_gate(14, &page_fault);
821 load_idt(&idt_descr);
822}
823
824void __init trap_init(void)
825{
826 int i;
827
828#ifdef CONFIG_EISA
829 void __iomem *p = early_ioremap(0x0FFFD9, 4);
830
831 if (readl(p) == 'E' + ('I'<<8) + ('S'<<16) + ('A'<<24))
832 EISA_bus = 1;
833 early_iounmap(p, 4);
834#endif
835
836 set_intr_gate(0, ÷_error);
837 set_intr_gate_ist(2, &nmi, NMI_STACK);
838 /* int4 can be called from all */
839 set_system_intr_gate(4, &overflow);
840 set_intr_gate(5, &bounds);
841 set_intr_gate(6, &invalid_op);
842 set_intr_gate(7, &device_not_available);
843#ifdef CONFIG_X86_32
844 set_task_gate(8, GDT_ENTRY_DOUBLEFAULT_TSS);
845#else
846 set_intr_gate_ist(8, &double_fault, DOUBLEFAULT_STACK);
847#endif
848 set_intr_gate(9, &coprocessor_segment_overrun);
849 set_intr_gate(10, &invalid_TSS);
850 set_intr_gate(11, &segment_not_present);
851 set_intr_gate_ist(12, &stack_segment, STACKFAULT_STACK);
852 set_intr_gate(13, &general_protection);
853 set_intr_gate(15, &spurious_interrupt_bug);
854 set_intr_gate(16, &coprocessor_error);
855 set_intr_gate(17, &alignment_check);
856#ifdef CONFIG_X86_MCE
857 set_intr_gate_ist(18, &machine_check, MCE_STACK);
858#endif
859 set_intr_gate(19, &simd_coprocessor_error);
860
861 /* Reserve all the builtin and the syscall vector: */
862 for (i = 0; i < FIRST_EXTERNAL_VECTOR; i++)
863 set_bit(i, used_vectors);
864
865#ifdef CONFIG_IA32_EMULATION
866 set_system_intr_gate(IA32_SYSCALL_VECTOR, ia32_syscall);
867 set_bit(IA32_SYSCALL_VECTOR, used_vectors);
868#endif
869
870#ifdef CONFIG_X86_32
871 set_system_trap_gate(SYSCALL_VECTOR, &system_call);
872 set_bit(SYSCALL_VECTOR, used_vectors);
873#endif
874
875 /*
876 * Should be a barrier for any external CPU state:
877 */
878 cpu_init();
879
880 x86_init.irqs.trap_init();
881}