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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 | /* * Copyright (C) 2014 Broadcom Corporation * Copyright 2014 Linaro Limited * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation version 2. * * This program is distributed "as is" WITHOUT ANY WARRANTY of any * kind, whether express or implied; without even the implied warranty * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include "clk-kona.h" #include "dt-bindings/clock/bcm21664.h" #define BCM21664_CCU_COMMON(_name, _capname) \ KONA_CCU_COMMON(BCM21664, _name, _capname) /* Root CCU */ static struct peri_clk_data frac_1m_data = { .gate = HW_SW_GATE(0x214, 16, 0, 1), .clocks = CLOCKS("ref_crystal"), }; static struct ccu_data root_ccu_data = { BCM21664_CCU_COMMON(root, ROOT), /* no policy control */ .kona_clks = { [BCM21664_ROOT_CCU_FRAC_1M] = KONA_CLK(root, frac_1m, peri), [BCM21664_ROOT_CCU_CLOCK_COUNT] = LAST_KONA_CLK, }, }; /* AON CCU */ static struct peri_clk_data hub_timer_data = { .gate = HW_SW_GATE(0x0414, 16, 0, 1), .hyst = HYST(0x0414, 8, 9), .clocks = CLOCKS("bbl_32k", "frac_1m", "dft_19_5m"), .sel = SELECTOR(0x0a10, 0, 2), .trig = TRIGGER(0x0a40, 4), }; static struct ccu_data aon_ccu_data = { BCM21664_CCU_COMMON(aon, AON), .policy = { .enable = CCU_LVM_EN(0x0034, 0), .control = CCU_POLICY_CTL(0x000c, 0, 1, 2), }, .kona_clks = { [BCM21664_AON_CCU_HUB_TIMER] = KONA_CLK(aon, hub_timer, peri), [BCM21664_AON_CCU_CLOCK_COUNT] = LAST_KONA_CLK, }, }; /* Master CCU */ static struct peri_clk_data sdio1_data = { .gate = HW_SW_GATE(0x0358, 18, 2, 3), .clocks = CLOCKS("ref_crystal", "var_52m", "ref_52m", "var_96m", "ref_96m"), .sel = SELECTOR(0x0a28, 0, 3), .div = DIVIDER(0x0a28, 4, 14), .trig = TRIGGER(0x0afc, 9), }; static struct peri_clk_data sdio2_data = { .gate = HW_SW_GATE(0x035c, 18, 2, 3), .clocks = CLOCKS("ref_crystal", "var_52m", "ref_52m", "var_96m", "ref_96m"), .sel = SELECTOR(0x0a2c, 0, 3), .div = DIVIDER(0x0a2c, 4, 14), .trig = TRIGGER(0x0afc, 10), }; static struct peri_clk_data sdio3_data = { .gate = HW_SW_GATE(0x0364, 18, 2, 3), .clocks = CLOCKS("ref_crystal", "var_52m", "ref_52m", "var_96m", "ref_96m"), .sel = SELECTOR(0x0a34, 0, 3), .div = DIVIDER(0x0a34, 4, 14), .trig = TRIGGER(0x0afc, 12), }; static struct peri_clk_data sdio4_data = { .gate = HW_SW_GATE(0x0360, 18, 2, 3), .clocks = CLOCKS("ref_crystal", "var_52m", "ref_52m", "var_96m", "ref_96m"), .sel = SELECTOR(0x0a30, 0, 3), .div = DIVIDER(0x0a30, 4, 14), .trig = TRIGGER(0x0afc, 11), }; static struct peri_clk_data sdio1_sleep_data = { .clocks = CLOCKS("ref_32k"), /* Verify */ .gate = HW_SW_GATE(0x0358, 18, 2, 3), }; static struct peri_clk_data sdio2_sleep_data = { .clocks = CLOCKS("ref_32k"), /* Verify */ .gate = HW_SW_GATE(0x035c, 18, 2, 3), }; static struct peri_clk_data sdio3_sleep_data = { .clocks = CLOCKS("ref_32k"), /* Verify */ .gate = HW_SW_GATE(0x0364, 18, 2, 3), }; static struct peri_clk_data sdio4_sleep_data = { .clocks = CLOCKS("ref_32k"), /* Verify */ .gate = HW_SW_GATE(0x0360, 18, 2, 3), }; static struct ccu_data master_ccu_data = { BCM21664_CCU_COMMON(master, MASTER), .policy = { .enable = CCU_LVM_EN(0x0034, 0), .control = CCU_POLICY_CTL(0x000c, 0, 1, 2), }, .kona_clks = { [BCM21664_MASTER_CCU_SDIO1] = KONA_CLK(master, sdio1, peri), [BCM21664_MASTER_CCU_SDIO2] = KONA_CLK(master, sdio2, peri), [BCM21664_MASTER_CCU_SDIO3] = KONA_CLK(master, sdio3, peri), [BCM21664_MASTER_CCU_SDIO4] = KONA_CLK(master, sdio4, peri), [BCM21664_MASTER_CCU_SDIO1_SLEEP] = KONA_CLK(master, sdio1_sleep, peri), [BCM21664_MASTER_CCU_SDIO2_SLEEP] = KONA_CLK(master, sdio2_sleep, peri), [BCM21664_MASTER_CCU_SDIO3_SLEEP] = KONA_CLK(master, sdio3_sleep, peri), [BCM21664_MASTER_CCU_SDIO4_SLEEP] = KONA_CLK(master, sdio4_sleep, peri), [BCM21664_MASTER_CCU_CLOCK_COUNT] = LAST_KONA_CLK, }, }; /* Slave CCU */ static struct peri_clk_data uartb_data = { .gate = HW_SW_GATE(0x0400, 18, 2, 3), .clocks = CLOCKS("ref_crystal", "var_156m", "ref_156m"), .sel = SELECTOR(0x0a10, 0, 2), .div = FRAC_DIVIDER(0x0a10, 4, 12, 8), .trig = TRIGGER(0x0afc, 2), }; static struct peri_clk_data uartb2_data = { .gate = HW_SW_GATE(0x0404, 18, 2, 3), .clocks = CLOCKS("ref_crystal", "var_156m", "ref_156m"), .sel = SELECTOR(0x0a14, 0, 2), .div = FRAC_DIVIDER(0x0a14, 4, 12, 8), .trig = TRIGGER(0x0afc, 3), }; static struct peri_clk_data uartb3_data = { .gate = HW_SW_GATE(0x0408, 18, 2, 3), .clocks = CLOCKS("ref_crystal", "var_156m", "ref_156m"), .sel = SELECTOR(0x0a18, 0, 2), .div = FRAC_DIVIDER(0x0a18, 4, 12, 8), .trig = TRIGGER(0x0afc, 4), }; static struct peri_clk_data bsc1_data = { .gate = HW_SW_GATE(0x0458, 18, 2, 3), .clocks = CLOCKS("ref_crystal", "var_104m", "ref_104m", "var_13m", "ref_13m"), .sel = SELECTOR(0x0a64, 0, 3), .trig = TRIGGER(0x0afc, 23), }; static struct peri_clk_data bsc2_data = { .gate = HW_SW_GATE(0x045c, 18, 2, 3), .clocks = CLOCKS("ref_crystal", "var_104m", "ref_104m", "var_13m", "ref_13m"), .sel = SELECTOR(0x0a68, 0, 3), .trig = TRIGGER(0x0afc, 24), }; static struct peri_clk_data bsc3_data = { .gate = HW_SW_GATE(0x0470, 18, 2, 3), .clocks = CLOCKS("ref_crystal", "var_104m", "ref_104m", "var_13m", "ref_13m"), .sel = SELECTOR(0x0a7c, 0, 3), .trig = TRIGGER(0x0afc, 18), }; static struct peri_clk_data bsc4_data = { .gate = HW_SW_GATE(0x0474, 18, 2, 3), .clocks = CLOCKS("ref_crystal", "var_104m", "ref_104m", "var_13m", "ref_13m"), .sel = SELECTOR(0x0a80, 0, 3), .trig = TRIGGER(0x0afc, 19), }; static struct ccu_data slave_ccu_data = { BCM21664_CCU_COMMON(slave, SLAVE), .policy = { .enable = CCU_LVM_EN(0x0034, 0), .control = CCU_POLICY_CTL(0x000c, 0, 1, 2), }, .kona_clks = { [BCM21664_SLAVE_CCU_UARTB] = KONA_CLK(slave, uartb, peri), [BCM21664_SLAVE_CCU_UARTB2] = KONA_CLK(slave, uartb2, peri), [BCM21664_SLAVE_CCU_UARTB3] = KONA_CLK(slave, uartb3, peri), [BCM21664_SLAVE_CCU_BSC1] = KONA_CLK(slave, bsc1, peri), [BCM21664_SLAVE_CCU_BSC2] = KONA_CLK(slave, bsc2, peri), [BCM21664_SLAVE_CCU_BSC3] = KONA_CLK(slave, bsc3, peri), [BCM21664_SLAVE_CCU_BSC4] = KONA_CLK(slave, bsc4, peri), [BCM21664_SLAVE_CCU_CLOCK_COUNT] = LAST_KONA_CLK, }, }; /* Device tree match table callback functions */ static void __init kona_dt_root_ccu_setup(struct device_node *node) { kona_dt_ccu_setup(&root_ccu_data, node); } static void __init kona_dt_aon_ccu_setup(struct device_node *node) { kona_dt_ccu_setup(&aon_ccu_data, node); } static void __init kona_dt_master_ccu_setup(struct device_node *node) { kona_dt_ccu_setup(&master_ccu_data, node); } static void __init kona_dt_slave_ccu_setup(struct device_node *node) { kona_dt_ccu_setup(&slave_ccu_data, node); } CLK_OF_DECLARE(bcm21664_root_ccu, BCM21664_DT_ROOT_CCU_COMPAT, kona_dt_root_ccu_setup); CLK_OF_DECLARE(bcm21664_aon_ccu, BCM21664_DT_AON_CCU_COMPAT, kona_dt_aon_ccu_setup); CLK_OF_DECLARE(bcm21664_master_ccu, BCM21664_DT_MASTER_CCU_COMPAT, kona_dt_master_ccu_setup); CLK_OF_DECLARE(bcm21664_slave_ccu, BCM21664_DT_SLAVE_CCU_COMPAT, kona_dt_slave_ccu_setup); |