1// SPDX-License-Identifier: GPL-2.0+
 2//
 3// OWL mux clock driver
 4//
 5// Copyright (c) 2014 Actions Semi Inc.
 6// Author: David Liu <liuwei@actions-semi.com>
 7//
 8// Copyright (c) 2018 Linaro Ltd.
 9// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
10
11#include <linux/clk-provider.h>
12#include <linux/regmap.h>
13
14#include "owl-mux.h"
15
16u8 owl_mux_helper_get_parent(const struct owl_clk_common *common,
17			     const struct owl_mux_hw *mux_hw)
18{
19	u32 reg;
20	u8 parent;
21
22	regmap_read(common->regmap, mux_hw->reg, &reg);
23	parent = reg >> mux_hw->shift;
24	parent &= BIT(mux_hw->width) - 1;
25
26	return parent;
27}
28
29static u8 owl_mux_get_parent(struct clk_hw *hw)
30{
31	struct owl_mux *mux = hw_to_owl_mux(hw);
32
33	return owl_mux_helper_get_parent(&mux->common, &mux->mux_hw);
34}
35
36int owl_mux_helper_set_parent(const struct owl_clk_common *common,
37			      struct owl_mux_hw *mux_hw, u8 index)
38{
39	u32 reg;
40
41	regmap_read(common->regmap, mux_hw->reg, &reg);
42	reg &= ~GENMASK(mux_hw->width + mux_hw->shift - 1, mux_hw->shift);
43	regmap_write(common->regmap, mux_hw->reg,
44			reg | (index << mux_hw->shift));
45
46	return 0;
47}
48
49static int owl_mux_set_parent(struct clk_hw *hw, u8 index)
50{
51	struct owl_mux *mux = hw_to_owl_mux(hw);
52
53	return owl_mux_helper_set_parent(&mux->common, &mux->mux_hw, index);
54}
55
56const struct clk_ops owl_mux_ops = {
57	.get_parent = owl_mux_get_parent,
58	.set_parent = owl_mux_set_parent,
59	.determine_rate = __clk_mux_determine_rate,
60};