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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 | /* * include/asm-xtensa/bitops.h * * Atomic operations that C can't guarantee us.Useful for resource counting etc. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2001 - 2007 Tensilica Inc. */ #ifndef _XTENSA_BITOPS_H #define _XTENSA_BITOPS_H #ifndef _LINUX_BITOPS_H #error only <linux/bitops.h> can be included directly #endif #include <asm/processor.h> #include <asm/byteorder.h> #include <asm/barrier.h> #include <asm-generic/bitops/non-atomic.h> #if XCHAL_HAVE_NSA static inline unsigned long __cntlz (unsigned long x) { int lz; asm ("nsau %0, %1" : "=r" (lz) : "r" (x)); return lz; } /* * ffz: Find first zero in word. Undefined if no zero exists. * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). */ static inline int ffz(unsigned long x) { return 31 - __cntlz(~x & -~x); } /* * __ffs: Find first bit set in word. Return 0 for bit 0 */ static inline unsigned long __ffs(unsigned long x) { return 31 - __cntlz(x & -x); } /* * ffs: Find first bit set in word. This is defined the same way as * the libc and compiler builtin ffs routines, therefore * differs in spirit from the above ffz (man ffs). */ static inline int ffs(unsigned long x) { return 32 - __cntlz(x & -x); } /* * fls: Find last (most-significant) bit set in word. * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. */ static inline int fls (unsigned int x) { return 32 - __cntlz(x); } /** * __fls - find last (most-significant) set bit in a long word * @word: the word to search * * Undefined if no set bit exists, so code should check against 0 first. */ static inline unsigned long __fls(unsigned long word) { return 31 - __cntlz(word); } #else /* Use the generic implementation if we don't have the nsa/nsau instructions. */ # include <asm-generic/bitops/ffs.h> # include <asm-generic/bitops/__ffs.h> # include <asm-generic/bitops/ffz.h> # include <asm-generic/bitops/fls.h> # include <asm-generic/bitops/__fls.h> #endif #include <asm-generic/bitops/fls64.h> #if XCHAL_HAVE_EXCLUSIVE static inline void set_bit(unsigned int bit, volatile unsigned long *p) { unsigned long tmp; unsigned long mask = 1UL << (bit & 31); p += bit >> 5; __asm__ __volatile__( "1: l32ex %0, %2\n" " or %0, %0, %1\n" " s32ex %0, %2\n" " getex %0\n" " beqz %0, 1b\n" : "=&a" (tmp) : "a" (mask), "a" (p) : "memory"); } static inline void clear_bit(unsigned int bit, volatile unsigned long *p) { unsigned long tmp; unsigned long mask = 1UL << (bit & 31); p += bit >> 5; __asm__ __volatile__( "1: l32ex %0, %2\n" " and %0, %0, %1\n" " s32ex %0, %2\n" " getex %0\n" " beqz %0, 1b\n" : "=&a" (tmp) : "a" (~mask), "a" (p) : "memory"); } static inline void change_bit(unsigned int bit, volatile unsigned long *p) { unsigned long tmp; unsigned long mask = 1UL << (bit & 31); p += bit >> 5; __asm__ __volatile__( "1: l32ex %0, %2\n" " xor %0, %0, %1\n" " s32ex %0, %2\n" " getex %0\n" " beqz %0, 1b\n" : "=&a" (tmp) : "a" (mask), "a" (p) : "memory"); } static inline int test_and_set_bit(unsigned int bit, volatile unsigned long *p) { unsigned long tmp, value; unsigned long mask = 1UL << (bit & 31); p += bit >> 5; __asm__ __volatile__( "1: l32ex %1, %3\n" " or %0, %1, %2\n" " s32ex %0, %3\n" " getex %0\n" " beqz %0, 1b\n" : "=&a" (tmp), "=&a" (value) : "a" (mask), "a" (p) : "memory"); return value & mask; } static inline int test_and_clear_bit(unsigned int bit, volatile unsigned long *p) { unsigned long tmp, value; unsigned long mask = 1UL << (bit & 31); p += bit >> 5; __asm__ __volatile__( "1: l32ex %1, %3\n" " and %0, %1, %2\n" " s32ex %0, %3\n" " getex %0\n" " beqz %0, 1b\n" : "=&a" (tmp), "=&a" (value) : "a" (~mask), "a" (p) : "memory"); return value & mask; } static inline int test_and_change_bit(unsigned int bit, volatile unsigned long *p) { unsigned long tmp, value; unsigned long mask = 1UL << (bit & 31); p += bit >> 5; __asm__ __volatile__( "1: l32ex %1, %3\n" " xor %0, %1, %2\n" " s32ex %0, %3\n" " getex %0\n" " beqz %0, 1b\n" : "=&a" (tmp), "=&a" (value) : "a" (mask), "a" (p) : "memory"); return value & mask; } #elif XCHAL_HAVE_S32C1I static inline void set_bit(unsigned int bit, volatile unsigned long *p) { unsigned long tmp, value; unsigned long mask = 1UL << (bit & 31); p += bit >> 5; __asm__ __volatile__( "1: l32i %1, %3, 0\n" " wsr %1, scompare1\n" " or %0, %1, %2\n" " s32c1i %0, %3, 0\n" " bne %0, %1, 1b\n" : "=&a" (tmp), "=&a" (value) : "a" (mask), "a" (p) : "memory"); } static inline void clear_bit(unsigned int bit, volatile unsigned long *p) { unsigned long tmp, value; unsigned long mask = 1UL << (bit & 31); p += bit >> 5; __asm__ __volatile__( "1: l32i %1, %3, 0\n" " wsr %1, scompare1\n" " and %0, %1, %2\n" " s32c1i %0, %3, 0\n" " bne %0, %1, 1b\n" : "=&a" (tmp), "=&a" (value) : "a" (~mask), "a" (p) : "memory"); } static inline void change_bit(unsigned int bit, volatile unsigned long *p) { unsigned long tmp, value; unsigned long mask = 1UL << (bit & 31); p += bit >> 5; __asm__ __volatile__( "1: l32i %1, %3, 0\n" " wsr %1, scompare1\n" " xor %0, %1, %2\n" " s32c1i %0, %3, 0\n" " bne %0, %1, 1b\n" : "=&a" (tmp), "=&a" (value) : "a" (mask), "a" (p) : "memory"); } static inline int test_and_set_bit(unsigned int bit, volatile unsigned long *p) { unsigned long tmp, value; unsigned long mask = 1UL << (bit & 31); p += bit >> 5; __asm__ __volatile__( "1: l32i %1, %3, 0\n" " wsr %1, scompare1\n" " or %0, %1, %2\n" " s32c1i %0, %3, 0\n" " bne %0, %1, 1b\n" : "=&a" (tmp), "=&a" (value) : "a" (mask), "a" (p) : "memory"); return tmp & mask; } static inline int test_and_clear_bit(unsigned int bit, volatile unsigned long *p) { unsigned long tmp, value; unsigned long mask = 1UL << (bit & 31); p += bit >> 5; __asm__ __volatile__( "1: l32i %1, %3, 0\n" " wsr %1, scompare1\n" " and %0, %1, %2\n" " s32c1i %0, %3, 0\n" " bne %0, %1, 1b\n" : "=&a" (tmp), "=&a" (value) : "a" (~mask), "a" (p) : "memory"); return tmp & mask; } static inline int test_and_change_bit(unsigned int bit, volatile unsigned long *p) { unsigned long tmp, value; unsigned long mask = 1UL << (bit & 31); p += bit >> 5; __asm__ __volatile__( "1: l32i %1, %3, 0\n" " wsr %1, scompare1\n" " xor %0, %1, %2\n" " s32c1i %0, %3, 0\n" " bne %0, %1, 1b\n" : "=&a" (tmp), "=&a" (value) : "a" (mask), "a" (p) : "memory"); return tmp & mask; } #else #include <asm-generic/bitops/atomic.h> #endif /* XCHAL_HAVE_S32C1I */ #include <asm-generic/bitops/find.h> #include <asm-generic/bitops/le.h> #include <asm-generic/bitops/ext2-atomic-setbit.h> #include <asm-generic/bitops/hweight.h> #include <asm-generic/bitops/lock.h> #include <asm-generic/bitops/sched.h> #endif /* _XTENSA_BITOPS_H */ |