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1===============================
2PINCTRL (PIN CONTROL) subsystem
3===============================
4
5This document outlines the pin control subsystem in Linux
6
7This subsystem deals with:
8
9- Enumerating and naming controllable pins
10
11- Multiplexing of pins, pads, fingers (etc) see below for details
12
13- Configuration of pins, pads, fingers (etc), such as software-controlled
14 biasing and driving mode specific pins, such as pull-up/down, open drain,
15 load capacitance etc.
16
17Top-level interface
18===================
19
20Definition of PIN CONTROLLER:
21
22- A pin controller is a piece of hardware, usually a set of registers, that
23 can control PINs. It may be able to multiplex, bias, set load capacitance,
24 set drive strength, etc. for individual pins or groups of pins.
25
26Definition of PIN:
27
28- PINS are equal to pads, fingers, balls or whatever packaging input or
29 output line you want to control and these are denoted by unsigned integers
30 in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
31 there may be several such number spaces in a system. This pin space may
32 be sparse - i.e. there may be gaps in the space with numbers where no
33 pin exists.
34
35When a PIN CONTROLLER is instantiated, it will register a descriptor to the
36pin control framework, and this descriptor contains an array of pin descriptors
37describing the pins handled by this specific pin controller.
38
39Here is an example of a PGA (Pin Grid Array) chip seen from underneath::
40
41 A B C D E F G H
42
43 8 o o o o o o o o
44
45 7 o o o o o o o o
46
47 6 o o o o o o o o
48
49 5 o o o o o o o o
50
51 4 o o o o o o o o
52
53 3 o o o o o o o o
54
55 2 o o o o o o o o
56
57 1 o o o o o o o o
58
59To register a pin controller and name all the pins on this package we can do
60this in our driver::
61
62 #include <linux/pinctrl/pinctrl.h>
63
64 const struct pinctrl_pin_desc foo_pins[] = {
65 PINCTRL_PIN(0, "A8"),
66 PINCTRL_PIN(1, "B8"),
67 PINCTRL_PIN(2, "C8"),
68 ...
69 PINCTRL_PIN(61, "F1"),
70 PINCTRL_PIN(62, "G1"),
71 PINCTRL_PIN(63, "H1"),
72 };
73
74 static struct pinctrl_desc foo_desc = {
75 .name = "foo",
76 .pins = foo_pins,
77 .npins = ARRAY_SIZE(foo_pins),
78 .owner = THIS_MODULE,
79 };
80
81 int __init foo_probe(void)
82 {
83 int error;
84
85 struct pinctrl_dev *pctl;
86
87 error = pinctrl_register_and_init(&foo_desc, <PARENT>,
88 NULL, &pctl);
89 if (error)
90 return error;
91
92 return pinctrl_enable(pctl);
93 }
94
95To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and
96selected drivers, you need to select them from your machine's Kconfig entry,
97since these are so tightly integrated with the machines they are used on.
98See for example arch/arm/mach-u300/Kconfig for an example.
99
100Pins usually have fancier names than this. You can find these in the datasheet
101for your chip. Notice that the core pinctrl.h file provides a fancy macro
102called PINCTRL_PIN() to create the struct entries. As you can see I enumerated
103the pins from 0 in the upper left corner to 63 in the lower right corner.
104This enumeration was arbitrarily chosen, in practice you need to think
105through your numbering system so that it matches the layout of registers
106and such things in your driver, or the code may become complicated. You must
107also consider matching of offsets to the GPIO ranges that may be handled by
108the pin controller.
109
110For a padring with 467 pads, as opposed to actual pins, I used an enumeration
111like this, walking around the edge of the chip, which seems to be industry
112standard too (all these pads had names, too)::
113
114
115 0 ..... 104
116 466 105
117 . .
118 . .
119 358 224
120 357 .... 225
121
122
123Pin groups
124==========
125
126Many controllers need to deal with groups of pins, so the pin controller
127subsystem has a mechanism for enumerating groups of pins and retrieving the
128actual enumerated pins that are part of a certain group.
129
130For example, say that we have a group of pins dealing with an SPI interface
131on { 0, 8, 16, 24 }, and a group of pins dealing with an I2C interface on pins
132on { 24, 25 }.
133
134These two groups are presented to the pin control subsystem by implementing
135some generic pinctrl_ops like this::
136
137 #include <linux/pinctrl/pinctrl.h>
138
139 struct foo_group {
140 const char *name;
141 const unsigned int *pins;
142 const unsigned num_pins;
143 };
144
145 static const unsigned int spi0_pins[] = { 0, 8, 16, 24 };
146 static const unsigned int i2c0_pins[] = { 24, 25 };
147
148 static const struct foo_group foo_groups[] = {
149 {
150 .name = "spi0_grp",
151 .pins = spi0_pins,
152 .num_pins = ARRAY_SIZE(spi0_pins),
153 },
154 {
155 .name = "i2c0_grp",
156 .pins = i2c0_pins,
157 .num_pins = ARRAY_SIZE(i2c0_pins),
158 },
159 };
160
161
162 static int foo_get_groups_count(struct pinctrl_dev *pctldev)
163 {
164 return ARRAY_SIZE(foo_groups);
165 }
166
167 static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
168 unsigned selector)
169 {
170 return foo_groups[selector].name;
171 }
172
173 static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
174 const unsigned **pins,
175 unsigned *num_pins)
176 {
177 *pins = (unsigned *) foo_groups[selector].pins;
178 *num_pins = foo_groups[selector].num_pins;
179 return 0;
180 }
181
182 static struct pinctrl_ops foo_pctrl_ops = {
183 .get_groups_count = foo_get_groups_count,
184 .get_group_name = foo_get_group_name,
185 .get_group_pins = foo_get_group_pins,
186 };
187
188
189 static struct pinctrl_desc foo_desc = {
190 ...
191 .pctlops = &foo_pctrl_ops,
192 };
193
194The pin control subsystem will call the .get_groups_count() function to
195determine the total number of legal selectors, then it will call the other functions
196to retrieve the name and pins of the group. Maintaining the data structure of
197the groups is up to the driver, this is just a simple example - in practice you
198may need more entries in your group structure, for example specific register
199ranges associated with each group and so on.
200
201
202Pin configuration
203=================
204
205Pins can sometimes be software-configured in various ways, mostly related
206to their electronic properties when used as inputs or outputs. For example you
207may be able to make an output pin high impedance, or "tristate" meaning it is
208effectively disconnected. You may be able to connect an input pin to VDD or GND
209using a certain resistor value - pull up and pull down - so that the pin has a
210stable value when nothing is driving the rail it is connected to, or when it's
211unconnected.
212
213Pin configuration can be programmed by adding configuration entries into the
214mapping table; see section "Board/machine configuration" below.
215
216The format and meaning of the configuration parameter, PLATFORM_X_PULL_UP
217above, is entirely defined by the pin controller driver.
218
219The pin configuration driver implements callbacks for changing pin
220configuration in the pin controller ops like this::
221
222 #include <linux/pinctrl/pinctrl.h>
223 #include <linux/pinctrl/pinconf.h>
224 #include "platform_x_pindefs.h"
225
226 static int foo_pin_config_get(struct pinctrl_dev *pctldev,
227 unsigned offset,
228 unsigned long *config)
229 {
230 struct my_conftype conf;
231
232 ... Find setting for pin @ offset ...
233
234 *config = (unsigned long) conf;
235 }
236
237 static int foo_pin_config_set(struct pinctrl_dev *pctldev,
238 unsigned offset,
239 unsigned long config)
240 {
241 struct my_conftype *conf = (struct my_conftype *) config;
242
243 switch (conf) {
244 case PLATFORM_X_PULL_UP:
245 ...
246 }
247 }
248 }
249
250 static int foo_pin_config_group_get (struct pinctrl_dev *pctldev,
251 unsigned selector,
252 unsigned long *config)
253 {
254 ...
255 }
256
257 static int foo_pin_config_group_set (struct pinctrl_dev *pctldev,
258 unsigned selector,
259 unsigned long config)
260 {
261 ...
262 }
263
264 static struct pinconf_ops foo_pconf_ops = {
265 .pin_config_get = foo_pin_config_get,
266 .pin_config_set = foo_pin_config_set,
267 .pin_config_group_get = foo_pin_config_group_get,
268 .pin_config_group_set = foo_pin_config_group_set,
269 };
270
271 /* Pin config operations are handled by some pin controller */
272 static struct pinctrl_desc foo_desc = {
273 ...
274 .confops = &foo_pconf_ops,
275 };
276
277Interaction with the GPIO subsystem
278===================================
279
280The GPIO drivers may want to perform operations of various types on the same
281physical pins that are also registered as pin controller pins.
282
283First and foremost, the two subsystems can be used as completely orthogonal,
284see the section named "pin control requests from drivers" and
285"drivers needing both pin control and GPIOs" below for details. But in some
286situations a cross-subsystem mapping between pins and GPIOs is needed.
287
288Since the pin controller subsystem has its pinspace local to the pin controller
289we need a mapping so that the pin control subsystem can figure out which pin
290controller handles control of a certain GPIO pin. Since a single pin controller
291may be muxing several GPIO ranges (typically SoCs that have one set of pins,
292but internally several GPIO silicon blocks, each modelled as a struct
293gpio_chip) any number of GPIO ranges can be added to a pin controller instance
294like this::
295
296 struct gpio_chip chip_a;
297 struct gpio_chip chip_b;
298
299 static struct pinctrl_gpio_range gpio_range_a = {
300 .name = "chip a",
301 .id = 0,
302 .base = 32,
303 .pin_base = 32,
304 .npins = 16,
305 .gc = &chip_a;
306 };
307
308 static struct pinctrl_gpio_range gpio_range_b = {
309 .name = "chip b",
310 .id = 0,
311 .base = 48,
312 .pin_base = 64,
313 .npins = 8,
314 .gc = &chip_b;
315 };
316
317 {
318 struct pinctrl_dev *pctl;
319 ...
320 pinctrl_add_gpio_range(pctl, &gpio_range_a);
321 pinctrl_add_gpio_range(pctl, &gpio_range_b);
322 }
323
324So this complex system has one pin controller handling two different
325GPIO chips. "chip a" has 16 pins and "chip b" has 8 pins. The "chip a" and
326"chip b" have different .pin_base, which means a start pin number of the
327GPIO range.
328
329The GPIO range of "chip a" starts from the GPIO base of 32 and actual
330pin range also starts from 32. However "chip b" has different starting
331offset for the GPIO range and pin range. The GPIO range of "chip b" starts
332from GPIO number 48, while the pin range of "chip b" starts from 64.
333
334We can convert a gpio number to actual pin number using this "pin_base".
335They are mapped in the global GPIO pin space at:
336
337chip a:
338 - GPIO range : [32 .. 47]
339 - pin range : [32 .. 47]
340chip b:
341 - GPIO range : [48 .. 55]
342 - pin range : [64 .. 71]
343
344The above examples assume the mapping between the GPIOs and pins is
345linear. If the mapping is sparse or haphazard, an array of arbitrary pin
346numbers can be encoded in the range like this::
347
348 static const unsigned range_pins[] = { 14, 1, 22, 17, 10, 8, 6, 2 };
349
350 static struct pinctrl_gpio_range gpio_range = {
351 .name = "chip",
352 .id = 0,
353 .base = 32,
354 .pins = &range_pins,
355 .npins = ARRAY_SIZE(range_pins),
356 .gc = &chip;
357 };
358
359In this case the pin_base property will be ignored. If the name of a pin
360group is known, the pins and npins elements of the above structure can be
361initialised using the function pinctrl_get_group_pins(), e.g. for pin
362group "foo"::
363
364 pinctrl_get_group_pins(pctl, "foo", &gpio_range.pins,
365 &gpio_range.npins);
366
367When GPIO-specific functions in the pin control subsystem are called, these
368ranges will be used to look up the appropriate pin controller by inspecting
369and matching the pin to the pin ranges across all controllers. When a
370pin controller handling the matching range is found, GPIO-specific functions
371will be called on that specific pin controller.
372
373For all functionalities dealing with pin biasing, pin muxing etc, the pin
374controller subsystem will look up the corresponding pin number from the passed
375in gpio number, and use the range's internals to retrieve a pin number. After
376that, the subsystem passes it on to the pin control driver, so the driver
377will get a pin number into its handled number range. Further it is also passed
378the range ID value, so that the pin controller knows which range it should
379deal with.
380
381Calling pinctrl_add_gpio_range from pinctrl driver is DEPRECATED. Please see
382section 2.1 of Documentation/devicetree/bindings/gpio/gpio.txt on how to bind
383pinctrl and gpio drivers.
384
385
386PINMUX interfaces
387=================
388
389These calls use the pinmux_* naming prefix. No other calls should use that
390prefix.
391
392
393What is pinmuxing?
394==================
395
396PINMUX, also known as padmux, ballmux, alternate functions or mission modes
397is a way for chip vendors producing some kind of electrical packages to use
398a certain physical pin (ball, pad, finger, etc) for multiple mutually exclusive
399functions, depending on the application. By "application" in this context
400we usually mean a way of soldering or wiring the package into an electronic
401system, even though the framework makes it possible to also change the function
402at runtime.
403
404Here is an example of a PGA (Pin Grid Array) chip seen from underneath::
405
406 A B C D E F G H
407 +---+
408 8 | o | o o o o o o o
409 | |
410 7 | o | o o o o o o o
411 | |
412 6 | o | o o o o o o o
413 +---+---+
414 5 | o | o | o o o o o o
415 +---+---+ +---+
416 4 o o o o o o | o | o
417 | |
418 3 o o o o o o | o | o
419 | |
420 2 o o o o o o | o | o
421 +-------+-------+-------+---+---+
422 1 | o o | o o | o o | o | o |
423 +-------+-------+-------+---+---+
424
425This is not tetris. The game to think of is chess. Not all PGA/BGA packages
426are chessboard-like, big ones have "holes" in some arrangement according to
427different design patterns, but we're using this as a simple example. Of the
428pins you see some will be taken by things like a few VCC and GND to feed power
429to the chip, and quite a few will be taken by large ports like an external
430memory interface. The remaining pins will often be subject to pin multiplexing.
431
432The example 8x8 PGA package above will have pin numbers 0 through 63 assigned
433to its physical pins. It will name the pins { A1, A2, A3 ... H6, H7, H8 } using
434pinctrl_register_pins() and a suitable data set as shown earlier.
435
436In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port
437(these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as
438some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can
439be used as an I2C port (these are just two pins: SCL, SDA). Needless to say,
440we cannot use the SPI port and I2C port at the same time. However in the inside
441of the package the silicon performing the SPI logic can alternatively be routed
442out on pins { G4, G3, G2, G1 }.
443
444On the bottom row at { A1, B1, C1, D1, E1, F1, G1, H1 } we have something
445special - it's an external MMC bus that can be 2, 4 or 8 bits wide, and it will
446consume 2, 4 or 8 pins respectively, so either { A1, B1 } are taken or
447{ A1, B1, C1, D1 } or all of them. If we use all 8 bits, we cannot use the SPI
448port on pins { G4, G3, G2, G1 } of course.
449
450This way the silicon blocks present inside the chip can be multiplexed "muxed"
451out on different pin ranges. Often contemporary SoC (systems on chip) will
452contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to
453different pins by pinmux settings.
454
455Since general-purpose I/O pins (GPIO) are typically always in shortage, it is
456common to be able to use almost any pin as a GPIO pin if it is not currently
457in use by some other I/O port.
458
459
460Pinmux conventions
461==================
462
463The purpose of the pinmux functionality in the pin controller subsystem is to
464abstract and provide pinmux settings to the devices you choose to instantiate
465in your machine configuration. It is inspired by the clk, GPIO and regulator
466subsystems, so devices will request their mux setting, but it's also possible
467to request a single pin for e.g. GPIO.
468
469Definitions:
470
471- FUNCTIONS can be switched in and out by a driver residing with the pin
472 control subsystem in the drivers/pinctrl/* directory of the kernel. The
473 pin control driver knows the possible functions. In the example above you can
474 identify three pinmux functions, one for spi, one for i2c and one for mmc.
475
476- FUNCTIONS are assumed to be enumerable from zero in a one-dimensional array.
477 In this case the array could be something like: { spi0, i2c0, mmc0 }
478 for the three available functions.
479
480- FUNCTIONS have PIN GROUPS as defined on the generic level - so a certain
481 function is *always* associated with a certain set of pin groups, could
482 be just a single one, but could also be many. In the example above the
483 function i2c is associated with the pins { A5, B5 }, enumerated as
484 { 24, 25 } in the controller pin space.
485
486 The Function spi is associated with pin groups { A8, A7, A6, A5 }
487 and { G4, G3, G2, G1 }, which are enumerated as { 0, 8, 16, 24 } and
488 { 38, 46, 54, 62 } respectively.
489
490 Group names must be unique per pin controller, no two groups on the same
491 controller may have the same name.
492
493- The combination of a FUNCTION and a PIN GROUP determine a certain function
494 for a certain set of pins. The knowledge of the functions and pin groups
495 and their machine-specific particulars are kept inside the pinmux driver,
496 from the outside only the enumerators are known, and the driver core can
497 request:
498
499 - The name of a function with a certain selector (>= 0)
500 - A list of groups associated with a certain function
501 - That a certain group in that list to be activated for a certain function
502
503 As already described above, pin groups are in turn self-descriptive, so
504 the core will retrieve the actual pin range in a certain group from the
505 driver.
506
507- FUNCTIONS and GROUPS on a certain PIN CONTROLLER are MAPPED to a certain
508 device by the board file, device tree or similar machine setup configuration
509 mechanism, similar to how regulators are connected to devices, usually by
510 name. Defining a pin controller, function and group thus uniquely identify
511 the set of pins to be used by a certain device. (If only one possible group
512 of pins is available for the function, no group name need to be supplied -
513 the core will simply select the first and only group available.)
514
515 In the example case we can define that this particular machine shall
516 use device spi0 with pinmux function fspi0 group gspi0 and i2c0 on function
517 fi2c0 group gi2c0, on the primary pin controller, we get mappings
518 like these::
519
520 {
521 {"map-spi0", spi0, pinctrl0, fspi0, gspi0},
522 {"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0}
523 }
524
525 Every map must be assigned a state name, pin controller, device and
526 function. The group is not compulsory - if it is omitted the first group
527 presented by the driver as applicable for the function will be selected,
528 which is useful for simple cases.
529
530 It is possible to map several groups to the same combination of device,
531 pin controller and function. This is for cases where a certain function on
532 a certain pin controller may use different sets of pins in different
533 configurations.
534
535- PINS for a certain FUNCTION using a certain PIN GROUP on a certain
536 PIN CONTROLLER are provided on a first-come first-serve basis, so if some
537 other device mux setting or GPIO pin request has already taken your physical
538 pin, you will be denied the use of it. To get (activate) a new setting, the
539 old one has to be put (deactivated) first.
540
541Sometimes the documentation and hardware registers will be oriented around
542pads (or "fingers") rather than pins - these are the soldering surfaces on the
543silicon inside the package, and may or may not match the actual number of
544pins/balls underneath the capsule. Pick some enumeration that makes sense to
545you. Define enumerators only for the pins you can control if that makes sense.
546
547Assumptions:
548
549We assume that the number of possible function maps to pin groups is limited by
550the hardware. I.e. we assume that there is no system where any function can be
551mapped to any pin, like in a phone exchange. So the available pin groups for
552a certain function will be limited to a few choices (say up to eight or so),
553not hundreds or any amount of choices. This is the characteristic we have found
554by inspecting available pinmux hardware, and a necessary assumption since we
555expect pinmux drivers to present *all* possible function vs pin group mappings
556to the subsystem.
557
558
559Pinmux drivers
560==============
561
562The pinmux core takes care of preventing conflicts on pins and calling
563the pin controller driver to execute different settings.
564
565It is the responsibility of the pinmux driver to impose further restrictions
566(say for example infer electronic limitations due to load, etc.) to determine
567whether or not the requested function can actually be allowed, and in case it
568is possible to perform the requested mux setting, poke the hardware so that
569this happens.
570
571Pinmux drivers are required to supply a few callback functions, some are
572optional. Usually the set_mux() function is implemented, writing values into
573some certain registers to activate a certain mux setting for a certain pin.
574
575A simple driver for the above example will work by setting bits 0, 1, 2, 3 or 4
576into some register named MUX to select a certain function with a certain
577group of pins would work something like this::
578
579 #include <linux/pinctrl/pinctrl.h>
580 #include <linux/pinctrl/pinmux.h>
581
582 struct foo_group {
583 const char *name;
584 const unsigned int *pins;
585 const unsigned num_pins;
586 };
587
588 static const unsigned spi0_0_pins[] = { 0, 8, 16, 24 };
589 static const unsigned spi0_1_pins[] = { 38, 46, 54, 62 };
590 static const unsigned i2c0_pins[] = { 24, 25 };
591 static const unsigned mmc0_1_pins[] = { 56, 57 };
592 static const unsigned mmc0_2_pins[] = { 58, 59 };
593 static const unsigned mmc0_3_pins[] = { 60, 61, 62, 63 };
594
595 static const struct foo_group foo_groups[] = {
596 {
597 .name = "spi0_0_grp",
598 .pins = spi0_0_pins,
599 .num_pins = ARRAY_SIZE(spi0_0_pins),
600 },
601 {
602 .name = "spi0_1_grp",
603 .pins = spi0_1_pins,
604 .num_pins = ARRAY_SIZE(spi0_1_pins),
605 },
606 {
607 .name = "i2c0_grp",
608 .pins = i2c0_pins,
609 .num_pins = ARRAY_SIZE(i2c0_pins),
610 },
611 {
612 .name = "mmc0_1_grp",
613 .pins = mmc0_1_pins,
614 .num_pins = ARRAY_SIZE(mmc0_1_pins),
615 },
616 {
617 .name = "mmc0_2_grp",
618 .pins = mmc0_2_pins,
619 .num_pins = ARRAY_SIZE(mmc0_2_pins),
620 },
621 {
622 .name = "mmc0_3_grp",
623 .pins = mmc0_3_pins,
624 .num_pins = ARRAY_SIZE(mmc0_3_pins),
625 },
626 };
627
628
629 static int foo_get_groups_count(struct pinctrl_dev *pctldev)
630 {
631 return ARRAY_SIZE(foo_groups);
632 }
633
634 static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
635 unsigned selector)
636 {
637 return foo_groups[selector].name;
638 }
639
640 static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
641 const unsigned ** pins,
642 unsigned * num_pins)
643 {
644 *pins = (unsigned *) foo_groups[selector].pins;
645 *num_pins = foo_groups[selector].num_pins;
646 return 0;
647 }
648
649 static struct pinctrl_ops foo_pctrl_ops = {
650 .get_groups_count = foo_get_groups_count,
651 .get_group_name = foo_get_group_name,
652 .get_group_pins = foo_get_group_pins,
653 };
654
655 struct foo_pmx_func {
656 const char *name;
657 const char * const *groups;
658 const unsigned num_groups;
659 };
660
661 static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" };
662 static const char * const i2c0_groups[] = { "i2c0_grp" };
663 static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp",
664 "mmc0_3_grp" };
665
666 static const struct foo_pmx_func foo_functions[] = {
667 {
668 .name = "spi0",
669 .groups = spi0_groups,
670 .num_groups = ARRAY_SIZE(spi0_groups),
671 },
672 {
673 .name = "i2c0",
674 .groups = i2c0_groups,
675 .num_groups = ARRAY_SIZE(i2c0_groups),
676 },
677 {
678 .name = "mmc0",
679 .groups = mmc0_groups,
680 .num_groups = ARRAY_SIZE(mmc0_groups),
681 },
682 };
683
684 static int foo_get_functions_count(struct pinctrl_dev *pctldev)
685 {
686 return ARRAY_SIZE(foo_functions);
687 }
688
689 static const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
690 {
691 return foo_functions[selector].name;
692 }
693
694 static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
695 const char * const **groups,
696 unsigned * const num_groups)
697 {
698 *groups = foo_functions[selector].groups;
699 *num_groups = foo_functions[selector].num_groups;
700 return 0;
701 }
702
703 static int foo_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
704 unsigned group)
705 {
706 u8 regbit = (1 << selector + group);
707
708 writeb((readb(MUX)|regbit), MUX);
709 return 0;
710 }
711
712 static struct pinmux_ops foo_pmxops = {
713 .get_functions_count = foo_get_functions_count,
714 .get_function_name = foo_get_fname,
715 .get_function_groups = foo_get_groups,
716 .set_mux = foo_set_mux,
717 .strict = true,
718 };
719
720 /* Pinmux operations are handled by some pin controller */
721 static struct pinctrl_desc foo_desc = {
722 ...
723 .pctlops = &foo_pctrl_ops,
724 .pmxops = &foo_pmxops,
725 };
726
727In the example activating muxing 0 and 1 at the same time setting bits
7280 and 1, uses one pin in common so they would collide.
729
730The beauty of the pinmux subsystem is that since it keeps track of all
731pins and who is using them, it will already have denied an impossible
732request like that, so the driver does not need to worry about such
733things - when it gets a selector passed in, the pinmux subsystem makes
734sure no other device or GPIO assignment is already using the selected
735pins. Thus bits 0 and 1 in the control register will never be set at the
736same time.
737
738All the above functions are mandatory to implement for a pinmux driver.
739
740
741Pin control interaction with the GPIO subsystem
742===============================================
743
744Note that the following implies that the use case is to use a certain pin
745from the Linux kernel using the API in <linux/gpio.h> with gpio_request()
746and similar functions. There are cases where you may be using something
747that your datasheet calls "GPIO mode", but actually is just an electrical
748configuration for a certain device. See the section below named
749"GPIO mode pitfalls" for more details on this scenario.
750
751The public pinmux API contains two functions named pinctrl_gpio_request()
752and pinctrl_gpio_free(). These two functions shall *ONLY* be called from
753gpiolib-based drivers as part of their gpio_request() and
754gpio_free() semantics. Likewise the pinctrl_gpio_direction_[input|output]
755shall only be called from within respective gpio_direction_[input|output]
756gpiolib implementation.
757
758NOTE that platforms and individual drivers shall *NOT* request GPIO pins to be
759controlled e.g. muxed in. Instead, implement a proper gpiolib driver and have
760that driver request proper muxing and other control for its pins.
761
762The function list could become long, especially if you can convert every
763individual pin into a GPIO pin independent of any other pins, and then try
764the approach to define every pin as a function.
765
766In this case, the function array would become 64 entries for each GPIO
767setting and then the device functions.
768
769For this reason there are two functions a pin control driver can implement
770to enable only GPIO on an individual pin: .gpio_request_enable() and
771.gpio_disable_free().
772
773This function will pass in the affected GPIO range identified by the pin
774controller core, so you know which GPIO pins are being affected by the request
775operation.
776
777If your driver needs to have an indication from the framework of whether the
778GPIO pin shall be used for input or output you can implement the
779.gpio_set_direction() function. As described this shall be called from the
780gpiolib driver and the affected GPIO range, pin offset and desired direction
781will be passed along to this function.
782
783Alternatively to using these special functions, it is fully allowed to use
784named functions for each GPIO pin, the pinctrl_gpio_request() will attempt to
785obtain the function "gpioN" where "N" is the global GPIO pin number if no
786special GPIO-handler is registered.
787
788
789GPIO mode pitfalls
790==================
791
792Due to the naming conventions used by hardware engineers, where "GPIO"
793is taken to mean different things than what the kernel does, the developer
794may be confused by a datasheet talking about a pin being possible to set
795into "GPIO mode". It appears that what hardware engineers mean with
796"GPIO mode" is not necessarily the use case that is implied in the kernel
797interface <linux/gpio.h>: a pin that you grab from kernel code and then
798either listen for input or drive high/low to assert/deassert some
799external line.
800
801Rather hardware engineers think that "GPIO mode" means that you can
802software-control a few electrical properties of the pin that you would
803not be able to control if the pin was in some other mode, such as muxed in
804for a device.
805
806The GPIO portions of a pin and its relation to a certain pin controller
807configuration and muxing logic can be constructed in several ways. Here
808are two examples::
809
810 (A)
811 pin config
812 logic regs
813 | +- SPI
814 Physical pins --- pad --- pinmux -+- I2C
815 | +- mmc
816 | +- GPIO
817 pin
818 multiplex
819 logic regs
820
821Here some electrical properties of the pin can be configured no matter
822whether the pin is used for GPIO or not. If you multiplex a GPIO onto a
823pin, you can also drive it high/low from "GPIO" registers.
824Alternatively, the pin can be controlled by a certain peripheral, while
825still applying desired pin config properties. GPIO functionality is thus
826orthogonal to any other device using the pin.
827
828In this arrangement the registers for the GPIO portions of the pin controller,
829or the registers for the GPIO hardware module are likely to reside in a
830separate memory range only intended for GPIO driving, and the register
831range dealing with pin config and pin multiplexing get placed into a
832different memory range and a separate section of the data sheet.
833
834A flag "strict" in struct pinmux_ops is available to check and deny
835simultaneous access to the same pin from GPIO and pin multiplexing
836consumers on hardware of this type. The pinctrl driver should set this flag
837accordingly.
838
839::
840
841 (B)
842
843 pin config
844 logic regs
845 | +- SPI
846 Physical pins --- pad --- pinmux -+- I2C
847 | | +- mmc
848 | |
849 GPIO pin
850 multiplex
851 logic regs
852
853In this arrangement, the GPIO functionality can always be enabled, such that
854e.g. a GPIO input can be used to "spy" on the SPI/I2C/MMC signal while it is
855pulsed out. It is likely possible to disrupt the traffic on the pin by doing
856wrong things on the GPIO block, as it is never really disconnected. It is
857possible that the GPIO, pin config and pin multiplex registers are placed into
858the same memory range and the same section of the data sheet, although that
859need not be the case.
860
861In some pin controllers, although the physical pins are designed in the same
862way as (B), the GPIO function still can't be enabled at the same time as the
863peripheral functions. So again the "strict" flag should be set, denying
864simultaneous activation by GPIO and other muxed in devices.
865
866From a kernel point of view, however, these are different aspects of the
867hardware and shall be put into different subsystems:
868
869- Registers (or fields within registers) that control electrical
870 properties of the pin such as biasing and drive strength should be
871 exposed through the pinctrl subsystem, as "pin configuration" settings.
872
873- Registers (or fields within registers) that control muxing of signals
874 from various other HW blocks (e.g. I2C, MMC, or GPIO) onto pins should
875 be exposed through the pinctrl subsystem, as mux functions.
876
877- Registers (or fields within registers) that control GPIO functionality
878 such as setting a GPIO's output value, reading a GPIO's input value, or
879 setting GPIO pin direction should be exposed through the GPIO subsystem,
880 and if they also support interrupt capabilities, through the irqchip
881 abstraction.
882
883Depending on the exact HW register design, some functions exposed by the
884GPIO subsystem may call into the pinctrl subsystem in order to
885co-ordinate register settings across HW modules. In particular, this may
886be needed for HW with separate GPIO and pin controller HW modules, where
887e.g. GPIO direction is determined by a register in the pin controller HW
888module rather than the GPIO HW module.
889
890Electrical properties of the pin such as biasing and drive strength
891may be placed at some pin-specific register in all cases or as part
892of the GPIO register in case (B) especially. This doesn't mean that such
893properties necessarily pertain to what the Linux kernel calls "GPIO".
894
895Example: a pin is usually muxed in to be used as a UART TX line. But during
896system sleep, we need to put this pin into "GPIO mode" and ground it.
897
898If you make a 1-to-1 map to the GPIO subsystem for this pin, you may start
899to think that you need to come up with something really complex, that the
900pin shall be used for UART TX and GPIO at the same time, that you will grab
901a pin control handle and set it to a certain state to enable UART TX to be
902muxed in, then twist it over to GPIO mode and use gpio_direction_output()
903to drive it low during sleep, then mux it over to UART TX again when you
904wake up and maybe even gpio_request/gpio_free as part of this cycle. This
905all gets very complicated.
906
907The solution is to not think that what the datasheet calls "GPIO mode"
908has to be handled by the <linux/gpio.h> interface. Instead view this as
909a certain pin config setting. Look in e.g. <linux/pinctrl/pinconf-generic.h>
910and you find this in the documentation:
911
912 PIN_CONFIG_OUTPUT:
913 this will configure the pin in output, use argument
914 1 to indicate high level, argument 0 to indicate low level.
915
916So it is perfectly possible to push a pin into "GPIO mode" and drive the
917line low as part of the usual pin control map. So for example your UART
918driver may look like this::
919
920 #include <linux/pinctrl/consumer.h>
921
922 struct pinctrl *pinctrl;
923 struct pinctrl_state *pins_default;
924 struct pinctrl_state *pins_sleep;
925
926 pins_default = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_DEFAULT);
927 pins_sleep = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_SLEEP);
928
929 /* Normal mode */
930 retval = pinctrl_select_state(pinctrl, pins_default);
931 /* Sleep mode */
932 retval = pinctrl_select_state(pinctrl, pins_sleep);
933
934And your machine configuration may look like this:
935--------------------------------------------------
936
937::
938
939 static unsigned long uart_default_mode[] = {
940 PIN_CONF_PACKED(PIN_CONFIG_DRIVE_PUSH_PULL, 0),
941 };
942
943 static unsigned long uart_sleep_mode[] = {
944 PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0),
945 };
946
947 static struct pinctrl_map pinmap[] __initdata = {
948 PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
949 "u0_group", "u0"),
950 PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
951 "UART_TX_PIN", uart_default_mode),
952 PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
953 "u0_group", "gpio-mode"),
954 PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
955 "UART_TX_PIN", uart_sleep_mode),
956 };
957
958 foo_init(void) {
959 pinctrl_register_mappings(pinmap, ARRAY_SIZE(pinmap));
960 }
961
962Here the pins we want to control are in the "u0_group" and there is some
963function called "u0" that can be enabled on this group of pins, and then
964everything is UART business as usual. But there is also some function
965named "gpio-mode" that can be mapped onto the same pins to move them into
966GPIO mode.
967
968This will give the desired effect without any bogus interaction with the
969GPIO subsystem. It is just an electrical configuration used by that device
970when going to sleep, it might imply that the pin is set into something the
971datasheet calls "GPIO mode", but that is not the point: it is still used
972by that UART device to control the pins that pertain to that very UART
973driver, putting them into modes needed by the UART. GPIO in the Linux
974kernel sense are just some 1-bit line, and is a different use case.
975
976How the registers are poked to attain the push or pull, and output low
977configuration and the muxing of the "u0" or "gpio-mode" group onto these
978pins is a question for the driver.
979
980Some datasheets will be more helpful and refer to the "GPIO mode" as
981"low power mode" rather than anything to do with GPIO. This often means
982the same thing electrically speaking, but in this latter case the
983software engineers will usually quickly identify that this is some
984specific muxing or configuration rather than anything related to the GPIO
985API.
986
987
988Board/machine configuration
989===========================
990
991Boards and machines define how a certain complete running system is put
992together, including how GPIOs and devices are muxed, how regulators are
993constrained and how the clock tree looks. Of course pinmux settings are also
994part of this.
995
996A pin controller configuration for a machine looks pretty much like a simple
997regulator configuration, so for the example array above we want to enable i2c
998and spi on the second function mapping::
999
1000 #include <linux/pinctrl/machine.h>
1001
1002 static const struct pinctrl_map mapping[] __initconst = {
1003 {
1004 .dev_name = "foo-spi.0",
1005 .name = PINCTRL_STATE_DEFAULT,
1006 .type = PIN_MAP_TYPE_MUX_GROUP,
1007 .ctrl_dev_name = "pinctrl-foo",
1008 .data.mux.function = "spi0",
1009 },
1010 {
1011 .dev_name = "foo-i2c.0",
1012 .name = PINCTRL_STATE_DEFAULT,
1013 .type = PIN_MAP_TYPE_MUX_GROUP,
1014 .ctrl_dev_name = "pinctrl-foo",
1015 .data.mux.function = "i2c0",
1016 },
1017 {
1018 .dev_name = "foo-mmc.0",
1019 .name = PINCTRL_STATE_DEFAULT,
1020 .type = PIN_MAP_TYPE_MUX_GROUP,
1021 .ctrl_dev_name = "pinctrl-foo",
1022 .data.mux.function = "mmc0",
1023 },
1024 };
1025
1026The dev_name here matches to the unique device name that can be used to look
1027up the device struct (just like with clockdev or regulators). The function name
1028must match a function provided by the pinmux driver handling this pin range.
1029
1030As you can see we may have several pin controllers on the system and thus
1031we need to specify which one of them contains the functions we wish to map.
1032
1033You register this pinmux mapping to the pinmux subsystem by simply::
1034
1035 ret = pinctrl_register_mappings(mapping, ARRAY_SIZE(mapping));
1036
1037Since the above construct is pretty common there is a helper macro to make
1038it even more compact which assumes you want to use pinctrl-foo and position
10390 for mapping, for example::
1040
1041 static struct pinctrl_map mapping[] __initdata = {
1042 PIN_MAP_MUX_GROUP("foo-i2c.o", PINCTRL_STATE_DEFAULT,
1043 "pinctrl-foo", NULL, "i2c0"),
1044 };
1045
1046The mapping table may also contain pin configuration entries. It's common for
1047each pin/group to have a number of configuration entries that affect it, so
1048the table entries for configuration reference an array of config parameters
1049and values. An example using the convenience macros is shown below::
1050
1051 static unsigned long i2c_grp_configs[] = {
1052 FOO_PIN_DRIVEN,
1053 FOO_PIN_PULLUP,
1054 };
1055
1056 static unsigned long i2c_pin_configs[] = {
1057 FOO_OPEN_COLLECTOR,
1058 FOO_SLEW_RATE_SLOW,
1059 };
1060
1061 static struct pinctrl_map mapping[] __initdata = {
1062 PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT,
1063 "pinctrl-foo", "i2c0", "i2c0"),
1064 PIN_MAP_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT,
1065 "pinctrl-foo", "i2c0", i2c_grp_configs),
1066 PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT,
1067 "pinctrl-foo", "i2c0scl", i2c_pin_configs),
1068 PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT,
1069 "pinctrl-foo", "i2c0sda", i2c_pin_configs),
1070 };
1071
1072Finally, some devices expect the mapping table to contain certain specific
1073named states. When running on hardware that doesn't need any pin controller
1074configuration, the mapping table must still contain those named states, in
1075order to explicitly indicate that the states were provided and intended to
1076be empty. Table entry macro PIN_MAP_DUMMY_STATE serves the purpose of defining
1077a named state without causing any pin controller to be programmed::
1078
1079 static struct pinctrl_map mapping[] __initdata = {
1080 PIN_MAP_DUMMY_STATE("foo-i2c.0", PINCTRL_STATE_DEFAULT),
1081 };
1082
1083
1084Complex mappings
1085================
1086
1087As it is possible to map a function to different groups of pins an optional
1088.group can be specified like this::
1089
1090 ...
1091 {
1092 .dev_name = "foo-spi.0",
1093 .name = "spi0-pos-A",
1094 .type = PIN_MAP_TYPE_MUX_GROUP,
1095 .ctrl_dev_name = "pinctrl-foo",
1096 .function = "spi0",
1097 .group = "spi0_0_grp",
1098 },
1099 {
1100 .dev_name = "foo-spi.0",
1101 .name = "spi0-pos-B",
1102 .type = PIN_MAP_TYPE_MUX_GROUP,
1103 .ctrl_dev_name = "pinctrl-foo",
1104 .function = "spi0",
1105 .group = "spi0_1_grp",
1106 },
1107 ...
1108
1109This example mapping is used to switch between two positions for spi0 at
1110runtime, as described further below under the heading "Runtime pinmuxing".
1111
1112Further it is possible for one named state to affect the muxing of several
1113groups of pins, say for example in the mmc0 example above, where you can
1114additively expand the mmc0 bus from 2 to 4 to 8 pins. If we want to use all
1115three groups for a total of 2+2+4 = 8 pins (for an 8-bit MMC bus as is the
1116case), we define a mapping like this::
1117
1118 ...
1119 {
1120 .dev_name = "foo-mmc.0",
1121 .name = "2bit"
1122 .type = PIN_MAP_TYPE_MUX_GROUP,
1123 .ctrl_dev_name = "pinctrl-foo",
1124 .function = "mmc0",
1125 .group = "mmc0_1_grp",
1126 },
1127 {
1128 .dev_name = "foo-mmc.0",
1129 .name = "4bit"
1130 .type = PIN_MAP_TYPE_MUX_GROUP,
1131 .ctrl_dev_name = "pinctrl-foo",
1132 .function = "mmc0",
1133 .group = "mmc0_1_grp",
1134 },
1135 {
1136 .dev_name = "foo-mmc.0",
1137 .name = "4bit"
1138 .type = PIN_MAP_TYPE_MUX_GROUP,
1139 .ctrl_dev_name = "pinctrl-foo",
1140 .function = "mmc0",
1141 .group = "mmc0_2_grp",
1142 },
1143 {
1144 .dev_name = "foo-mmc.0",
1145 .name = "8bit"
1146 .type = PIN_MAP_TYPE_MUX_GROUP,
1147 .ctrl_dev_name = "pinctrl-foo",
1148 .function = "mmc0",
1149 .group = "mmc0_1_grp",
1150 },
1151 {
1152 .dev_name = "foo-mmc.0",
1153 .name = "8bit"
1154 .type = PIN_MAP_TYPE_MUX_GROUP,
1155 .ctrl_dev_name = "pinctrl-foo",
1156 .function = "mmc0",
1157 .group = "mmc0_2_grp",
1158 },
1159 {
1160 .dev_name = "foo-mmc.0",
1161 .name = "8bit"
1162 .type = PIN_MAP_TYPE_MUX_GROUP,
1163 .ctrl_dev_name = "pinctrl-foo",
1164 .function = "mmc0",
1165 .group = "mmc0_3_grp",
1166 },
1167 ...
1168
1169The result of grabbing this mapping from the device with something like
1170this (see next paragraph)::
1171
1172 p = devm_pinctrl_get(dev);
1173 s = pinctrl_lookup_state(p, "8bit");
1174 ret = pinctrl_select_state(p, s);
1175
1176or more simply::
1177
1178 p = devm_pinctrl_get_select(dev, "8bit");
1179
1180Will be that you activate all the three bottom records in the mapping at
1181once. Since they share the same name, pin controller device, function and
1182device, and since we allow multiple groups to match to a single device, they
1183all get selected, and they all get enabled and disable simultaneously by the
1184pinmux core.
1185
1186
1187Pin control requests from drivers
1188=================================
1189
1190When a device driver is about to probe the device core will automatically
1191attempt to issue pinctrl_get_select_default() on these devices.
1192This way driver writers do not need to add any of the boilerplate code
1193of the type found below. However when doing fine-grained state selection
1194and not using the "default" state, you may have to do some device driver
1195handling of the pinctrl handles and states.
1196
1197So if you just want to put the pins for a certain device into the default
1198state and be done with it, there is nothing you need to do besides
1199providing the proper mapping table. The device core will take care of
1200the rest.
1201
1202Generally it is discouraged to let individual drivers get and enable pin
1203control. So if possible, handle the pin control in platform code or some other
1204place where you have access to all the affected struct device * pointers. In
1205some cases where a driver needs to e.g. switch between different mux mappings
1206at runtime this is not possible.
1207
1208A typical case is if a driver needs to switch bias of pins from normal
1209operation and going to sleep, moving from the PINCTRL_STATE_DEFAULT to
1210PINCTRL_STATE_SLEEP at runtime, re-biasing or even re-muxing pins to save
1211current in sleep mode.
1212
1213A driver may request a certain control state to be activated, usually just the
1214default state like this::
1215
1216 #include <linux/pinctrl/consumer.h>
1217
1218 struct foo_state {
1219 struct pinctrl *p;
1220 struct pinctrl_state *s;
1221 ...
1222 };
1223
1224 foo_probe()
1225 {
1226 /* Allocate a state holder named "foo" etc */
1227 struct foo_state *foo = ...;
1228
1229 foo->p = devm_pinctrl_get(&device);
1230 if (IS_ERR(foo->p)) {
1231 /* FIXME: clean up "foo" here */
1232 return PTR_ERR(foo->p);
1233 }
1234
1235 foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
1236 if (IS_ERR(foo->s)) {
1237 /* FIXME: clean up "foo" here */
1238 return PTR_ERR(s);
1239 }
1240
1241 ret = pinctrl_select_state(foo->s);
1242 if (ret < 0) {
1243 /* FIXME: clean up "foo" here */
1244 return ret;
1245 }
1246 }
1247
1248This get/lookup/select/put sequence can just as well be handled by bus drivers
1249if you don't want each and every driver to handle it and you know the
1250arrangement on your bus.
1251
1252The semantics of the pinctrl APIs are:
1253
1254- pinctrl_get() is called in process context to obtain a handle to all pinctrl
1255 information for a given client device. It will allocate a struct from the
1256 kernel memory to hold the pinmux state. All mapping table parsing or similar
1257 slow operations take place within this API.
1258
1259- devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put()
1260 to be called automatically on the retrieved pointer when the associated
1261 device is removed. It is recommended to use this function over plain
1262 pinctrl_get().
1263
1264- pinctrl_lookup_state() is called in process context to obtain a handle to a
1265 specific state for a client device. This operation may be slow, too.
1266
1267- pinctrl_select_state() programs pin controller hardware according to the
1268 definition of the state as given by the mapping table. In theory, this is a
1269 fast-path operation, since it only involved blasting some register settings
1270 into hardware. However, note that some pin controllers may have their
1271 registers on a slow/IRQ-based bus, so client devices should not assume they
1272 can call pinctrl_select_state() from non-blocking contexts.
1273
1274- pinctrl_put() frees all information associated with a pinctrl handle.
1275
1276- devm_pinctrl_put() is a variant of pinctrl_put() that may be used to
1277 explicitly destroy a pinctrl object returned by devm_pinctrl_get().
1278 However, use of this function will be rare, due to the automatic cleanup
1279 that will occur even without calling it.
1280
1281 pinctrl_get() must be paired with a plain pinctrl_put().
1282 pinctrl_get() may not be paired with devm_pinctrl_put().
1283 devm_pinctrl_get() can optionally be paired with devm_pinctrl_put().
1284 devm_pinctrl_get() may not be paired with plain pinctrl_put().
1285
1286Usually the pin control core handled the get/put pair and call out to the
1287device drivers bookkeeping operations, like checking available functions and
1288the associated pins, whereas select_state pass on to the pin controller
1289driver which takes care of activating and/or deactivating the mux setting by
1290quickly poking some registers.
1291
1292The pins are allocated for your device when you issue the devm_pinctrl_get()
1293call, after this you should be able to see this in the debugfs listing of all
1294pins.
1295
1296NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the
1297requested pinctrl handles, for example if the pinctrl driver has not yet
1298registered. Thus make sure that the error path in your driver gracefully
1299cleans up and is ready to retry the probing later in the startup process.
1300
1301
1302Drivers needing both pin control and GPIOs
1303==========================================
1304
1305Again, it is discouraged to let drivers lookup and select pin control states
1306themselves, but again sometimes this is unavoidable.
1307
1308So say that your driver is fetching its resources like this::
1309
1310 #include <linux/pinctrl/consumer.h>
1311 #include <linux/gpio.h>
1312
1313 struct pinctrl *pinctrl;
1314 int gpio;
1315
1316 pinctrl = devm_pinctrl_get_select_default(&dev);
1317 gpio = devm_gpio_request(&dev, 14, "foo");
1318
1319Here we first request a certain pin state and then request GPIO 14 to be
1320used. If you're using the subsystems orthogonally like this, you should
1321nominally always get your pinctrl handle and select the desired pinctrl
1322state BEFORE requesting the GPIO. This is a semantic convention to avoid
1323situations that can be electrically unpleasant, you will certainly want to
1324mux in and bias pins in a certain way before the GPIO subsystems starts to
1325deal with them.
1326
1327The above can be hidden: using the device core, the pinctrl core may be
1328setting up the config and muxing for the pins right before the device is
1329probing, nevertheless orthogonal to the GPIO subsystem.
1330
1331But there are also situations where it makes sense for the GPIO subsystem
1332to communicate directly with the pinctrl subsystem, using the latter as a
1333back-end. This is when the GPIO driver may call out to the functions
1334described in the section "Pin control interaction with the GPIO subsystem"
1335above. This only involves per-pin multiplexing, and will be completely
1336hidden behind the gpio_*() function namespace. In this case, the driver
1337need not interact with the pin control subsystem at all.
1338
1339If a pin control driver and a GPIO driver is dealing with the same pins
1340and the use cases involve multiplexing, you MUST implement the pin controller
1341as a back-end for the GPIO driver like this, unless your hardware design
1342is such that the GPIO controller can override the pin controller's
1343multiplexing state through hardware without the need to interact with the
1344pin control system.
1345
1346
1347System pin control hogging
1348==========================
1349
1350Pin control map entries can be hogged by the core when the pin controller
1351is registered. This means that the core will attempt to call pinctrl_get(),
1352lookup_state() and select_state() on it immediately after the pin control
1353device has been registered.
1354
1355This occurs for mapping table entries where the client device name is equal
1356to the pin controller device name, and the state name is PINCTRL_STATE_DEFAULT::
1357
1358 {
1359 .dev_name = "pinctrl-foo",
1360 .name = PINCTRL_STATE_DEFAULT,
1361 .type = PIN_MAP_TYPE_MUX_GROUP,
1362 .ctrl_dev_name = "pinctrl-foo",
1363 .function = "power_func",
1364 },
1365
1366Since it may be common to request the core to hog a few always-applicable
1367mux settings on the primary pin controller, there is a convenience macro for
1368this::
1369
1370 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-foo", NULL /* group */,
1371 "power_func")
1372
1373This gives the exact same result as the above construction.
1374
1375
1376Runtime pinmuxing
1377=================
1378
1379It is possible to mux a certain function in and out at runtime, say to move
1380an SPI port from one set of pins to another set of pins. Say for example for
1381spi0 in the example above, we expose two different groups of pins for the same
1382function, but with different named in the mapping as described under
1383"Advanced mapping" above. So that for an SPI device, we have two states named
1384"pos-A" and "pos-B".
1385
1386This snippet first initializes a state object for both groups (in foo_probe()),
1387then muxes the function in the pins defined by group A, and finally muxes it in
1388on the pins defined by group B::
1389
1390 #include <linux/pinctrl/consumer.h>
1391
1392 struct pinctrl *p;
1393 struct pinctrl_state *s1, *s2;
1394
1395 foo_probe()
1396 {
1397 /* Setup */
1398 p = devm_pinctrl_get(&device);
1399 if (IS_ERR(p))
1400 ...
1401
1402 s1 = pinctrl_lookup_state(foo->p, "pos-A");
1403 if (IS_ERR(s1))
1404 ...
1405
1406 s2 = pinctrl_lookup_state(foo->p, "pos-B");
1407 if (IS_ERR(s2))
1408 ...
1409 }
1410
1411 foo_switch()
1412 {
1413 /* Enable on position A */
1414 ret = pinctrl_select_state(s1);
1415 if (ret < 0)
1416 ...
1417
1418 ...
1419
1420 /* Enable on position B */
1421 ret = pinctrl_select_state(s2);
1422 if (ret < 0)
1423 ...
1424
1425 ...
1426 }
1427
1428The above has to be done from process context. The reservation of the pins
1429will be done when the state is activated, so in effect one specific pin
1430can be used by different functions at different times on a running system.