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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Application UART driver for:
4 * Freescale STMP37XX/STMP378X
5 * Alphascale ASM9260
6 *
7 * Author: dmitry pervushin <dimka@embeddedalley.com>
8 *
9 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
10 * Provide Alphascale ASM9260 support.
11 * Copyright 2008-2010 Freescale Semiconductor, Inc.
12 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
13 */
14
15#if defined(CONFIG_SERIAL_MXS_AUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
16#define SUPPORT_SYSRQ
17#endif
18
19#include <linux/kernel.h>
20#include <linux/errno.h>
21#include <linux/init.h>
22#include <linux/console.h>
23#include <linux/interrupt.h>
24#include <linux/module.h>
25#include <linux/slab.h>
26#include <linux/wait.h>
27#include <linux/tty.h>
28#include <linux/tty_driver.h>
29#include <linux/tty_flip.h>
30#include <linux/serial.h>
31#include <linux/serial_core.h>
32#include <linux/platform_device.h>
33#include <linux/device.h>
34#include <linux/clk.h>
35#include <linux/delay.h>
36#include <linux/io.h>
37#include <linux/of_device.h>
38#include <linux/dma-mapping.h>
39#include <linux/dmaengine.h>
40
41#include <asm/cacheflush.h>
42
43#include <linux/gpio/consumer.h>
44#include <linux/err.h>
45#include <linux/irq.h>
46#include "serial_mctrl_gpio.h"
47
48#define MXS_AUART_PORTS 5
49#define MXS_AUART_FIFO_SIZE 16
50
51#define SET_REG 0x4
52#define CLR_REG 0x8
53#define TOG_REG 0xc
54
55#define AUART_CTRL0 0x00000000
56#define AUART_CTRL1 0x00000010
57#define AUART_CTRL2 0x00000020
58#define AUART_LINECTRL 0x00000030
59#define AUART_LINECTRL2 0x00000040
60#define AUART_INTR 0x00000050
61#define AUART_DATA 0x00000060
62#define AUART_STAT 0x00000070
63#define AUART_DEBUG 0x00000080
64#define AUART_VERSION 0x00000090
65#define AUART_AUTOBAUD 0x000000a0
66
67#define AUART_CTRL0_SFTRST (1 << 31)
68#define AUART_CTRL0_CLKGATE (1 << 30)
69#define AUART_CTRL0_RXTO_ENABLE (1 << 27)
70#define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16)
71#define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff)
72
73#define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff)
74
75#define AUART_CTRL2_DMAONERR (1 << 26)
76#define AUART_CTRL2_TXDMAE (1 << 25)
77#define AUART_CTRL2_RXDMAE (1 << 24)
78
79#define AUART_CTRL2_CTSEN (1 << 15)
80#define AUART_CTRL2_RTSEN (1 << 14)
81#define AUART_CTRL2_RTS (1 << 11)
82#define AUART_CTRL2_RXE (1 << 9)
83#define AUART_CTRL2_TXE (1 << 8)
84#define AUART_CTRL2_UARTEN (1 << 0)
85
86#define AUART_LINECTRL_BAUD_DIV_MAX 0x003fffc0
87#define AUART_LINECTRL_BAUD_DIV_MIN 0x000000ec
88#define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16
89#define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000
90#define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
91#define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8
92#define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00
93#define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
94#define AUART_LINECTRL_SPS (1 << 7)
95#define AUART_LINECTRL_WLEN_MASK 0x00000060
96#define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5)
97#define AUART_LINECTRL_FEN (1 << 4)
98#define AUART_LINECTRL_STP2 (1 << 3)
99#define AUART_LINECTRL_EPS (1 << 2)
100#define AUART_LINECTRL_PEN (1 << 1)
101#define AUART_LINECTRL_BRK (1 << 0)
102
103#define AUART_INTR_RTIEN (1 << 22)
104#define AUART_INTR_TXIEN (1 << 21)
105#define AUART_INTR_RXIEN (1 << 20)
106#define AUART_INTR_CTSMIEN (1 << 17)
107#define AUART_INTR_RTIS (1 << 6)
108#define AUART_INTR_TXIS (1 << 5)
109#define AUART_INTR_RXIS (1 << 4)
110#define AUART_INTR_CTSMIS (1 << 1)
111
112#define AUART_STAT_BUSY (1 << 29)
113#define AUART_STAT_CTS (1 << 28)
114#define AUART_STAT_TXFE (1 << 27)
115#define AUART_STAT_TXFF (1 << 25)
116#define AUART_STAT_RXFE (1 << 24)
117#define AUART_STAT_OERR (1 << 19)
118#define AUART_STAT_BERR (1 << 18)
119#define AUART_STAT_PERR (1 << 17)
120#define AUART_STAT_FERR (1 << 16)
121#define AUART_STAT_RXCOUNT_MASK 0xffff
122
123/*
124 * Start of Alphascale asm9260 defines
125 * This list contains only differences of existing bits
126 * between imx2x and asm9260
127 */
128#define ASM9260_HW_CTRL0 0x0000
129/*
130 * RW. Tell the UART to execute the RX DMA Command. The
131 * UART will clear this bit at the end of receive execution.
132 */
133#define ASM9260_BM_CTRL0_RXDMA_RUN BIT(28)
134/* RW. 0 use FIFO for status register; 1 use DMA */
135#define ASM9260_BM_CTRL0_RXTO_SOURCE_STATUS BIT(25)
136/*
137 * RW. RX TIMEOUT Enable. Valid for FIFO and DMA.
138 * Warning: If this bit is set to 0, the RX timeout will not affect receive DMA
139 * operation. If this bit is set to 1, a receive timeout will cause the receive
140 * DMA logic to terminate by filling the remaining DMA bytes with garbage data.
141 */
142#define ASM9260_BM_CTRL0_RXTO_ENABLE BIT(24)
143/*
144 * RW. Receive Timeout Counter Value: number of 8-bit-time to wait before
145 * asserting timeout on the RX input. If the RXFIFO is not empty and the RX
146 * input is idle, then the watchdog counter will decrement each bit-time. Note
147 * 7-bit-time is added to the programmed value, so a value of zero will set
148 * the counter to 7-bit-time, a value of 0x1 gives 15-bit-time and so on. Also
149 * note that the counter is reloaded at the end of each frame, so if the frame
150 * is 10 bits long and the timeout counter value is zero, then timeout will
151 * occur (when FIFO is not empty) even if the RX input is not idle. The default
152 * value is 0x3 (31 bit-time).
153 */
154#define ASM9260_BM_CTRL0_RXTO_MASK (0xff << 16)
155/* TIMEOUT = (100*7+1)*(1/BAUD) */
156#define ASM9260_BM_CTRL0_DEFAULT_RXTIMEOUT (20 << 16)
157
158/* TX ctrl register */
159#define ASM9260_HW_CTRL1 0x0010
160/*
161 * RW. Tell the UART to execute the TX DMA Command. The
162 * UART will clear this bit at the end of transmit execution.
163 */
164#define ASM9260_BM_CTRL1_TXDMA_RUN BIT(28)
165
166#define ASM9260_HW_CTRL2 0x0020
167/*
168 * RW. Receive Interrupt FIFO Level Select.
169 * The trigger points for the receive interrupt are as follows:
170 * ONE_EIGHTHS = 0x0 Trigger on FIFO full to at least 2 of 16 entries.
171 * ONE_QUARTER = 0x1 Trigger on FIFO full to at least 4 of 16 entries.
172 * ONE_HALF = 0x2 Trigger on FIFO full to at least 8 of 16 entries.
173 * THREE_QUARTERS = 0x3 Trigger on FIFO full to at least 12 of 16 entries.
174 * SEVEN_EIGHTHS = 0x4 Trigger on FIFO full to at least 14 of 16 entries.
175 */
176#define ASM9260_BM_CTRL2_RXIFLSEL (7 << 20)
177#define ASM9260_BM_CTRL2_DEFAULT_RXIFLSEL (3 << 20)
178/* RW. Same as RXIFLSEL */
179#define ASM9260_BM_CTRL2_TXIFLSEL (7 << 16)
180#define ASM9260_BM_CTRL2_DEFAULT_TXIFLSEL (2 << 16)
181/* RW. Set DTR. When this bit is 1, the output is 0. */
182#define ASM9260_BM_CTRL2_DTR BIT(10)
183/* RW. Loop Back Enable */
184#define ASM9260_BM_CTRL2_LBE BIT(7)
185#define ASM9260_BM_CTRL2_PORT_ENABLE BIT(0)
186
187#define ASM9260_HW_LINECTRL 0x0030
188/*
189 * RW. Stick Parity Select. When bits 1, 2, and 7 of this register are set, the
190 * parity bit is transmitted and checked as a 0. When bits 1 and 7 are set,
191 * and bit 2 is 0, the parity bit is transmitted and checked as a 1. When this
192 * bit is cleared stick parity is disabled.
193 */
194#define ASM9260_BM_LCTRL_SPS BIT(7)
195/* RW. Word length */
196#define ASM9260_BM_LCTRL_WLEN (3 << 5)
197#define ASM9260_BM_LCTRL_CHRL_5 (0 << 5)
198#define ASM9260_BM_LCTRL_CHRL_6 (1 << 5)
199#define ASM9260_BM_LCTRL_CHRL_7 (2 << 5)
200#define ASM9260_BM_LCTRL_CHRL_8 (3 << 5)
201
202/*
203 * Interrupt register.
204 * contains the interrupt enables and the interrupt status bits
205 */
206#define ASM9260_HW_INTR 0x0040
207/* Tx FIFO EMPTY Raw Interrupt enable */
208#define ASM9260_BM_INTR_TFEIEN BIT(27)
209/* Overrun Error Interrupt Enable. */
210#define ASM9260_BM_INTR_OEIEN BIT(26)
211/* Break Error Interrupt Enable. */
212#define ASM9260_BM_INTR_BEIEN BIT(25)
213/* Parity Error Interrupt Enable. */
214#define ASM9260_BM_INTR_PEIEN BIT(24)
215/* Framing Error Interrupt Enable. */
216#define ASM9260_BM_INTR_FEIEN BIT(23)
217
218/* nUARTDSR Modem Interrupt Enable. */
219#define ASM9260_BM_INTR_DSRMIEN BIT(19)
220/* nUARTDCD Modem Interrupt Enable. */
221#define ASM9260_BM_INTR_DCDMIEN BIT(18)
222/* nUARTRI Modem Interrupt Enable. */
223#define ASM9260_BM_INTR_RIMIEN BIT(16)
224/* Auto-Boud Timeout */
225#define ASM9260_BM_INTR_ABTO BIT(13)
226#define ASM9260_BM_INTR_ABEO BIT(12)
227/* Tx FIFO EMPTY Raw Interrupt state */
228#define ASM9260_BM_INTR_TFEIS BIT(11)
229/* Overrun Error */
230#define ASM9260_BM_INTR_OEIS BIT(10)
231/* Break Error */
232#define ASM9260_BM_INTR_BEIS BIT(9)
233/* Parity Error */
234#define ASM9260_BM_INTR_PEIS BIT(8)
235/* Framing Error */
236#define ASM9260_BM_INTR_FEIS BIT(7)
237#define ASM9260_BM_INTR_DSRMIS BIT(3)
238#define ASM9260_BM_INTR_DCDMIS BIT(2)
239#define ASM9260_BM_INTR_RIMIS BIT(0)
240
241/*
242 * RW. In DMA mode, up to 4 Received/Transmit characters can be accessed at a
243 * time. In PIO mode, only one character can be accessed at a time. The status
244 * register contains the receive data flags and valid bits.
245 */
246#define ASM9260_HW_DATA 0x0050
247
248#define ASM9260_HW_STAT 0x0060
249/* RO. If 1, UARTAPP is present in this product. */
250#define ASM9260_BM_STAT_PRESENT BIT(31)
251/* RO. If 1, HISPEED is present in this product. */
252#define ASM9260_BM_STAT_HISPEED BIT(30)
253/* RO. Receive FIFO Full. */
254#define ASM9260_BM_STAT_RXFULL BIT(26)
255
256/* RO. The UART Debug Register contains the state of the DMA signals. */
257#define ASM9260_HW_DEBUG 0x0070
258/* DMA Command Run Status */
259#define ASM9260_BM_DEBUG_TXDMARUN BIT(5)
260#define ASM9260_BM_DEBUG_RXDMARUN BIT(4)
261/* DMA Command End Status */
262#define ASM9260_BM_DEBUG_TXCMDEND BIT(3)
263#define ASM9260_BM_DEBUG_RXCMDEND BIT(2)
264/* DMA Request Status */
265#define ASM9260_BM_DEBUG_TXDMARQ BIT(1)
266#define ASM9260_BM_DEBUG_RXDMARQ BIT(0)
267
268#define ASM9260_HW_ILPR 0x0080
269
270#define ASM9260_HW_RS485CTRL 0x0090
271/*
272 * RW. This bit reverses the polarity of the direction control signal on the RTS
273 * (or DTR) pin.
274 * If 0, The direction control pin will be driven to logic ‘0’ when the
275 * transmitter has data to be sent. It will be driven to logic ‘1’ after the
276 * last bit of data has been transmitted.
277 */
278#define ASM9260_BM_RS485CTRL_ONIV BIT(5)
279/* RW. Enable Auto Direction Control. */
280#define ASM9260_BM_RS485CTRL_DIR_CTRL BIT(4)
281/*
282 * RW. If 0 and DIR_CTRL = 1, pin RTS is used for direction control.
283 * If 1 and DIR_CTRL = 1, pin DTR is used for direction control.
284 */
285#define ASM9260_BM_RS485CTRL_PINSEL BIT(3)
286/* RW. Enable Auto Address Detect (AAD). */
287#define ASM9260_BM_RS485CTRL_AADEN BIT(2)
288/* RW. Disable receiver. */
289#define ASM9260_BM_RS485CTRL_RXDIS BIT(1)
290/* RW. Enable RS-485/EIA-485 Normal Multidrop Mode (NMM) */
291#define ASM9260_BM_RS485CTRL_RS485EN BIT(0)
292
293#define ASM9260_HW_RS485ADRMATCH 0x00a0
294/* Contains the address match value. */
295#define ASM9260_BM_RS485ADRMATCH_MASK (0xff << 0)
296
297#define ASM9260_HW_RS485DLY 0x00b0
298/*
299 * RW. Contains the direction control (RTS or DTR) delay value. This delay time
300 * is in periods of the baud clock.
301 */
302#define ASM9260_BM_RS485DLY_MASK (0xff << 0)
303
304#define ASM9260_HW_AUTOBAUD 0x00c0
305/* WO. Auto-baud time-out interrupt clear bit. */
306#define ASM9260_BM_AUTOBAUD_TO_INT_CLR BIT(9)
307/* WO. End of auto-baud interrupt clear bit. */
308#define ASM9260_BM_AUTOBAUD_EO_INT_CLR BIT(8)
309/* Restart in case of timeout (counter restarts at next UART Rx falling edge) */
310#define ASM9260_BM_AUTOBAUD_AUTORESTART BIT(2)
311/* Auto-baud mode select bit. 0 - Mode 0, 1 - Mode 1. */
312#define ASM9260_BM_AUTOBAUD_MODE BIT(1)
313/*
314 * Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is
315 * automatically cleared after auto-baud completion.
316 */
317#define ASM9260_BM_AUTOBAUD_START BIT(0)
318
319#define ASM9260_HW_CTRL3 0x00d0
320#define ASM9260_BM_CTRL3_OUTCLK_DIV_MASK (0xffff << 16)
321/*
322 * RW. Provide clk over OUTCLK pin. In case of asm9260 it can be configured on
323 * pins 137 and 144.
324 */
325#define ASM9260_BM_CTRL3_MASTERMODE BIT(6)
326/* RW. Baud Rate Mode: 1 - Enable sync mode. 0 - async mode. */
327#define ASM9260_BM_CTRL3_SYNCMODE BIT(4)
328/* RW. 1 - MSB bit send frist; 0 - LSB bit frist. */
329#define ASM9260_BM_CTRL3_MSBF BIT(2)
330/* RW. 1 - sample rate = 8 x Baudrate; 0 - sample rate = 16 x Baudrate. */
331#define ASM9260_BM_CTRL3_BAUD8 BIT(1)
332/* RW. 1 - Set word length to 9bit. 0 - use ASM9260_BM_LCTRL_WLEN */
333#define ASM9260_BM_CTRL3_9BIT BIT(0)
334
335#define ASM9260_HW_ISO7816_CTRL 0x00e0
336/* RW. Enable High Speed mode. */
337#define ASM9260_BM_ISO7816CTRL_HS BIT(12)
338/* Disable Successive Receive NACK */
339#define ASM9260_BM_ISO7816CTRL_DS_NACK BIT(8)
340#define ASM9260_BM_ISO7816CTRL_MAX_ITER_MASK (0xff << 4)
341/* Receive NACK Inhibit */
342#define ASM9260_BM_ISO7816CTRL_INACK BIT(3)
343#define ASM9260_BM_ISO7816CTRL_NEG_DATA BIT(2)
344/* RW. 1 - ISO7816 mode; 0 - USART mode */
345#define ASM9260_BM_ISO7816CTRL_ENABLE BIT(0)
346
347#define ASM9260_HW_ISO7816_ERRCNT 0x00f0
348/* Parity error counter. Will be cleared after reading */
349#define ASM9260_BM_ISO7816_NB_ERRORS_MASK (0xff << 0)
350
351#define ASM9260_HW_ISO7816_STATUS 0x0100
352/* Max number of Repetitions Reached */
353#define ASM9260_BM_ISO7816_STAT_ITERATION BIT(0)
354
355/* End of Alphascale asm9260 defines */
356
357static struct uart_driver auart_driver;
358
359enum mxs_auart_type {
360 IMX23_AUART,
361 IMX28_AUART,
362 ASM9260_AUART,
363};
364
365struct vendor_data {
366 const u16 *reg_offset;
367};
368
369enum {
370 REG_CTRL0,
371 REG_CTRL1,
372 REG_CTRL2,
373 REG_LINECTRL,
374 REG_LINECTRL2,
375 REG_INTR,
376 REG_DATA,
377 REG_STAT,
378 REG_DEBUG,
379 REG_VERSION,
380 REG_AUTOBAUD,
381
382 /* The size of the array - must be last */
383 REG_ARRAY_SIZE,
384};
385
386static const u16 mxs_asm9260_offsets[REG_ARRAY_SIZE] = {
387 [REG_CTRL0] = ASM9260_HW_CTRL0,
388 [REG_CTRL1] = ASM9260_HW_CTRL1,
389 [REG_CTRL2] = ASM9260_HW_CTRL2,
390 [REG_LINECTRL] = ASM9260_HW_LINECTRL,
391 [REG_INTR] = ASM9260_HW_INTR,
392 [REG_DATA] = ASM9260_HW_DATA,
393 [REG_STAT] = ASM9260_HW_STAT,
394 [REG_DEBUG] = ASM9260_HW_DEBUG,
395 [REG_AUTOBAUD] = ASM9260_HW_AUTOBAUD,
396};
397
398static const u16 mxs_stmp37xx_offsets[REG_ARRAY_SIZE] = {
399 [REG_CTRL0] = AUART_CTRL0,
400 [REG_CTRL1] = AUART_CTRL1,
401 [REG_CTRL2] = AUART_CTRL2,
402 [REG_LINECTRL] = AUART_LINECTRL,
403 [REG_LINECTRL2] = AUART_LINECTRL2,
404 [REG_INTR] = AUART_INTR,
405 [REG_DATA] = AUART_DATA,
406 [REG_STAT] = AUART_STAT,
407 [REG_DEBUG] = AUART_DEBUG,
408 [REG_VERSION] = AUART_VERSION,
409 [REG_AUTOBAUD] = AUART_AUTOBAUD,
410};
411
412static const struct vendor_data vendor_alphascale_asm9260 = {
413 .reg_offset = mxs_asm9260_offsets,
414};
415
416static const struct vendor_data vendor_freescale_stmp37xx = {
417 .reg_offset = mxs_stmp37xx_offsets,
418};
419
420struct mxs_auart_port {
421 struct uart_port port;
422
423#define MXS_AUART_DMA_ENABLED 0x2
424#define MXS_AUART_DMA_TX_SYNC 2 /* bit 2 */
425#define MXS_AUART_DMA_RX_READY 3 /* bit 3 */
426#define MXS_AUART_RTSCTS 4 /* bit 4 */
427 unsigned long flags;
428 unsigned int mctrl_prev;
429 enum mxs_auart_type devtype;
430 const struct vendor_data *vendor;
431
432 struct clk *clk;
433 struct clk *clk_ahb;
434 struct device *dev;
435
436 /* for DMA */
437 struct scatterlist tx_sgl;
438 struct dma_chan *tx_dma_chan;
439 void *tx_dma_buf;
440
441 struct scatterlist rx_sgl;
442 struct dma_chan *rx_dma_chan;
443 void *rx_dma_buf;
444
445 struct mctrl_gpios *gpios;
446 int gpio_irq[UART_GPIO_MAX];
447 bool ms_irq_enabled;
448};
449
450static const struct platform_device_id mxs_auart_devtype[] = {
451 { .name = "mxs-auart-imx23", .driver_data = IMX23_AUART },
452 { .name = "mxs-auart-imx28", .driver_data = IMX28_AUART },
453 { .name = "as-auart-asm9260", .driver_data = ASM9260_AUART },
454 { /* sentinel */ }
455};
456MODULE_DEVICE_TABLE(platform, mxs_auart_devtype);
457
458static const struct of_device_id mxs_auart_dt_ids[] = {
459 {
460 .compatible = "fsl,imx28-auart",
461 .data = &mxs_auart_devtype[IMX28_AUART]
462 }, {
463 .compatible = "fsl,imx23-auart",
464 .data = &mxs_auart_devtype[IMX23_AUART]
465 }, {
466 .compatible = "alphascale,asm9260-auart",
467 .data = &mxs_auart_devtype[ASM9260_AUART]
468 }, { /* sentinel */ }
469};
470MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids);
471
472static inline int is_imx28_auart(struct mxs_auart_port *s)
473{
474 return s->devtype == IMX28_AUART;
475}
476
477static inline int is_asm9260_auart(struct mxs_auart_port *s)
478{
479 return s->devtype == ASM9260_AUART;
480}
481
482static inline bool auart_dma_enabled(struct mxs_auart_port *s)
483{
484 return s->flags & MXS_AUART_DMA_ENABLED;
485}
486
487static unsigned int mxs_reg_to_offset(const struct mxs_auart_port *uap,
488 unsigned int reg)
489{
490 return uap->vendor->reg_offset[reg];
491}
492
493static unsigned int mxs_read(const struct mxs_auart_port *uap,
494 unsigned int reg)
495{
496 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
497
498 return readl_relaxed(addr);
499}
500
501static void mxs_write(unsigned int val, struct mxs_auart_port *uap,
502 unsigned int reg)
503{
504 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
505
506 writel_relaxed(val, addr);
507}
508
509static void mxs_set(unsigned int val, struct mxs_auart_port *uap,
510 unsigned int reg)
511{
512 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
513
514 writel_relaxed(val, addr + SET_REG);
515}
516
517static void mxs_clr(unsigned int val, struct mxs_auart_port *uap,
518 unsigned int reg)
519{
520 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
521
522 writel_relaxed(val, addr + CLR_REG);
523}
524
525static void mxs_auart_stop_tx(struct uart_port *u);
526
527#define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
528
529static void mxs_auart_tx_chars(struct mxs_auart_port *s);
530
531static void dma_tx_callback(void *param)
532{
533 struct mxs_auart_port *s = param;
534 struct circ_buf *xmit = &s->port.state->xmit;
535
536 dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE);
537
538 /* clear the bit used to serialize the DMA tx. */
539 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
540 smp_mb__after_atomic();
541
542 /* wake up the possible processes. */
543 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
544 uart_write_wakeup(&s->port);
545
546 mxs_auart_tx_chars(s);
547}
548
549static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size)
550{
551 struct dma_async_tx_descriptor *desc;
552 struct scatterlist *sgl = &s->tx_sgl;
553 struct dma_chan *channel = s->tx_dma_chan;
554 u32 pio;
555
556 /* [1] : send PIO. Note, the first pio word is CTRL1. */
557 pio = AUART_CTRL1_XFER_COUNT(size);
558 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)&pio,
559 1, DMA_TRANS_NONE, 0);
560 if (!desc) {
561 dev_err(s->dev, "step 1 error\n");
562 return -EINVAL;
563 }
564
565 /* [2] : set DMA buffer. */
566 sg_init_one(sgl, s->tx_dma_buf, size);
567 dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE);
568 desc = dmaengine_prep_slave_sg(channel, sgl,
569 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
570 if (!desc) {
571 dev_err(s->dev, "step 2 error\n");
572 return -EINVAL;
573 }
574
575 /* [3] : submit the DMA */
576 desc->callback = dma_tx_callback;
577 desc->callback_param = s;
578 dmaengine_submit(desc);
579 dma_async_issue_pending(channel);
580 return 0;
581}
582
583static void mxs_auart_tx_chars(struct mxs_auart_port *s)
584{
585 struct circ_buf *xmit = &s->port.state->xmit;
586
587 if (auart_dma_enabled(s)) {
588 u32 i = 0;
589 int size;
590 void *buffer = s->tx_dma_buf;
591
592 if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, &s->flags))
593 return;
594
595 while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
596 size = min_t(u32, UART_XMIT_SIZE - i,
597 CIRC_CNT_TO_END(xmit->head,
598 xmit->tail,
599 UART_XMIT_SIZE));
600 memcpy(buffer + i, xmit->buf + xmit->tail, size);
601 xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1);
602
603 i += size;
604 if (i >= UART_XMIT_SIZE)
605 break;
606 }
607
608 if (uart_tx_stopped(&s->port))
609 mxs_auart_stop_tx(&s->port);
610
611 if (i) {
612 mxs_auart_dma_tx(s, i);
613 } else {
614 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
615 smp_mb__after_atomic();
616 }
617 return;
618 }
619
620
621 while (!(mxs_read(s, REG_STAT) & AUART_STAT_TXFF)) {
622 if (s->port.x_char) {
623 s->port.icount.tx++;
624 mxs_write(s->port.x_char, s, REG_DATA);
625 s->port.x_char = 0;
626 continue;
627 }
628 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
629 s->port.icount.tx++;
630 mxs_write(xmit->buf[xmit->tail], s, REG_DATA);
631 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
632 } else
633 break;
634 }
635 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
636 uart_write_wakeup(&s->port);
637
638 if (uart_circ_empty(&(s->port.state->xmit)))
639 mxs_clr(AUART_INTR_TXIEN, s, REG_INTR);
640 else
641 mxs_set(AUART_INTR_TXIEN, s, REG_INTR);
642
643 if (uart_tx_stopped(&s->port))
644 mxs_auart_stop_tx(&s->port);
645}
646
647static void mxs_auart_rx_char(struct mxs_auart_port *s)
648{
649 int flag;
650 u32 stat;
651 u8 c;
652
653 c = mxs_read(s, REG_DATA);
654 stat = mxs_read(s, REG_STAT);
655
656 flag = TTY_NORMAL;
657 s->port.icount.rx++;
658
659 if (stat & AUART_STAT_BERR) {
660 s->port.icount.brk++;
661 if (uart_handle_break(&s->port))
662 goto out;
663 } else if (stat & AUART_STAT_PERR) {
664 s->port.icount.parity++;
665 } else if (stat & AUART_STAT_FERR) {
666 s->port.icount.frame++;
667 }
668
669 /*
670 * Mask off conditions which should be ingored.
671 */
672 stat &= s->port.read_status_mask;
673
674 if (stat & AUART_STAT_BERR) {
675 flag = TTY_BREAK;
676 } else if (stat & AUART_STAT_PERR)
677 flag = TTY_PARITY;
678 else if (stat & AUART_STAT_FERR)
679 flag = TTY_FRAME;
680
681 if (stat & AUART_STAT_OERR)
682 s->port.icount.overrun++;
683
684 if (uart_handle_sysrq_char(&s->port, c))
685 goto out;
686
687 uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
688out:
689 mxs_write(stat, s, REG_STAT);
690}
691
692static void mxs_auart_rx_chars(struct mxs_auart_port *s)
693{
694 u32 stat = 0;
695
696 for (;;) {
697 stat = mxs_read(s, REG_STAT);
698 if (stat & AUART_STAT_RXFE)
699 break;
700 mxs_auart_rx_char(s);
701 }
702
703 mxs_write(stat, s, REG_STAT);
704 tty_flip_buffer_push(&s->port.state->port);
705}
706
707static int mxs_auart_request_port(struct uart_port *u)
708{
709 return 0;
710}
711
712static int mxs_auart_verify_port(struct uart_port *u,
713 struct serial_struct *ser)
714{
715 if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
716 return -EINVAL;
717 return 0;
718}
719
720static void mxs_auart_config_port(struct uart_port *u, int flags)
721{
722}
723
724static const char *mxs_auart_type(struct uart_port *u)
725{
726 struct mxs_auart_port *s = to_auart_port(u);
727
728 return dev_name(s->dev);
729}
730
731static void mxs_auart_release_port(struct uart_port *u)
732{
733}
734
735static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
736{
737 struct mxs_auart_port *s = to_auart_port(u);
738
739 u32 ctrl = mxs_read(s, REG_CTRL2);
740
741 ctrl &= ~(AUART_CTRL2_RTSEN | AUART_CTRL2_RTS);
742 if (mctrl & TIOCM_RTS) {
743 if (uart_cts_enabled(u))
744 ctrl |= AUART_CTRL2_RTSEN;
745 else
746 ctrl |= AUART_CTRL2_RTS;
747 }
748
749 mxs_write(ctrl, s, REG_CTRL2);
750
751 mctrl_gpio_set(s->gpios, mctrl);
752}
753
754#define MCTRL_ANY_DELTA (TIOCM_RI | TIOCM_DSR | TIOCM_CD | TIOCM_CTS)
755static u32 mxs_auart_modem_status(struct mxs_auart_port *s, u32 mctrl)
756{
757 u32 mctrl_diff;
758
759 mctrl_diff = mctrl ^ s->mctrl_prev;
760 s->mctrl_prev = mctrl;
761 if (mctrl_diff & MCTRL_ANY_DELTA && s->ms_irq_enabled &&
762 s->port.state != NULL) {
763 if (mctrl_diff & TIOCM_RI)
764 s->port.icount.rng++;
765 if (mctrl_diff & TIOCM_DSR)
766 s->port.icount.dsr++;
767 if (mctrl_diff & TIOCM_CD)
768 uart_handle_dcd_change(&s->port, mctrl & TIOCM_CD);
769 if (mctrl_diff & TIOCM_CTS)
770 uart_handle_cts_change(&s->port, mctrl & TIOCM_CTS);
771
772 wake_up_interruptible(&s->port.state->port.delta_msr_wait);
773 }
774 return mctrl;
775}
776
777static u32 mxs_auart_get_mctrl(struct uart_port *u)
778{
779 struct mxs_auart_port *s = to_auart_port(u);
780 u32 stat = mxs_read(s, REG_STAT);
781 u32 mctrl = 0;
782
783 if (stat & AUART_STAT_CTS)
784 mctrl |= TIOCM_CTS;
785
786 return mctrl_gpio_get(s->gpios, &mctrl);
787}
788
789/*
790 * Enable modem status interrupts
791 */
792static void mxs_auart_enable_ms(struct uart_port *port)
793{
794 struct mxs_auart_port *s = to_auart_port(port);
795
796 /*
797 * Interrupt should not be enabled twice
798 */
799 if (s->ms_irq_enabled)
800 return;
801
802 s->ms_irq_enabled = true;
803
804 if (s->gpio_irq[UART_GPIO_CTS] >= 0)
805 enable_irq(s->gpio_irq[UART_GPIO_CTS]);
806 /* TODO: enable AUART_INTR_CTSMIEN otherwise */
807
808 if (s->gpio_irq[UART_GPIO_DSR] >= 0)
809 enable_irq(s->gpio_irq[UART_GPIO_DSR]);
810
811 if (s->gpio_irq[UART_GPIO_RI] >= 0)
812 enable_irq(s->gpio_irq[UART_GPIO_RI]);
813
814 if (s->gpio_irq[UART_GPIO_DCD] >= 0)
815 enable_irq(s->gpio_irq[UART_GPIO_DCD]);
816}
817
818/*
819 * Disable modem status interrupts
820 */
821static void mxs_auart_disable_ms(struct uart_port *port)
822{
823 struct mxs_auart_port *s = to_auart_port(port);
824
825 /*
826 * Interrupt should not be disabled twice
827 */
828 if (!s->ms_irq_enabled)
829 return;
830
831 s->ms_irq_enabled = false;
832
833 if (s->gpio_irq[UART_GPIO_CTS] >= 0)
834 disable_irq(s->gpio_irq[UART_GPIO_CTS]);
835 /* TODO: disable AUART_INTR_CTSMIEN otherwise */
836
837 if (s->gpio_irq[UART_GPIO_DSR] >= 0)
838 disable_irq(s->gpio_irq[UART_GPIO_DSR]);
839
840 if (s->gpio_irq[UART_GPIO_RI] >= 0)
841 disable_irq(s->gpio_irq[UART_GPIO_RI]);
842
843 if (s->gpio_irq[UART_GPIO_DCD] >= 0)
844 disable_irq(s->gpio_irq[UART_GPIO_DCD]);
845}
846
847static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s);
848static void dma_rx_callback(void *arg)
849{
850 struct mxs_auart_port *s = (struct mxs_auart_port *) arg;
851 struct tty_port *port = &s->port.state->port;
852 int count;
853 u32 stat;
854
855 dma_unmap_sg(s->dev, &s->rx_sgl, 1, DMA_FROM_DEVICE);
856
857 stat = mxs_read(s, REG_STAT);
858 stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR |
859 AUART_STAT_PERR | AUART_STAT_FERR);
860
861 count = stat & AUART_STAT_RXCOUNT_MASK;
862 tty_insert_flip_string(port, s->rx_dma_buf, count);
863
864 mxs_write(stat, s, REG_STAT);
865 tty_flip_buffer_push(port);
866
867 /* start the next DMA for RX. */
868 mxs_auart_dma_prep_rx(s);
869}
870
871static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s)
872{
873 struct dma_async_tx_descriptor *desc;
874 struct scatterlist *sgl = &s->rx_sgl;
875 struct dma_chan *channel = s->rx_dma_chan;
876 u32 pio[1];
877
878 /* [1] : send PIO */
879 pio[0] = AUART_CTRL0_RXTO_ENABLE
880 | AUART_CTRL0_RXTIMEOUT(0x80)
881 | AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE);
882 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
883 1, DMA_TRANS_NONE, 0);
884 if (!desc) {
885 dev_err(s->dev, "step 1 error\n");
886 return -EINVAL;
887 }
888
889 /* [2] : send DMA request */
890 sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE);
891 dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE);
892 desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_DEV_TO_MEM,
893 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
894 if (!desc) {
895 dev_err(s->dev, "step 2 error\n");
896 return -1;
897 }
898
899 /* [3] : submit the DMA, but do not issue it. */
900 desc->callback = dma_rx_callback;
901 desc->callback_param = s;
902 dmaengine_submit(desc);
903 dma_async_issue_pending(channel);
904 return 0;
905}
906
907static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s)
908{
909 if (s->tx_dma_chan) {
910 dma_release_channel(s->tx_dma_chan);
911 s->tx_dma_chan = NULL;
912 }
913 if (s->rx_dma_chan) {
914 dma_release_channel(s->rx_dma_chan);
915 s->rx_dma_chan = NULL;
916 }
917
918 kfree(s->tx_dma_buf);
919 kfree(s->rx_dma_buf);
920 s->tx_dma_buf = NULL;
921 s->rx_dma_buf = NULL;
922}
923
924static void mxs_auart_dma_exit(struct mxs_auart_port *s)
925{
926
927 mxs_clr(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR,
928 s, REG_CTRL2);
929
930 mxs_auart_dma_exit_channel(s);
931 s->flags &= ~MXS_AUART_DMA_ENABLED;
932 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
933 clear_bit(MXS_AUART_DMA_RX_READY, &s->flags);
934}
935
936static int mxs_auart_dma_init(struct mxs_auart_port *s)
937{
938 if (auart_dma_enabled(s))
939 return 0;
940
941 /* init for RX */
942 s->rx_dma_chan = dma_request_slave_channel(s->dev, "rx");
943 if (!s->rx_dma_chan)
944 goto err_out;
945 s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
946 if (!s->rx_dma_buf)
947 goto err_out;
948
949 /* init for TX */
950 s->tx_dma_chan = dma_request_slave_channel(s->dev, "tx");
951 if (!s->tx_dma_chan)
952 goto err_out;
953 s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
954 if (!s->tx_dma_buf)
955 goto err_out;
956
957 /* set the flags */
958 s->flags |= MXS_AUART_DMA_ENABLED;
959 dev_dbg(s->dev, "enabled the DMA support.");
960
961 /* The DMA buffer is now the FIFO the TTY subsystem can use */
962 s->port.fifosize = UART_XMIT_SIZE;
963
964 return 0;
965
966err_out:
967 mxs_auart_dma_exit_channel(s);
968 return -EINVAL;
969
970}
971
972#define RTS_AT_AUART() !mctrl_gpio_to_gpiod(s->gpios, UART_GPIO_RTS)
973#define CTS_AT_AUART() !mctrl_gpio_to_gpiod(s->gpios, UART_GPIO_CTS)
974static void mxs_auart_settermios(struct uart_port *u,
975 struct ktermios *termios,
976 struct ktermios *old)
977{
978 struct mxs_auart_port *s = to_auart_port(u);
979 u32 bm, ctrl, ctrl2, div;
980 unsigned int cflag, baud, baud_min, baud_max;
981
982 cflag = termios->c_cflag;
983
984 ctrl = AUART_LINECTRL_FEN;
985 ctrl2 = mxs_read(s, REG_CTRL2);
986
987 /* byte size */
988 switch (cflag & CSIZE) {
989 case CS5:
990 bm = 0;
991 break;
992 case CS6:
993 bm = 1;
994 break;
995 case CS7:
996 bm = 2;
997 break;
998 case CS8:
999 bm = 3;
1000 break;
1001 default:
1002 return;
1003 }
1004
1005 ctrl |= AUART_LINECTRL_WLEN(bm);
1006
1007 /* parity */
1008 if (cflag & PARENB) {
1009 ctrl |= AUART_LINECTRL_PEN;
1010 if ((cflag & PARODD) == 0)
1011 ctrl |= AUART_LINECTRL_EPS;
1012 if (cflag & CMSPAR)
1013 ctrl |= AUART_LINECTRL_SPS;
1014 }
1015
1016 u->read_status_mask = AUART_STAT_OERR;
1017
1018 if (termios->c_iflag & INPCK)
1019 u->read_status_mask |= AUART_STAT_PERR;
1020 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1021 u->read_status_mask |= AUART_STAT_BERR;
1022
1023 /*
1024 * Characters to ignore
1025 */
1026 u->ignore_status_mask = 0;
1027 if (termios->c_iflag & IGNPAR)
1028 u->ignore_status_mask |= AUART_STAT_PERR;
1029 if (termios->c_iflag & IGNBRK) {
1030 u->ignore_status_mask |= AUART_STAT_BERR;
1031 /*
1032 * If we're ignoring parity and break indicators,
1033 * ignore overruns too (for real raw support).
1034 */
1035 if (termios->c_iflag & IGNPAR)
1036 u->ignore_status_mask |= AUART_STAT_OERR;
1037 }
1038
1039 /*
1040 * ignore all characters if CREAD is not set
1041 */
1042 if (cflag & CREAD)
1043 ctrl2 |= AUART_CTRL2_RXE;
1044 else
1045 ctrl2 &= ~AUART_CTRL2_RXE;
1046
1047 /* figure out the stop bits requested */
1048 if (cflag & CSTOPB)
1049 ctrl |= AUART_LINECTRL_STP2;
1050
1051 /* figure out the hardware flow control settings */
1052 ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN);
1053 if (cflag & CRTSCTS) {
1054 /*
1055 * The DMA has a bug(see errata:2836) in mx23.
1056 * So we can not implement the DMA for auart in mx23,
1057 * we can only implement the DMA support for auart
1058 * in mx28.
1059 */
1060 if (is_imx28_auart(s)
1061 && test_bit(MXS_AUART_RTSCTS, &s->flags)) {
1062 if (!mxs_auart_dma_init(s))
1063 /* enable DMA tranfer */
1064 ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE
1065 | AUART_CTRL2_DMAONERR;
1066 }
1067 /* Even if RTS is GPIO line RTSEN can be enabled because
1068 * the pinctrl configuration decides about RTS pin function */
1069 ctrl2 |= AUART_CTRL2_RTSEN;
1070 if (CTS_AT_AUART())
1071 ctrl2 |= AUART_CTRL2_CTSEN;
1072 }
1073
1074 /* set baud rate */
1075 if (is_asm9260_auart(s)) {
1076 baud = uart_get_baud_rate(u, termios, old,
1077 u->uartclk * 4 / 0x3FFFFF,
1078 u->uartclk / 16);
1079 div = u->uartclk * 4 / baud;
1080 } else {
1081 baud_min = DIV_ROUND_UP(u->uartclk * 32,
1082 AUART_LINECTRL_BAUD_DIV_MAX);
1083 baud_max = u->uartclk * 32 / AUART_LINECTRL_BAUD_DIV_MIN;
1084 baud = uart_get_baud_rate(u, termios, old, baud_min, baud_max);
1085 div = DIV_ROUND_CLOSEST(u->uartclk * 32, baud);
1086 }
1087
1088 ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
1089 ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
1090 mxs_write(ctrl, s, REG_LINECTRL);
1091
1092 mxs_write(ctrl2, s, REG_CTRL2);
1093
1094 uart_update_timeout(u, termios->c_cflag, baud);
1095
1096 /* prepare for the DMA RX. */
1097 if (auart_dma_enabled(s) &&
1098 !test_and_set_bit(MXS_AUART_DMA_RX_READY, &s->flags)) {
1099 if (!mxs_auart_dma_prep_rx(s)) {
1100 /* Disable the normal RX interrupt. */
1101 mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN,
1102 s, REG_INTR);
1103 } else {
1104 mxs_auart_dma_exit(s);
1105 dev_err(s->dev, "We can not start up the DMA.\n");
1106 }
1107 }
1108
1109 /* CTS flow-control and modem-status interrupts */
1110 if (UART_ENABLE_MS(u, termios->c_cflag))
1111 mxs_auart_enable_ms(u);
1112 else
1113 mxs_auart_disable_ms(u);
1114}
1115
1116static void mxs_auart_set_ldisc(struct uart_port *port,
1117 struct ktermios *termios)
1118{
1119 if (termios->c_line == N_PPS) {
1120 port->flags |= UPF_HARDPPS_CD;
1121 mxs_auart_enable_ms(port);
1122 } else {
1123 port->flags &= ~UPF_HARDPPS_CD;
1124 }
1125}
1126
1127static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
1128{
1129 u32 istat;
1130 struct mxs_auart_port *s = context;
1131 u32 mctrl_temp = s->mctrl_prev;
1132 u32 stat = mxs_read(s, REG_STAT);
1133
1134 istat = mxs_read(s, REG_INTR);
1135
1136 /* ack irq */
1137 mxs_clr(istat & (AUART_INTR_RTIS | AUART_INTR_TXIS | AUART_INTR_RXIS
1138 | AUART_INTR_CTSMIS), s, REG_INTR);
1139
1140 /*
1141 * Dealing with GPIO interrupt
1142 */
1143 if (irq == s->gpio_irq[UART_GPIO_CTS] ||
1144 irq == s->gpio_irq[UART_GPIO_DCD] ||
1145 irq == s->gpio_irq[UART_GPIO_DSR] ||
1146 irq == s->gpio_irq[UART_GPIO_RI])
1147 mxs_auart_modem_status(s,
1148 mctrl_gpio_get(s->gpios, &mctrl_temp));
1149
1150 if (istat & AUART_INTR_CTSMIS) {
1151 if (CTS_AT_AUART() && s->ms_irq_enabled)
1152 uart_handle_cts_change(&s->port,
1153 stat & AUART_STAT_CTS);
1154 mxs_clr(AUART_INTR_CTSMIS, s, REG_INTR);
1155 istat &= ~AUART_INTR_CTSMIS;
1156 }
1157
1158 if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
1159 if (!auart_dma_enabled(s))
1160 mxs_auart_rx_chars(s);
1161 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
1162 }
1163
1164 if (istat & AUART_INTR_TXIS) {
1165 mxs_auart_tx_chars(s);
1166 istat &= ~AUART_INTR_TXIS;
1167 }
1168
1169 return IRQ_HANDLED;
1170}
1171
1172static void mxs_auart_reset_deassert(struct mxs_auart_port *s)
1173{
1174 int i;
1175 unsigned int reg;
1176
1177 mxs_clr(AUART_CTRL0_SFTRST, s, REG_CTRL0);
1178
1179 for (i = 0; i < 10000; i++) {
1180 reg = mxs_read(s, REG_CTRL0);
1181 if (!(reg & AUART_CTRL0_SFTRST))
1182 break;
1183 udelay(3);
1184 }
1185 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1186}
1187
1188static void mxs_auart_reset_assert(struct mxs_auart_port *s)
1189{
1190 int i;
1191 u32 reg;
1192
1193 reg = mxs_read(s, REG_CTRL0);
1194 /* if already in reset state, keep it untouched */
1195 if (reg & AUART_CTRL0_SFTRST)
1196 return;
1197
1198 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1199 mxs_set(AUART_CTRL0_SFTRST, s, REG_CTRL0);
1200
1201 for (i = 0; i < 1000; i++) {
1202 reg = mxs_read(s, REG_CTRL0);
1203 /* reset is finished when the clock is gated */
1204 if (reg & AUART_CTRL0_CLKGATE)
1205 return;
1206 udelay(10);
1207 }
1208
1209 dev_err(s->dev, "Failed to reset the unit.");
1210}
1211
1212static int mxs_auart_startup(struct uart_port *u)
1213{
1214 int ret;
1215 struct mxs_auart_port *s = to_auart_port(u);
1216
1217 ret = clk_prepare_enable(s->clk);
1218 if (ret)
1219 return ret;
1220
1221 if (uart_console(u)) {
1222 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1223 } else {
1224 /* reset the unit to a well known state */
1225 mxs_auart_reset_assert(s);
1226 mxs_auart_reset_deassert(s);
1227 }
1228
1229 mxs_set(AUART_CTRL2_UARTEN, s, REG_CTRL2);
1230
1231 mxs_write(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
1232 s, REG_INTR);
1233
1234 /* Reset FIFO size (it could have changed if DMA was enabled) */
1235 u->fifosize = MXS_AUART_FIFO_SIZE;
1236
1237 /*
1238 * Enable fifo so all four bytes of a DMA word are written to
1239 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
1240 */
1241 mxs_set(AUART_LINECTRL_FEN, s, REG_LINECTRL);
1242
1243 /* get initial status of modem lines */
1244 mctrl_gpio_get(s->gpios, &s->mctrl_prev);
1245
1246 s->ms_irq_enabled = false;
1247 return 0;
1248}
1249
1250static void mxs_auart_shutdown(struct uart_port *u)
1251{
1252 struct mxs_auart_port *s = to_auart_port(u);
1253
1254 mxs_auart_disable_ms(u);
1255
1256 if (auart_dma_enabled(s))
1257 mxs_auart_dma_exit(s);
1258
1259 if (uart_console(u)) {
1260 mxs_clr(AUART_CTRL2_UARTEN, s, REG_CTRL2);
1261
1262 mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN |
1263 AUART_INTR_CTSMIEN, s, REG_INTR);
1264 mxs_set(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1265 } else {
1266 mxs_auart_reset_assert(s);
1267 }
1268
1269 clk_disable_unprepare(s->clk);
1270}
1271
1272static unsigned int mxs_auart_tx_empty(struct uart_port *u)
1273{
1274 struct mxs_auart_port *s = to_auart_port(u);
1275
1276 if ((mxs_read(s, REG_STAT) &
1277 (AUART_STAT_TXFE | AUART_STAT_BUSY)) == AUART_STAT_TXFE)
1278 return TIOCSER_TEMT;
1279
1280 return 0;
1281}
1282
1283static void mxs_auart_start_tx(struct uart_port *u)
1284{
1285 struct mxs_auart_port *s = to_auart_port(u);
1286
1287 /* enable transmitter */
1288 mxs_set(AUART_CTRL2_TXE, s, REG_CTRL2);
1289
1290 mxs_auart_tx_chars(s);
1291}
1292
1293static void mxs_auart_stop_tx(struct uart_port *u)
1294{
1295 struct mxs_auart_port *s = to_auart_port(u);
1296
1297 mxs_clr(AUART_CTRL2_TXE, s, REG_CTRL2);
1298}
1299
1300static void mxs_auart_stop_rx(struct uart_port *u)
1301{
1302 struct mxs_auart_port *s = to_auart_port(u);
1303
1304 mxs_clr(AUART_CTRL2_RXE, s, REG_CTRL2);
1305}
1306
1307static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
1308{
1309 struct mxs_auart_port *s = to_auart_port(u);
1310
1311 if (ctl)
1312 mxs_set(AUART_LINECTRL_BRK, s, REG_LINECTRL);
1313 else
1314 mxs_clr(AUART_LINECTRL_BRK, s, REG_LINECTRL);
1315}
1316
1317static const struct uart_ops mxs_auart_ops = {
1318 .tx_empty = mxs_auart_tx_empty,
1319 .start_tx = mxs_auart_start_tx,
1320 .stop_tx = mxs_auart_stop_tx,
1321 .stop_rx = mxs_auart_stop_rx,
1322 .enable_ms = mxs_auart_enable_ms,
1323 .break_ctl = mxs_auart_break_ctl,
1324 .set_mctrl = mxs_auart_set_mctrl,
1325 .get_mctrl = mxs_auart_get_mctrl,
1326 .startup = mxs_auart_startup,
1327 .shutdown = mxs_auart_shutdown,
1328 .set_termios = mxs_auart_settermios,
1329 .set_ldisc = mxs_auart_set_ldisc,
1330 .type = mxs_auart_type,
1331 .release_port = mxs_auart_release_port,
1332 .request_port = mxs_auart_request_port,
1333 .config_port = mxs_auart_config_port,
1334 .verify_port = mxs_auart_verify_port,
1335};
1336
1337static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
1338
1339#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
1340static void mxs_auart_console_putchar(struct uart_port *port, int ch)
1341{
1342 struct mxs_auart_port *s = to_auart_port(port);
1343 unsigned int to = 1000;
1344
1345 while (mxs_read(s, REG_STAT) & AUART_STAT_TXFF) {
1346 if (!to--)
1347 break;
1348 udelay(1);
1349 }
1350
1351 mxs_write(ch, s, REG_DATA);
1352}
1353
1354static void
1355auart_console_write(struct console *co, const char *str, unsigned int count)
1356{
1357 struct mxs_auart_port *s;
1358 struct uart_port *port;
1359 unsigned int old_ctrl0, old_ctrl2;
1360 unsigned int to = 20000;
1361
1362 if (co->index >= MXS_AUART_PORTS || co->index < 0)
1363 return;
1364
1365 s = auart_port[co->index];
1366 port = &s->port;
1367
1368 clk_enable(s->clk);
1369
1370 /* First save the CR then disable the interrupts */
1371 old_ctrl2 = mxs_read(s, REG_CTRL2);
1372 old_ctrl0 = mxs_read(s, REG_CTRL0);
1373
1374 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1375 mxs_set(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE, s, REG_CTRL2);
1376
1377 uart_console_write(port, str, count, mxs_auart_console_putchar);
1378
1379 /* Finally, wait for transmitter to become empty ... */
1380 while (mxs_read(s, REG_STAT) & AUART_STAT_BUSY) {
1381 udelay(1);
1382 if (!to--)
1383 break;
1384 }
1385
1386 /*
1387 * ... and restore the TCR if we waited long enough for the transmitter
1388 * to be idle. This might keep the transmitter enabled although it is
1389 * unused, but that is better than to disable it while it is still
1390 * transmitting.
1391 */
1392 if (!(mxs_read(s, REG_STAT) & AUART_STAT_BUSY)) {
1393 mxs_write(old_ctrl0, s, REG_CTRL0);
1394 mxs_write(old_ctrl2, s, REG_CTRL2);
1395 }
1396
1397 clk_disable(s->clk);
1398}
1399
1400static void __init
1401auart_console_get_options(struct mxs_auart_port *s, int *baud,
1402 int *parity, int *bits)
1403{
1404 struct uart_port *port = &s->port;
1405 unsigned int lcr_h, quot;
1406
1407 if (!(mxs_read(s, REG_CTRL2) & AUART_CTRL2_UARTEN))
1408 return;
1409
1410 lcr_h = mxs_read(s, REG_LINECTRL);
1411
1412 *parity = 'n';
1413 if (lcr_h & AUART_LINECTRL_PEN) {
1414 if (lcr_h & AUART_LINECTRL_EPS)
1415 *parity = 'e';
1416 else
1417 *parity = 'o';
1418 }
1419
1420 if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2))
1421 *bits = 7;
1422 else
1423 *bits = 8;
1424
1425 quot = ((mxs_read(s, REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVINT_MASK))
1426 >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
1427 quot |= ((mxs_read(s, REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVFRAC_MASK))
1428 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
1429 if (quot == 0)
1430 quot = 1;
1431
1432 *baud = (port->uartclk << 2) / quot;
1433}
1434
1435static int __init
1436auart_console_setup(struct console *co, char *options)
1437{
1438 struct mxs_auart_port *s;
1439 int baud = 9600;
1440 int bits = 8;
1441 int parity = 'n';
1442 int flow = 'n';
1443 int ret;
1444
1445 /*
1446 * Check whether an invalid uart number has been specified, and
1447 * if so, search for the first available port that does have
1448 * console support.
1449 */
1450 if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
1451 co->index = 0;
1452 s = auart_port[co->index];
1453 if (!s)
1454 return -ENODEV;
1455
1456 ret = clk_prepare_enable(s->clk);
1457 if (ret)
1458 return ret;
1459
1460 if (options)
1461 uart_parse_options(options, &baud, &parity, &bits, &flow);
1462 else
1463 auart_console_get_options(s, &baud, &parity, &bits);
1464
1465 ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
1466
1467 clk_disable_unprepare(s->clk);
1468
1469 return ret;
1470}
1471
1472static struct console auart_console = {
1473 .name = "ttyAPP",
1474 .write = auart_console_write,
1475 .device = uart_console_device,
1476 .setup = auart_console_setup,
1477 .flags = CON_PRINTBUFFER,
1478 .index = -1,
1479 .data = &auart_driver,
1480};
1481#endif
1482
1483static struct uart_driver auart_driver = {
1484 .owner = THIS_MODULE,
1485 .driver_name = "ttyAPP",
1486 .dev_name = "ttyAPP",
1487 .major = 0,
1488 .minor = 0,
1489 .nr = MXS_AUART_PORTS,
1490#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
1491 .cons = &auart_console,
1492#endif
1493};
1494
1495static void mxs_init_regs(struct mxs_auart_port *s)
1496{
1497 if (is_asm9260_auart(s))
1498 s->vendor = &vendor_alphascale_asm9260;
1499 else
1500 s->vendor = &vendor_freescale_stmp37xx;
1501}
1502
1503static int mxs_get_clks(struct mxs_auart_port *s,
1504 struct platform_device *pdev)
1505{
1506 int err;
1507
1508 if (!is_asm9260_auart(s)) {
1509 s->clk = devm_clk_get(&pdev->dev, NULL);
1510 return PTR_ERR_OR_ZERO(s->clk);
1511 }
1512
1513 s->clk = devm_clk_get(s->dev, "mod");
1514 if (IS_ERR(s->clk)) {
1515 dev_err(s->dev, "Failed to get \"mod\" clk\n");
1516 return PTR_ERR(s->clk);
1517 }
1518
1519 s->clk_ahb = devm_clk_get(s->dev, "ahb");
1520 if (IS_ERR(s->clk_ahb)) {
1521 dev_err(s->dev, "Failed to get \"ahb\" clk\n");
1522 return PTR_ERR(s->clk_ahb);
1523 }
1524
1525 err = clk_prepare_enable(s->clk_ahb);
1526 if (err) {
1527 dev_err(s->dev, "Failed to enable ahb_clk!\n");
1528 return err;
1529 }
1530
1531 err = clk_set_rate(s->clk, clk_get_rate(s->clk_ahb));
1532 if (err) {
1533 dev_err(s->dev, "Failed to set rate!\n");
1534 goto disable_clk_ahb;
1535 }
1536
1537 err = clk_prepare_enable(s->clk);
1538 if (err) {
1539 dev_err(s->dev, "Failed to enable clk!\n");
1540 goto disable_clk_ahb;
1541 }
1542
1543 return 0;
1544
1545disable_clk_ahb:
1546 clk_disable_unprepare(s->clk_ahb);
1547 return err;
1548}
1549
1550/*
1551 * This function returns 1 if pdev isn't a device instatiated by dt, 0 if it
1552 * could successfully get all information from dt or a negative errno.
1553 */
1554static int serial_mxs_probe_dt(struct mxs_auart_port *s,
1555 struct platform_device *pdev)
1556{
1557 struct device_node *np = pdev->dev.of_node;
1558 int ret;
1559
1560 if (!np)
1561 /* no device tree device */
1562 return 1;
1563
1564 ret = of_alias_get_id(np, "serial");
1565 if (ret < 0) {
1566 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);
1567 return ret;
1568 }
1569 s->port.line = ret;
1570
1571 if (of_get_property(np, "uart-has-rtscts", NULL) ||
1572 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
1573 set_bit(MXS_AUART_RTSCTS, &s->flags);
1574
1575 return 0;
1576}
1577
1578static int mxs_auart_init_gpios(struct mxs_auart_port *s, struct device *dev)
1579{
1580 enum mctrl_gpio_idx i;
1581 struct gpio_desc *gpiod;
1582
1583 s->gpios = mctrl_gpio_init_noauto(dev, 0);
1584 if (IS_ERR(s->gpios))
1585 return PTR_ERR(s->gpios);
1586
1587 /* Block (enabled before) DMA option if RTS or CTS is GPIO line */
1588 if (!RTS_AT_AUART() || !CTS_AT_AUART()) {
1589 if (test_bit(MXS_AUART_RTSCTS, &s->flags))
1590 dev_warn(dev,
1591 "DMA and flow control via gpio may cause some problems. DMA disabled!\n");
1592 clear_bit(MXS_AUART_RTSCTS, &s->flags);
1593 }
1594
1595 for (i = 0; i < UART_GPIO_MAX; i++) {
1596 gpiod = mctrl_gpio_to_gpiod(s->gpios, i);
1597 if (gpiod && (gpiod_get_direction(gpiod) == 1))
1598 s->gpio_irq[i] = gpiod_to_irq(gpiod);
1599 else
1600 s->gpio_irq[i] = -EINVAL;
1601 }
1602
1603 return 0;
1604}
1605
1606static void mxs_auart_free_gpio_irq(struct mxs_auart_port *s)
1607{
1608 enum mctrl_gpio_idx i;
1609
1610 for (i = 0; i < UART_GPIO_MAX; i++)
1611 if (s->gpio_irq[i] >= 0)
1612 free_irq(s->gpio_irq[i], s);
1613}
1614
1615static int mxs_auart_request_gpio_irq(struct mxs_auart_port *s)
1616{
1617 int *irq = s->gpio_irq;
1618 enum mctrl_gpio_idx i;
1619 int err = 0;
1620
1621 for (i = 0; (i < UART_GPIO_MAX) && !err; i++) {
1622 if (irq[i] < 0)
1623 continue;
1624
1625 irq_set_status_flags(irq[i], IRQ_NOAUTOEN);
1626 err = request_irq(irq[i], mxs_auart_irq_handle,
1627 IRQ_TYPE_EDGE_BOTH, dev_name(s->dev), s);
1628 if (err)
1629 dev_err(s->dev, "%s - Can't get %d irq\n",
1630 __func__, irq[i]);
1631 }
1632
1633 /*
1634 * If something went wrong, rollback.
1635 * Be careful: i may be unsigned.
1636 */
1637 while (err && (i-- > 0))
1638 if (irq[i] >= 0)
1639 free_irq(irq[i], s);
1640
1641 return err;
1642}
1643
1644static int mxs_auart_probe(struct platform_device *pdev)
1645{
1646 const struct of_device_id *of_id =
1647 of_match_device(mxs_auart_dt_ids, &pdev->dev);
1648 struct mxs_auart_port *s;
1649 u32 version;
1650 int ret, irq;
1651 struct resource *r;
1652
1653 s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL);
1654 if (!s)
1655 return -ENOMEM;
1656
1657 s->port.dev = &pdev->dev;
1658 s->dev = &pdev->dev;
1659
1660 ret = serial_mxs_probe_dt(s, pdev);
1661 if (ret > 0)
1662 s->port.line = pdev->id < 0 ? 0 : pdev->id;
1663 else if (ret < 0)
1664 return ret;
1665 if (s->port.line >= ARRAY_SIZE(auart_port)) {
1666 dev_err(&pdev->dev, "serial%d out of range\n", s->port.line);
1667 return -EINVAL;
1668 }
1669
1670 if (of_id) {
1671 pdev->id_entry = of_id->data;
1672 s->devtype = pdev->id_entry->driver_data;
1673 }
1674
1675 ret = mxs_get_clks(s, pdev);
1676 if (ret)
1677 return ret;
1678
1679 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1680 if (!r) {
1681 ret = -ENXIO;
1682 goto out_disable_clks;
1683 }
1684
1685 s->port.mapbase = r->start;
1686 s->port.membase = ioremap(r->start, resource_size(r));
1687 if (!s->port.membase) {
1688 ret = -ENOMEM;
1689 goto out_disable_clks;
1690 }
1691 s->port.ops = &mxs_auart_ops;
1692 s->port.iotype = UPIO_MEM;
1693 s->port.fifosize = MXS_AUART_FIFO_SIZE;
1694 s->port.uartclk = clk_get_rate(s->clk);
1695 s->port.type = PORT_IMX;
1696
1697 mxs_init_regs(s);
1698
1699 s->mctrl_prev = 0;
1700
1701 irq = platform_get_irq(pdev, 0);
1702 if (irq < 0) {
1703 ret = irq;
1704 goto out_disable_clks;
1705 }
1706
1707 s->port.irq = irq;
1708 ret = devm_request_irq(&pdev->dev, irq, mxs_auart_irq_handle, 0,
1709 dev_name(&pdev->dev), s);
1710 if (ret)
1711 goto out_disable_clks;
1712
1713 platform_set_drvdata(pdev, s);
1714
1715 ret = mxs_auart_init_gpios(s, &pdev->dev);
1716 if (ret) {
1717 dev_err(&pdev->dev, "Failed to initialize GPIOs.\n");
1718 goto out_disable_clks;
1719 }
1720
1721 /*
1722 * Get the GPIO lines IRQ
1723 */
1724 ret = mxs_auart_request_gpio_irq(s);
1725 if (ret)
1726 goto out_disable_clks;
1727
1728 auart_port[s->port.line] = s;
1729
1730 mxs_auart_reset_deassert(s);
1731
1732 ret = uart_add_one_port(&auart_driver, &s->port);
1733 if (ret)
1734 goto out_free_qpio_irq;
1735
1736 /* ASM9260 don't have version reg */
1737 if (is_asm9260_auart(s)) {
1738 dev_info(&pdev->dev, "Found APPUART ASM9260\n");
1739 } else {
1740 version = mxs_read(s, REG_VERSION);
1741 dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
1742 (version >> 24) & 0xff,
1743 (version >> 16) & 0xff, version & 0xffff);
1744 }
1745
1746 return 0;
1747
1748out_free_qpio_irq:
1749 mxs_auart_free_gpio_irq(s);
1750 auart_port[pdev->id] = NULL;
1751
1752out_disable_clks:
1753 if (is_asm9260_auart(s)) {
1754 clk_disable_unprepare(s->clk);
1755 clk_disable_unprepare(s->clk_ahb);
1756 }
1757 return ret;
1758}
1759
1760static int mxs_auart_remove(struct platform_device *pdev)
1761{
1762 struct mxs_auart_port *s = platform_get_drvdata(pdev);
1763
1764 uart_remove_one_port(&auart_driver, &s->port);
1765 auart_port[pdev->id] = NULL;
1766 mxs_auart_free_gpio_irq(s);
1767 if (is_asm9260_auart(s)) {
1768 clk_disable_unprepare(s->clk);
1769 clk_disable_unprepare(s->clk_ahb);
1770 }
1771
1772 return 0;
1773}
1774
1775static struct platform_driver mxs_auart_driver = {
1776 .probe = mxs_auart_probe,
1777 .remove = mxs_auart_remove,
1778 .driver = {
1779 .name = "mxs-auart",
1780 .of_match_table = mxs_auart_dt_ids,
1781 },
1782};
1783
1784static int __init mxs_auart_init(void)
1785{
1786 int r;
1787
1788 r = uart_register_driver(&auart_driver);
1789 if (r)
1790 goto out;
1791
1792 r = platform_driver_register(&mxs_auart_driver);
1793 if (r)
1794 goto out_err;
1795
1796 return 0;
1797out_err:
1798 uart_unregister_driver(&auart_driver);
1799out:
1800 return r;
1801}
1802
1803static void __exit mxs_auart_exit(void)
1804{
1805 platform_driver_unregister(&mxs_auart_driver);
1806 uart_unregister_driver(&auart_driver);
1807}
1808
1809module_init(mxs_auart_init);
1810module_exit(mxs_auart_exit);
1811MODULE_LICENSE("GPL");
1812MODULE_DESCRIPTION("Freescale MXS application uart driver");
1813MODULE_ALIAS("platform:mxs-auart");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Application UART driver for:
4 * Freescale STMP37XX/STMP378X
5 * Alphascale ASM9260
6 *
7 * Author: dmitry pervushin <dimka@embeddedalley.com>
8 *
9 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
10 * Provide Alphascale ASM9260 support.
11 * Copyright 2008-2010 Freescale Semiconductor, Inc.
12 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
13 */
14
15#include <linux/kernel.h>
16#include <linux/errno.h>
17#include <linux/init.h>
18#include <linux/console.h>
19#include <linux/interrupt.h>
20#include <linux/module.h>
21#include <linux/slab.h>
22#include <linux/wait.h>
23#include <linux/tty.h>
24#include <linux/tty_driver.h>
25#include <linux/tty_flip.h>
26#include <linux/serial.h>
27#include <linux/serial_core.h>
28#include <linux/platform_device.h>
29#include <linux/device.h>
30#include <linux/clk.h>
31#include <linux/delay.h>
32#include <linux/io.h>
33#include <linux/of.h>
34#include <linux/dma-mapping.h>
35#include <linux/dmaengine.h>
36
37#include <linux/gpio/consumer.h>
38#include <linux/err.h>
39#include <linux/irq.h>
40#include "serial_mctrl_gpio.h"
41
42#define MXS_AUART_PORTS 5
43#define MXS_AUART_FIFO_SIZE 16
44
45#define SET_REG 0x4
46#define CLR_REG 0x8
47#define TOG_REG 0xc
48
49#define AUART_CTRL0 0x00000000
50#define AUART_CTRL1 0x00000010
51#define AUART_CTRL2 0x00000020
52#define AUART_LINECTRL 0x00000030
53#define AUART_LINECTRL2 0x00000040
54#define AUART_INTR 0x00000050
55#define AUART_DATA 0x00000060
56#define AUART_STAT 0x00000070
57#define AUART_DEBUG 0x00000080
58#define AUART_VERSION 0x00000090
59#define AUART_AUTOBAUD 0x000000a0
60
61#define AUART_CTRL0_SFTRST (1 << 31)
62#define AUART_CTRL0_CLKGATE (1 << 30)
63#define AUART_CTRL0_RXTO_ENABLE (1 << 27)
64#define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16)
65#define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff)
66
67#define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff)
68
69#define AUART_CTRL2_DMAONERR (1 << 26)
70#define AUART_CTRL2_TXDMAE (1 << 25)
71#define AUART_CTRL2_RXDMAE (1 << 24)
72
73#define AUART_CTRL2_CTSEN (1 << 15)
74#define AUART_CTRL2_RTSEN (1 << 14)
75#define AUART_CTRL2_RTS (1 << 11)
76#define AUART_CTRL2_RXE (1 << 9)
77#define AUART_CTRL2_TXE (1 << 8)
78#define AUART_CTRL2_UARTEN (1 << 0)
79
80#define AUART_LINECTRL_BAUD_DIV_MAX 0x003fffc0
81#define AUART_LINECTRL_BAUD_DIV_MIN 0x000000ec
82#define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16
83#define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000
84#define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
85#define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8
86#define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00
87#define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
88#define AUART_LINECTRL_SPS (1 << 7)
89#define AUART_LINECTRL_WLEN_MASK 0x00000060
90#define AUART_LINECTRL_WLEN(v) ((((v) - 5) & 0x3) << 5)
91#define AUART_LINECTRL_FEN (1 << 4)
92#define AUART_LINECTRL_STP2 (1 << 3)
93#define AUART_LINECTRL_EPS (1 << 2)
94#define AUART_LINECTRL_PEN (1 << 1)
95#define AUART_LINECTRL_BRK (1 << 0)
96
97#define AUART_INTR_RTIEN (1 << 22)
98#define AUART_INTR_TXIEN (1 << 21)
99#define AUART_INTR_RXIEN (1 << 20)
100#define AUART_INTR_CTSMIEN (1 << 17)
101#define AUART_INTR_RTIS (1 << 6)
102#define AUART_INTR_TXIS (1 << 5)
103#define AUART_INTR_RXIS (1 << 4)
104#define AUART_INTR_CTSMIS (1 << 1)
105
106#define AUART_STAT_BUSY (1 << 29)
107#define AUART_STAT_CTS (1 << 28)
108#define AUART_STAT_TXFE (1 << 27)
109#define AUART_STAT_TXFF (1 << 25)
110#define AUART_STAT_RXFE (1 << 24)
111#define AUART_STAT_OERR (1 << 19)
112#define AUART_STAT_BERR (1 << 18)
113#define AUART_STAT_PERR (1 << 17)
114#define AUART_STAT_FERR (1 << 16)
115#define AUART_STAT_RXCOUNT_MASK 0xffff
116
117/*
118 * Start of Alphascale asm9260 defines
119 * This list contains only differences of existing bits
120 * between imx2x and asm9260
121 */
122#define ASM9260_HW_CTRL0 0x0000
123/*
124 * RW. Tell the UART to execute the RX DMA Command. The
125 * UART will clear this bit at the end of receive execution.
126 */
127#define ASM9260_BM_CTRL0_RXDMA_RUN BIT(28)
128/* RW. 0 use FIFO for status register; 1 use DMA */
129#define ASM9260_BM_CTRL0_RXTO_SOURCE_STATUS BIT(25)
130/*
131 * RW. RX TIMEOUT Enable. Valid for FIFO and DMA.
132 * Warning: If this bit is set to 0, the RX timeout will not affect receive DMA
133 * operation. If this bit is set to 1, a receive timeout will cause the receive
134 * DMA logic to terminate by filling the remaining DMA bytes with garbage data.
135 */
136#define ASM9260_BM_CTRL0_RXTO_ENABLE BIT(24)
137/*
138 * RW. Receive Timeout Counter Value: number of 8-bit-time to wait before
139 * asserting timeout on the RX input. If the RXFIFO is not empty and the RX
140 * input is idle, then the watchdog counter will decrement each bit-time. Note
141 * 7-bit-time is added to the programmed value, so a value of zero will set
142 * the counter to 7-bit-time, a value of 0x1 gives 15-bit-time and so on. Also
143 * note that the counter is reloaded at the end of each frame, so if the frame
144 * is 10 bits long and the timeout counter value is zero, then timeout will
145 * occur (when FIFO is not empty) even if the RX input is not idle. The default
146 * value is 0x3 (31 bit-time).
147 */
148#define ASM9260_BM_CTRL0_RXTO_MASK (0xff << 16)
149/* TIMEOUT = (100*7+1)*(1/BAUD) */
150#define ASM9260_BM_CTRL0_DEFAULT_RXTIMEOUT (20 << 16)
151
152/* TX ctrl register */
153#define ASM9260_HW_CTRL1 0x0010
154/*
155 * RW. Tell the UART to execute the TX DMA Command. The
156 * UART will clear this bit at the end of transmit execution.
157 */
158#define ASM9260_BM_CTRL1_TXDMA_RUN BIT(28)
159
160#define ASM9260_HW_CTRL2 0x0020
161/*
162 * RW. Receive Interrupt FIFO Level Select.
163 * The trigger points for the receive interrupt are as follows:
164 * ONE_EIGHTHS = 0x0 Trigger on FIFO full to at least 2 of 16 entries.
165 * ONE_QUARTER = 0x1 Trigger on FIFO full to at least 4 of 16 entries.
166 * ONE_HALF = 0x2 Trigger on FIFO full to at least 8 of 16 entries.
167 * THREE_QUARTERS = 0x3 Trigger on FIFO full to at least 12 of 16 entries.
168 * SEVEN_EIGHTHS = 0x4 Trigger on FIFO full to at least 14 of 16 entries.
169 */
170#define ASM9260_BM_CTRL2_RXIFLSEL (7 << 20)
171#define ASM9260_BM_CTRL2_DEFAULT_RXIFLSEL (3 << 20)
172/* RW. Same as RXIFLSEL */
173#define ASM9260_BM_CTRL2_TXIFLSEL (7 << 16)
174#define ASM9260_BM_CTRL2_DEFAULT_TXIFLSEL (2 << 16)
175/* RW. Set DTR. When this bit is 1, the output is 0. */
176#define ASM9260_BM_CTRL2_DTR BIT(10)
177/* RW. Loop Back Enable */
178#define ASM9260_BM_CTRL2_LBE BIT(7)
179#define ASM9260_BM_CTRL2_PORT_ENABLE BIT(0)
180
181#define ASM9260_HW_LINECTRL 0x0030
182/*
183 * RW. Stick Parity Select. When bits 1, 2, and 7 of this register are set, the
184 * parity bit is transmitted and checked as a 0. When bits 1 and 7 are set,
185 * and bit 2 is 0, the parity bit is transmitted and checked as a 1. When this
186 * bit is cleared stick parity is disabled.
187 */
188#define ASM9260_BM_LCTRL_SPS BIT(7)
189/* RW. Word length */
190#define ASM9260_BM_LCTRL_WLEN (3 << 5)
191#define ASM9260_BM_LCTRL_CHRL_5 (0 << 5)
192#define ASM9260_BM_LCTRL_CHRL_6 (1 << 5)
193#define ASM9260_BM_LCTRL_CHRL_7 (2 << 5)
194#define ASM9260_BM_LCTRL_CHRL_8 (3 << 5)
195
196/*
197 * Interrupt register.
198 * contains the interrupt enables and the interrupt status bits
199 */
200#define ASM9260_HW_INTR 0x0040
201/* Tx FIFO EMPTY Raw Interrupt enable */
202#define ASM9260_BM_INTR_TFEIEN BIT(27)
203/* Overrun Error Interrupt Enable. */
204#define ASM9260_BM_INTR_OEIEN BIT(26)
205/* Break Error Interrupt Enable. */
206#define ASM9260_BM_INTR_BEIEN BIT(25)
207/* Parity Error Interrupt Enable. */
208#define ASM9260_BM_INTR_PEIEN BIT(24)
209/* Framing Error Interrupt Enable. */
210#define ASM9260_BM_INTR_FEIEN BIT(23)
211
212/* nUARTDSR Modem Interrupt Enable. */
213#define ASM9260_BM_INTR_DSRMIEN BIT(19)
214/* nUARTDCD Modem Interrupt Enable. */
215#define ASM9260_BM_INTR_DCDMIEN BIT(18)
216/* nUARTRI Modem Interrupt Enable. */
217#define ASM9260_BM_INTR_RIMIEN BIT(16)
218/* Auto-Boud Timeout */
219#define ASM9260_BM_INTR_ABTO BIT(13)
220#define ASM9260_BM_INTR_ABEO BIT(12)
221/* Tx FIFO EMPTY Raw Interrupt state */
222#define ASM9260_BM_INTR_TFEIS BIT(11)
223/* Overrun Error */
224#define ASM9260_BM_INTR_OEIS BIT(10)
225/* Break Error */
226#define ASM9260_BM_INTR_BEIS BIT(9)
227/* Parity Error */
228#define ASM9260_BM_INTR_PEIS BIT(8)
229/* Framing Error */
230#define ASM9260_BM_INTR_FEIS BIT(7)
231#define ASM9260_BM_INTR_DSRMIS BIT(3)
232#define ASM9260_BM_INTR_DCDMIS BIT(2)
233#define ASM9260_BM_INTR_RIMIS BIT(0)
234
235/*
236 * RW. In DMA mode, up to 4 Received/Transmit characters can be accessed at a
237 * time. In PIO mode, only one character can be accessed at a time. The status
238 * register contains the receive data flags and valid bits.
239 */
240#define ASM9260_HW_DATA 0x0050
241
242#define ASM9260_HW_STAT 0x0060
243/* RO. If 1, UARTAPP is present in this product. */
244#define ASM9260_BM_STAT_PRESENT BIT(31)
245/* RO. If 1, HISPEED is present in this product. */
246#define ASM9260_BM_STAT_HISPEED BIT(30)
247/* RO. Receive FIFO Full. */
248#define ASM9260_BM_STAT_RXFULL BIT(26)
249
250/* RO. The UART Debug Register contains the state of the DMA signals. */
251#define ASM9260_HW_DEBUG 0x0070
252/* DMA Command Run Status */
253#define ASM9260_BM_DEBUG_TXDMARUN BIT(5)
254#define ASM9260_BM_DEBUG_RXDMARUN BIT(4)
255/* DMA Command End Status */
256#define ASM9260_BM_DEBUG_TXCMDEND BIT(3)
257#define ASM9260_BM_DEBUG_RXCMDEND BIT(2)
258/* DMA Request Status */
259#define ASM9260_BM_DEBUG_TXDMARQ BIT(1)
260#define ASM9260_BM_DEBUG_RXDMARQ BIT(0)
261
262#define ASM9260_HW_ILPR 0x0080
263
264#define ASM9260_HW_RS485CTRL 0x0090
265/*
266 * RW. This bit reverses the polarity of the direction control signal on the RTS
267 * (or DTR) pin.
268 * If 0, The direction control pin will be driven to logic ‘0’ when the
269 * transmitter has data to be sent. It will be driven to logic ‘1’ after the
270 * last bit of data has been transmitted.
271 */
272#define ASM9260_BM_RS485CTRL_ONIV BIT(5)
273/* RW. Enable Auto Direction Control. */
274#define ASM9260_BM_RS485CTRL_DIR_CTRL BIT(4)
275/*
276 * RW. If 0 and DIR_CTRL = 1, pin RTS is used for direction control.
277 * If 1 and DIR_CTRL = 1, pin DTR is used for direction control.
278 */
279#define ASM9260_BM_RS485CTRL_PINSEL BIT(3)
280/* RW. Enable Auto Address Detect (AAD). */
281#define ASM9260_BM_RS485CTRL_AADEN BIT(2)
282/* RW. Disable receiver. */
283#define ASM9260_BM_RS485CTRL_RXDIS BIT(1)
284/* RW. Enable RS-485/EIA-485 Normal Multidrop Mode (NMM) */
285#define ASM9260_BM_RS485CTRL_RS485EN BIT(0)
286
287#define ASM9260_HW_RS485ADRMATCH 0x00a0
288/* Contains the address match value. */
289#define ASM9260_BM_RS485ADRMATCH_MASK (0xff << 0)
290
291#define ASM9260_HW_RS485DLY 0x00b0
292/*
293 * RW. Contains the direction control (RTS or DTR) delay value. This delay time
294 * is in periods of the baud clock.
295 */
296#define ASM9260_BM_RS485DLY_MASK (0xff << 0)
297
298#define ASM9260_HW_AUTOBAUD 0x00c0
299/* WO. Auto-baud time-out interrupt clear bit. */
300#define ASM9260_BM_AUTOBAUD_TO_INT_CLR BIT(9)
301/* WO. End of auto-baud interrupt clear bit. */
302#define ASM9260_BM_AUTOBAUD_EO_INT_CLR BIT(8)
303/* Restart in case of timeout (counter restarts at next UART Rx falling edge) */
304#define ASM9260_BM_AUTOBAUD_AUTORESTART BIT(2)
305/* Auto-baud mode select bit. 0 - Mode 0, 1 - Mode 1. */
306#define ASM9260_BM_AUTOBAUD_MODE BIT(1)
307/*
308 * Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is
309 * automatically cleared after auto-baud completion.
310 */
311#define ASM9260_BM_AUTOBAUD_START BIT(0)
312
313#define ASM9260_HW_CTRL3 0x00d0
314#define ASM9260_BM_CTRL3_OUTCLK_DIV_MASK (0xffff << 16)
315/*
316 * RW. Provide clk over OUTCLK pin. In case of asm9260 it can be configured on
317 * pins 137 and 144.
318 */
319#define ASM9260_BM_CTRL3_MASTERMODE BIT(6)
320/* RW. Baud Rate Mode: 1 - Enable sync mode. 0 - async mode. */
321#define ASM9260_BM_CTRL3_SYNCMODE BIT(4)
322/* RW. 1 - MSB bit send frist; 0 - LSB bit frist. */
323#define ASM9260_BM_CTRL3_MSBF BIT(2)
324/* RW. 1 - sample rate = 8 x Baudrate; 0 - sample rate = 16 x Baudrate. */
325#define ASM9260_BM_CTRL3_BAUD8 BIT(1)
326/* RW. 1 - Set word length to 9bit. 0 - use ASM9260_BM_LCTRL_WLEN */
327#define ASM9260_BM_CTRL3_9BIT BIT(0)
328
329#define ASM9260_HW_ISO7816_CTRL 0x00e0
330/* RW. Enable High Speed mode. */
331#define ASM9260_BM_ISO7816CTRL_HS BIT(12)
332/* Disable Successive Receive NACK */
333#define ASM9260_BM_ISO7816CTRL_DS_NACK BIT(8)
334#define ASM9260_BM_ISO7816CTRL_MAX_ITER_MASK (0xff << 4)
335/* Receive NACK Inhibit */
336#define ASM9260_BM_ISO7816CTRL_INACK BIT(3)
337#define ASM9260_BM_ISO7816CTRL_NEG_DATA BIT(2)
338/* RW. 1 - ISO7816 mode; 0 - USART mode */
339#define ASM9260_BM_ISO7816CTRL_ENABLE BIT(0)
340
341#define ASM9260_HW_ISO7816_ERRCNT 0x00f0
342/* Parity error counter. Will be cleared after reading */
343#define ASM9260_BM_ISO7816_NB_ERRORS_MASK (0xff << 0)
344
345#define ASM9260_HW_ISO7816_STATUS 0x0100
346/* Max number of Repetitions Reached */
347#define ASM9260_BM_ISO7816_STAT_ITERATION BIT(0)
348
349/* End of Alphascale asm9260 defines */
350
351static struct uart_driver auart_driver;
352
353enum mxs_auart_type {
354 IMX23_AUART,
355 IMX28_AUART,
356 ASM9260_AUART,
357};
358
359struct vendor_data {
360 const u16 *reg_offset;
361};
362
363enum {
364 REG_CTRL0,
365 REG_CTRL1,
366 REG_CTRL2,
367 REG_LINECTRL,
368 REG_LINECTRL2,
369 REG_INTR,
370 REG_DATA,
371 REG_STAT,
372 REG_DEBUG,
373 REG_VERSION,
374 REG_AUTOBAUD,
375
376 /* The size of the array - must be last */
377 REG_ARRAY_SIZE,
378};
379
380static const u16 mxs_asm9260_offsets[REG_ARRAY_SIZE] = {
381 [REG_CTRL0] = ASM9260_HW_CTRL0,
382 [REG_CTRL1] = ASM9260_HW_CTRL1,
383 [REG_CTRL2] = ASM9260_HW_CTRL2,
384 [REG_LINECTRL] = ASM9260_HW_LINECTRL,
385 [REG_INTR] = ASM9260_HW_INTR,
386 [REG_DATA] = ASM9260_HW_DATA,
387 [REG_STAT] = ASM9260_HW_STAT,
388 [REG_DEBUG] = ASM9260_HW_DEBUG,
389 [REG_AUTOBAUD] = ASM9260_HW_AUTOBAUD,
390};
391
392static const u16 mxs_stmp37xx_offsets[REG_ARRAY_SIZE] = {
393 [REG_CTRL0] = AUART_CTRL0,
394 [REG_CTRL1] = AUART_CTRL1,
395 [REG_CTRL2] = AUART_CTRL2,
396 [REG_LINECTRL] = AUART_LINECTRL,
397 [REG_LINECTRL2] = AUART_LINECTRL2,
398 [REG_INTR] = AUART_INTR,
399 [REG_DATA] = AUART_DATA,
400 [REG_STAT] = AUART_STAT,
401 [REG_DEBUG] = AUART_DEBUG,
402 [REG_VERSION] = AUART_VERSION,
403 [REG_AUTOBAUD] = AUART_AUTOBAUD,
404};
405
406static const struct vendor_data vendor_alphascale_asm9260 = {
407 .reg_offset = mxs_asm9260_offsets,
408};
409
410static const struct vendor_data vendor_freescale_stmp37xx = {
411 .reg_offset = mxs_stmp37xx_offsets,
412};
413
414struct mxs_auart_port {
415 struct uart_port port;
416
417#define MXS_AUART_DMA_ENABLED 0x2
418#define MXS_AUART_DMA_TX_SYNC 2 /* bit 2 */
419#define MXS_AUART_DMA_RX_READY 3 /* bit 3 */
420#define MXS_AUART_RTSCTS 4 /* bit 4 */
421 unsigned long flags;
422 unsigned int mctrl_prev;
423 enum mxs_auart_type devtype;
424 const struct vendor_data *vendor;
425
426 struct clk *clk;
427 struct clk *clk_ahb;
428 struct device *dev;
429
430 /* for DMA */
431 struct scatterlist tx_sgl;
432 struct dma_chan *tx_dma_chan;
433 void *tx_dma_buf;
434
435 struct scatterlist rx_sgl;
436 struct dma_chan *rx_dma_chan;
437 void *rx_dma_buf;
438
439 struct mctrl_gpios *gpios;
440 int gpio_irq[UART_GPIO_MAX];
441 bool ms_irq_enabled;
442};
443
444static const struct of_device_id mxs_auart_dt_ids[] = {
445 {
446 .compatible = "fsl,imx28-auart",
447 .data = (const void *)IMX28_AUART
448 }, {
449 .compatible = "fsl,imx23-auart",
450 .data = (const void *)IMX23_AUART
451 }, {
452 .compatible = "alphascale,asm9260-auart",
453 .data = (const void *)ASM9260_AUART
454 }, { /* sentinel */ }
455};
456MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids);
457
458static inline int is_imx28_auart(struct mxs_auart_port *s)
459{
460 return s->devtype == IMX28_AUART;
461}
462
463static inline int is_asm9260_auart(struct mxs_auart_port *s)
464{
465 return s->devtype == ASM9260_AUART;
466}
467
468static inline bool auart_dma_enabled(struct mxs_auart_port *s)
469{
470 return s->flags & MXS_AUART_DMA_ENABLED;
471}
472
473static unsigned int mxs_reg_to_offset(const struct mxs_auart_port *uap,
474 unsigned int reg)
475{
476 return uap->vendor->reg_offset[reg];
477}
478
479static unsigned int mxs_read(const struct mxs_auart_port *uap,
480 unsigned int reg)
481{
482 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
483
484 return readl_relaxed(addr);
485}
486
487static void mxs_write(unsigned int val, struct mxs_auart_port *uap,
488 unsigned int reg)
489{
490 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
491
492 writel_relaxed(val, addr);
493}
494
495static void mxs_set(unsigned int val, struct mxs_auart_port *uap,
496 unsigned int reg)
497{
498 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
499
500 writel_relaxed(val, addr + SET_REG);
501}
502
503static void mxs_clr(unsigned int val, struct mxs_auart_port *uap,
504 unsigned int reg)
505{
506 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
507
508 writel_relaxed(val, addr + CLR_REG);
509}
510
511static void mxs_auart_stop_tx(struct uart_port *u);
512
513#define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
514
515static void mxs_auart_tx_chars(struct mxs_auart_port *s);
516
517static void dma_tx_callback(void *param)
518{
519 struct mxs_auart_port *s = param;
520 struct circ_buf *xmit = &s->port.state->xmit;
521
522 dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE);
523
524 /* clear the bit used to serialize the DMA tx. */
525 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
526 smp_mb__after_atomic();
527
528 /* wake up the possible processes. */
529 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
530 uart_write_wakeup(&s->port);
531
532 mxs_auart_tx_chars(s);
533}
534
535static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size)
536{
537 struct dma_async_tx_descriptor *desc;
538 struct scatterlist *sgl = &s->tx_sgl;
539 struct dma_chan *channel = s->tx_dma_chan;
540 u32 pio;
541
542 /* [1] : send PIO. Note, the first pio word is CTRL1. */
543 pio = AUART_CTRL1_XFER_COUNT(size);
544 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)&pio,
545 1, DMA_TRANS_NONE, 0);
546 if (!desc) {
547 dev_err(s->dev, "step 1 error\n");
548 return -EINVAL;
549 }
550
551 /* [2] : set DMA buffer. */
552 sg_init_one(sgl, s->tx_dma_buf, size);
553 dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE);
554 desc = dmaengine_prep_slave_sg(channel, sgl,
555 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
556 if (!desc) {
557 dev_err(s->dev, "step 2 error\n");
558 return -EINVAL;
559 }
560
561 /* [3] : submit the DMA */
562 desc->callback = dma_tx_callback;
563 desc->callback_param = s;
564 dmaengine_submit(desc);
565 dma_async_issue_pending(channel);
566 return 0;
567}
568
569static void mxs_auart_tx_chars(struct mxs_auart_port *s)
570{
571 struct circ_buf *xmit = &s->port.state->xmit;
572 bool pending;
573 u8 ch;
574
575 if (auart_dma_enabled(s)) {
576 u32 i = 0;
577 int size;
578 void *buffer = s->tx_dma_buf;
579
580 if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, &s->flags))
581 return;
582
583 while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
584 size = min_t(u32, UART_XMIT_SIZE - i,
585 CIRC_CNT_TO_END(xmit->head,
586 xmit->tail,
587 UART_XMIT_SIZE));
588 memcpy(buffer + i, xmit->buf + xmit->tail, size);
589 xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1);
590
591 i += size;
592 if (i >= UART_XMIT_SIZE)
593 break;
594 }
595
596 if (uart_tx_stopped(&s->port))
597 mxs_auart_stop_tx(&s->port);
598
599 if (i) {
600 mxs_auart_dma_tx(s, i);
601 } else {
602 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
603 smp_mb__after_atomic();
604 }
605 return;
606 }
607
608 pending = uart_port_tx_flags(&s->port, ch, UART_TX_NOSTOP,
609 !(mxs_read(s, REG_STAT) & AUART_STAT_TXFF),
610 mxs_write(ch, s, REG_DATA));
611 if (pending)
612 mxs_set(AUART_INTR_TXIEN, s, REG_INTR);
613 else
614 mxs_clr(AUART_INTR_TXIEN, s, REG_INTR);
615
616 if (uart_tx_stopped(&s->port))
617 mxs_auart_stop_tx(&s->port);
618}
619
620static void mxs_auart_rx_char(struct mxs_auart_port *s)
621{
622 u32 stat;
623 u8 c, flag;
624
625 c = mxs_read(s, REG_DATA);
626 stat = mxs_read(s, REG_STAT);
627
628 flag = TTY_NORMAL;
629 s->port.icount.rx++;
630
631 if (stat & AUART_STAT_BERR) {
632 s->port.icount.brk++;
633 if (uart_handle_break(&s->port))
634 goto out;
635 } else if (stat & AUART_STAT_PERR) {
636 s->port.icount.parity++;
637 } else if (stat & AUART_STAT_FERR) {
638 s->port.icount.frame++;
639 }
640
641 /*
642 * Mask off conditions which should be ingored.
643 */
644 stat &= s->port.read_status_mask;
645
646 if (stat & AUART_STAT_BERR) {
647 flag = TTY_BREAK;
648 } else if (stat & AUART_STAT_PERR)
649 flag = TTY_PARITY;
650 else if (stat & AUART_STAT_FERR)
651 flag = TTY_FRAME;
652
653 if (stat & AUART_STAT_OERR)
654 s->port.icount.overrun++;
655
656 if (uart_handle_sysrq_char(&s->port, c))
657 goto out;
658
659 uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
660out:
661 mxs_write(stat, s, REG_STAT);
662}
663
664static void mxs_auart_rx_chars(struct mxs_auart_port *s)
665{
666 u32 stat = 0;
667
668 for (;;) {
669 stat = mxs_read(s, REG_STAT);
670 if (stat & AUART_STAT_RXFE)
671 break;
672 mxs_auart_rx_char(s);
673 }
674
675 mxs_write(stat, s, REG_STAT);
676 tty_flip_buffer_push(&s->port.state->port);
677}
678
679static int mxs_auart_request_port(struct uart_port *u)
680{
681 return 0;
682}
683
684static int mxs_auart_verify_port(struct uart_port *u,
685 struct serial_struct *ser)
686{
687 if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
688 return -EINVAL;
689 return 0;
690}
691
692static void mxs_auart_config_port(struct uart_port *u, int flags)
693{
694}
695
696static const char *mxs_auart_type(struct uart_port *u)
697{
698 struct mxs_auart_port *s = to_auart_port(u);
699
700 return dev_name(s->dev);
701}
702
703static void mxs_auart_release_port(struct uart_port *u)
704{
705}
706
707static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
708{
709 struct mxs_auart_port *s = to_auart_port(u);
710
711 u32 ctrl = mxs_read(s, REG_CTRL2);
712
713 ctrl &= ~(AUART_CTRL2_RTSEN | AUART_CTRL2_RTS);
714 if (mctrl & TIOCM_RTS) {
715 if (uart_cts_enabled(u))
716 ctrl |= AUART_CTRL2_RTSEN;
717 else
718 ctrl |= AUART_CTRL2_RTS;
719 }
720
721 mxs_write(ctrl, s, REG_CTRL2);
722
723 mctrl_gpio_set(s->gpios, mctrl);
724}
725
726#define MCTRL_ANY_DELTA (TIOCM_RI | TIOCM_DSR | TIOCM_CD | TIOCM_CTS)
727static u32 mxs_auart_modem_status(struct mxs_auart_port *s, u32 mctrl)
728{
729 u32 mctrl_diff;
730
731 mctrl_diff = mctrl ^ s->mctrl_prev;
732 s->mctrl_prev = mctrl;
733 if (mctrl_diff & MCTRL_ANY_DELTA && s->ms_irq_enabled &&
734 s->port.state != NULL) {
735 if (mctrl_diff & TIOCM_RI)
736 s->port.icount.rng++;
737 if (mctrl_diff & TIOCM_DSR)
738 s->port.icount.dsr++;
739 if (mctrl_diff & TIOCM_CD)
740 uart_handle_dcd_change(&s->port, mctrl & TIOCM_CD);
741 if (mctrl_diff & TIOCM_CTS)
742 uart_handle_cts_change(&s->port, mctrl & TIOCM_CTS);
743
744 wake_up_interruptible(&s->port.state->port.delta_msr_wait);
745 }
746 return mctrl;
747}
748
749static u32 mxs_auart_get_mctrl(struct uart_port *u)
750{
751 struct mxs_auart_port *s = to_auart_port(u);
752 u32 stat = mxs_read(s, REG_STAT);
753 u32 mctrl = 0;
754
755 if (stat & AUART_STAT_CTS)
756 mctrl |= TIOCM_CTS;
757
758 return mctrl_gpio_get(s->gpios, &mctrl);
759}
760
761/*
762 * Enable modem status interrupts
763 */
764static void mxs_auart_enable_ms(struct uart_port *port)
765{
766 struct mxs_auart_port *s = to_auart_port(port);
767
768 /*
769 * Interrupt should not be enabled twice
770 */
771 if (s->ms_irq_enabled)
772 return;
773
774 s->ms_irq_enabled = true;
775
776 if (s->gpio_irq[UART_GPIO_CTS] >= 0)
777 enable_irq(s->gpio_irq[UART_GPIO_CTS]);
778 /* TODO: enable AUART_INTR_CTSMIEN otherwise */
779
780 if (s->gpio_irq[UART_GPIO_DSR] >= 0)
781 enable_irq(s->gpio_irq[UART_GPIO_DSR]);
782
783 if (s->gpio_irq[UART_GPIO_RI] >= 0)
784 enable_irq(s->gpio_irq[UART_GPIO_RI]);
785
786 if (s->gpio_irq[UART_GPIO_DCD] >= 0)
787 enable_irq(s->gpio_irq[UART_GPIO_DCD]);
788}
789
790/*
791 * Disable modem status interrupts
792 */
793static void mxs_auart_disable_ms(struct uart_port *port)
794{
795 struct mxs_auart_port *s = to_auart_port(port);
796
797 /*
798 * Interrupt should not be disabled twice
799 */
800 if (!s->ms_irq_enabled)
801 return;
802
803 s->ms_irq_enabled = false;
804
805 if (s->gpio_irq[UART_GPIO_CTS] >= 0)
806 disable_irq(s->gpio_irq[UART_GPIO_CTS]);
807 /* TODO: disable AUART_INTR_CTSMIEN otherwise */
808
809 if (s->gpio_irq[UART_GPIO_DSR] >= 0)
810 disable_irq(s->gpio_irq[UART_GPIO_DSR]);
811
812 if (s->gpio_irq[UART_GPIO_RI] >= 0)
813 disable_irq(s->gpio_irq[UART_GPIO_RI]);
814
815 if (s->gpio_irq[UART_GPIO_DCD] >= 0)
816 disable_irq(s->gpio_irq[UART_GPIO_DCD]);
817}
818
819static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s);
820static void dma_rx_callback(void *arg)
821{
822 struct mxs_auart_port *s = (struct mxs_auart_port *) arg;
823 struct tty_port *port = &s->port.state->port;
824 int count;
825 u32 stat;
826
827 dma_unmap_sg(s->dev, &s->rx_sgl, 1, DMA_FROM_DEVICE);
828
829 stat = mxs_read(s, REG_STAT);
830 stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR |
831 AUART_STAT_PERR | AUART_STAT_FERR);
832
833 count = stat & AUART_STAT_RXCOUNT_MASK;
834 tty_insert_flip_string(port, s->rx_dma_buf, count);
835
836 mxs_write(stat, s, REG_STAT);
837 tty_flip_buffer_push(port);
838
839 /* start the next DMA for RX. */
840 mxs_auart_dma_prep_rx(s);
841}
842
843static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s)
844{
845 struct dma_async_tx_descriptor *desc;
846 struct scatterlist *sgl = &s->rx_sgl;
847 struct dma_chan *channel = s->rx_dma_chan;
848 u32 pio[1];
849
850 /* [1] : send PIO */
851 pio[0] = AUART_CTRL0_RXTO_ENABLE
852 | AUART_CTRL0_RXTIMEOUT(0x80)
853 | AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE);
854 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
855 1, DMA_TRANS_NONE, 0);
856 if (!desc) {
857 dev_err(s->dev, "step 1 error\n");
858 return -EINVAL;
859 }
860
861 /* [2] : send DMA request */
862 sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE);
863 dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE);
864 desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_DEV_TO_MEM,
865 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
866 if (!desc) {
867 dev_err(s->dev, "step 2 error\n");
868 return -1;
869 }
870
871 /* [3] : submit the DMA, but do not issue it. */
872 desc->callback = dma_rx_callback;
873 desc->callback_param = s;
874 dmaengine_submit(desc);
875 dma_async_issue_pending(channel);
876 return 0;
877}
878
879static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s)
880{
881 if (s->tx_dma_chan) {
882 dma_release_channel(s->tx_dma_chan);
883 s->tx_dma_chan = NULL;
884 }
885 if (s->rx_dma_chan) {
886 dma_release_channel(s->rx_dma_chan);
887 s->rx_dma_chan = NULL;
888 }
889
890 kfree(s->tx_dma_buf);
891 kfree(s->rx_dma_buf);
892 s->tx_dma_buf = NULL;
893 s->rx_dma_buf = NULL;
894}
895
896static void mxs_auart_dma_exit(struct mxs_auart_port *s)
897{
898
899 mxs_clr(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR,
900 s, REG_CTRL2);
901
902 mxs_auart_dma_exit_channel(s);
903 s->flags &= ~MXS_AUART_DMA_ENABLED;
904 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
905 clear_bit(MXS_AUART_DMA_RX_READY, &s->flags);
906}
907
908static int mxs_auart_dma_init(struct mxs_auart_port *s)
909{
910 struct dma_chan *chan;
911
912 if (auart_dma_enabled(s))
913 return 0;
914
915 /* init for RX */
916 chan = dma_request_chan(s->dev, "rx");
917 if (IS_ERR(chan))
918 goto err_out;
919 s->rx_dma_chan = chan;
920
921 s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
922 if (!s->rx_dma_buf)
923 goto err_out;
924
925 /* init for TX */
926 chan = dma_request_chan(s->dev, "tx");
927 if (IS_ERR(chan))
928 goto err_out;
929 s->tx_dma_chan = chan;
930
931 s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
932 if (!s->tx_dma_buf)
933 goto err_out;
934
935 /* set the flags */
936 s->flags |= MXS_AUART_DMA_ENABLED;
937 dev_dbg(s->dev, "enabled the DMA support.");
938
939 /* The DMA buffer is now the FIFO the TTY subsystem can use */
940 s->port.fifosize = UART_XMIT_SIZE;
941
942 return 0;
943
944err_out:
945 mxs_auart_dma_exit_channel(s);
946 return -EINVAL;
947
948}
949
950#define RTS_AT_AUART() !mctrl_gpio_to_gpiod(s->gpios, UART_GPIO_RTS)
951#define CTS_AT_AUART() !mctrl_gpio_to_gpiod(s->gpios, UART_GPIO_CTS)
952static void mxs_auart_settermios(struct uart_port *u,
953 struct ktermios *termios,
954 const struct ktermios *old)
955{
956 struct mxs_auart_port *s = to_auart_port(u);
957 u32 ctrl, ctrl2, div;
958 unsigned int cflag, baud, baud_min, baud_max;
959
960 cflag = termios->c_cflag;
961
962 ctrl = AUART_LINECTRL_FEN;
963 ctrl2 = mxs_read(s, REG_CTRL2);
964
965 ctrl |= AUART_LINECTRL_WLEN(tty_get_char_size(cflag));
966
967 /* parity */
968 if (cflag & PARENB) {
969 ctrl |= AUART_LINECTRL_PEN;
970 if ((cflag & PARODD) == 0)
971 ctrl |= AUART_LINECTRL_EPS;
972 if (cflag & CMSPAR)
973 ctrl |= AUART_LINECTRL_SPS;
974 }
975
976 u->read_status_mask = AUART_STAT_OERR;
977
978 if (termios->c_iflag & INPCK)
979 u->read_status_mask |= AUART_STAT_PERR;
980 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
981 u->read_status_mask |= AUART_STAT_BERR;
982
983 /*
984 * Characters to ignore
985 */
986 u->ignore_status_mask = 0;
987 if (termios->c_iflag & IGNPAR)
988 u->ignore_status_mask |= AUART_STAT_PERR;
989 if (termios->c_iflag & IGNBRK) {
990 u->ignore_status_mask |= AUART_STAT_BERR;
991 /*
992 * If we're ignoring parity and break indicators,
993 * ignore overruns too (for real raw support).
994 */
995 if (termios->c_iflag & IGNPAR)
996 u->ignore_status_mask |= AUART_STAT_OERR;
997 }
998
999 /*
1000 * ignore all characters if CREAD is not set
1001 */
1002 if (cflag & CREAD)
1003 ctrl2 |= AUART_CTRL2_RXE;
1004 else
1005 ctrl2 &= ~AUART_CTRL2_RXE;
1006
1007 /* figure out the stop bits requested */
1008 if (cflag & CSTOPB)
1009 ctrl |= AUART_LINECTRL_STP2;
1010
1011 /* figure out the hardware flow control settings */
1012 ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN);
1013 if (cflag & CRTSCTS) {
1014 /*
1015 * The DMA has a bug(see errata:2836) in mx23.
1016 * So we can not implement the DMA for auart in mx23,
1017 * we can only implement the DMA support for auart
1018 * in mx28.
1019 */
1020 if (is_imx28_auart(s)
1021 && test_bit(MXS_AUART_RTSCTS, &s->flags)) {
1022 if (!mxs_auart_dma_init(s))
1023 /* enable DMA tranfer */
1024 ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE
1025 | AUART_CTRL2_DMAONERR;
1026 }
1027 /* Even if RTS is GPIO line RTSEN can be enabled because
1028 * the pinctrl configuration decides about RTS pin function */
1029 ctrl2 |= AUART_CTRL2_RTSEN;
1030 if (CTS_AT_AUART())
1031 ctrl2 |= AUART_CTRL2_CTSEN;
1032 }
1033
1034 /* set baud rate */
1035 if (is_asm9260_auart(s)) {
1036 baud = uart_get_baud_rate(u, termios, old,
1037 u->uartclk * 4 / 0x3FFFFF,
1038 u->uartclk / 16);
1039 div = u->uartclk * 4 / baud;
1040 } else {
1041 baud_min = DIV_ROUND_UP(u->uartclk * 32,
1042 AUART_LINECTRL_BAUD_DIV_MAX);
1043 baud_max = u->uartclk * 32 / AUART_LINECTRL_BAUD_DIV_MIN;
1044 baud = uart_get_baud_rate(u, termios, old, baud_min, baud_max);
1045 div = DIV_ROUND_CLOSEST(u->uartclk * 32, baud);
1046 }
1047
1048 ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
1049 ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
1050 mxs_write(ctrl, s, REG_LINECTRL);
1051
1052 mxs_write(ctrl2, s, REG_CTRL2);
1053
1054 uart_update_timeout(u, termios->c_cflag, baud);
1055
1056 /* prepare for the DMA RX. */
1057 if (auart_dma_enabled(s) &&
1058 !test_and_set_bit(MXS_AUART_DMA_RX_READY, &s->flags)) {
1059 if (!mxs_auart_dma_prep_rx(s)) {
1060 /* Disable the normal RX interrupt. */
1061 mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN,
1062 s, REG_INTR);
1063 } else {
1064 mxs_auart_dma_exit(s);
1065 dev_err(s->dev, "We can not start up the DMA.\n");
1066 }
1067 }
1068
1069 /* CTS flow-control and modem-status interrupts */
1070 if (UART_ENABLE_MS(u, termios->c_cflag))
1071 mxs_auart_enable_ms(u);
1072 else
1073 mxs_auart_disable_ms(u);
1074}
1075
1076static void mxs_auart_set_ldisc(struct uart_port *port,
1077 struct ktermios *termios)
1078{
1079 if (termios->c_line == N_PPS) {
1080 port->flags |= UPF_HARDPPS_CD;
1081 mxs_auart_enable_ms(port);
1082 } else {
1083 port->flags &= ~UPF_HARDPPS_CD;
1084 }
1085}
1086
1087static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
1088{
1089 u32 istat, stat;
1090 struct mxs_auart_port *s = context;
1091 u32 mctrl_temp = s->mctrl_prev;
1092
1093 uart_port_lock(&s->port);
1094
1095 stat = mxs_read(s, REG_STAT);
1096 istat = mxs_read(s, REG_INTR);
1097
1098 /* ack irq */
1099 mxs_clr(istat & (AUART_INTR_RTIS | AUART_INTR_TXIS | AUART_INTR_RXIS
1100 | AUART_INTR_CTSMIS), s, REG_INTR);
1101
1102 /*
1103 * Dealing with GPIO interrupt
1104 */
1105 if (irq == s->gpio_irq[UART_GPIO_CTS] ||
1106 irq == s->gpio_irq[UART_GPIO_DCD] ||
1107 irq == s->gpio_irq[UART_GPIO_DSR] ||
1108 irq == s->gpio_irq[UART_GPIO_RI])
1109 mxs_auart_modem_status(s,
1110 mctrl_gpio_get(s->gpios, &mctrl_temp));
1111
1112 if (istat & AUART_INTR_CTSMIS) {
1113 if (CTS_AT_AUART() && s->ms_irq_enabled)
1114 uart_handle_cts_change(&s->port,
1115 stat & AUART_STAT_CTS);
1116 mxs_clr(AUART_INTR_CTSMIS, s, REG_INTR);
1117 istat &= ~AUART_INTR_CTSMIS;
1118 }
1119
1120 if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
1121 if (!auart_dma_enabled(s))
1122 mxs_auart_rx_chars(s);
1123 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
1124 }
1125
1126 if (istat & AUART_INTR_TXIS) {
1127 mxs_auart_tx_chars(s);
1128 istat &= ~AUART_INTR_TXIS;
1129 }
1130
1131 uart_port_unlock(&s->port);
1132
1133 return IRQ_HANDLED;
1134}
1135
1136static void mxs_auart_reset_deassert(struct mxs_auart_port *s)
1137{
1138 int i;
1139 unsigned int reg;
1140
1141 mxs_clr(AUART_CTRL0_SFTRST, s, REG_CTRL0);
1142
1143 for (i = 0; i < 10000; i++) {
1144 reg = mxs_read(s, REG_CTRL0);
1145 if (!(reg & AUART_CTRL0_SFTRST))
1146 break;
1147 udelay(3);
1148 }
1149 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1150}
1151
1152static void mxs_auart_reset_assert(struct mxs_auart_port *s)
1153{
1154 int i;
1155 u32 reg;
1156
1157 reg = mxs_read(s, REG_CTRL0);
1158 /* if already in reset state, keep it untouched */
1159 if (reg & AUART_CTRL0_SFTRST)
1160 return;
1161
1162 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1163 mxs_set(AUART_CTRL0_SFTRST, s, REG_CTRL0);
1164
1165 for (i = 0; i < 1000; i++) {
1166 reg = mxs_read(s, REG_CTRL0);
1167 /* reset is finished when the clock is gated */
1168 if (reg & AUART_CTRL0_CLKGATE)
1169 return;
1170 udelay(10);
1171 }
1172
1173 dev_err(s->dev, "Failed to reset the unit.");
1174}
1175
1176static int mxs_auart_startup(struct uart_port *u)
1177{
1178 int ret;
1179 struct mxs_auart_port *s = to_auart_port(u);
1180
1181 ret = clk_prepare_enable(s->clk);
1182 if (ret)
1183 return ret;
1184
1185 if (uart_console(u)) {
1186 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1187 } else {
1188 /* reset the unit to a well known state */
1189 mxs_auart_reset_assert(s);
1190 mxs_auart_reset_deassert(s);
1191 }
1192
1193 mxs_set(AUART_CTRL2_UARTEN, s, REG_CTRL2);
1194
1195 mxs_write(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
1196 s, REG_INTR);
1197
1198 /* Reset FIFO size (it could have changed if DMA was enabled) */
1199 u->fifosize = MXS_AUART_FIFO_SIZE;
1200
1201 /*
1202 * Enable fifo so all four bytes of a DMA word are written to
1203 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
1204 */
1205 mxs_set(AUART_LINECTRL_FEN, s, REG_LINECTRL);
1206
1207 /* get initial status of modem lines */
1208 mctrl_gpio_get(s->gpios, &s->mctrl_prev);
1209
1210 s->ms_irq_enabled = false;
1211 return 0;
1212}
1213
1214static void mxs_auart_shutdown(struct uart_port *u)
1215{
1216 struct mxs_auart_port *s = to_auart_port(u);
1217
1218 mxs_auart_disable_ms(u);
1219
1220 if (auart_dma_enabled(s))
1221 mxs_auart_dma_exit(s);
1222
1223 if (uart_console(u)) {
1224 mxs_clr(AUART_CTRL2_UARTEN, s, REG_CTRL2);
1225
1226 mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN |
1227 AUART_INTR_CTSMIEN, s, REG_INTR);
1228 mxs_set(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1229 } else {
1230 mxs_auart_reset_assert(s);
1231 }
1232
1233 clk_disable_unprepare(s->clk);
1234}
1235
1236static unsigned int mxs_auart_tx_empty(struct uart_port *u)
1237{
1238 struct mxs_auart_port *s = to_auart_port(u);
1239
1240 if ((mxs_read(s, REG_STAT) &
1241 (AUART_STAT_TXFE | AUART_STAT_BUSY)) == AUART_STAT_TXFE)
1242 return TIOCSER_TEMT;
1243
1244 return 0;
1245}
1246
1247static void mxs_auart_start_tx(struct uart_port *u)
1248{
1249 struct mxs_auart_port *s = to_auart_port(u);
1250
1251 /* enable transmitter */
1252 mxs_set(AUART_CTRL2_TXE, s, REG_CTRL2);
1253
1254 mxs_auart_tx_chars(s);
1255}
1256
1257static void mxs_auart_stop_tx(struct uart_port *u)
1258{
1259 struct mxs_auart_port *s = to_auart_port(u);
1260
1261 mxs_clr(AUART_CTRL2_TXE, s, REG_CTRL2);
1262}
1263
1264static void mxs_auart_stop_rx(struct uart_port *u)
1265{
1266 struct mxs_auart_port *s = to_auart_port(u);
1267
1268 mxs_clr(AUART_CTRL2_RXE, s, REG_CTRL2);
1269}
1270
1271static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
1272{
1273 struct mxs_auart_port *s = to_auart_port(u);
1274
1275 if (ctl)
1276 mxs_set(AUART_LINECTRL_BRK, s, REG_LINECTRL);
1277 else
1278 mxs_clr(AUART_LINECTRL_BRK, s, REG_LINECTRL);
1279}
1280
1281static const struct uart_ops mxs_auart_ops = {
1282 .tx_empty = mxs_auart_tx_empty,
1283 .start_tx = mxs_auart_start_tx,
1284 .stop_tx = mxs_auart_stop_tx,
1285 .stop_rx = mxs_auart_stop_rx,
1286 .enable_ms = mxs_auart_enable_ms,
1287 .break_ctl = mxs_auart_break_ctl,
1288 .set_mctrl = mxs_auart_set_mctrl,
1289 .get_mctrl = mxs_auart_get_mctrl,
1290 .startup = mxs_auart_startup,
1291 .shutdown = mxs_auart_shutdown,
1292 .set_termios = mxs_auart_settermios,
1293 .set_ldisc = mxs_auart_set_ldisc,
1294 .type = mxs_auart_type,
1295 .release_port = mxs_auart_release_port,
1296 .request_port = mxs_auart_request_port,
1297 .config_port = mxs_auart_config_port,
1298 .verify_port = mxs_auart_verify_port,
1299};
1300
1301static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
1302
1303#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
1304static void mxs_auart_console_putchar(struct uart_port *port, unsigned char ch)
1305{
1306 struct mxs_auart_port *s = to_auart_port(port);
1307 unsigned int to = 1000;
1308
1309 while (mxs_read(s, REG_STAT) & AUART_STAT_TXFF) {
1310 if (!to--)
1311 break;
1312 udelay(1);
1313 }
1314
1315 mxs_write(ch, s, REG_DATA);
1316}
1317
1318static void
1319auart_console_write(struct console *co, const char *str, unsigned int count)
1320{
1321 struct mxs_auart_port *s;
1322 struct uart_port *port;
1323 unsigned int old_ctrl0, old_ctrl2;
1324 unsigned int to = 20000;
1325
1326 if (co->index >= MXS_AUART_PORTS || co->index < 0)
1327 return;
1328
1329 s = auart_port[co->index];
1330 port = &s->port;
1331
1332 clk_enable(s->clk);
1333
1334 /* First save the CR then disable the interrupts */
1335 old_ctrl2 = mxs_read(s, REG_CTRL2);
1336 old_ctrl0 = mxs_read(s, REG_CTRL0);
1337
1338 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1339 mxs_set(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE, s, REG_CTRL2);
1340
1341 uart_console_write(port, str, count, mxs_auart_console_putchar);
1342
1343 /* Finally, wait for transmitter to become empty ... */
1344 while (mxs_read(s, REG_STAT) & AUART_STAT_BUSY) {
1345 udelay(1);
1346 if (!to--)
1347 break;
1348 }
1349
1350 /*
1351 * ... and restore the TCR if we waited long enough for the transmitter
1352 * to be idle. This might keep the transmitter enabled although it is
1353 * unused, but that is better than to disable it while it is still
1354 * transmitting.
1355 */
1356 if (!(mxs_read(s, REG_STAT) & AUART_STAT_BUSY)) {
1357 mxs_write(old_ctrl0, s, REG_CTRL0);
1358 mxs_write(old_ctrl2, s, REG_CTRL2);
1359 }
1360
1361 clk_disable(s->clk);
1362}
1363
1364static void __init
1365auart_console_get_options(struct mxs_auart_port *s, int *baud,
1366 int *parity, int *bits)
1367{
1368 struct uart_port *port = &s->port;
1369 unsigned int lcr_h, quot;
1370
1371 if (!(mxs_read(s, REG_CTRL2) & AUART_CTRL2_UARTEN))
1372 return;
1373
1374 lcr_h = mxs_read(s, REG_LINECTRL);
1375
1376 *parity = 'n';
1377 if (lcr_h & AUART_LINECTRL_PEN) {
1378 if (lcr_h & AUART_LINECTRL_EPS)
1379 *parity = 'e';
1380 else
1381 *parity = 'o';
1382 }
1383
1384 if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(7))
1385 *bits = 7;
1386 else
1387 *bits = 8;
1388
1389 quot = ((mxs_read(s, REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVINT_MASK))
1390 >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
1391 quot |= ((mxs_read(s, REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVFRAC_MASK))
1392 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
1393 if (quot == 0)
1394 quot = 1;
1395
1396 *baud = (port->uartclk << 2) / quot;
1397}
1398
1399static int __init
1400auart_console_setup(struct console *co, char *options)
1401{
1402 struct mxs_auart_port *s;
1403 int baud = 9600;
1404 int bits = 8;
1405 int parity = 'n';
1406 int flow = 'n';
1407 int ret;
1408
1409 /*
1410 * Check whether an invalid uart number has been specified, and
1411 * if so, search for the first available port that does have
1412 * console support.
1413 */
1414 if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
1415 co->index = 0;
1416 s = auart_port[co->index];
1417 if (!s)
1418 return -ENODEV;
1419
1420 ret = clk_prepare_enable(s->clk);
1421 if (ret)
1422 return ret;
1423
1424 if (options)
1425 uart_parse_options(options, &baud, &parity, &bits, &flow);
1426 else
1427 auart_console_get_options(s, &baud, &parity, &bits);
1428
1429 ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
1430
1431 clk_disable_unprepare(s->clk);
1432
1433 return ret;
1434}
1435
1436static struct console auart_console = {
1437 .name = "ttyAPP",
1438 .write = auart_console_write,
1439 .device = uart_console_device,
1440 .setup = auart_console_setup,
1441 .flags = CON_PRINTBUFFER,
1442 .index = -1,
1443 .data = &auart_driver,
1444};
1445#endif
1446
1447static struct uart_driver auart_driver = {
1448 .owner = THIS_MODULE,
1449 .driver_name = "ttyAPP",
1450 .dev_name = "ttyAPP",
1451 .major = 0,
1452 .minor = 0,
1453 .nr = MXS_AUART_PORTS,
1454#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
1455 .cons = &auart_console,
1456#endif
1457};
1458
1459static void mxs_init_regs(struct mxs_auart_port *s)
1460{
1461 if (is_asm9260_auart(s))
1462 s->vendor = &vendor_alphascale_asm9260;
1463 else
1464 s->vendor = &vendor_freescale_stmp37xx;
1465}
1466
1467static int mxs_get_clks(struct mxs_auart_port *s,
1468 struct platform_device *pdev)
1469{
1470 int err;
1471
1472 if (!is_asm9260_auart(s)) {
1473 s->clk = devm_clk_get(&pdev->dev, NULL);
1474 return PTR_ERR_OR_ZERO(s->clk);
1475 }
1476
1477 s->clk = devm_clk_get(s->dev, "mod");
1478 if (IS_ERR(s->clk)) {
1479 dev_err(s->dev, "Failed to get \"mod\" clk\n");
1480 return PTR_ERR(s->clk);
1481 }
1482
1483 s->clk_ahb = devm_clk_get(s->dev, "ahb");
1484 if (IS_ERR(s->clk_ahb)) {
1485 dev_err(s->dev, "Failed to get \"ahb\" clk\n");
1486 return PTR_ERR(s->clk_ahb);
1487 }
1488
1489 err = clk_prepare_enable(s->clk_ahb);
1490 if (err) {
1491 dev_err(s->dev, "Failed to enable ahb_clk!\n");
1492 return err;
1493 }
1494
1495 err = clk_set_rate(s->clk, clk_get_rate(s->clk_ahb));
1496 if (err) {
1497 dev_err(s->dev, "Failed to set rate!\n");
1498 goto disable_clk_ahb;
1499 }
1500
1501 err = clk_prepare_enable(s->clk);
1502 if (err) {
1503 dev_err(s->dev, "Failed to enable clk!\n");
1504 goto disable_clk_ahb;
1505 }
1506
1507 return 0;
1508
1509disable_clk_ahb:
1510 clk_disable_unprepare(s->clk_ahb);
1511 return err;
1512}
1513
1514static int mxs_auart_init_gpios(struct mxs_auart_port *s, struct device *dev)
1515{
1516 enum mctrl_gpio_idx i;
1517 struct gpio_desc *gpiod;
1518
1519 s->gpios = mctrl_gpio_init_noauto(dev, 0);
1520 if (IS_ERR(s->gpios))
1521 return PTR_ERR(s->gpios);
1522
1523 /* Block (enabled before) DMA option if RTS or CTS is GPIO line */
1524 if (!RTS_AT_AUART() || !CTS_AT_AUART()) {
1525 if (test_bit(MXS_AUART_RTSCTS, &s->flags))
1526 dev_warn(dev,
1527 "DMA and flow control via gpio may cause some problems. DMA disabled!\n");
1528 clear_bit(MXS_AUART_RTSCTS, &s->flags);
1529 }
1530
1531 for (i = 0; i < UART_GPIO_MAX; i++) {
1532 gpiod = mctrl_gpio_to_gpiod(s->gpios, i);
1533 if (gpiod && (gpiod_get_direction(gpiod) == 1))
1534 s->gpio_irq[i] = gpiod_to_irq(gpiod);
1535 else
1536 s->gpio_irq[i] = -EINVAL;
1537 }
1538
1539 return 0;
1540}
1541
1542static void mxs_auart_free_gpio_irq(struct mxs_auart_port *s)
1543{
1544 enum mctrl_gpio_idx i;
1545
1546 for (i = 0; i < UART_GPIO_MAX; i++)
1547 if (s->gpio_irq[i] >= 0)
1548 free_irq(s->gpio_irq[i], s);
1549}
1550
1551static int mxs_auart_request_gpio_irq(struct mxs_auart_port *s)
1552{
1553 int *irq = s->gpio_irq;
1554 enum mctrl_gpio_idx i;
1555 int err = 0;
1556
1557 for (i = 0; (i < UART_GPIO_MAX) && !err; i++) {
1558 if (irq[i] < 0)
1559 continue;
1560
1561 irq_set_status_flags(irq[i], IRQ_NOAUTOEN);
1562 err = request_irq(irq[i], mxs_auart_irq_handle,
1563 IRQ_TYPE_EDGE_BOTH, dev_name(s->dev), s);
1564 if (err)
1565 dev_err(s->dev, "%s - Can't get %d irq\n",
1566 __func__, irq[i]);
1567 }
1568
1569 /*
1570 * If something went wrong, rollback.
1571 * Be careful: i may be unsigned.
1572 */
1573 while (err && (i-- > 0))
1574 if (irq[i] >= 0)
1575 free_irq(irq[i], s);
1576
1577 return err;
1578}
1579
1580static int mxs_auart_probe(struct platform_device *pdev)
1581{
1582 struct device_node *np = pdev->dev.of_node;
1583 struct mxs_auart_port *s;
1584 u32 version;
1585 int ret, irq;
1586 struct resource *r;
1587
1588 s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL);
1589 if (!s)
1590 return -ENOMEM;
1591
1592 s->port.dev = &pdev->dev;
1593 s->dev = &pdev->dev;
1594
1595 ret = of_alias_get_id(np, "serial");
1596 if (ret < 0) {
1597 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);
1598 return ret;
1599 }
1600 s->port.line = ret;
1601
1602 if (of_property_read_bool(np, "uart-has-rtscts") ||
1603 of_property_read_bool(np, "fsl,uart-has-rtscts") /* deprecated */)
1604 set_bit(MXS_AUART_RTSCTS, &s->flags);
1605
1606 if (s->port.line >= ARRAY_SIZE(auart_port)) {
1607 dev_err(&pdev->dev, "serial%d out of range\n", s->port.line);
1608 return -EINVAL;
1609 }
1610
1611 s->devtype = (enum mxs_auart_type)of_device_get_match_data(&pdev->dev);
1612
1613 ret = mxs_get_clks(s, pdev);
1614 if (ret)
1615 return ret;
1616
1617 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1618 if (!r) {
1619 ret = -ENXIO;
1620 goto out_disable_clks;
1621 }
1622
1623 s->port.mapbase = r->start;
1624 s->port.membase = ioremap(r->start, resource_size(r));
1625 if (!s->port.membase) {
1626 ret = -ENOMEM;
1627 goto out_disable_clks;
1628 }
1629 s->port.ops = &mxs_auart_ops;
1630 s->port.iotype = UPIO_MEM;
1631 s->port.fifosize = MXS_AUART_FIFO_SIZE;
1632 s->port.uartclk = clk_get_rate(s->clk);
1633 s->port.type = PORT_IMX;
1634 s->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_MXS_AUART_CONSOLE);
1635
1636 mxs_init_regs(s);
1637
1638 s->mctrl_prev = 0;
1639
1640 irq = platform_get_irq(pdev, 0);
1641 if (irq < 0) {
1642 ret = irq;
1643 goto out_iounmap;
1644 }
1645
1646 s->port.irq = irq;
1647 ret = devm_request_irq(&pdev->dev, irq, mxs_auart_irq_handle, 0,
1648 dev_name(&pdev->dev), s);
1649 if (ret)
1650 goto out_iounmap;
1651
1652 platform_set_drvdata(pdev, s);
1653
1654 ret = mxs_auart_init_gpios(s, &pdev->dev);
1655 if (ret) {
1656 dev_err(&pdev->dev, "Failed to initialize GPIOs.\n");
1657 goto out_iounmap;
1658 }
1659
1660 /*
1661 * Get the GPIO lines IRQ
1662 */
1663 ret = mxs_auart_request_gpio_irq(s);
1664 if (ret)
1665 goto out_iounmap;
1666
1667 auart_port[s->port.line] = s;
1668
1669 mxs_auart_reset_deassert(s);
1670
1671 ret = uart_add_one_port(&auart_driver, &s->port);
1672 if (ret)
1673 goto out_free_qpio_irq;
1674
1675 /* ASM9260 don't have version reg */
1676 if (is_asm9260_auart(s)) {
1677 dev_info(&pdev->dev, "Found APPUART ASM9260\n");
1678 } else {
1679 version = mxs_read(s, REG_VERSION);
1680 dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
1681 (version >> 24) & 0xff,
1682 (version >> 16) & 0xff, version & 0xffff);
1683 }
1684
1685 return 0;
1686
1687out_free_qpio_irq:
1688 mxs_auart_free_gpio_irq(s);
1689 auart_port[pdev->id] = NULL;
1690
1691out_iounmap:
1692 iounmap(s->port.membase);
1693
1694out_disable_clks:
1695 if (is_asm9260_auart(s)) {
1696 clk_disable_unprepare(s->clk);
1697 clk_disable_unprepare(s->clk_ahb);
1698 }
1699 return ret;
1700}
1701
1702static void mxs_auart_remove(struct platform_device *pdev)
1703{
1704 struct mxs_auart_port *s = platform_get_drvdata(pdev);
1705
1706 uart_remove_one_port(&auart_driver, &s->port);
1707 auart_port[pdev->id] = NULL;
1708 mxs_auart_free_gpio_irq(s);
1709 iounmap(s->port.membase);
1710 if (is_asm9260_auart(s)) {
1711 clk_disable_unprepare(s->clk);
1712 clk_disable_unprepare(s->clk_ahb);
1713 }
1714}
1715
1716static struct platform_driver mxs_auart_driver = {
1717 .probe = mxs_auart_probe,
1718 .remove_new = mxs_auart_remove,
1719 .driver = {
1720 .name = "mxs-auart",
1721 .of_match_table = mxs_auart_dt_ids,
1722 },
1723};
1724
1725static int __init mxs_auart_init(void)
1726{
1727 int r;
1728
1729 r = uart_register_driver(&auart_driver);
1730 if (r)
1731 goto out;
1732
1733 r = platform_driver_register(&mxs_auart_driver);
1734 if (r)
1735 goto out_err;
1736
1737 return 0;
1738out_err:
1739 uart_unregister_driver(&auart_driver);
1740out:
1741 return r;
1742}
1743
1744static void __exit mxs_auart_exit(void)
1745{
1746 platform_driver_unregister(&mxs_auart_driver);
1747 uart_unregister_driver(&auart_driver);
1748}
1749
1750module_init(mxs_auart_init);
1751module_exit(mxs_auart_exit);
1752MODULE_LICENSE("GPL");
1753MODULE_DESCRIPTION("Freescale MXS application uart driver");
1754MODULE_ALIAS("platform:mxs-auart");