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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Driver for msm7k serial device and console
4 *
5 * Copyright (C) 2007 Google, Inc.
6 * Author: Robert Love <rlove@google.com>
7 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
8 */
9
10#if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
11# define SUPPORT_SYSRQ
12#endif
13
14#include <linux/kernel.h>
15#include <linux/atomic.h>
16#include <linux/dma-mapping.h>
17#include <linux/dmaengine.h>
18#include <linux/module.h>
19#include <linux/io.h>
20#include <linux/ioport.h>
21#include <linux/interrupt.h>
22#include <linux/init.h>
23#include <linux/console.h>
24#include <linux/tty.h>
25#include <linux/tty_flip.h>
26#include <linux/serial_core.h>
27#include <linux/slab.h>
28#include <linux/clk.h>
29#include <linux/platform_device.h>
30#include <linux/delay.h>
31#include <linux/of.h>
32#include <linux/of_device.h>
33#include <linux/wait.h>
34
35#define UART_MR1 0x0000
36
37#define UART_MR1_AUTO_RFR_LEVEL0 0x3F
38#define UART_MR1_AUTO_RFR_LEVEL1 0x3FF00
39#define UART_DM_MR1_AUTO_RFR_LEVEL1 0xFFFFFF00
40#define UART_MR1_RX_RDY_CTL BIT(7)
41#define UART_MR1_CTS_CTL BIT(6)
42
43#define UART_MR2 0x0004
44#define UART_MR2_ERROR_MODE BIT(6)
45#define UART_MR2_BITS_PER_CHAR 0x30
46#define UART_MR2_BITS_PER_CHAR_5 (0x0 << 4)
47#define UART_MR2_BITS_PER_CHAR_6 (0x1 << 4)
48#define UART_MR2_BITS_PER_CHAR_7 (0x2 << 4)
49#define UART_MR2_BITS_PER_CHAR_8 (0x3 << 4)
50#define UART_MR2_STOP_BIT_LEN_ONE (0x1 << 2)
51#define UART_MR2_STOP_BIT_LEN_TWO (0x3 << 2)
52#define UART_MR2_PARITY_MODE_NONE 0x0
53#define UART_MR2_PARITY_MODE_ODD 0x1
54#define UART_MR2_PARITY_MODE_EVEN 0x2
55#define UART_MR2_PARITY_MODE_SPACE 0x3
56#define UART_MR2_PARITY_MODE 0x3
57
58#define UART_CSR 0x0008
59
60#define UART_TF 0x000C
61#define UARTDM_TF 0x0070
62
63#define UART_CR 0x0010
64#define UART_CR_CMD_NULL (0 << 4)
65#define UART_CR_CMD_RESET_RX (1 << 4)
66#define UART_CR_CMD_RESET_TX (2 << 4)
67#define UART_CR_CMD_RESET_ERR (3 << 4)
68#define UART_CR_CMD_RESET_BREAK_INT (4 << 4)
69#define UART_CR_CMD_START_BREAK (5 << 4)
70#define UART_CR_CMD_STOP_BREAK (6 << 4)
71#define UART_CR_CMD_RESET_CTS (7 << 4)
72#define UART_CR_CMD_RESET_STALE_INT (8 << 4)
73#define UART_CR_CMD_PACKET_MODE (9 << 4)
74#define UART_CR_CMD_MODE_RESET (12 << 4)
75#define UART_CR_CMD_SET_RFR (13 << 4)
76#define UART_CR_CMD_RESET_RFR (14 << 4)
77#define UART_CR_CMD_PROTECTION_EN (16 << 4)
78#define UART_CR_CMD_STALE_EVENT_DISABLE (6 << 8)
79#define UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4)
80#define UART_CR_CMD_FORCE_STALE (4 << 8)
81#define UART_CR_CMD_RESET_TX_READY (3 << 8)
82#define UART_CR_TX_DISABLE BIT(3)
83#define UART_CR_TX_ENABLE BIT(2)
84#define UART_CR_RX_DISABLE BIT(1)
85#define UART_CR_RX_ENABLE BIT(0)
86#define UART_CR_CMD_RESET_RXBREAK_START ((1 << 11) | (2 << 4))
87
88#define UART_IMR 0x0014
89#define UART_IMR_TXLEV BIT(0)
90#define UART_IMR_RXSTALE BIT(3)
91#define UART_IMR_RXLEV BIT(4)
92#define UART_IMR_DELTA_CTS BIT(5)
93#define UART_IMR_CURRENT_CTS BIT(6)
94#define UART_IMR_RXBREAK_START BIT(10)
95
96#define UART_IPR_RXSTALE_LAST 0x20
97#define UART_IPR_STALE_LSB 0x1F
98#define UART_IPR_STALE_TIMEOUT_MSB 0x3FF80
99#define UART_DM_IPR_STALE_TIMEOUT_MSB 0xFFFFFF80
100
101#define UART_IPR 0x0018
102#define UART_TFWR 0x001C
103#define UART_RFWR 0x0020
104#define UART_HCR 0x0024
105
106#define UART_MREG 0x0028
107#define UART_NREG 0x002C
108#define UART_DREG 0x0030
109#define UART_MNDREG 0x0034
110#define UART_IRDA 0x0038
111#define UART_MISR_MODE 0x0040
112#define UART_MISR_RESET 0x0044
113#define UART_MISR_EXPORT 0x0048
114#define UART_MISR_VAL 0x004C
115#define UART_TEST_CTRL 0x0050
116
117#define UART_SR 0x0008
118#define UART_SR_HUNT_CHAR BIT(7)
119#define UART_SR_RX_BREAK BIT(6)
120#define UART_SR_PAR_FRAME_ERR BIT(5)
121#define UART_SR_OVERRUN BIT(4)
122#define UART_SR_TX_EMPTY BIT(3)
123#define UART_SR_TX_READY BIT(2)
124#define UART_SR_RX_FULL BIT(1)
125#define UART_SR_RX_READY BIT(0)
126
127#define UART_RF 0x000C
128#define UARTDM_RF 0x0070
129#define UART_MISR 0x0010
130#define UART_ISR 0x0014
131#define UART_ISR_TX_READY BIT(7)
132
133#define UARTDM_RXFS 0x50
134#define UARTDM_RXFS_BUF_SHIFT 0x7
135#define UARTDM_RXFS_BUF_MASK 0x7
136
137#define UARTDM_DMEN 0x3C
138#define UARTDM_DMEN_RX_SC_ENABLE BIT(5)
139#define UARTDM_DMEN_TX_SC_ENABLE BIT(4)
140
141#define UARTDM_DMEN_TX_BAM_ENABLE BIT(2) /* UARTDM_1P4 */
142#define UARTDM_DMEN_TX_DM_ENABLE BIT(0) /* < UARTDM_1P4 */
143
144#define UARTDM_DMEN_RX_BAM_ENABLE BIT(3) /* UARTDM_1P4 */
145#define UARTDM_DMEN_RX_DM_ENABLE BIT(1) /* < UARTDM_1P4 */
146
147#define UARTDM_DMRX 0x34
148#define UARTDM_NCF_TX 0x40
149#define UARTDM_RX_TOTAL_SNAP 0x38
150
151#define UARTDM_BURST_SIZE 16 /* in bytes */
152#define UARTDM_TX_AIGN(x) ((x) & ~0x3) /* valid for > 1p3 */
153#define UARTDM_TX_MAX 256 /* in bytes, valid for <= 1p3 */
154#define UARTDM_RX_SIZE (UART_XMIT_SIZE / 4)
155
156enum {
157 UARTDM_1P1 = 1,
158 UARTDM_1P2,
159 UARTDM_1P3,
160 UARTDM_1P4,
161};
162
163struct msm_dma {
164 struct dma_chan *chan;
165 enum dma_data_direction dir;
166 dma_addr_t phys;
167 unsigned char *virt;
168 dma_cookie_t cookie;
169 u32 enable_bit;
170 unsigned int count;
171 struct dma_async_tx_descriptor *desc;
172};
173
174struct msm_port {
175 struct uart_port uart;
176 char name[16];
177 struct clk *clk;
178 struct clk *pclk;
179 unsigned int imr;
180 int is_uartdm;
181 unsigned int old_snap_state;
182 bool break_detected;
183 struct msm_dma tx_dma;
184 struct msm_dma rx_dma;
185};
186
187#define UART_TO_MSM(uart_port) container_of(uart_port, struct msm_port, uart)
188
189static
190void msm_write(struct uart_port *port, unsigned int val, unsigned int off)
191{
192 writel_relaxed(val, port->membase + off);
193}
194
195static
196unsigned int msm_read(struct uart_port *port, unsigned int off)
197{
198 return readl_relaxed(port->membase + off);
199}
200
201/*
202 * Setup the MND registers to use the TCXO clock.
203 */
204static void msm_serial_set_mnd_regs_tcxo(struct uart_port *port)
205{
206 msm_write(port, 0x06, UART_MREG);
207 msm_write(port, 0xF1, UART_NREG);
208 msm_write(port, 0x0F, UART_DREG);
209 msm_write(port, 0x1A, UART_MNDREG);
210 port->uartclk = 1843200;
211}
212
213/*
214 * Setup the MND registers to use the TCXO clock divided by 4.
215 */
216static void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port)
217{
218 msm_write(port, 0x18, UART_MREG);
219 msm_write(port, 0xF6, UART_NREG);
220 msm_write(port, 0x0F, UART_DREG);
221 msm_write(port, 0x0A, UART_MNDREG);
222 port->uartclk = 1843200;
223}
224
225static void msm_serial_set_mnd_regs(struct uart_port *port)
226{
227 struct msm_port *msm_port = UART_TO_MSM(port);
228
229 /*
230 * These registers don't exist so we change the clk input rate
231 * on uartdm hardware instead
232 */
233 if (msm_port->is_uartdm)
234 return;
235
236 if (port->uartclk == 19200000)
237 msm_serial_set_mnd_regs_tcxo(port);
238 else if (port->uartclk == 4800000)
239 msm_serial_set_mnd_regs_tcxoby4(port);
240}
241
242static void msm_handle_tx(struct uart_port *port);
243static void msm_start_rx_dma(struct msm_port *msm_port);
244
245static void msm_stop_dma(struct uart_port *port, struct msm_dma *dma)
246{
247 struct device *dev = port->dev;
248 unsigned int mapped;
249 u32 val;
250
251 mapped = dma->count;
252 dma->count = 0;
253
254 dmaengine_terminate_all(dma->chan);
255
256 /*
257 * DMA Stall happens if enqueue and flush command happens concurrently.
258 * For example before changing the baud rate/protocol configuration and
259 * sending flush command to ADM, disable the channel of UARTDM.
260 * Note: should not reset the receiver here immediately as it is not
261 * suggested to do disable/reset or reset/disable at the same time.
262 */
263 val = msm_read(port, UARTDM_DMEN);
264 val &= ~dma->enable_bit;
265 msm_write(port, val, UARTDM_DMEN);
266
267 if (mapped)
268 dma_unmap_single(dev, dma->phys, mapped, dma->dir);
269}
270
271static void msm_release_dma(struct msm_port *msm_port)
272{
273 struct msm_dma *dma;
274
275 dma = &msm_port->tx_dma;
276 if (dma->chan) {
277 msm_stop_dma(&msm_port->uart, dma);
278 dma_release_channel(dma->chan);
279 }
280
281 memset(dma, 0, sizeof(*dma));
282
283 dma = &msm_port->rx_dma;
284 if (dma->chan) {
285 msm_stop_dma(&msm_port->uart, dma);
286 dma_release_channel(dma->chan);
287 kfree(dma->virt);
288 }
289
290 memset(dma, 0, sizeof(*dma));
291}
292
293static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base)
294{
295 struct device *dev = msm_port->uart.dev;
296 struct dma_slave_config conf;
297 struct msm_dma *dma;
298 u32 crci = 0;
299 int ret;
300
301 dma = &msm_port->tx_dma;
302
303 /* allocate DMA resources, if available */
304 dma->chan = dma_request_slave_channel_reason(dev, "tx");
305 if (IS_ERR(dma->chan))
306 goto no_tx;
307
308 of_property_read_u32(dev->of_node, "qcom,tx-crci", &crci);
309
310 memset(&conf, 0, sizeof(conf));
311 conf.direction = DMA_MEM_TO_DEV;
312 conf.device_fc = true;
313 conf.dst_addr = base + UARTDM_TF;
314 conf.dst_maxburst = UARTDM_BURST_SIZE;
315 conf.slave_id = crci;
316
317 ret = dmaengine_slave_config(dma->chan, &conf);
318 if (ret)
319 goto rel_tx;
320
321 dma->dir = DMA_TO_DEVICE;
322
323 if (msm_port->is_uartdm < UARTDM_1P4)
324 dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE;
325 else
326 dma->enable_bit = UARTDM_DMEN_TX_BAM_ENABLE;
327
328 return;
329
330rel_tx:
331 dma_release_channel(dma->chan);
332no_tx:
333 memset(dma, 0, sizeof(*dma));
334}
335
336static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base)
337{
338 struct device *dev = msm_port->uart.dev;
339 struct dma_slave_config conf;
340 struct msm_dma *dma;
341 u32 crci = 0;
342 int ret;
343
344 dma = &msm_port->rx_dma;
345
346 /* allocate DMA resources, if available */
347 dma->chan = dma_request_slave_channel_reason(dev, "rx");
348 if (IS_ERR(dma->chan))
349 goto no_rx;
350
351 of_property_read_u32(dev->of_node, "qcom,rx-crci", &crci);
352
353 dma->virt = kzalloc(UARTDM_RX_SIZE, GFP_KERNEL);
354 if (!dma->virt)
355 goto rel_rx;
356
357 memset(&conf, 0, sizeof(conf));
358 conf.direction = DMA_DEV_TO_MEM;
359 conf.device_fc = true;
360 conf.src_addr = base + UARTDM_RF;
361 conf.src_maxburst = UARTDM_BURST_SIZE;
362 conf.slave_id = crci;
363
364 ret = dmaengine_slave_config(dma->chan, &conf);
365 if (ret)
366 goto err;
367
368 dma->dir = DMA_FROM_DEVICE;
369
370 if (msm_port->is_uartdm < UARTDM_1P4)
371 dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE;
372 else
373 dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE;
374
375 return;
376err:
377 kfree(dma->virt);
378rel_rx:
379 dma_release_channel(dma->chan);
380no_rx:
381 memset(dma, 0, sizeof(*dma));
382}
383
384static inline void msm_wait_for_xmitr(struct uart_port *port)
385{
386 unsigned int timeout = 500000;
387
388 while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {
389 if (msm_read(port, UART_ISR) & UART_ISR_TX_READY)
390 break;
391 udelay(1);
392 if (!timeout--)
393 break;
394 }
395 msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);
396}
397
398static void msm_stop_tx(struct uart_port *port)
399{
400 struct msm_port *msm_port = UART_TO_MSM(port);
401
402 msm_port->imr &= ~UART_IMR_TXLEV;
403 msm_write(port, msm_port->imr, UART_IMR);
404}
405
406static void msm_start_tx(struct uart_port *port)
407{
408 struct msm_port *msm_port = UART_TO_MSM(port);
409 struct msm_dma *dma = &msm_port->tx_dma;
410
411 /* Already started in DMA mode */
412 if (dma->count)
413 return;
414
415 msm_port->imr |= UART_IMR_TXLEV;
416 msm_write(port, msm_port->imr, UART_IMR);
417}
418
419static void msm_reset_dm_count(struct uart_port *port, int count)
420{
421 msm_wait_for_xmitr(port);
422 msm_write(port, count, UARTDM_NCF_TX);
423 msm_read(port, UARTDM_NCF_TX);
424}
425
426static void msm_complete_tx_dma(void *args)
427{
428 struct msm_port *msm_port = args;
429 struct uart_port *port = &msm_port->uart;
430 struct circ_buf *xmit = &port->state->xmit;
431 struct msm_dma *dma = &msm_port->tx_dma;
432 struct dma_tx_state state;
433 enum dma_status status;
434 unsigned long flags;
435 unsigned int count;
436 u32 val;
437
438 spin_lock_irqsave(&port->lock, flags);
439
440 /* Already stopped */
441 if (!dma->count)
442 goto done;
443
444 status = dmaengine_tx_status(dma->chan, dma->cookie, &state);
445
446 dma_unmap_single(port->dev, dma->phys, dma->count, dma->dir);
447
448 val = msm_read(port, UARTDM_DMEN);
449 val &= ~dma->enable_bit;
450 msm_write(port, val, UARTDM_DMEN);
451
452 if (msm_port->is_uartdm > UARTDM_1P3) {
453 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
454 msm_write(port, UART_CR_TX_ENABLE, UART_CR);
455 }
456
457 count = dma->count - state.residue;
458 port->icount.tx += count;
459 dma->count = 0;
460
461 xmit->tail += count;
462 xmit->tail &= UART_XMIT_SIZE - 1;
463
464 /* Restore "Tx FIFO below watermark" interrupt */
465 msm_port->imr |= UART_IMR_TXLEV;
466 msm_write(port, msm_port->imr, UART_IMR);
467
468 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
469 uart_write_wakeup(port);
470
471 msm_handle_tx(port);
472done:
473 spin_unlock_irqrestore(&port->lock, flags);
474}
475
476static int msm_handle_tx_dma(struct msm_port *msm_port, unsigned int count)
477{
478 struct circ_buf *xmit = &msm_port->uart.state->xmit;
479 struct uart_port *port = &msm_port->uart;
480 struct msm_dma *dma = &msm_port->tx_dma;
481 void *cpu_addr;
482 int ret;
483 u32 val;
484
485 cpu_addr = &xmit->buf[xmit->tail];
486
487 dma->phys = dma_map_single(port->dev, cpu_addr, count, dma->dir);
488 ret = dma_mapping_error(port->dev, dma->phys);
489 if (ret)
490 return ret;
491
492 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
493 count, DMA_MEM_TO_DEV,
494 DMA_PREP_INTERRUPT |
495 DMA_PREP_FENCE);
496 if (!dma->desc) {
497 ret = -EIO;
498 goto unmap;
499 }
500
501 dma->desc->callback = msm_complete_tx_dma;
502 dma->desc->callback_param = msm_port;
503
504 dma->cookie = dmaengine_submit(dma->desc);
505 ret = dma_submit_error(dma->cookie);
506 if (ret)
507 goto unmap;
508
509 /*
510 * Using DMA complete for Tx FIFO reload, no need for
511 * "Tx FIFO below watermark" one, disable it
512 */
513 msm_port->imr &= ~UART_IMR_TXLEV;
514 msm_write(port, msm_port->imr, UART_IMR);
515
516 dma->count = count;
517
518 val = msm_read(port, UARTDM_DMEN);
519 val |= dma->enable_bit;
520
521 if (msm_port->is_uartdm < UARTDM_1P4)
522 msm_write(port, val, UARTDM_DMEN);
523
524 msm_reset_dm_count(port, count);
525
526 if (msm_port->is_uartdm > UARTDM_1P3)
527 msm_write(port, val, UARTDM_DMEN);
528
529 dma_async_issue_pending(dma->chan);
530 return 0;
531unmap:
532 dma_unmap_single(port->dev, dma->phys, count, dma->dir);
533 return ret;
534}
535
536static void msm_complete_rx_dma(void *args)
537{
538 struct msm_port *msm_port = args;
539 struct uart_port *port = &msm_port->uart;
540 struct tty_port *tport = &port->state->port;
541 struct msm_dma *dma = &msm_port->rx_dma;
542 int count = 0, i, sysrq;
543 unsigned long flags;
544 u32 val;
545
546 spin_lock_irqsave(&port->lock, flags);
547
548 /* Already stopped */
549 if (!dma->count)
550 goto done;
551
552 val = msm_read(port, UARTDM_DMEN);
553 val &= ~dma->enable_bit;
554 msm_write(port, val, UARTDM_DMEN);
555
556 if (msm_read(port, UART_SR) & UART_SR_OVERRUN) {
557 port->icount.overrun++;
558 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
559 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
560 }
561
562 count = msm_read(port, UARTDM_RX_TOTAL_SNAP);
563
564 port->icount.rx += count;
565
566 dma->count = 0;
567
568 dma_unmap_single(port->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
569
570 for (i = 0; i < count; i++) {
571 char flag = TTY_NORMAL;
572
573 if (msm_port->break_detected && dma->virt[i] == 0) {
574 port->icount.brk++;
575 flag = TTY_BREAK;
576 msm_port->break_detected = false;
577 if (uart_handle_break(port))
578 continue;
579 }
580
581 if (!(port->read_status_mask & UART_SR_RX_BREAK))
582 flag = TTY_NORMAL;
583
584 spin_unlock_irqrestore(&port->lock, flags);
585 sysrq = uart_handle_sysrq_char(port, dma->virt[i]);
586 spin_lock_irqsave(&port->lock, flags);
587 if (!sysrq)
588 tty_insert_flip_char(tport, dma->virt[i], flag);
589 }
590
591 msm_start_rx_dma(msm_port);
592done:
593 spin_unlock_irqrestore(&port->lock, flags);
594
595 if (count)
596 tty_flip_buffer_push(tport);
597}
598
599static void msm_start_rx_dma(struct msm_port *msm_port)
600{
601 struct msm_dma *dma = &msm_port->rx_dma;
602 struct uart_port *uart = &msm_port->uart;
603 u32 val;
604 int ret;
605
606 if (!dma->chan)
607 return;
608
609 dma->phys = dma_map_single(uart->dev, dma->virt,
610 UARTDM_RX_SIZE, dma->dir);
611 ret = dma_mapping_error(uart->dev, dma->phys);
612 if (ret)
613 return;
614
615 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
616 UARTDM_RX_SIZE, DMA_DEV_TO_MEM,
617 DMA_PREP_INTERRUPT);
618 if (!dma->desc)
619 goto unmap;
620
621 dma->desc->callback = msm_complete_rx_dma;
622 dma->desc->callback_param = msm_port;
623
624 dma->cookie = dmaengine_submit(dma->desc);
625 ret = dma_submit_error(dma->cookie);
626 if (ret)
627 goto unmap;
628 /*
629 * Using DMA for FIFO off-load, no need for "Rx FIFO over
630 * watermark" or "stale" interrupts, disable them
631 */
632 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
633
634 /*
635 * Well, when DMA is ADM3 engine(implied by <= UARTDM v1.3),
636 * we need RXSTALE to flush input DMA fifo to memory
637 */
638 if (msm_port->is_uartdm < UARTDM_1P4)
639 msm_port->imr |= UART_IMR_RXSTALE;
640
641 msm_write(uart, msm_port->imr, UART_IMR);
642
643 dma->count = UARTDM_RX_SIZE;
644
645 dma_async_issue_pending(dma->chan);
646
647 msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR);
648 msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
649
650 val = msm_read(uart, UARTDM_DMEN);
651 val |= dma->enable_bit;
652
653 if (msm_port->is_uartdm < UARTDM_1P4)
654 msm_write(uart, val, UARTDM_DMEN);
655
656 msm_write(uart, UARTDM_RX_SIZE, UARTDM_DMRX);
657
658 if (msm_port->is_uartdm > UARTDM_1P3)
659 msm_write(uart, val, UARTDM_DMEN);
660
661 return;
662unmap:
663 dma_unmap_single(uart->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
664}
665
666static void msm_stop_rx(struct uart_port *port)
667{
668 struct msm_port *msm_port = UART_TO_MSM(port);
669 struct msm_dma *dma = &msm_port->rx_dma;
670
671 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
672 msm_write(port, msm_port->imr, UART_IMR);
673
674 if (dma->chan)
675 msm_stop_dma(port, dma);
676}
677
678static void msm_enable_ms(struct uart_port *port)
679{
680 struct msm_port *msm_port = UART_TO_MSM(port);
681
682 msm_port->imr |= UART_IMR_DELTA_CTS;
683 msm_write(port, msm_port->imr, UART_IMR);
684}
685
686static void msm_handle_rx_dm(struct uart_port *port, unsigned int misr)
687{
688 struct tty_port *tport = &port->state->port;
689 unsigned int sr;
690 int count = 0;
691 struct msm_port *msm_port = UART_TO_MSM(port);
692
693 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
694 port->icount.overrun++;
695 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
696 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
697 }
698
699 if (misr & UART_IMR_RXSTALE) {
700 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
701 msm_port->old_snap_state;
702 msm_port->old_snap_state = 0;
703 } else {
704 count = 4 * (msm_read(port, UART_RFWR));
705 msm_port->old_snap_state += count;
706 }
707
708 /* TODO: Precise error reporting */
709
710 port->icount.rx += count;
711
712 while (count > 0) {
713 unsigned char buf[4];
714 int sysrq, r_count, i;
715
716 sr = msm_read(port, UART_SR);
717 if ((sr & UART_SR_RX_READY) == 0) {
718 msm_port->old_snap_state -= count;
719 break;
720 }
721
722 ioread32_rep(port->membase + UARTDM_RF, buf, 1);
723 r_count = min_t(int, count, sizeof(buf));
724
725 for (i = 0; i < r_count; i++) {
726 char flag = TTY_NORMAL;
727
728 if (msm_port->break_detected && buf[i] == 0) {
729 port->icount.brk++;
730 flag = TTY_BREAK;
731 msm_port->break_detected = false;
732 if (uart_handle_break(port))
733 continue;
734 }
735
736 if (!(port->read_status_mask & UART_SR_RX_BREAK))
737 flag = TTY_NORMAL;
738
739 spin_unlock(&port->lock);
740 sysrq = uart_handle_sysrq_char(port, buf[i]);
741 spin_lock(&port->lock);
742 if (!sysrq)
743 tty_insert_flip_char(tport, buf[i], flag);
744 }
745 count -= r_count;
746 }
747
748 spin_unlock(&port->lock);
749 tty_flip_buffer_push(tport);
750 spin_lock(&port->lock);
751
752 if (misr & (UART_IMR_RXSTALE))
753 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
754 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
755 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
756
757 /* Try to use DMA */
758 msm_start_rx_dma(msm_port);
759}
760
761static void msm_handle_rx(struct uart_port *port)
762{
763 struct tty_port *tport = &port->state->port;
764 unsigned int sr;
765
766 /*
767 * Handle overrun. My understanding of the hardware is that overrun
768 * is not tied to the RX buffer, so we handle the case out of band.
769 */
770 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
771 port->icount.overrun++;
772 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
773 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
774 }
775
776 /* and now the main RX loop */
777 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
778 unsigned int c;
779 char flag = TTY_NORMAL;
780 int sysrq;
781
782 c = msm_read(port, UART_RF);
783
784 if (sr & UART_SR_RX_BREAK) {
785 port->icount.brk++;
786 if (uart_handle_break(port))
787 continue;
788 } else if (sr & UART_SR_PAR_FRAME_ERR) {
789 port->icount.frame++;
790 } else {
791 port->icount.rx++;
792 }
793
794 /* Mask conditions we're ignorning. */
795 sr &= port->read_status_mask;
796
797 if (sr & UART_SR_RX_BREAK)
798 flag = TTY_BREAK;
799 else if (sr & UART_SR_PAR_FRAME_ERR)
800 flag = TTY_FRAME;
801
802 spin_unlock(&port->lock);
803 sysrq = uart_handle_sysrq_char(port, c);
804 spin_lock(&port->lock);
805 if (!sysrq)
806 tty_insert_flip_char(tport, c, flag);
807 }
808
809 spin_unlock(&port->lock);
810 tty_flip_buffer_push(tport);
811 spin_lock(&port->lock);
812}
813
814static void msm_handle_tx_pio(struct uart_port *port, unsigned int tx_count)
815{
816 struct circ_buf *xmit = &port->state->xmit;
817 struct msm_port *msm_port = UART_TO_MSM(port);
818 unsigned int num_chars;
819 unsigned int tf_pointer = 0;
820 void __iomem *tf;
821
822 if (msm_port->is_uartdm)
823 tf = port->membase + UARTDM_TF;
824 else
825 tf = port->membase + UART_TF;
826
827 if (tx_count && msm_port->is_uartdm)
828 msm_reset_dm_count(port, tx_count);
829
830 while (tf_pointer < tx_count) {
831 int i;
832 char buf[4] = { 0 };
833
834 if (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
835 break;
836
837 if (msm_port->is_uartdm)
838 num_chars = min(tx_count - tf_pointer,
839 (unsigned int)sizeof(buf));
840 else
841 num_chars = 1;
842
843 for (i = 0; i < num_chars; i++) {
844 buf[i] = xmit->buf[xmit->tail + i];
845 port->icount.tx++;
846 }
847
848 iowrite32_rep(tf, buf, 1);
849 xmit->tail = (xmit->tail + num_chars) & (UART_XMIT_SIZE - 1);
850 tf_pointer += num_chars;
851 }
852
853 /* disable tx interrupts if nothing more to send */
854 if (uart_circ_empty(xmit))
855 msm_stop_tx(port);
856
857 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
858 uart_write_wakeup(port);
859}
860
861static void msm_handle_tx(struct uart_port *port)
862{
863 struct msm_port *msm_port = UART_TO_MSM(port);
864 struct circ_buf *xmit = &msm_port->uart.state->xmit;
865 struct msm_dma *dma = &msm_port->tx_dma;
866 unsigned int pio_count, dma_count, dma_min;
867 char buf[4] = { 0 };
868 void __iomem *tf;
869 int err = 0;
870
871 if (port->x_char) {
872 if (msm_port->is_uartdm)
873 tf = port->membase + UARTDM_TF;
874 else
875 tf = port->membase + UART_TF;
876
877 buf[0] = port->x_char;
878
879 if (msm_port->is_uartdm)
880 msm_reset_dm_count(port, 1);
881
882 iowrite32_rep(tf, buf, 1);
883 port->icount.tx++;
884 port->x_char = 0;
885 return;
886 }
887
888 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
889 msm_stop_tx(port);
890 return;
891 }
892
893 pio_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
894 dma_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
895
896 dma_min = 1; /* Always DMA */
897 if (msm_port->is_uartdm > UARTDM_1P3) {
898 dma_count = UARTDM_TX_AIGN(dma_count);
899 dma_min = UARTDM_BURST_SIZE;
900 } else {
901 if (dma_count > UARTDM_TX_MAX)
902 dma_count = UARTDM_TX_MAX;
903 }
904
905 if (pio_count > port->fifosize)
906 pio_count = port->fifosize;
907
908 if (!dma->chan || dma_count < dma_min)
909 msm_handle_tx_pio(port, pio_count);
910 else
911 err = msm_handle_tx_dma(msm_port, dma_count);
912
913 if (err) /* fall back to PIO mode */
914 msm_handle_tx_pio(port, pio_count);
915}
916
917static void msm_handle_delta_cts(struct uart_port *port)
918{
919 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
920 port->icount.cts++;
921 wake_up_interruptible(&port->state->port.delta_msr_wait);
922}
923
924static irqreturn_t msm_uart_irq(int irq, void *dev_id)
925{
926 struct uart_port *port = dev_id;
927 struct msm_port *msm_port = UART_TO_MSM(port);
928 struct msm_dma *dma = &msm_port->rx_dma;
929 unsigned long flags;
930 unsigned int misr;
931 u32 val;
932
933 spin_lock_irqsave(&port->lock, flags);
934 misr = msm_read(port, UART_MISR);
935 msm_write(port, 0, UART_IMR); /* disable interrupt */
936
937 if (misr & UART_IMR_RXBREAK_START) {
938 msm_port->break_detected = true;
939 msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR);
940 }
941
942 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
943 if (dma->count) {
944 val = UART_CR_CMD_STALE_EVENT_DISABLE;
945 msm_write(port, val, UART_CR);
946 val = UART_CR_CMD_RESET_STALE_INT;
947 msm_write(port, val, UART_CR);
948 /*
949 * Flush DMA input fifo to memory, this will also
950 * trigger DMA RX completion
951 */
952 dmaengine_terminate_all(dma->chan);
953 } else if (msm_port->is_uartdm) {
954 msm_handle_rx_dm(port, misr);
955 } else {
956 msm_handle_rx(port);
957 }
958 }
959 if (misr & UART_IMR_TXLEV)
960 msm_handle_tx(port);
961 if (misr & UART_IMR_DELTA_CTS)
962 msm_handle_delta_cts(port);
963
964 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
965 spin_unlock_irqrestore(&port->lock, flags);
966
967 return IRQ_HANDLED;
968}
969
970static unsigned int msm_tx_empty(struct uart_port *port)
971{
972 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
973}
974
975static unsigned int msm_get_mctrl(struct uart_port *port)
976{
977 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
978}
979
980static void msm_reset(struct uart_port *port)
981{
982 struct msm_port *msm_port = UART_TO_MSM(port);
983
984 /* reset everything */
985 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
986 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
987 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
988 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
989 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
990 msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);
991
992 /* Disable DM modes */
993 if (msm_port->is_uartdm)
994 msm_write(port, 0, UARTDM_DMEN);
995}
996
997static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
998{
999 unsigned int mr;
1000
1001 mr = msm_read(port, UART_MR1);
1002
1003 if (!(mctrl & TIOCM_RTS)) {
1004 mr &= ~UART_MR1_RX_RDY_CTL;
1005 msm_write(port, mr, UART_MR1);
1006 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
1007 } else {
1008 mr |= UART_MR1_RX_RDY_CTL;
1009 msm_write(port, mr, UART_MR1);
1010 }
1011}
1012
1013static void msm_break_ctl(struct uart_port *port, int break_ctl)
1014{
1015 if (break_ctl)
1016 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
1017 else
1018 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
1019}
1020
1021struct msm_baud_map {
1022 u16 divisor;
1023 u8 code;
1024 u8 rxstale;
1025};
1026
1027static const struct msm_baud_map *
1028msm_find_best_baud(struct uart_port *port, unsigned int baud,
1029 unsigned long *rate)
1030{
1031 struct msm_port *msm_port = UART_TO_MSM(port);
1032 unsigned int divisor, result;
1033 unsigned long target, old, best_rate = 0, diff, best_diff = ULONG_MAX;
1034 const struct msm_baud_map *entry, *end, *best;
1035 static const struct msm_baud_map table[] = {
1036 { 1, 0xff, 31 },
1037 { 2, 0xee, 16 },
1038 { 3, 0xdd, 8 },
1039 { 4, 0xcc, 6 },
1040 { 6, 0xbb, 6 },
1041 { 8, 0xaa, 6 },
1042 { 12, 0x99, 6 },
1043 { 16, 0x88, 1 },
1044 { 24, 0x77, 1 },
1045 { 32, 0x66, 1 },
1046 { 48, 0x55, 1 },
1047 { 96, 0x44, 1 },
1048 { 192, 0x33, 1 },
1049 { 384, 0x22, 1 },
1050 { 768, 0x11, 1 },
1051 { 1536, 0x00, 1 },
1052 };
1053
1054 best = table; /* Default to smallest divider */
1055 target = clk_round_rate(msm_port->clk, 16 * baud);
1056 divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
1057
1058 end = table + ARRAY_SIZE(table);
1059 entry = table;
1060 while (entry < end) {
1061 if (entry->divisor <= divisor) {
1062 result = target / entry->divisor / 16;
1063 diff = abs(result - baud);
1064
1065 /* Keep track of best entry */
1066 if (diff < best_diff) {
1067 best_diff = diff;
1068 best = entry;
1069 best_rate = target;
1070 }
1071
1072 if (result == baud)
1073 break;
1074 } else if (entry->divisor > divisor) {
1075 old = target;
1076 target = clk_round_rate(msm_port->clk, old + 1);
1077 /*
1078 * The rate didn't get any faster so we can't do
1079 * better at dividing it down
1080 */
1081 if (target == old)
1082 break;
1083
1084 /* Start the divisor search over at this new rate */
1085 entry = table;
1086 divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
1087 continue;
1088 }
1089 entry++;
1090 }
1091
1092 *rate = best_rate;
1093 return best;
1094}
1095
1096static int msm_set_baud_rate(struct uart_port *port, unsigned int baud,
1097 unsigned long *saved_flags)
1098{
1099 unsigned int rxstale, watermark, mask;
1100 struct msm_port *msm_port = UART_TO_MSM(port);
1101 const struct msm_baud_map *entry;
1102 unsigned long flags, rate;
1103
1104 flags = *saved_flags;
1105 spin_unlock_irqrestore(&port->lock, flags);
1106
1107 entry = msm_find_best_baud(port, baud, &rate);
1108 clk_set_rate(msm_port->clk, rate);
1109 baud = rate / 16 / entry->divisor;
1110
1111 spin_lock_irqsave(&port->lock, flags);
1112 *saved_flags = flags;
1113 port->uartclk = rate;
1114
1115 msm_write(port, entry->code, UART_CSR);
1116
1117 /* RX stale watermark */
1118 rxstale = entry->rxstale;
1119 watermark = UART_IPR_STALE_LSB & rxstale;
1120 if (msm_port->is_uartdm) {
1121 mask = UART_DM_IPR_STALE_TIMEOUT_MSB;
1122 } else {
1123 watermark |= UART_IPR_RXSTALE_LAST;
1124 mask = UART_IPR_STALE_TIMEOUT_MSB;
1125 }
1126
1127 watermark |= mask & (rxstale << 2);
1128
1129 msm_write(port, watermark, UART_IPR);
1130
1131 /* set RX watermark */
1132 watermark = (port->fifosize * 3) / 4;
1133 msm_write(port, watermark, UART_RFWR);
1134
1135 /* set TX watermark */
1136 msm_write(port, 10, UART_TFWR);
1137
1138 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
1139 msm_reset(port);
1140
1141 /* Enable RX and TX */
1142 msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR);
1143
1144 /* turn on RX and CTS interrupts */
1145 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
1146 UART_IMR_CURRENT_CTS | UART_IMR_RXBREAK_START;
1147
1148 msm_write(port, msm_port->imr, UART_IMR);
1149
1150 if (msm_port->is_uartdm) {
1151 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
1152 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1153 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
1154 }
1155
1156 return baud;
1157}
1158
1159static void msm_init_clock(struct uart_port *port)
1160{
1161 struct msm_port *msm_port = UART_TO_MSM(port);
1162
1163 clk_prepare_enable(msm_port->clk);
1164 clk_prepare_enable(msm_port->pclk);
1165 msm_serial_set_mnd_regs(port);
1166}
1167
1168static int msm_startup(struct uart_port *port)
1169{
1170 struct msm_port *msm_port = UART_TO_MSM(port);
1171 unsigned int data, rfr_level, mask;
1172 int ret;
1173
1174 snprintf(msm_port->name, sizeof(msm_port->name),
1175 "msm_serial%d", port->line);
1176
1177 msm_init_clock(port);
1178
1179 if (likely(port->fifosize > 12))
1180 rfr_level = port->fifosize - 12;
1181 else
1182 rfr_level = port->fifosize;
1183
1184 /* set automatic RFR level */
1185 data = msm_read(port, UART_MR1);
1186
1187 if (msm_port->is_uartdm)
1188 mask = UART_DM_MR1_AUTO_RFR_LEVEL1;
1189 else
1190 mask = UART_MR1_AUTO_RFR_LEVEL1;
1191
1192 data &= ~mask;
1193 data &= ~UART_MR1_AUTO_RFR_LEVEL0;
1194 data |= mask & (rfr_level << 2);
1195 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
1196 msm_write(port, data, UART_MR1);
1197
1198 if (msm_port->is_uartdm) {
1199 msm_request_tx_dma(msm_port, msm_port->uart.mapbase);
1200 msm_request_rx_dma(msm_port, msm_port->uart.mapbase);
1201 }
1202
1203 ret = request_irq(port->irq, msm_uart_irq, IRQF_TRIGGER_HIGH,
1204 msm_port->name, port);
1205 if (unlikely(ret))
1206 goto err_irq;
1207
1208 return 0;
1209
1210err_irq:
1211 if (msm_port->is_uartdm)
1212 msm_release_dma(msm_port);
1213
1214 clk_disable_unprepare(msm_port->pclk);
1215 clk_disable_unprepare(msm_port->clk);
1216
1217 return ret;
1218}
1219
1220static void msm_shutdown(struct uart_port *port)
1221{
1222 struct msm_port *msm_port = UART_TO_MSM(port);
1223
1224 msm_port->imr = 0;
1225 msm_write(port, 0, UART_IMR); /* disable interrupts */
1226
1227 if (msm_port->is_uartdm)
1228 msm_release_dma(msm_port);
1229
1230 clk_disable_unprepare(msm_port->clk);
1231
1232 free_irq(port->irq, port);
1233}
1234
1235static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
1236 struct ktermios *old)
1237{
1238 struct msm_port *msm_port = UART_TO_MSM(port);
1239 struct msm_dma *dma = &msm_port->rx_dma;
1240 unsigned long flags;
1241 unsigned int baud, mr;
1242
1243 spin_lock_irqsave(&port->lock, flags);
1244
1245 if (dma->chan) /* Terminate if any */
1246 msm_stop_dma(port, dma);
1247
1248 /* calculate and set baud rate */
1249 baud = uart_get_baud_rate(port, termios, old, 300, 4000000);
1250 baud = msm_set_baud_rate(port, baud, &flags);
1251 if (tty_termios_baud_rate(termios))
1252 tty_termios_encode_baud_rate(termios, baud, baud);
1253
1254 /* calculate parity */
1255 mr = msm_read(port, UART_MR2);
1256 mr &= ~UART_MR2_PARITY_MODE;
1257 if (termios->c_cflag & PARENB) {
1258 if (termios->c_cflag & PARODD)
1259 mr |= UART_MR2_PARITY_MODE_ODD;
1260 else if (termios->c_cflag & CMSPAR)
1261 mr |= UART_MR2_PARITY_MODE_SPACE;
1262 else
1263 mr |= UART_MR2_PARITY_MODE_EVEN;
1264 }
1265
1266 /* calculate bits per char */
1267 mr &= ~UART_MR2_BITS_PER_CHAR;
1268 switch (termios->c_cflag & CSIZE) {
1269 case CS5:
1270 mr |= UART_MR2_BITS_PER_CHAR_5;
1271 break;
1272 case CS6:
1273 mr |= UART_MR2_BITS_PER_CHAR_6;
1274 break;
1275 case CS7:
1276 mr |= UART_MR2_BITS_PER_CHAR_7;
1277 break;
1278 case CS8:
1279 default:
1280 mr |= UART_MR2_BITS_PER_CHAR_8;
1281 break;
1282 }
1283
1284 /* calculate stop bits */
1285 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
1286 if (termios->c_cflag & CSTOPB)
1287 mr |= UART_MR2_STOP_BIT_LEN_TWO;
1288 else
1289 mr |= UART_MR2_STOP_BIT_LEN_ONE;
1290
1291 /* set parity, bits per char, and stop bit */
1292 msm_write(port, mr, UART_MR2);
1293
1294 /* calculate and set hardware flow control */
1295 mr = msm_read(port, UART_MR1);
1296 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
1297 if (termios->c_cflag & CRTSCTS) {
1298 mr |= UART_MR1_CTS_CTL;
1299 mr |= UART_MR1_RX_RDY_CTL;
1300 }
1301 msm_write(port, mr, UART_MR1);
1302
1303 /* Configure status bits to ignore based on termio flags. */
1304 port->read_status_mask = 0;
1305 if (termios->c_iflag & INPCK)
1306 port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
1307 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1308 port->read_status_mask |= UART_SR_RX_BREAK;
1309
1310 uart_update_timeout(port, termios->c_cflag, baud);
1311
1312 /* Try to use DMA */
1313 msm_start_rx_dma(msm_port);
1314
1315 spin_unlock_irqrestore(&port->lock, flags);
1316}
1317
1318static const char *msm_type(struct uart_port *port)
1319{
1320 return "MSM";
1321}
1322
1323static void msm_release_port(struct uart_port *port)
1324{
1325 struct platform_device *pdev = to_platform_device(port->dev);
1326 struct resource *uart_resource;
1327 resource_size_t size;
1328
1329 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1330 if (unlikely(!uart_resource))
1331 return;
1332 size = resource_size(uart_resource);
1333
1334 release_mem_region(port->mapbase, size);
1335 iounmap(port->membase);
1336 port->membase = NULL;
1337}
1338
1339static int msm_request_port(struct uart_port *port)
1340{
1341 struct platform_device *pdev = to_platform_device(port->dev);
1342 struct resource *uart_resource;
1343 resource_size_t size;
1344 int ret;
1345
1346 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1347 if (unlikely(!uart_resource))
1348 return -ENXIO;
1349
1350 size = resource_size(uart_resource);
1351
1352 if (!request_mem_region(port->mapbase, size, "msm_serial"))
1353 return -EBUSY;
1354
1355 port->membase = ioremap(port->mapbase, size);
1356 if (!port->membase) {
1357 ret = -EBUSY;
1358 goto fail_release_port;
1359 }
1360
1361 return 0;
1362
1363fail_release_port:
1364 release_mem_region(port->mapbase, size);
1365 return ret;
1366}
1367
1368static void msm_config_port(struct uart_port *port, int flags)
1369{
1370 int ret;
1371
1372 if (flags & UART_CONFIG_TYPE) {
1373 port->type = PORT_MSM;
1374 ret = msm_request_port(port);
1375 if (ret)
1376 return;
1377 }
1378}
1379
1380static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
1381{
1382 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
1383 return -EINVAL;
1384 if (unlikely(port->irq != ser->irq))
1385 return -EINVAL;
1386 return 0;
1387}
1388
1389static void msm_power(struct uart_port *port, unsigned int state,
1390 unsigned int oldstate)
1391{
1392 struct msm_port *msm_port = UART_TO_MSM(port);
1393
1394 switch (state) {
1395 case 0:
1396 clk_prepare_enable(msm_port->clk);
1397 clk_prepare_enable(msm_port->pclk);
1398 break;
1399 case 3:
1400 clk_disable_unprepare(msm_port->clk);
1401 clk_disable_unprepare(msm_port->pclk);
1402 break;
1403 default:
1404 pr_err("msm_serial: Unknown PM state %d\n", state);
1405 }
1406}
1407
1408#ifdef CONFIG_CONSOLE_POLL
1409static int msm_poll_get_char_single(struct uart_port *port)
1410{
1411 struct msm_port *msm_port = UART_TO_MSM(port);
1412 unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : UART_RF;
1413
1414 if (!(msm_read(port, UART_SR) & UART_SR_RX_READY))
1415 return NO_POLL_CHAR;
1416
1417 return msm_read(port, rf_reg) & 0xff;
1418}
1419
1420static int msm_poll_get_char_dm(struct uart_port *port)
1421{
1422 int c;
1423 static u32 slop;
1424 static int count;
1425 unsigned char *sp = (unsigned char *)&slop;
1426
1427 /* Check if a previous read had more than one char */
1428 if (count) {
1429 c = sp[sizeof(slop) - count];
1430 count--;
1431 /* Or if FIFO is empty */
1432 } else if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) {
1433 /*
1434 * If RX packing buffer has less than a word, force stale to
1435 * push contents into RX FIFO
1436 */
1437 count = msm_read(port, UARTDM_RXFS);
1438 count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK;
1439 if (count) {
1440 msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR);
1441 slop = msm_read(port, UARTDM_RF);
1442 c = sp[0];
1443 count--;
1444 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
1445 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1446 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE,
1447 UART_CR);
1448 } else {
1449 c = NO_POLL_CHAR;
1450 }
1451 /* FIFO has a word */
1452 } else {
1453 slop = msm_read(port, UARTDM_RF);
1454 c = sp[0];
1455 count = sizeof(slop) - 1;
1456 }
1457
1458 return c;
1459}
1460
1461static int msm_poll_get_char(struct uart_port *port)
1462{
1463 u32 imr;
1464 int c;
1465 struct msm_port *msm_port = UART_TO_MSM(port);
1466
1467 /* Disable all interrupts */
1468 imr = msm_read(port, UART_IMR);
1469 msm_write(port, 0, UART_IMR);
1470
1471 if (msm_port->is_uartdm)
1472 c = msm_poll_get_char_dm(port);
1473 else
1474 c = msm_poll_get_char_single(port);
1475
1476 /* Enable interrupts */
1477 msm_write(port, imr, UART_IMR);
1478
1479 return c;
1480}
1481
1482static void msm_poll_put_char(struct uart_port *port, unsigned char c)
1483{
1484 u32 imr;
1485 struct msm_port *msm_port = UART_TO_MSM(port);
1486
1487 /* Disable all interrupts */
1488 imr = msm_read(port, UART_IMR);
1489 msm_write(port, 0, UART_IMR);
1490
1491 if (msm_port->is_uartdm)
1492 msm_reset_dm_count(port, 1);
1493
1494 /* Wait until FIFO is empty */
1495 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1496 cpu_relax();
1497
1498 /* Write a character */
1499 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
1500
1501 /* Wait until FIFO is empty */
1502 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1503 cpu_relax();
1504
1505 /* Enable interrupts */
1506 msm_write(port, imr, UART_IMR);
1507}
1508#endif
1509
1510static struct uart_ops msm_uart_pops = {
1511 .tx_empty = msm_tx_empty,
1512 .set_mctrl = msm_set_mctrl,
1513 .get_mctrl = msm_get_mctrl,
1514 .stop_tx = msm_stop_tx,
1515 .start_tx = msm_start_tx,
1516 .stop_rx = msm_stop_rx,
1517 .enable_ms = msm_enable_ms,
1518 .break_ctl = msm_break_ctl,
1519 .startup = msm_startup,
1520 .shutdown = msm_shutdown,
1521 .set_termios = msm_set_termios,
1522 .type = msm_type,
1523 .release_port = msm_release_port,
1524 .request_port = msm_request_port,
1525 .config_port = msm_config_port,
1526 .verify_port = msm_verify_port,
1527 .pm = msm_power,
1528#ifdef CONFIG_CONSOLE_POLL
1529 .poll_get_char = msm_poll_get_char,
1530 .poll_put_char = msm_poll_put_char,
1531#endif
1532};
1533
1534static struct msm_port msm_uart_ports[] = {
1535 {
1536 .uart = {
1537 .iotype = UPIO_MEM,
1538 .ops = &msm_uart_pops,
1539 .flags = UPF_BOOT_AUTOCONF,
1540 .fifosize = 64,
1541 .line = 0,
1542 },
1543 },
1544 {
1545 .uart = {
1546 .iotype = UPIO_MEM,
1547 .ops = &msm_uart_pops,
1548 .flags = UPF_BOOT_AUTOCONF,
1549 .fifosize = 64,
1550 .line = 1,
1551 },
1552 },
1553 {
1554 .uart = {
1555 .iotype = UPIO_MEM,
1556 .ops = &msm_uart_pops,
1557 .flags = UPF_BOOT_AUTOCONF,
1558 .fifosize = 64,
1559 .line = 2,
1560 },
1561 },
1562};
1563
1564#define UART_NR ARRAY_SIZE(msm_uart_ports)
1565
1566static inline struct uart_port *msm_get_port_from_line(unsigned int line)
1567{
1568 return &msm_uart_ports[line].uart;
1569}
1570
1571#ifdef CONFIG_SERIAL_MSM_CONSOLE
1572static void __msm_console_write(struct uart_port *port, const char *s,
1573 unsigned int count, bool is_uartdm)
1574{
1575 int i;
1576 int num_newlines = 0;
1577 bool replaced = false;
1578 void __iomem *tf;
1579
1580 if (is_uartdm)
1581 tf = port->membase + UARTDM_TF;
1582 else
1583 tf = port->membase + UART_TF;
1584
1585 /* Account for newlines that will get a carriage return added */
1586 for (i = 0; i < count; i++)
1587 if (s[i] == '\n')
1588 num_newlines++;
1589 count += num_newlines;
1590
1591 spin_lock(&port->lock);
1592 if (is_uartdm)
1593 msm_reset_dm_count(port, count);
1594
1595 i = 0;
1596 while (i < count) {
1597 int j;
1598 unsigned int num_chars;
1599 char buf[4] = { 0 };
1600
1601 if (is_uartdm)
1602 num_chars = min(count - i, (unsigned int)sizeof(buf));
1603 else
1604 num_chars = 1;
1605
1606 for (j = 0; j < num_chars; j++) {
1607 char c = *s;
1608
1609 if (c == '\n' && !replaced) {
1610 buf[j] = '\r';
1611 j++;
1612 replaced = true;
1613 }
1614 if (j < num_chars) {
1615 buf[j] = c;
1616 s++;
1617 replaced = false;
1618 }
1619 }
1620
1621 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1622 cpu_relax();
1623
1624 iowrite32_rep(tf, buf, 1);
1625 i += num_chars;
1626 }
1627 spin_unlock(&port->lock);
1628}
1629
1630static void msm_console_write(struct console *co, const char *s,
1631 unsigned int count)
1632{
1633 struct uart_port *port;
1634 struct msm_port *msm_port;
1635
1636 BUG_ON(co->index < 0 || co->index >= UART_NR);
1637
1638 port = msm_get_port_from_line(co->index);
1639 msm_port = UART_TO_MSM(port);
1640
1641 __msm_console_write(port, s, count, msm_port->is_uartdm);
1642}
1643
1644static int msm_console_setup(struct console *co, char *options)
1645{
1646 struct uart_port *port;
1647 int baud = 115200;
1648 int bits = 8;
1649 int parity = 'n';
1650 int flow = 'n';
1651
1652 if (unlikely(co->index >= UART_NR || co->index < 0))
1653 return -ENXIO;
1654
1655 port = msm_get_port_from_line(co->index);
1656
1657 if (unlikely(!port->membase))
1658 return -ENXIO;
1659
1660 msm_init_clock(port);
1661
1662 if (options)
1663 uart_parse_options(options, &baud, &parity, &bits, &flow);
1664
1665 pr_info("msm_serial: console setup on port #%d\n", port->line);
1666
1667 return uart_set_options(port, co, baud, parity, bits, flow);
1668}
1669
1670static void
1671msm_serial_early_write(struct console *con, const char *s, unsigned n)
1672{
1673 struct earlycon_device *dev = con->data;
1674
1675 __msm_console_write(&dev->port, s, n, false);
1676}
1677
1678static int __init
1679msm_serial_early_console_setup(struct earlycon_device *device, const char *opt)
1680{
1681 if (!device->port.membase)
1682 return -ENODEV;
1683
1684 device->con->write = msm_serial_early_write;
1685 return 0;
1686}
1687OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart",
1688 msm_serial_early_console_setup);
1689
1690static void
1691msm_serial_early_write_dm(struct console *con, const char *s, unsigned n)
1692{
1693 struct earlycon_device *dev = con->data;
1694
1695 __msm_console_write(&dev->port, s, n, true);
1696}
1697
1698static int __init
1699msm_serial_early_console_setup_dm(struct earlycon_device *device,
1700 const char *opt)
1701{
1702 if (!device->port.membase)
1703 return -ENODEV;
1704
1705 device->con->write = msm_serial_early_write_dm;
1706 return 0;
1707}
1708OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm",
1709 msm_serial_early_console_setup_dm);
1710
1711static struct uart_driver msm_uart_driver;
1712
1713static struct console msm_console = {
1714 .name = "ttyMSM",
1715 .write = msm_console_write,
1716 .device = uart_console_device,
1717 .setup = msm_console_setup,
1718 .flags = CON_PRINTBUFFER,
1719 .index = -1,
1720 .data = &msm_uart_driver,
1721};
1722
1723#define MSM_CONSOLE (&msm_console)
1724
1725#else
1726#define MSM_CONSOLE NULL
1727#endif
1728
1729static struct uart_driver msm_uart_driver = {
1730 .owner = THIS_MODULE,
1731 .driver_name = "msm_serial",
1732 .dev_name = "ttyMSM",
1733 .nr = UART_NR,
1734 .cons = MSM_CONSOLE,
1735};
1736
1737static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
1738
1739static const struct of_device_id msm_uartdm_table[] = {
1740 { .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 },
1741 { .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 },
1742 { .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 },
1743 { .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 },
1744 { }
1745};
1746
1747static int msm_serial_probe(struct platform_device *pdev)
1748{
1749 struct msm_port *msm_port;
1750 struct resource *resource;
1751 struct uart_port *port;
1752 const struct of_device_id *id;
1753 int irq, line;
1754
1755 if (pdev->dev.of_node)
1756 line = of_alias_get_id(pdev->dev.of_node, "serial");
1757 else
1758 line = pdev->id;
1759
1760 if (line < 0)
1761 line = atomic_inc_return(&msm_uart_next_id) - 1;
1762
1763 if (unlikely(line < 0 || line >= UART_NR))
1764 return -ENXIO;
1765
1766 dev_info(&pdev->dev, "msm_serial: detected port #%d\n", line);
1767
1768 port = msm_get_port_from_line(line);
1769 port->dev = &pdev->dev;
1770 msm_port = UART_TO_MSM(port);
1771
1772 id = of_match_device(msm_uartdm_table, &pdev->dev);
1773 if (id)
1774 msm_port->is_uartdm = (unsigned long)id->data;
1775 else
1776 msm_port->is_uartdm = 0;
1777
1778 msm_port->clk = devm_clk_get(&pdev->dev, "core");
1779 if (IS_ERR(msm_port->clk))
1780 return PTR_ERR(msm_port->clk);
1781
1782 if (msm_port->is_uartdm) {
1783 msm_port->pclk = devm_clk_get(&pdev->dev, "iface");
1784 if (IS_ERR(msm_port->pclk))
1785 return PTR_ERR(msm_port->pclk);
1786 }
1787
1788 port->uartclk = clk_get_rate(msm_port->clk);
1789 dev_info(&pdev->dev, "uartclk = %d\n", port->uartclk);
1790
1791 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1792 if (unlikely(!resource))
1793 return -ENXIO;
1794 port->mapbase = resource->start;
1795
1796 irq = platform_get_irq(pdev, 0);
1797 if (unlikely(irq < 0))
1798 return -ENXIO;
1799 port->irq = irq;
1800
1801 platform_set_drvdata(pdev, port);
1802
1803 return uart_add_one_port(&msm_uart_driver, port);
1804}
1805
1806static int msm_serial_remove(struct platform_device *pdev)
1807{
1808 struct uart_port *port = platform_get_drvdata(pdev);
1809
1810 uart_remove_one_port(&msm_uart_driver, port);
1811
1812 return 0;
1813}
1814
1815static const struct of_device_id msm_match_table[] = {
1816 { .compatible = "qcom,msm-uart" },
1817 { .compatible = "qcom,msm-uartdm" },
1818 {}
1819};
1820MODULE_DEVICE_TABLE(of, msm_match_table);
1821
1822static int __maybe_unused msm_serial_suspend(struct device *dev)
1823{
1824 struct msm_port *port = dev_get_drvdata(dev);
1825
1826 uart_suspend_port(&msm_uart_driver, &port->uart);
1827
1828 return 0;
1829}
1830
1831static int __maybe_unused msm_serial_resume(struct device *dev)
1832{
1833 struct msm_port *port = dev_get_drvdata(dev);
1834
1835 uart_resume_port(&msm_uart_driver, &port->uart);
1836
1837 return 0;
1838}
1839
1840static const struct dev_pm_ops msm_serial_dev_pm_ops = {
1841 SET_SYSTEM_SLEEP_PM_OPS(msm_serial_suspend, msm_serial_resume)
1842};
1843
1844static struct platform_driver msm_platform_driver = {
1845 .remove = msm_serial_remove,
1846 .probe = msm_serial_probe,
1847 .driver = {
1848 .name = "msm_serial",
1849 .pm = &msm_serial_dev_pm_ops,
1850 .of_match_table = msm_match_table,
1851 },
1852};
1853
1854static int __init msm_serial_init(void)
1855{
1856 int ret;
1857
1858 ret = uart_register_driver(&msm_uart_driver);
1859 if (unlikely(ret))
1860 return ret;
1861
1862 ret = platform_driver_register(&msm_platform_driver);
1863 if (unlikely(ret))
1864 uart_unregister_driver(&msm_uart_driver);
1865
1866 pr_info("msm_serial: driver initialized\n");
1867
1868 return ret;
1869}
1870
1871static void __exit msm_serial_exit(void)
1872{
1873 platform_driver_unregister(&msm_platform_driver);
1874 uart_unregister_driver(&msm_uart_driver);
1875}
1876
1877module_init(msm_serial_init);
1878module_exit(msm_serial_exit);
1879
1880MODULE_AUTHOR("Robert Love <rlove@google.com>");
1881MODULE_DESCRIPTION("Driver for msm7x serial device");
1882MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Driver for msm7k serial device and console
4 *
5 * Copyright (C) 2007 Google, Inc.
6 * Author: Robert Love <rlove@google.com>
7 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
8 */
9
10#include <linux/kernel.h>
11#include <linux/atomic.h>
12#include <linux/dma/qcom_adm.h>
13#include <linux/dma-mapping.h>
14#include <linux/dmaengine.h>
15#include <linux/module.h>
16#include <linux/io.h>
17#include <linux/ioport.h>
18#include <linux/interrupt.h>
19#include <linux/init.h>
20#include <linux/console.h>
21#include <linux/tty.h>
22#include <linux/tty_flip.h>
23#include <linux/serial_core.h>
24#include <linux/slab.h>
25#include <linux/clk.h>
26#include <linux/platform_device.h>
27#include <linux/pm_opp.h>
28#include <linux/delay.h>
29#include <linux/of.h>
30#include <linux/of_device.h>
31#include <linux/wait.h>
32
33#define MSM_UART_MR1 0x0000
34
35#define MSM_UART_MR1_AUTO_RFR_LEVEL0 0x3F
36#define MSM_UART_MR1_AUTO_RFR_LEVEL1 0x3FF00
37#define MSM_UART_DM_MR1_AUTO_RFR_LEVEL1 0xFFFFFF00
38#define MSM_UART_MR1_RX_RDY_CTL BIT(7)
39#define MSM_UART_MR1_CTS_CTL BIT(6)
40
41#define MSM_UART_MR2 0x0004
42#define MSM_UART_MR2_ERROR_MODE BIT(6)
43#define MSM_UART_MR2_BITS_PER_CHAR 0x30
44#define MSM_UART_MR2_BITS_PER_CHAR_5 (0x0 << 4)
45#define MSM_UART_MR2_BITS_PER_CHAR_6 (0x1 << 4)
46#define MSM_UART_MR2_BITS_PER_CHAR_7 (0x2 << 4)
47#define MSM_UART_MR2_BITS_PER_CHAR_8 (0x3 << 4)
48#define MSM_UART_MR2_STOP_BIT_LEN_ONE (0x1 << 2)
49#define MSM_UART_MR2_STOP_BIT_LEN_TWO (0x3 << 2)
50#define MSM_UART_MR2_PARITY_MODE_NONE 0x0
51#define MSM_UART_MR2_PARITY_MODE_ODD 0x1
52#define MSM_UART_MR2_PARITY_MODE_EVEN 0x2
53#define MSM_UART_MR2_PARITY_MODE_SPACE 0x3
54#define MSM_UART_MR2_PARITY_MODE 0x3
55
56#define MSM_UART_CSR 0x0008
57
58#define MSM_UART_TF 0x000C
59#define UARTDM_TF 0x0070
60
61#define MSM_UART_CR 0x0010
62#define MSM_UART_CR_CMD_NULL (0 << 4)
63#define MSM_UART_CR_CMD_RESET_RX (1 << 4)
64#define MSM_UART_CR_CMD_RESET_TX (2 << 4)
65#define MSM_UART_CR_CMD_RESET_ERR (3 << 4)
66#define MSM_UART_CR_CMD_RESET_BREAK_INT (4 << 4)
67#define MSM_UART_CR_CMD_START_BREAK (5 << 4)
68#define MSM_UART_CR_CMD_STOP_BREAK (6 << 4)
69#define MSM_UART_CR_CMD_RESET_CTS (7 << 4)
70#define MSM_UART_CR_CMD_RESET_STALE_INT (8 << 4)
71#define MSM_UART_CR_CMD_PACKET_MODE (9 << 4)
72#define MSM_UART_CR_CMD_MODE_RESET (12 << 4)
73#define MSM_UART_CR_CMD_SET_RFR (13 << 4)
74#define MSM_UART_CR_CMD_RESET_RFR (14 << 4)
75#define MSM_UART_CR_CMD_PROTECTION_EN (16 << 4)
76#define MSM_UART_CR_CMD_STALE_EVENT_DISABLE (6 << 8)
77#define MSM_UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4)
78#define MSM_UART_CR_CMD_FORCE_STALE (4 << 8)
79#define MSM_UART_CR_CMD_RESET_TX_READY (3 << 8)
80#define MSM_UART_CR_TX_DISABLE BIT(3)
81#define MSM_UART_CR_TX_ENABLE BIT(2)
82#define MSM_UART_CR_RX_DISABLE BIT(1)
83#define MSM_UART_CR_RX_ENABLE BIT(0)
84#define MSM_UART_CR_CMD_RESET_RXBREAK_START ((1 << 11) | (2 << 4))
85
86#define MSM_UART_IMR 0x0014
87#define MSM_UART_IMR_TXLEV BIT(0)
88#define MSM_UART_IMR_RXSTALE BIT(3)
89#define MSM_UART_IMR_RXLEV BIT(4)
90#define MSM_UART_IMR_DELTA_CTS BIT(5)
91#define MSM_UART_IMR_CURRENT_CTS BIT(6)
92#define MSM_UART_IMR_RXBREAK_START BIT(10)
93
94#define MSM_UART_IPR_RXSTALE_LAST 0x20
95#define MSM_UART_IPR_STALE_LSB 0x1F
96#define MSM_UART_IPR_STALE_TIMEOUT_MSB 0x3FF80
97#define MSM_UART_DM_IPR_STALE_TIMEOUT_MSB 0xFFFFFF80
98
99#define MSM_UART_IPR 0x0018
100#define MSM_UART_TFWR 0x001C
101#define MSM_UART_RFWR 0x0020
102#define MSM_UART_HCR 0x0024
103
104#define MSM_UART_MREG 0x0028
105#define MSM_UART_NREG 0x002C
106#define MSM_UART_DREG 0x0030
107#define MSM_UART_MNDREG 0x0034
108#define MSM_UART_IRDA 0x0038
109#define MSM_UART_MISR_MODE 0x0040
110#define MSM_UART_MISR_RESET 0x0044
111#define MSM_UART_MISR_EXPORT 0x0048
112#define MSM_UART_MISR_VAL 0x004C
113#define MSM_UART_TEST_CTRL 0x0050
114
115#define MSM_UART_SR 0x0008
116#define MSM_UART_SR_HUNT_CHAR BIT(7)
117#define MSM_UART_SR_RX_BREAK BIT(6)
118#define MSM_UART_SR_PAR_FRAME_ERR BIT(5)
119#define MSM_UART_SR_OVERRUN BIT(4)
120#define MSM_UART_SR_TX_EMPTY BIT(3)
121#define MSM_UART_SR_TX_READY BIT(2)
122#define MSM_UART_SR_RX_FULL BIT(1)
123#define MSM_UART_SR_RX_READY BIT(0)
124
125#define MSM_UART_RF 0x000C
126#define UARTDM_RF 0x0070
127#define MSM_UART_MISR 0x0010
128#define MSM_UART_ISR 0x0014
129#define MSM_UART_ISR_TX_READY BIT(7)
130
131#define UARTDM_RXFS 0x50
132#define UARTDM_RXFS_BUF_SHIFT 0x7
133#define UARTDM_RXFS_BUF_MASK 0x7
134
135#define UARTDM_DMEN 0x3C
136#define UARTDM_DMEN_RX_SC_ENABLE BIT(5)
137#define UARTDM_DMEN_TX_SC_ENABLE BIT(4)
138
139#define UARTDM_DMEN_TX_BAM_ENABLE BIT(2) /* UARTDM_1P4 */
140#define UARTDM_DMEN_TX_DM_ENABLE BIT(0) /* < UARTDM_1P4 */
141
142#define UARTDM_DMEN_RX_BAM_ENABLE BIT(3) /* UARTDM_1P4 */
143#define UARTDM_DMEN_RX_DM_ENABLE BIT(1) /* < UARTDM_1P4 */
144
145#define UARTDM_DMRX 0x34
146#define UARTDM_NCF_TX 0x40
147#define UARTDM_RX_TOTAL_SNAP 0x38
148
149#define UARTDM_BURST_SIZE 16 /* in bytes */
150#define UARTDM_TX_AIGN(x) ((x) & ~0x3) /* valid for > 1p3 */
151#define UARTDM_TX_MAX 256 /* in bytes, valid for <= 1p3 */
152#define UARTDM_RX_SIZE (UART_XMIT_SIZE / 4)
153
154enum {
155 UARTDM_1P1 = 1,
156 UARTDM_1P2,
157 UARTDM_1P3,
158 UARTDM_1P4,
159};
160
161struct msm_dma {
162 struct dma_chan *chan;
163 enum dma_data_direction dir;
164 dma_addr_t phys;
165 unsigned char *virt;
166 dma_cookie_t cookie;
167 u32 enable_bit;
168 unsigned int count;
169 struct dma_async_tx_descriptor *desc;
170};
171
172struct msm_port {
173 struct uart_port uart;
174 char name[16];
175 struct clk *clk;
176 struct clk *pclk;
177 unsigned int imr;
178 int is_uartdm;
179 unsigned int old_snap_state;
180 bool break_detected;
181 struct msm_dma tx_dma;
182 struct msm_dma rx_dma;
183};
184
185static inline struct msm_port *to_msm_port(struct uart_port *up)
186{
187 return container_of(up, struct msm_port, uart);
188}
189
190static
191void msm_write(struct uart_port *port, unsigned int val, unsigned int off)
192{
193 writel_relaxed(val, port->membase + off);
194}
195
196static
197unsigned int msm_read(struct uart_port *port, unsigned int off)
198{
199 return readl_relaxed(port->membase + off);
200}
201
202/*
203 * Setup the MND registers to use the TCXO clock.
204 */
205static void msm_serial_set_mnd_regs_tcxo(struct uart_port *port)
206{
207 msm_write(port, 0x06, MSM_UART_MREG);
208 msm_write(port, 0xF1, MSM_UART_NREG);
209 msm_write(port, 0x0F, MSM_UART_DREG);
210 msm_write(port, 0x1A, MSM_UART_MNDREG);
211 port->uartclk = 1843200;
212}
213
214/*
215 * Setup the MND registers to use the TCXO clock divided by 4.
216 */
217static void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port)
218{
219 msm_write(port, 0x18, MSM_UART_MREG);
220 msm_write(port, 0xF6, MSM_UART_NREG);
221 msm_write(port, 0x0F, MSM_UART_DREG);
222 msm_write(port, 0x0A, MSM_UART_MNDREG);
223 port->uartclk = 1843200;
224}
225
226static void msm_serial_set_mnd_regs(struct uart_port *port)
227{
228 struct msm_port *msm_port = to_msm_port(port);
229
230 /*
231 * These registers don't exist so we change the clk input rate
232 * on uartdm hardware instead
233 */
234 if (msm_port->is_uartdm)
235 return;
236
237 if (port->uartclk == 19200000)
238 msm_serial_set_mnd_regs_tcxo(port);
239 else if (port->uartclk == 4800000)
240 msm_serial_set_mnd_regs_tcxoby4(port);
241}
242
243static void msm_handle_tx(struct uart_port *port);
244static void msm_start_rx_dma(struct msm_port *msm_port);
245
246static void msm_stop_dma(struct uart_port *port, struct msm_dma *dma)
247{
248 struct device *dev = port->dev;
249 unsigned int mapped;
250 u32 val;
251
252 mapped = dma->count;
253 dma->count = 0;
254
255 dmaengine_terminate_all(dma->chan);
256
257 /*
258 * DMA Stall happens if enqueue and flush command happens concurrently.
259 * For example before changing the baud rate/protocol configuration and
260 * sending flush command to ADM, disable the channel of UARTDM.
261 * Note: should not reset the receiver here immediately as it is not
262 * suggested to do disable/reset or reset/disable at the same time.
263 */
264 val = msm_read(port, UARTDM_DMEN);
265 val &= ~dma->enable_bit;
266 msm_write(port, val, UARTDM_DMEN);
267
268 if (mapped)
269 dma_unmap_single(dev, dma->phys, mapped, dma->dir);
270}
271
272static void msm_release_dma(struct msm_port *msm_port)
273{
274 struct msm_dma *dma;
275
276 dma = &msm_port->tx_dma;
277 if (dma->chan) {
278 msm_stop_dma(&msm_port->uart, dma);
279 dma_release_channel(dma->chan);
280 }
281
282 memset(dma, 0, sizeof(*dma));
283
284 dma = &msm_port->rx_dma;
285 if (dma->chan) {
286 msm_stop_dma(&msm_port->uart, dma);
287 dma_release_channel(dma->chan);
288 kfree(dma->virt);
289 }
290
291 memset(dma, 0, sizeof(*dma));
292}
293
294static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base)
295{
296 struct device *dev = msm_port->uart.dev;
297 struct dma_slave_config conf;
298 struct qcom_adm_peripheral_config periph_conf = {};
299 struct msm_dma *dma;
300 u32 crci = 0;
301 int ret;
302
303 dma = &msm_port->tx_dma;
304
305 /* allocate DMA resources, if available */
306 dma->chan = dma_request_chan(dev, "tx");
307 if (IS_ERR(dma->chan))
308 goto no_tx;
309
310 of_property_read_u32(dev->of_node, "qcom,tx-crci", &crci);
311
312 memset(&conf, 0, sizeof(conf));
313 conf.direction = DMA_MEM_TO_DEV;
314 conf.device_fc = true;
315 conf.dst_addr = base + UARTDM_TF;
316 conf.dst_maxburst = UARTDM_BURST_SIZE;
317 if (crci) {
318 conf.peripheral_config = &periph_conf;
319 conf.peripheral_size = sizeof(periph_conf);
320 periph_conf.crci = crci;
321 }
322
323 ret = dmaengine_slave_config(dma->chan, &conf);
324 if (ret)
325 goto rel_tx;
326
327 dma->dir = DMA_TO_DEVICE;
328
329 if (msm_port->is_uartdm < UARTDM_1P4)
330 dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE;
331 else
332 dma->enable_bit = UARTDM_DMEN_TX_BAM_ENABLE;
333
334 return;
335
336rel_tx:
337 dma_release_channel(dma->chan);
338no_tx:
339 memset(dma, 0, sizeof(*dma));
340}
341
342static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base)
343{
344 struct device *dev = msm_port->uart.dev;
345 struct dma_slave_config conf;
346 struct qcom_adm_peripheral_config periph_conf = {};
347 struct msm_dma *dma;
348 u32 crci = 0;
349 int ret;
350
351 dma = &msm_port->rx_dma;
352
353 /* allocate DMA resources, if available */
354 dma->chan = dma_request_chan(dev, "rx");
355 if (IS_ERR(dma->chan))
356 goto no_rx;
357
358 of_property_read_u32(dev->of_node, "qcom,rx-crci", &crci);
359
360 dma->virt = kzalloc(UARTDM_RX_SIZE, GFP_KERNEL);
361 if (!dma->virt)
362 goto rel_rx;
363
364 memset(&conf, 0, sizeof(conf));
365 conf.direction = DMA_DEV_TO_MEM;
366 conf.device_fc = true;
367 conf.src_addr = base + UARTDM_RF;
368 conf.src_maxburst = UARTDM_BURST_SIZE;
369 if (crci) {
370 conf.peripheral_config = &periph_conf;
371 conf.peripheral_size = sizeof(periph_conf);
372 periph_conf.crci = crci;
373 }
374
375 ret = dmaengine_slave_config(dma->chan, &conf);
376 if (ret)
377 goto err;
378
379 dma->dir = DMA_FROM_DEVICE;
380
381 if (msm_port->is_uartdm < UARTDM_1P4)
382 dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE;
383 else
384 dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE;
385
386 return;
387err:
388 kfree(dma->virt);
389rel_rx:
390 dma_release_channel(dma->chan);
391no_rx:
392 memset(dma, 0, sizeof(*dma));
393}
394
395static inline void msm_wait_for_xmitr(struct uart_port *port)
396{
397 unsigned int timeout = 500000;
398
399 while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_EMPTY)) {
400 if (msm_read(port, MSM_UART_ISR) & MSM_UART_ISR_TX_READY)
401 break;
402 udelay(1);
403 if (!timeout--)
404 break;
405 }
406 msm_write(port, MSM_UART_CR_CMD_RESET_TX_READY, MSM_UART_CR);
407}
408
409static void msm_stop_tx(struct uart_port *port)
410{
411 struct msm_port *msm_port = to_msm_port(port);
412
413 msm_port->imr &= ~MSM_UART_IMR_TXLEV;
414 msm_write(port, msm_port->imr, MSM_UART_IMR);
415}
416
417static void msm_start_tx(struct uart_port *port)
418{
419 struct msm_port *msm_port = to_msm_port(port);
420 struct msm_dma *dma = &msm_port->tx_dma;
421
422 /* Already started in DMA mode */
423 if (dma->count)
424 return;
425
426 msm_port->imr |= MSM_UART_IMR_TXLEV;
427 msm_write(port, msm_port->imr, MSM_UART_IMR);
428}
429
430static void msm_reset_dm_count(struct uart_port *port, int count)
431{
432 msm_wait_for_xmitr(port);
433 msm_write(port, count, UARTDM_NCF_TX);
434 msm_read(port, UARTDM_NCF_TX);
435}
436
437static void msm_complete_tx_dma(void *args)
438{
439 struct msm_port *msm_port = args;
440 struct uart_port *port = &msm_port->uart;
441 struct circ_buf *xmit = &port->state->xmit;
442 struct msm_dma *dma = &msm_port->tx_dma;
443 struct dma_tx_state state;
444 unsigned long flags;
445 unsigned int count;
446 u32 val;
447
448 uart_port_lock_irqsave(port, &flags);
449
450 /* Already stopped */
451 if (!dma->count)
452 goto done;
453
454 dmaengine_tx_status(dma->chan, dma->cookie, &state);
455
456 dma_unmap_single(port->dev, dma->phys, dma->count, dma->dir);
457
458 val = msm_read(port, UARTDM_DMEN);
459 val &= ~dma->enable_bit;
460 msm_write(port, val, UARTDM_DMEN);
461
462 if (msm_port->is_uartdm > UARTDM_1P3) {
463 msm_write(port, MSM_UART_CR_CMD_RESET_TX, MSM_UART_CR);
464 msm_write(port, MSM_UART_CR_TX_ENABLE, MSM_UART_CR);
465 }
466
467 count = dma->count - state.residue;
468 uart_xmit_advance(port, count);
469 dma->count = 0;
470
471 /* Restore "Tx FIFO below watermark" interrupt */
472 msm_port->imr |= MSM_UART_IMR_TXLEV;
473 msm_write(port, msm_port->imr, MSM_UART_IMR);
474
475 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
476 uart_write_wakeup(port);
477
478 msm_handle_tx(port);
479done:
480 uart_port_unlock_irqrestore(port, flags);
481}
482
483static int msm_handle_tx_dma(struct msm_port *msm_port, unsigned int count)
484{
485 struct circ_buf *xmit = &msm_port->uart.state->xmit;
486 struct uart_port *port = &msm_port->uart;
487 struct msm_dma *dma = &msm_port->tx_dma;
488 void *cpu_addr;
489 int ret;
490 u32 val;
491
492 cpu_addr = &xmit->buf[xmit->tail];
493
494 dma->phys = dma_map_single(port->dev, cpu_addr, count, dma->dir);
495 ret = dma_mapping_error(port->dev, dma->phys);
496 if (ret)
497 return ret;
498
499 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
500 count, DMA_MEM_TO_DEV,
501 DMA_PREP_INTERRUPT |
502 DMA_PREP_FENCE);
503 if (!dma->desc) {
504 ret = -EIO;
505 goto unmap;
506 }
507
508 dma->desc->callback = msm_complete_tx_dma;
509 dma->desc->callback_param = msm_port;
510
511 dma->cookie = dmaengine_submit(dma->desc);
512 ret = dma_submit_error(dma->cookie);
513 if (ret)
514 goto unmap;
515
516 /*
517 * Using DMA complete for Tx FIFO reload, no need for
518 * "Tx FIFO below watermark" one, disable it
519 */
520 msm_port->imr &= ~MSM_UART_IMR_TXLEV;
521 msm_write(port, msm_port->imr, MSM_UART_IMR);
522
523 dma->count = count;
524
525 val = msm_read(port, UARTDM_DMEN);
526 val |= dma->enable_bit;
527
528 if (msm_port->is_uartdm < UARTDM_1P4)
529 msm_write(port, val, UARTDM_DMEN);
530
531 msm_reset_dm_count(port, count);
532
533 if (msm_port->is_uartdm > UARTDM_1P3)
534 msm_write(port, val, UARTDM_DMEN);
535
536 dma_async_issue_pending(dma->chan);
537 return 0;
538unmap:
539 dma_unmap_single(port->dev, dma->phys, count, dma->dir);
540 return ret;
541}
542
543static void msm_complete_rx_dma(void *args)
544{
545 struct msm_port *msm_port = args;
546 struct uart_port *port = &msm_port->uart;
547 struct tty_port *tport = &port->state->port;
548 struct msm_dma *dma = &msm_port->rx_dma;
549 int count = 0, i, sysrq;
550 unsigned long flags;
551 u32 val;
552
553 uart_port_lock_irqsave(port, &flags);
554
555 /* Already stopped */
556 if (!dma->count)
557 goto done;
558
559 val = msm_read(port, UARTDM_DMEN);
560 val &= ~dma->enable_bit;
561 msm_write(port, val, UARTDM_DMEN);
562
563 if (msm_read(port, MSM_UART_SR) & MSM_UART_SR_OVERRUN) {
564 port->icount.overrun++;
565 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
566 msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);
567 }
568
569 count = msm_read(port, UARTDM_RX_TOTAL_SNAP);
570
571 port->icount.rx += count;
572
573 dma->count = 0;
574
575 dma_unmap_single(port->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
576
577 for (i = 0; i < count; i++) {
578 char flag = TTY_NORMAL;
579
580 if (msm_port->break_detected && dma->virt[i] == 0) {
581 port->icount.brk++;
582 flag = TTY_BREAK;
583 msm_port->break_detected = false;
584 if (uart_handle_break(port))
585 continue;
586 }
587
588 if (!(port->read_status_mask & MSM_UART_SR_RX_BREAK))
589 flag = TTY_NORMAL;
590
591 sysrq = uart_prepare_sysrq_char(port, dma->virt[i]);
592 if (!sysrq)
593 tty_insert_flip_char(tport, dma->virt[i], flag);
594 }
595
596 msm_start_rx_dma(msm_port);
597done:
598 uart_unlock_and_check_sysrq_irqrestore(port, flags);
599
600 if (count)
601 tty_flip_buffer_push(tport);
602}
603
604static void msm_start_rx_dma(struct msm_port *msm_port)
605{
606 struct msm_dma *dma = &msm_port->rx_dma;
607 struct uart_port *uart = &msm_port->uart;
608 u32 val;
609 int ret;
610
611 if (IS_ENABLED(CONFIG_CONSOLE_POLL))
612 return;
613
614 if (!dma->chan)
615 return;
616
617 dma->phys = dma_map_single(uart->dev, dma->virt,
618 UARTDM_RX_SIZE, dma->dir);
619 ret = dma_mapping_error(uart->dev, dma->phys);
620 if (ret)
621 goto sw_mode;
622
623 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
624 UARTDM_RX_SIZE, DMA_DEV_TO_MEM,
625 DMA_PREP_INTERRUPT);
626 if (!dma->desc)
627 goto unmap;
628
629 dma->desc->callback = msm_complete_rx_dma;
630 dma->desc->callback_param = msm_port;
631
632 dma->cookie = dmaengine_submit(dma->desc);
633 ret = dma_submit_error(dma->cookie);
634 if (ret)
635 goto unmap;
636 /*
637 * Using DMA for FIFO off-load, no need for "Rx FIFO over
638 * watermark" or "stale" interrupts, disable them
639 */
640 msm_port->imr &= ~(MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE);
641
642 /*
643 * Well, when DMA is ADM3 engine(implied by <= UARTDM v1.3),
644 * we need RXSTALE to flush input DMA fifo to memory
645 */
646 if (msm_port->is_uartdm < UARTDM_1P4)
647 msm_port->imr |= MSM_UART_IMR_RXSTALE;
648
649 msm_write(uart, msm_port->imr, MSM_UART_IMR);
650
651 dma->count = UARTDM_RX_SIZE;
652
653 dma_async_issue_pending(dma->chan);
654
655 msm_write(uart, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);
656 msm_write(uart, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);
657
658 val = msm_read(uart, UARTDM_DMEN);
659 val |= dma->enable_bit;
660
661 if (msm_port->is_uartdm < UARTDM_1P4)
662 msm_write(uart, val, UARTDM_DMEN);
663
664 msm_write(uart, UARTDM_RX_SIZE, UARTDM_DMRX);
665
666 if (msm_port->is_uartdm > UARTDM_1P3)
667 msm_write(uart, val, UARTDM_DMEN);
668
669 return;
670unmap:
671 dma_unmap_single(uart->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
672
673sw_mode:
674 /*
675 * Switch from DMA to SW/FIFO mode. After clearing Rx BAM (UARTDM_DMEN),
676 * receiver must be reset.
677 */
678 msm_write(uart, MSM_UART_CR_CMD_RESET_RX, MSM_UART_CR);
679 msm_write(uart, MSM_UART_CR_RX_ENABLE, MSM_UART_CR);
680
681 msm_write(uart, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);
682 msm_write(uart, 0xFFFFFF, UARTDM_DMRX);
683 msm_write(uart, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);
684
685 /* Re-enable RX interrupts */
686 msm_port->imr |= MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE;
687 msm_write(uart, msm_port->imr, MSM_UART_IMR);
688}
689
690static void msm_stop_rx(struct uart_port *port)
691{
692 struct msm_port *msm_port = to_msm_port(port);
693 struct msm_dma *dma = &msm_port->rx_dma;
694
695 msm_port->imr &= ~(MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE);
696 msm_write(port, msm_port->imr, MSM_UART_IMR);
697
698 if (dma->chan)
699 msm_stop_dma(port, dma);
700}
701
702static void msm_enable_ms(struct uart_port *port)
703{
704 struct msm_port *msm_port = to_msm_port(port);
705
706 msm_port->imr |= MSM_UART_IMR_DELTA_CTS;
707 msm_write(port, msm_port->imr, MSM_UART_IMR);
708}
709
710static void msm_handle_rx_dm(struct uart_port *port, unsigned int misr)
711 __must_hold(&port->lock)
712{
713 struct tty_port *tport = &port->state->port;
714 unsigned int sr;
715 int count = 0;
716 struct msm_port *msm_port = to_msm_port(port);
717
718 if ((msm_read(port, MSM_UART_SR) & MSM_UART_SR_OVERRUN)) {
719 port->icount.overrun++;
720 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
721 msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);
722 }
723
724 if (misr & MSM_UART_IMR_RXSTALE) {
725 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
726 msm_port->old_snap_state;
727 msm_port->old_snap_state = 0;
728 } else {
729 count = 4 * (msm_read(port, MSM_UART_RFWR));
730 msm_port->old_snap_state += count;
731 }
732
733 /* TODO: Precise error reporting */
734
735 port->icount.rx += count;
736
737 while (count > 0) {
738 unsigned char buf[4];
739 int sysrq, r_count, i;
740
741 sr = msm_read(port, MSM_UART_SR);
742 if ((sr & MSM_UART_SR_RX_READY) == 0) {
743 msm_port->old_snap_state -= count;
744 break;
745 }
746
747 ioread32_rep(port->membase + UARTDM_RF, buf, 1);
748 r_count = min_t(int, count, sizeof(buf));
749
750 for (i = 0; i < r_count; i++) {
751 char flag = TTY_NORMAL;
752
753 if (msm_port->break_detected && buf[i] == 0) {
754 port->icount.brk++;
755 flag = TTY_BREAK;
756 msm_port->break_detected = false;
757 if (uart_handle_break(port))
758 continue;
759 }
760
761 if (!(port->read_status_mask & MSM_UART_SR_RX_BREAK))
762 flag = TTY_NORMAL;
763
764 sysrq = uart_prepare_sysrq_char(port, buf[i]);
765 if (!sysrq)
766 tty_insert_flip_char(tport, buf[i], flag);
767 }
768 count -= r_count;
769 }
770
771 tty_flip_buffer_push(tport);
772
773 if (misr & (MSM_UART_IMR_RXSTALE))
774 msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);
775 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
776 msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);
777
778 /* Try to use DMA */
779 msm_start_rx_dma(msm_port);
780}
781
782static void msm_handle_rx(struct uart_port *port)
783 __must_hold(&port->lock)
784{
785 struct tty_port *tport = &port->state->port;
786 unsigned int sr;
787
788 /*
789 * Handle overrun. My understanding of the hardware is that overrun
790 * is not tied to the RX buffer, so we handle the case out of band.
791 */
792 if ((msm_read(port, MSM_UART_SR) & MSM_UART_SR_OVERRUN)) {
793 port->icount.overrun++;
794 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
795 msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);
796 }
797
798 /* and now the main RX loop */
799 while ((sr = msm_read(port, MSM_UART_SR)) & MSM_UART_SR_RX_READY) {
800 unsigned int c;
801 char flag = TTY_NORMAL;
802 int sysrq;
803
804 c = msm_read(port, MSM_UART_RF);
805
806 if (sr & MSM_UART_SR_RX_BREAK) {
807 port->icount.brk++;
808 if (uart_handle_break(port))
809 continue;
810 } else if (sr & MSM_UART_SR_PAR_FRAME_ERR) {
811 port->icount.frame++;
812 } else {
813 port->icount.rx++;
814 }
815
816 /* Mask conditions we're ignoring. */
817 sr &= port->read_status_mask;
818
819 if (sr & MSM_UART_SR_RX_BREAK)
820 flag = TTY_BREAK;
821 else if (sr & MSM_UART_SR_PAR_FRAME_ERR)
822 flag = TTY_FRAME;
823
824 sysrq = uart_prepare_sysrq_char(port, c);
825 if (!sysrq)
826 tty_insert_flip_char(tport, c, flag);
827 }
828
829 tty_flip_buffer_push(tport);
830}
831
832static void msm_handle_tx_pio(struct uart_port *port, unsigned int tx_count)
833{
834 struct circ_buf *xmit = &port->state->xmit;
835 struct msm_port *msm_port = to_msm_port(port);
836 unsigned int num_chars;
837 unsigned int tf_pointer = 0;
838 void __iomem *tf;
839
840 if (msm_port->is_uartdm)
841 tf = port->membase + UARTDM_TF;
842 else
843 tf = port->membase + MSM_UART_TF;
844
845 if (tx_count && msm_port->is_uartdm)
846 msm_reset_dm_count(port, tx_count);
847
848 while (tf_pointer < tx_count) {
849 int i;
850 char buf[4] = { 0 };
851
852 if (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY))
853 break;
854
855 if (msm_port->is_uartdm)
856 num_chars = min(tx_count - tf_pointer,
857 (unsigned int)sizeof(buf));
858 else
859 num_chars = 1;
860
861 for (i = 0; i < num_chars; i++)
862 buf[i] = xmit->buf[xmit->tail + i];
863
864 iowrite32_rep(tf, buf, 1);
865 uart_xmit_advance(port, num_chars);
866 tf_pointer += num_chars;
867 }
868
869 /* disable tx interrupts if nothing more to send */
870 if (uart_circ_empty(xmit))
871 msm_stop_tx(port);
872
873 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
874 uart_write_wakeup(port);
875}
876
877static void msm_handle_tx(struct uart_port *port)
878{
879 struct msm_port *msm_port = to_msm_port(port);
880 struct circ_buf *xmit = &msm_port->uart.state->xmit;
881 struct msm_dma *dma = &msm_port->tx_dma;
882 unsigned int pio_count, dma_count, dma_min;
883 char buf[4] = { 0 };
884 void __iomem *tf;
885 int err = 0;
886
887 if (port->x_char) {
888 if (msm_port->is_uartdm)
889 tf = port->membase + UARTDM_TF;
890 else
891 tf = port->membase + MSM_UART_TF;
892
893 buf[0] = port->x_char;
894
895 if (msm_port->is_uartdm)
896 msm_reset_dm_count(port, 1);
897
898 iowrite32_rep(tf, buf, 1);
899 port->icount.tx++;
900 port->x_char = 0;
901 return;
902 }
903
904 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
905 msm_stop_tx(port);
906 return;
907 }
908
909 pio_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
910 dma_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
911
912 dma_min = 1; /* Always DMA */
913 if (msm_port->is_uartdm > UARTDM_1P3) {
914 dma_count = UARTDM_TX_AIGN(dma_count);
915 dma_min = UARTDM_BURST_SIZE;
916 } else {
917 if (dma_count > UARTDM_TX_MAX)
918 dma_count = UARTDM_TX_MAX;
919 }
920
921 if (pio_count > port->fifosize)
922 pio_count = port->fifosize;
923
924 if (!dma->chan || dma_count < dma_min)
925 msm_handle_tx_pio(port, pio_count);
926 else
927 err = msm_handle_tx_dma(msm_port, dma_count);
928
929 if (err) /* fall back to PIO mode */
930 msm_handle_tx_pio(port, pio_count);
931}
932
933static void msm_handle_delta_cts(struct uart_port *port)
934{
935 msm_write(port, MSM_UART_CR_CMD_RESET_CTS, MSM_UART_CR);
936 port->icount.cts++;
937 wake_up_interruptible(&port->state->port.delta_msr_wait);
938}
939
940static irqreturn_t msm_uart_irq(int irq, void *dev_id)
941{
942 struct uart_port *port = dev_id;
943 struct msm_port *msm_port = to_msm_port(port);
944 struct msm_dma *dma = &msm_port->rx_dma;
945 unsigned int misr;
946 u32 val;
947
948 uart_port_lock(port);
949 misr = msm_read(port, MSM_UART_MISR);
950 msm_write(port, 0, MSM_UART_IMR); /* disable interrupt */
951
952 if (misr & MSM_UART_IMR_RXBREAK_START) {
953 msm_port->break_detected = true;
954 msm_write(port, MSM_UART_CR_CMD_RESET_RXBREAK_START, MSM_UART_CR);
955 }
956
957 if (misr & (MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE)) {
958 if (dma->count) {
959 val = MSM_UART_CR_CMD_STALE_EVENT_DISABLE;
960 msm_write(port, val, MSM_UART_CR);
961 val = MSM_UART_CR_CMD_RESET_STALE_INT;
962 msm_write(port, val, MSM_UART_CR);
963 /*
964 * Flush DMA input fifo to memory, this will also
965 * trigger DMA RX completion
966 */
967 dmaengine_terminate_all(dma->chan);
968 } else if (msm_port->is_uartdm) {
969 msm_handle_rx_dm(port, misr);
970 } else {
971 msm_handle_rx(port);
972 }
973 }
974 if (misr & MSM_UART_IMR_TXLEV)
975 msm_handle_tx(port);
976 if (misr & MSM_UART_IMR_DELTA_CTS)
977 msm_handle_delta_cts(port);
978
979 msm_write(port, msm_port->imr, MSM_UART_IMR); /* restore interrupt */
980 uart_unlock_and_check_sysrq(port);
981
982 return IRQ_HANDLED;
983}
984
985static unsigned int msm_tx_empty(struct uart_port *port)
986{
987 return (msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
988}
989
990static unsigned int msm_get_mctrl(struct uart_port *port)
991{
992 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
993}
994
995static void msm_reset(struct uart_port *port)
996{
997 struct msm_port *msm_port = to_msm_port(port);
998 unsigned int mr;
999
1000 /* reset everything */
1001 msm_write(port, MSM_UART_CR_CMD_RESET_RX, MSM_UART_CR);
1002 msm_write(port, MSM_UART_CR_CMD_RESET_TX, MSM_UART_CR);
1003 msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);
1004 msm_write(port, MSM_UART_CR_CMD_RESET_BREAK_INT, MSM_UART_CR);
1005 msm_write(port, MSM_UART_CR_CMD_RESET_CTS, MSM_UART_CR);
1006 msm_write(port, MSM_UART_CR_CMD_RESET_RFR, MSM_UART_CR);
1007 mr = msm_read(port, MSM_UART_MR1);
1008 mr &= ~MSM_UART_MR1_RX_RDY_CTL;
1009 msm_write(port, mr, MSM_UART_MR1);
1010
1011 /* Disable DM modes */
1012 if (msm_port->is_uartdm)
1013 msm_write(port, 0, UARTDM_DMEN);
1014}
1015
1016static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
1017{
1018 unsigned int mr;
1019
1020 mr = msm_read(port, MSM_UART_MR1);
1021
1022 if (!(mctrl & TIOCM_RTS)) {
1023 mr &= ~MSM_UART_MR1_RX_RDY_CTL;
1024 msm_write(port, mr, MSM_UART_MR1);
1025 msm_write(port, MSM_UART_CR_CMD_RESET_RFR, MSM_UART_CR);
1026 } else {
1027 mr |= MSM_UART_MR1_RX_RDY_CTL;
1028 msm_write(port, mr, MSM_UART_MR1);
1029 }
1030}
1031
1032static void msm_break_ctl(struct uart_port *port, int break_ctl)
1033{
1034 if (break_ctl)
1035 msm_write(port, MSM_UART_CR_CMD_START_BREAK, MSM_UART_CR);
1036 else
1037 msm_write(port, MSM_UART_CR_CMD_STOP_BREAK, MSM_UART_CR);
1038}
1039
1040struct msm_baud_map {
1041 u16 divisor;
1042 u8 code;
1043 u8 rxstale;
1044};
1045
1046static const struct msm_baud_map *
1047msm_find_best_baud(struct uart_port *port, unsigned int baud,
1048 unsigned long *rate)
1049{
1050 struct msm_port *msm_port = to_msm_port(port);
1051 unsigned int divisor, result;
1052 unsigned long target, old, best_rate = 0, diff, best_diff = ULONG_MAX;
1053 const struct msm_baud_map *entry, *end, *best;
1054 static const struct msm_baud_map table[] = {
1055 { 1, 0xff, 31 },
1056 { 2, 0xee, 16 },
1057 { 3, 0xdd, 8 },
1058 { 4, 0xcc, 6 },
1059 { 6, 0xbb, 6 },
1060 { 8, 0xaa, 6 },
1061 { 12, 0x99, 6 },
1062 { 16, 0x88, 1 },
1063 { 24, 0x77, 1 },
1064 { 32, 0x66, 1 },
1065 { 48, 0x55, 1 },
1066 { 96, 0x44, 1 },
1067 { 192, 0x33, 1 },
1068 { 384, 0x22, 1 },
1069 { 768, 0x11, 1 },
1070 { 1536, 0x00, 1 },
1071 };
1072
1073 best = table; /* Default to smallest divider */
1074 target = clk_round_rate(msm_port->clk, 16 * baud);
1075 divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
1076
1077 end = table + ARRAY_SIZE(table);
1078 entry = table;
1079 while (entry < end) {
1080 if (entry->divisor <= divisor) {
1081 result = target / entry->divisor / 16;
1082 diff = abs(result - baud);
1083
1084 /* Keep track of best entry */
1085 if (diff < best_diff) {
1086 best_diff = diff;
1087 best = entry;
1088 best_rate = target;
1089 }
1090
1091 if (result == baud)
1092 break;
1093 } else if (entry->divisor > divisor) {
1094 old = target;
1095 target = clk_round_rate(msm_port->clk, old + 1);
1096 /*
1097 * The rate didn't get any faster so we can't do
1098 * better at dividing it down
1099 */
1100 if (target == old)
1101 break;
1102
1103 /* Start the divisor search over at this new rate */
1104 entry = table;
1105 divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
1106 continue;
1107 }
1108 entry++;
1109 }
1110
1111 *rate = best_rate;
1112 return best;
1113}
1114
1115static int msm_set_baud_rate(struct uart_port *port, unsigned int baud,
1116 unsigned long *saved_flags)
1117 __must_hold(&port->lock)
1118{
1119 unsigned int rxstale, watermark, mask;
1120 struct msm_port *msm_port = to_msm_port(port);
1121 const struct msm_baud_map *entry;
1122 unsigned long flags, rate;
1123
1124 flags = *saved_flags;
1125 uart_port_unlock_irqrestore(port, flags);
1126
1127 entry = msm_find_best_baud(port, baud, &rate);
1128 dev_pm_opp_set_rate(port->dev, rate);
1129 baud = rate / 16 / entry->divisor;
1130
1131 uart_port_lock_irqsave(port, &flags);
1132 *saved_flags = flags;
1133 port->uartclk = rate;
1134
1135 msm_write(port, entry->code, MSM_UART_CSR);
1136
1137 /* RX stale watermark */
1138 rxstale = entry->rxstale;
1139 watermark = MSM_UART_IPR_STALE_LSB & rxstale;
1140 if (msm_port->is_uartdm) {
1141 mask = MSM_UART_DM_IPR_STALE_TIMEOUT_MSB;
1142 } else {
1143 watermark |= MSM_UART_IPR_RXSTALE_LAST;
1144 mask = MSM_UART_IPR_STALE_TIMEOUT_MSB;
1145 }
1146
1147 watermark |= mask & (rxstale << 2);
1148
1149 msm_write(port, watermark, MSM_UART_IPR);
1150
1151 /* set RX watermark */
1152 watermark = (port->fifosize * 3) / 4;
1153 msm_write(port, watermark, MSM_UART_RFWR);
1154
1155 /* set TX watermark */
1156 msm_write(port, 10, MSM_UART_TFWR);
1157
1158 msm_write(port, MSM_UART_CR_CMD_PROTECTION_EN, MSM_UART_CR);
1159 msm_reset(port);
1160
1161 /* Enable RX and TX */
1162 msm_write(port, MSM_UART_CR_TX_ENABLE | MSM_UART_CR_RX_ENABLE, MSM_UART_CR);
1163
1164 /* turn on RX and CTS interrupts */
1165 msm_port->imr = MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE |
1166 MSM_UART_IMR_CURRENT_CTS | MSM_UART_IMR_RXBREAK_START;
1167
1168 msm_write(port, msm_port->imr, MSM_UART_IMR);
1169
1170 if (msm_port->is_uartdm) {
1171 msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);
1172 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1173 msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);
1174 }
1175
1176 return baud;
1177}
1178
1179static void msm_init_clock(struct uart_port *port)
1180{
1181 struct msm_port *msm_port = to_msm_port(port);
1182
1183 dev_pm_opp_set_rate(port->dev, port->uartclk);
1184 clk_prepare_enable(msm_port->clk);
1185 clk_prepare_enable(msm_port->pclk);
1186 msm_serial_set_mnd_regs(port);
1187}
1188
1189static int msm_startup(struct uart_port *port)
1190{
1191 struct msm_port *msm_port = to_msm_port(port);
1192 unsigned int data, rfr_level, mask;
1193 int ret;
1194
1195 snprintf(msm_port->name, sizeof(msm_port->name),
1196 "msm_serial%d", port->line);
1197
1198 msm_init_clock(port);
1199
1200 if (likely(port->fifosize > 12))
1201 rfr_level = port->fifosize - 12;
1202 else
1203 rfr_level = port->fifosize;
1204
1205 /* set automatic RFR level */
1206 data = msm_read(port, MSM_UART_MR1);
1207
1208 if (msm_port->is_uartdm)
1209 mask = MSM_UART_DM_MR1_AUTO_RFR_LEVEL1;
1210 else
1211 mask = MSM_UART_MR1_AUTO_RFR_LEVEL1;
1212
1213 data &= ~mask;
1214 data &= ~MSM_UART_MR1_AUTO_RFR_LEVEL0;
1215 data |= mask & (rfr_level << 2);
1216 data |= MSM_UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
1217 msm_write(port, data, MSM_UART_MR1);
1218
1219 if (msm_port->is_uartdm) {
1220 msm_request_tx_dma(msm_port, msm_port->uart.mapbase);
1221 msm_request_rx_dma(msm_port, msm_port->uart.mapbase);
1222 }
1223
1224 ret = request_irq(port->irq, msm_uart_irq, IRQF_TRIGGER_HIGH,
1225 msm_port->name, port);
1226 if (unlikely(ret))
1227 goto err_irq;
1228
1229 return 0;
1230
1231err_irq:
1232 if (msm_port->is_uartdm)
1233 msm_release_dma(msm_port);
1234
1235 clk_disable_unprepare(msm_port->pclk);
1236 clk_disable_unprepare(msm_port->clk);
1237 dev_pm_opp_set_rate(port->dev, 0);
1238
1239 return ret;
1240}
1241
1242static void msm_shutdown(struct uart_port *port)
1243{
1244 struct msm_port *msm_port = to_msm_port(port);
1245
1246 msm_port->imr = 0;
1247 msm_write(port, 0, MSM_UART_IMR); /* disable interrupts */
1248
1249 if (msm_port->is_uartdm)
1250 msm_release_dma(msm_port);
1251
1252 clk_disable_unprepare(msm_port->clk);
1253 dev_pm_opp_set_rate(port->dev, 0);
1254
1255 free_irq(port->irq, port);
1256}
1257
1258static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
1259 const struct ktermios *old)
1260{
1261 struct msm_port *msm_port = to_msm_port(port);
1262 struct msm_dma *dma = &msm_port->rx_dma;
1263 unsigned long flags;
1264 unsigned int baud, mr;
1265
1266 uart_port_lock_irqsave(port, &flags);
1267
1268 if (dma->chan) /* Terminate if any */
1269 msm_stop_dma(port, dma);
1270
1271 /* calculate and set baud rate */
1272 baud = uart_get_baud_rate(port, termios, old, 300, 4000000);
1273 baud = msm_set_baud_rate(port, baud, &flags);
1274 if (tty_termios_baud_rate(termios))
1275 tty_termios_encode_baud_rate(termios, baud, baud);
1276
1277 /* calculate parity */
1278 mr = msm_read(port, MSM_UART_MR2);
1279 mr &= ~MSM_UART_MR2_PARITY_MODE;
1280 if (termios->c_cflag & PARENB) {
1281 if (termios->c_cflag & PARODD)
1282 mr |= MSM_UART_MR2_PARITY_MODE_ODD;
1283 else if (termios->c_cflag & CMSPAR)
1284 mr |= MSM_UART_MR2_PARITY_MODE_SPACE;
1285 else
1286 mr |= MSM_UART_MR2_PARITY_MODE_EVEN;
1287 }
1288
1289 /* calculate bits per char */
1290 mr &= ~MSM_UART_MR2_BITS_PER_CHAR;
1291 switch (termios->c_cflag & CSIZE) {
1292 case CS5:
1293 mr |= MSM_UART_MR2_BITS_PER_CHAR_5;
1294 break;
1295 case CS6:
1296 mr |= MSM_UART_MR2_BITS_PER_CHAR_6;
1297 break;
1298 case CS7:
1299 mr |= MSM_UART_MR2_BITS_PER_CHAR_7;
1300 break;
1301 case CS8:
1302 default:
1303 mr |= MSM_UART_MR2_BITS_PER_CHAR_8;
1304 break;
1305 }
1306
1307 /* calculate stop bits */
1308 mr &= ~(MSM_UART_MR2_STOP_BIT_LEN_ONE | MSM_UART_MR2_STOP_BIT_LEN_TWO);
1309 if (termios->c_cflag & CSTOPB)
1310 mr |= MSM_UART_MR2_STOP_BIT_LEN_TWO;
1311 else
1312 mr |= MSM_UART_MR2_STOP_BIT_LEN_ONE;
1313
1314 /* set parity, bits per char, and stop bit */
1315 msm_write(port, mr, MSM_UART_MR2);
1316
1317 /* calculate and set hardware flow control */
1318 mr = msm_read(port, MSM_UART_MR1);
1319 mr &= ~(MSM_UART_MR1_CTS_CTL | MSM_UART_MR1_RX_RDY_CTL);
1320 if (termios->c_cflag & CRTSCTS) {
1321 mr |= MSM_UART_MR1_CTS_CTL;
1322 mr |= MSM_UART_MR1_RX_RDY_CTL;
1323 }
1324 msm_write(port, mr, MSM_UART_MR1);
1325
1326 /* Configure status bits to ignore based on termio flags. */
1327 port->read_status_mask = 0;
1328 if (termios->c_iflag & INPCK)
1329 port->read_status_mask |= MSM_UART_SR_PAR_FRAME_ERR;
1330 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1331 port->read_status_mask |= MSM_UART_SR_RX_BREAK;
1332
1333 uart_update_timeout(port, termios->c_cflag, baud);
1334
1335 /* Try to use DMA */
1336 msm_start_rx_dma(msm_port);
1337
1338 uart_port_unlock_irqrestore(port, flags);
1339}
1340
1341static const char *msm_type(struct uart_port *port)
1342{
1343 return "MSM";
1344}
1345
1346static void msm_release_port(struct uart_port *port)
1347{
1348 struct platform_device *pdev = to_platform_device(port->dev);
1349 struct resource *uart_resource;
1350 resource_size_t size;
1351
1352 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1353 if (unlikely(!uart_resource))
1354 return;
1355 size = resource_size(uart_resource);
1356
1357 release_mem_region(port->mapbase, size);
1358 iounmap(port->membase);
1359 port->membase = NULL;
1360}
1361
1362static int msm_request_port(struct uart_port *port)
1363{
1364 struct platform_device *pdev = to_platform_device(port->dev);
1365 struct resource *uart_resource;
1366 resource_size_t size;
1367 int ret;
1368
1369 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1370 if (unlikely(!uart_resource))
1371 return -ENXIO;
1372
1373 size = resource_size(uart_resource);
1374
1375 if (!request_mem_region(port->mapbase, size, "msm_serial"))
1376 return -EBUSY;
1377
1378 port->membase = ioremap(port->mapbase, size);
1379 if (!port->membase) {
1380 ret = -EBUSY;
1381 goto fail_release_port;
1382 }
1383
1384 return 0;
1385
1386fail_release_port:
1387 release_mem_region(port->mapbase, size);
1388 return ret;
1389}
1390
1391static void msm_config_port(struct uart_port *port, int flags)
1392{
1393 int ret;
1394
1395 if (flags & UART_CONFIG_TYPE) {
1396 port->type = PORT_MSM;
1397 ret = msm_request_port(port);
1398 if (ret)
1399 return;
1400 }
1401}
1402
1403static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
1404{
1405 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
1406 return -EINVAL;
1407 if (unlikely(port->irq != ser->irq))
1408 return -EINVAL;
1409 return 0;
1410}
1411
1412static void msm_power(struct uart_port *port, unsigned int state,
1413 unsigned int oldstate)
1414{
1415 struct msm_port *msm_port = to_msm_port(port);
1416
1417 switch (state) {
1418 case 0:
1419 dev_pm_opp_set_rate(port->dev, port->uartclk);
1420 clk_prepare_enable(msm_port->clk);
1421 clk_prepare_enable(msm_port->pclk);
1422 break;
1423 case 3:
1424 clk_disable_unprepare(msm_port->clk);
1425 dev_pm_opp_set_rate(port->dev, 0);
1426 clk_disable_unprepare(msm_port->pclk);
1427 break;
1428 default:
1429 pr_err("msm_serial: Unknown PM state %d\n", state);
1430 }
1431}
1432
1433#ifdef CONFIG_CONSOLE_POLL
1434static int msm_poll_get_char_single(struct uart_port *port)
1435{
1436 struct msm_port *msm_port = to_msm_port(port);
1437 unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : MSM_UART_RF;
1438
1439 if (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_RX_READY))
1440 return NO_POLL_CHAR;
1441
1442 return msm_read(port, rf_reg) & 0xff;
1443}
1444
1445static int msm_poll_get_char_dm(struct uart_port *port)
1446{
1447 int c;
1448 static u32 slop;
1449 static int count;
1450 unsigned char *sp = (unsigned char *)&slop;
1451
1452 /* Check if a previous read had more than one char */
1453 if (count) {
1454 c = sp[sizeof(slop) - count];
1455 count--;
1456 /* Or if FIFO is empty */
1457 } else if (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_RX_READY)) {
1458 /*
1459 * If RX packing buffer has less than a word, force stale to
1460 * push contents into RX FIFO
1461 */
1462 count = msm_read(port, UARTDM_RXFS);
1463 count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK;
1464 if (count) {
1465 msm_write(port, MSM_UART_CR_CMD_FORCE_STALE, MSM_UART_CR);
1466 slop = msm_read(port, UARTDM_RF);
1467 c = sp[0];
1468 count--;
1469 msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);
1470 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1471 msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);
1472 } else {
1473 c = NO_POLL_CHAR;
1474 }
1475 /* FIFO has a word */
1476 } else {
1477 slop = msm_read(port, UARTDM_RF);
1478 c = sp[0];
1479 count = sizeof(slop) - 1;
1480 }
1481
1482 return c;
1483}
1484
1485static int msm_poll_get_char(struct uart_port *port)
1486{
1487 u32 imr;
1488 int c;
1489 struct msm_port *msm_port = to_msm_port(port);
1490
1491 /* Disable all interrupts */
1492 imr = msm_read(port, MSM_UART_IMR);
1493 msm_write(port, 0, MSM_UART_IMR);
1494
1495 if (msm_port->is_uartdm)
1496 c = msm_poll_get_char_dm(port);
1497 else
1498 c = msm_poll_get_char_single(port);
1499
1500 /* Enable interrupts */
1501 msm_write(port, imr, MSM_UART_IMR);
1502
1503 return c;
1504}
1505
1506static void msm_poll_put_char(struct uart_port *port, unsigned char c)
1507{
1508 u32 imr;
1509 struct msm_port *msm_port = to_msm_port(port);
1510
1511 /* Disable all interrupts */
1512 imr = msm_read(port, MSM_UART_IMR);
1513 msm_write(port, 0, MSM_UART_IMR);
1514
1515 if (msm_port->is_uartdm)
1516 msm_reset_dm_count(port, 1);
1517
1518 /* Wait until FIFO is empty */
1519 while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY))
1520 cpu_relax();
1521
1522 /* Write a character */
1523 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : MSM_UART_TF);
1524
1525 /* Wait until FIFO is empty */
1526 while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY))
1527 cpu_relax();
1528
1529 /* Enable interrupts */
1530 msm_write(port, imr, MSM_UART_IMR);
1531}
1532#endif
1533
1534static const struct uart_ops msm_uart_pops = {
1535 .tx_empty = msm_tx_empty,
1536 .set_mctrl = msm_set_mctrl,
1537 .get_mctrl = msm_get_mctrl,
1538 .stop_tx = msm_stop_tx,
1539 .start_tx = msm_start_tx,
1540 .stop_rx = msm_stop_rx,
1541 .enable_ms = msm_enable_ms,
1542 .break_ctl = msm_break_ctl,
1543 .startup = msm_startup,
1544 .shutdown = msm_shutdown,
1545 .set_termios = msm_set_termios,
1546 .type = msm_type,
1547 .release_port = msm_release_port,
1548 .request_port = msm_request_port,
1549 .config_port = msm_config_port,
1550 .verify_port = msm_verify_port,
1551 .pm = msm_power,
1552#ifdef CONFIG_CONSOLE_POLL
1553 .poll_get_char = msm_poll_get_char,
1554 .poll_put_char = msm_poll_put_char,
1555#endif
1556};
1557
1558static struct msm_port msm_uart_ports[] = {
1559 {
1560 .uart = {
1561 .iotype = UPIO_MEM,
1562 .ops = &msm_uart_pops,
1563 .flags = UPF_BOOT_AUTOCONF,
1564 .fifosize = 64,
1565 .line = 0,
1566 },
1567 },
1568 {
1569 .uart = {
1570 .iotype = UPIO_MEM,
1571 .ops = &msm_uart_pops,
1572 .flags = UPF_BOOT_AUTOCONF,
1573 .fifosize = 64,
1574 .line = 1,
1575 },
1576 },
1577 {
1578 .uart = {
1579 .iotype = UPIO_MEM,
1580 .ops = &msm_uart_pops,
1581 .flags = UPF_BOOT_AUTOCONF,
1582 .fifosize = 64,
1583 .line = 2,
1584 },
1585 },
1586};
1587
1588#define MSM_UART_NR ARRAY_SIZE(msm_uart_ports)
1589
1590static inline struct uart_port *msm_get_port_from_line(unsigned int line)
1591{
1592 return &msm_uart_ports[line].uart;
1593}
1594
1595#ifdef CONFIG_SERIAL_MSM_CONSOLE
1596static void __msm_console_write(struct uart_port *port, const char *s,
1597 unsigned int count, bool is_uartdm)
1598{
1599 unsigned long flags;
1600 int i;
1601 int num_newlines = 0;
1602 bool replaced = false;
1603 void __iomem *tf;
1604 int locked = 1;
1605
1606 if (is_uartdm)
1607 tf = port->membase + UARTDM_TF;
1608 else
1609 tf = port->membase + MSM_UART_TF;
1610
1611 /* Account for newlines that will get a carriage return added */
1612 for (i = 0; i < count; i++)
1613 if (s[i] == '\n')
1614 num_newlines++;
1615 count += num_newlines;
1616
1617 if (oops_in_progress)
1618 locked = uart_port_trylock_irqsave(port, &flags);
1619 else
1620 uart_port_lock_irqsave(port, &flags);
1621
1622 if (is_uartdm)
1623 msm_reset_dm_count(port, count);
1624
1625 i = 0;
1626 while (i < count) {
1627 int j;
1628 unsigned int num_chars;
1629 char buf[4] = { 0 };
1630
1631 if (is_uartdm)
1632 num_chars = min(count - i, (unsigned int)sizeof(buf));
1633 else
1634 num_chars = 1;
1635
1636 for (j = 0; j < num_chars; j++) {
1637 char c = *s;
1638
1639 if (c == '\n' && !replaced) {
1640 buf[j] = '\r';
1641 j++;
1642 replaced = true;
1643 }
1644 if (j < num_chars) {
1645 buf[j] = c;
1646 s++;
1647 replaced = false;
1648 }
1649 }
1650
1651 while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY))
1652 cpu_relax();
1653
1654 iowrite32_rep(tf, buf, 1);
1655 i += num_chars;
1656 }
1657
1658 if (locked)
1659 uart_port_unlock_irqrestore(port, flags);
1660}
1661
1662static void msm_console_write(struct console *co, const char *s,
1663 unsigned int count)
1664{
1665 struct uart_port *port;
1666 struct msm_port *msm_port;
1667
1668 BUG_ON(co->index < 0 || co->index >= MSM_UART_NR);
1669
1670 port = msm_get_port_from_line(co->index);
1671 msm_port = to_msm_port(port);
1672
1673 __msm_console_write(port, s, count, msm_port->is_uartdm);
1674}
1675
1676static int msm_console_setup(struct console *co, char *options)
1677{
1678 struct uart_port *port;
1679 int baud = 115200;
1680 int bits = 8;
1681 int parity = 'n';
1682 int flow = 'n';
1683
1684 if (unlikely(co->index >= MSM_UART_NR || co->index < 0))
1685 return -ENXIO;
1686
1687 port = msm_get_port_from_line(co->index);
1688
1689 if (unlikely(!port->membase))
1690 return -ENXIO;
1691
1692 msm_init_clock(port);
1693
1694 if (options)
1695 uart_parse_options(options, &baud, &parity, &bits, &flow);
1696
1697 pr_info("msm_serial: console setup on port #%d\n", port->line);
1698
1699 return uart_set_options(port, co, baud, parity, bits, flow);
1700}
1701
1702static void
1703msm_serial_early_write(struct console *con, const char *s, unsigned n)
1704{
1705 struct earlycon_device *dev = con->data;
1706
1707 __msm_console_write(&dev->port, s, n, false);
1708}
1709
1710static int __init
1711msm_serial_early_console_setup(struct earlycon_device *device, const char *opt)
1712{
1713 if (!device->port.membase)
1714 return -ENODEV;
1715
1716 device->con->write = msm_serial_early_write;
1717 return 0;
1718}
1719OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart",
1720 msm_serial_early_console_setup);
1721
1722static void
1723msm_serial_early_write_dm(struct console *con, const char *s, unsigned n)
1724{
1725 struct earlycon_device *dev = con->data;
1726
1727 __msm_console_write(&dev->port, s, n, true);
1728}
1729
1730static int __init
1731msm_serial_early_console_setup_dm(struct earlycon_device *device,
1732 const char *opt)
1733{
1734 if (!device->port.membase)
1735 return -ENODEV;
1736
1737 device->con->write = msm_serial_early_write_dm;
1738 return 0;
1739}
1740OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm",
1741 msm_serial_early_console_setup_dm);
1742
1743static struct uart_driver msm_uart_driver;
1744
1745static struct console msm_console = {
1746 .name = "ttyMSM",
1747 .write = msm_console_write,
1748 .device = uart_console_device,
1749 .setup = msm_console_setup,
1750 .flags = CON_PRINTBUFFER,
1751 .index = -1,
1752 .data = &msm_uart_driver,
1753};
1754
1755#define MSM_CONSOLE (&msm_console)
1756
1757#else
1758#define MSM_CONSOLE NULL
1759#endif
1760
1761static struct uart_driver msm_uart_driver = {
1762 .owner = THIS_MODULE,
1763 .driver_name = "msm_serial",
1764 .dev_name = "ttyMSM",
1765 .nr = MSM_UART_NR,
1766 .cons = MSM_CONSOLE,
1767};
1768
1769static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
1770
1771static const struct of_device_id msm_uartdm_table[] = {
1772 { .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 },
1773 { .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 },
1774 { .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 },
1775 { .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 },
1776 { }
1777};
1778
1779static int msm_serial_probe(struct platform_device *pdev)
1780{
1781 struct msm_port *msm_port;
1782 struct resource *resource;
1783 struct uart_port *port;
1784 const struct of_device_id *id;
1785 int irq, line, ret;
1786
1787 if (pdev->dev.of_node)
1788 line = of_alias_get_id(pdev->dev.of_node, "serial");
1789 else
1790 line = pdev->id;
1791
1792 if (line < 0)
1793 line = atomic_inc_return(&msm_uart_next_id) - 1;
1794
1795 if (unlikely(line < 0 || line >= MSM_UART_NR))
1796 return -ENXIO;
1797
1798 dev_info(&pdev->dev, "msm_serial: detected port #%d\n", line);
1799
1800 port = msm_get_port_from_line(line);
1801 port->dev = &pdev->dev;
1802 msm_port = to_msm_port(port);
1803
1804 id = of_match_device(msm_uartdm_table, &pdev->dev);
1805 if (id)
1806 msm_port->is_uartdm = (unsigned long)id->data;
1807 else
1808 msm_port->is_uartdm = 0;
1809
1810 msm_port->clk = devm_clk_get(&pdev->dev, "core");
1811 if (IS_ERR(msm_port->clk))
1812 return PTR_ERR(msm_port->clk);
1813
1814 if (msm_port->is_uartdm) {
1815 msm_port->pclk = devm_clk_get(&pdev->dev, "iface");
1816 if (IS_ERR(msm_port->pclk))
1817 return PTR_ERR(msm_port->pclk);
1818 }
1819
1820 ret = devm_pm_opp_set_clkname(&pdev->dev, "core");
1821 if (ret)
1822 return ret;
1823
1824 /* OPP table is optional */
1825 ret = devm_pm_opp_of_add_table(&pdev->dev);
1826 if (ret && ret != -ENODEV)
1827 return dev_err_probe(&pdev->dev, ret, "invalid OPP table\n");
1828
1829 port->uartclk = clk_get_rate(msm_port->clk);
1830 dev_info(&pdev->dev, "uartclk = %d\n", port->uartclk);
1831
1832 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1833 if (unlikely(!resource))
1834 return -ENXIO;
1835 port->mapbase = resource->start;
1836
1837 irq = platform_get_irq(pdev, 0);
1838 if (unlikely(irq < 0))
1839 return -ENXIO;
1840 port->irq = irq;
1841 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MSM_CONSOLE);
1842
1843 platform_set_drvdata(pdev, port);
1844
1845 return uart_add_one_port(&msm_uart_driver, port);
1846}
1847
1848static void msm_serial_remove(struct platform_device *pdev)
1849{
1850 struct uart_port *port = platform_get_drvdata(pdev);
1851
1852 uart_remove_one_port(&msm_uart_driver, port);
1853}
1854
1855static const struct of_device_id msm_match_table[] = {
1856 { .compatible = "qcom,msm-uart" },
1857 { .compatible = "qcom,msm-uartdm" },
1858 {}
1859};
1860MODULE_DEVICE_TABLE(of, msm_match_table);
1861
1862static int __maybe_unused msm_serial_suspend(struct device *dev)
1863{
1864 struct msm_port *port = dev_get_drvdata(dev);
1865
1866 uart_suspend_port(&msm_uart_driver, &port->uart);
1867
1868 return 0;
1869}
1870
1871static int __maybe_unused msm_serial_resume(struct device *dev)
1872{
1873 struct msm_port *port = dev_get_drvdata(dev);
1874
1875 uart_resume_port(&msm_uart_driver, &port->uart);
1876
1877 return 0;
1878}
1879
1880static const struct dev_pm_ops msm_serial_dev_pm_ops = {
1881 SET_SYSTEM_SLEEP_PM_OPS(msm_serial_suspend, msm_serial_resume)
1882};
1883
1884static struct platform_driver msm_platform_driver = {
1885 .remove_new = msm_serial_remove,
1886 .probe = msm_serial_probe,
1887 .driver = {
1888 .name = "msm_serial",
1889 .pm = &msm_serial_dev_pm_ops,
1890 .of_match_table = msm_match_table,
1891 },
1892};
1893
1894static int __init msm_serial_init(void)
1895{
1896 int ret;
1897
1898 ret = uart_register_driver(&msm_uart_driver);
1899 if (unlikely(ret))
1900 return ret;
1901
1902 ret = platform_driver_register(&msm_platform_driver);
1903 if (unlikely(ret))
1904 uart_unregister_driver(&msm_uart_driver);
1905
1906 pr_info("msm_serial: driver initialized\n");
1907
1908 return ret;
1909}
1910
1911static void __exit msm_serial_exit(void)
1912{
1913 platform_driver_unregister(&msm_platform_driver);
1914 uart_unregister_driver(&msm_uart_driver);
1915}
1916
1917module_init(msm_serial_init);
1918module_exit(msm_serial_exit);
1919
1920MODULE_AUTHOR("Robert Love <rlove@google.com>");
1921MODULE_DESCRIPTION("Driver for msm7x serial device");
1922MODULE_LICENSE("GPL");