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1/*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24/*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30#include <linux/dma-mapping.h>
31#include <linux/swiotlb.h>
32
33#include "nouveau_drv.h"
34#include "nouveau_dma.h"
35#include "nouveau_fence.h"
36
37#include "nouveau_bo.h"
38#include "nouveau_ttm.h"
39#include "nouveau_gem.h"
40#include "nouveau_mem.h"
41#include "nouveau_vmm.h"
42
43#include <nvif/class.h>
44#include <nvif/if500b.h>
45#include <nvif/if900b.h>
46
47/*
48 * NV10-NV40 tiling helpers
49 */
50
51static void
52nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
53 u32 addr, u32 size, u32 pitch, u32 flags)
54{
55 struct nouveau_drm *drm = nouveau_drm(dev);
56 int i = reg - drm->tile.reg;
57 struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
58 struct nvkm_fb_tile *tile = &fb->tile.region[i];
59
60 nouveau_fence_unref(®->fence);
61
62 if (tile->pitch)
63 nvkm_fb_tile_fini(fb, i, tile);
64
65 if (pitch)
66 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
67
68 nvkm_fb_tile_prog(fb, i, tile);
69}
70
71static struct nouveau_drm_tile *
72nv10_bo_get_tile_region(struct drm_device *dev, int i)
73{
74 struct nouveau_drm *drm = nouveau_drm(dev);
75 struct nouveau_drm_tile *tile = &drm->tile.reg[i];
76
77 spin_lock(&drm->tile.lock);
78
79 if (!tile->used &&
80 (!tile->fence || nouveau_fence_done(tile->fence)))
81 tile->used = true;
82 else
83 tile = NULL;
84
85 spin_unlock(&drm->tile.lock);
86 return tile;
87}
88
89static void
90nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
91 struct dma_fence *fence)
92{
93 struct nouveau_drm *drm = nouveau_drm(dev);
94
95 if (tile) {
96 spin_lock(&drm->tile.lock);
97 tile->fence = (struct nouveau_fence *)dma_fence_get(fence);
98 tile->used = false;
99 spin_unlock(&drm->tile.lock);
100 }
101}
102
103static struct nouveau_drm_tile *
104nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
105 u32 size, u32 pitch, u32 zeta)
106{
107 struct nouveau_drm *drm = nouveau_drm(dev);
108 struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
109 struct nouveau_drm_tile *tile, *found = NULL;
110 int i;
111
112 for (i = 0; i < fb->tile.regions; i++) {
113 tile = nv10_bo_get_tile_region(dev, i);
114
115 if (pitch && !found) {
116 found = tile;
117 continue;
118
119 } else if (tile && fb->tile.region[i].pitch) {
120 /* Kill an unused tile region. */
121 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
122 }
123
124 nv10_bo_put_tile_region(dev, tile, NULL);
125 }
126
127 if (found)
128 nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta);
129 return found;
130}
131
132static void
133nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
134{
135 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
136 struct drm_device *dev = drm->dev;
137 struct nouveau_bo *nvbo = nouveau_bo(bo);
138
139 WARN_ON(nvbo->pin_refcnt > 0);
140 nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
141
142 /*
143 * If nouveau_bo_new() allocated this buffer, the GEM object was never
144 * initialized, so don't attempt to release it.
145 */
146 if (bo->base.dev)
147 drm_gem_object_release(&bo->base);
148
149 kfree(nvbo);
150}
151
152static inline u64
153roundup_64(u64 x, u32 y)
154{
155 x += y - 1;
156 do_div(x, y);
157 return x * y;
158}
159
160static void
161nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
162 int *align, u64 *size)
163{
164 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
165 struct nvif_device *device = &drm->client.device;
166
167 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
168 if (nvbo->mode) {
169 if (device->info.chipset >= 0x40) {
170 *align = 65536;
171 *size = roundup_64(*size, 64 * nvbo->mode);
172
173 } else if (device->info.chipset >= 0x30) {
174 *align = 32768;
175 *size = roundup_64(*size, 64 * nvbo->mode);
176
177 } else if (device->info.chipset >= 0x20) {
178 *align = 16384;
179 *size = roundup_64(*size, 64 * nvbo->mode);
180
181 } else if (device->info.chipset >= 0x10) {
182 *align = 16384;
183 *size = roundup_64(*size, 32 * nvbo->mode);
184 }
185 }
186 } else {
187 *size = roundup_64(*size, (1 << nvbo->page));
188 *align = max((1 << nvbo->page), *align);
189 }
190
191 *size = roundup_64(*size, PAGE_SIZE);
192}
193
194struct nouveau_bo *
195nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 flags,
196 u32 tile_mode, u32 tile_flags)
197{
198 struct nouveau_drm *drm = cli->drm;
199 struct nouveau_bo *nvbo;
200 struct nvif_mmu *mmu = &cli->mmu;
201 struct nvif_vmm *vmm = cli->svm.cli ? &cli->svm.vmm : &cli->vmm.vmm;
202 int i, pi = -1;
203
204 if (!*size) {
205 NV_WARN(drm, "skipped size %016llx\n", *size);
206 return ERR_PTR(-EINVAL);
207 }
208
209 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
210 if (!nvbo)
211 return ERR_PTR(-ENOMEM);
212 INIT_LIST_HEAD(&nvbo->head);
213 INIT_LIST_HEAD(&nvbo->entry);
214 INIT_LIST_HEAD(&nvbo->vma_list);
215 nvbo->bo.bdev = &drm->ttm.bdev;
216
217 /* This is confusing, and doesn't actually mean we want an uncached
218 * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated
219 * into in nouveau_gem_new().
220 */
221 if (flags & TTM_PL_FLAG_UNCACHED) {
222 /* Determine if we can get a cache-coherent map, forcing
223 * uncached mapping if we can't.
224 */
225 if (!nouveau_drm_use_coherent_gpu_mapping(drm))
226 nvbo->force_coherent = true;
227 }
228
229 if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) {
230 nvbo->kind = (tile_flags & 0x0000ff00) >> 8;
231 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
232 kfree(nvbo);
233 return ERR_PTR(-EINVAL);
234 }
235
236 nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind;
237 } else
238 if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
239 nvbo->kind = (tile_flags & 0x00007f00) >> 8;
240 nvbo->comp = (tile_flags & 0x00030000) >> 16;
241 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
242 kfree(nvbo);
243 return ERR_PTR(-EINVAL);
244 }
245 } else {
246 nvbo->zeta = (tile_flags & 0x00000007);
247 }
248 nvbo->mode = tile_mode;
249 nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG);
250
251 /* Determine the desirable target GPU page size for the buffer. */
252 for (i = 0; i < vmm->page_nr; i++) {
253 /* Because we cannot currently allow VMM maps to fail
254 * during buffer migration, we need to determine page
255 * size for the buffer up-front, and pre-allocate its
256 * page tables.
257 *
258 * Skip page sizes that can't support needed domains.
259 */
260 if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE &&
261 (flags & TTM_PL_FLAG_VRAM) && !vmm->page[i].vram)
262 continue;
263 if ((flags & TTM_PL_FLAG_TT) &&
264 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))
265 continue;
266
267 /* Select this page size if it's the first that supports
268 * the potential memory domains, or when it's compatible
269 * with the requested compression settings.
270 */
271 if (pi < 0 || !nvbo->comp || vmm->page[i].comp)
272 pi = i;
273
274 /* Stop once the buffer is larger than the current page size. */
275 if (*size >= 1ULL << vmm->page[i].shift)
276 break;
277 }
278
279 if (WARN_ON(pi < 0))
280 return ERR_PTR(-EINVAL);
281
282 /* Disable compression if suitable settings couldn't be found. */
283 if (nvbo->comp && !vmm->page[pi].comp) {
284 if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100)
285 nvbo->kind = mmu->kind[nvbo->kind];
286 nvbo->comp = 0;
287 }
288 nvbo->page = vmm->page[pi].shift;
289
290 nouveau_bo_fixup_align(nvbo, flags, align, size);
291
292 return nvbo;
293}
294
295int
296nouveau_bo_init(struct nouveau_bo *nvbo, u64 size, int align, u32 flags,
297 struct sg_table *sg, struct dma_resv *robj)
298{
299 int type = sg ? ttm_bo_type_sg : ttm_bo_type_device;
300 size_t acc_size;
301 int ret;
302
303 acc_size = ttm_bo_dma_acc_size(nvbo->bo.bdev, size, sizeof(*nvbo));
304
305 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
306 nouveau_bo_placement_set(nvbo, flags, 0);
307
308 ret = ttm_bo_init(nvbo->bo.bdev, &nvbo->bo, size, type,
309 &nvbo->placement, align >> PAGE_SHIFT, false,
310 acc_size, sg, robj, nouveau_bo_del_ttm);
311 if (ret) {
312 /* ttm will call nouveau_bo_del_ttm if it fails.. */
313 return ret;
314 }
315
316 return 0;
317}
318
319int
320nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align,
321 uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
322 struct sg_table *sg, struct dma_resv *robj,
323 struct nouveau_bo **pnvbo)
324{
325 struct nouveau_bo *nvbo;
326 int ret;
327
328 nvbo = nouveau_bo_alloc(cli, &size, &align, flags, tile_mode,
329 tile_flags);
330 if (IS_ERR(nvbo))
331 return PTR_ERR(nvbo);
332
333 ret = nouveau_bo_init(nvbo, size, align, flags, sg, robj);
334 if (ret)
335 return ret;
336
337 *pnvbo = nvbo;
338 return 0;
339}
340
341static void
342set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t type, uint32_t flags)
343{
344 *n = 0;
345
346 if (type & TTM_PL_FLAG_VRAM)
347 pl[(*n)++].flags = TTM_PL_FLAG_VRAM | flags;
348 if (type & TTM_PL_FLAG_TT)
349 pl[(*n)++].flags = TTM_PL_FLAG_TT | flags;
350 if (type & TTM_PL_FLAG_SYSTEM)
351 pl[(*n)++].flags = TTM_PL_FLAG_SYSTEM | flags;
352}
353
354static void
355set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
356{
357 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
358 u32 vram_pages = drm->client.device.info.ram_size >> PAGE_SHIFT;
359 unsigned i, fpfn, lpfn;
360
361 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
362 nvbo->mode && (type & TTM_PL_FLAG_VRAM) &&
363 nvbo->bo.mem.num_pages < vram_pages / 4) {
364 /*
365 * Make sure that the color and depth buffers are handled
366 * by independent memory controller units. Up to a 9x
367 * speed up when alpha-blending and depth-test are enabled
368 * at the same time.
369 */
370 if (nvbo->zeta) {
371 fpfn = vram_pages / 2;
372 lpfn = ~0;
373 } else {
374 fpfn = 0;
375 lpfn = vram_pages / 2;
376 }
377 for (i = 0; i < nvbo->placement.num_placement; ++i) {
378 nvbo->placements[i].fpfn = fpfn;
379 nvbo->placements[i].lpfn = lpfn;
380 }
381 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
382 nvbo->busy_placements[i].fpfn = fpfn;
383 nvbo->busy_placements[i].lpfn = lpfn;
384 }
385 }
386}
387
388void
389nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
390{
391 struct ttm_placement *pl = &nvbo->placement;
392 uint32_t flags = (nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED :
393 TTM_PL_MASK_CACHING) |
394 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
395
396 pl->placement = nvbo->placements;
397 set_placement_list(nvbo->placements, &pl->num_placement,
398 type, flags);
399
400 pl->busy_placement = nvbo->busy_placements;
401 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
402 type | busy, flags);
403
404 set_placement_range(nvbo, type);
405}
406
407int
408nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype, bool contig)
409{
410 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
411 struct ttm_buffer_object *bo = &nvbo->bo;
412 bool force = false, evict = false;
413 int ret;
414
415 ret = ttm_bo_reserve(bo, false, false, NULL);
416 if (ret)
417 return ret;
418
419 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
420 memtype == TTM_PL_FLAG_VRAM && contig) {
421 if (!nvbo->contig) {
422 nvbo->contig = true;
423 force = true;
424 evict = true;
425 }
426 }
427
428 if (nvbo->pin_refcnt) {
429 if (!(memtype & (1 << bo->mem.mem_type)) || evict) {
430 NV_ERROR(drm, "bo %p pinned elsewhere: "
431 "0x%08x vs 0x%08x\n", bo,
432 1 << bo->mem.mem_type, memtype);
433 ret = -EBUSY;
434 }
435 nvbo->pin_refcnt++;
436 goto out;
437 }
438
439 if (evict) {
440 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, 0);
441 ret = nouveau_bo_validate(nvbo, false, false);
442 if (ret)
443 goto out;
444 }
445
446 nvbo->pin_refcnt++;
447 nouveau_bo_placement_set(nvbo, memtype, 0);
448
449 /* drop pin_refcnt temporarily, so we don't trip the assertion
450 * in nouveau_bo_move() that makes sure we're not trying to
451 * move a pinned buffer
452 */
453 nvbo->pin_refcnt--;
454 ret = nouveau_bo_validate(nvbo, false, false);
455 if (ret)
456 goto out;
457 nvbo->pin_refcnt++;
458
459 switch (bo->mem.mem_type) {
460 case TTM_PL_VRAM:
461 drm->gem.vram_available -= bo->mem.size;
462 break;
463 case TTM_PL_TT:
464 drm->gem.gart_available -= bo->mem.size;
465 break;
466 default:
467 break;
468 }
469
470out:
471 if (force && ret)
472 nvbo->contig = false;
473 ttm_bo_unreserve(bo);
474 return ret;
475}
476
477int
478nouveau_bo_unpin(struct nouveau_bo *nvbo)
479{
480 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
481 struct ttm_buffer_object *bo = &nvbo->bo;
482 int ret, ref;
483
484 ret = ttm_bo_reserve(bo, false, false, NULL);
485 if (ret)
486 return ret;
487
488 ref = --nvbo->pin_refcnt;
489 WARN_ON_ONCE(ref < 0);
490 if (ref)
491 goto out;
492
493 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
494
495 ret = nouveau_bo_validate(nvbo, false, false);
496 if (ret == 0) {
497 switch (bo->mem.mem_type) {
498 case TTM_PL_VRAM:
499 drm->gem.vram_available += bo->mem.size;
500 break;
501 case TTM_PL_TT:
502 drm->gem.gart_available += bo->mem.size;
503 break;
504 default:
505 break;
506 }
507 }
508
509out:
510 ttm_bo_unreserve(bo);
511 return ret;
512}
513
514int
515nouveau_bo_map(struct nouveau_bo *nvbo)
516{
517 int ret;
518
519 ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL);
520 if (ret)
521 return ret;
522
523 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
524
525 ttm_bo_unreserve(&nvbo->bo);
526 return ret;
527}
528
529void
530nouveau_bo_unmap(struct nouveau_bo *nvbo)
531{
532 if (!nvbo)
533 return;
534
535 ttm_bo_kunmap(&nvbo->kmap);
536}
537
538void
539nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
540{
541 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
542 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
543 int i;
544
545 if (!ttm_dma)
546 return;
547
548 /* Don't waste time looping if the object is coherent */
549 if (nvbo->force_coherent)
550 return;
551
552 for (i = 0; i < ttm_dma->ttm.num_pages; i++)
553 dma_sync_single_for_device(drm->dev->dev,
554 ttm_dma->dma_address[i],
555 PAGE_SIZE, DMA_TO_DEVICE);
556}
557
558void
559nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
560{
561 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
562 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
563 int i;
564
565 if (!ttm_dma)
566 return;
567
568 /* Don't waste time looping if the object is coherent */
569 if (nvbo->force_coherent)
570 return;
571
572 for (i = 0; i < ttm_dma->ttm.num_pages; i++)
573 dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i],
574 PAGE_SIZE, DMA_FROM_DEVICE);
575}
576
577int
578nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
579 bool no_wait_gpu)
580{
581 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
582 int ret;
583
584 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx);
585 if (ret)
586 return ret;
587
588 nouveau_bo_sync_for_device(nvbo);
589
590 return 0;
591}
592
593void
594nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
595{
596 bool is_iomem;
597 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
598
599 mem += index;
600
601 if (is_iomem)
602 iowrite16_native(val, (void __force __iomem *)mem);
603 else
604 *mem = val;
605}
606
607u32
608nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
609{
610 bool is_iomem;
611 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
612
613 mem += index;
614
615 if (is_iomem)
616 return ioread32_native((void __force __iomem *)mem);
617 else
618 return *mem;
619}
620
621void
622nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
623{
624 bool is_iomem;
625 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
626
627 mem += index;
628
629 if (is_iomem)
630 iowrite32_native(val, (void __force __iomem *)mem);
631 else
632 *mem = val;
633}
634
635static struct ttm_tt *
636nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags)
637{
638#if IS_ENABLED(CONFIG_AGP)
639 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
640
641 if (drm->agp.bridge) {
642 return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags);
643 }
644#endif
645
646 return nouveau_sgdma_create_ttm(bo, page_flags);
647}
648
649static int
650nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
651{
652 /* We'll do this from user space. */
653 return 0;
654}
655
656static int
657nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
658 struct ttm_mem_type_manager *man)
659{
660 struct nouveau_drm *drm = nouveau_bdev(bdev);
661 struct nvif_mmu *mmu = &drm->client.mmu;
662
663 switch (type) {
664 case TTM_PL_SYSTEM:
665 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
666 man->available_caching = TTM_PL_MASK_CACHING;
667 man->default_caching = TTM_PL_FLAG_CACHED;
668 break;
669 case TTM_PL_VRAM:
670 man->flags = TTM_MEMTYPE_FLAG_FIXED |
671 TTM_MEMTYPE_FLAG_MAPPABLE;
672 man->available_caching = TTM_PL_FLAG_UNCACHED |
673 TTM_PL_FLAG_WC;
674 man->default_caching = TTM_PL_FLAG_WC;
675
676 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
677 /* Some BARs do not support being ioremapped WC */
678 const u8 type = mmu->type[drm->ttm.type_vram].type;
679 if (type & NVIF_MEM_UNCACHED) {
680 man->available_caching = TTM_PL_FLAG_UNCACHED;
681 man->default_caching = TTM_PL_FLAG_UNCACHED;
682 }
683
684 man->func = &nouveau_vram_manager;
685 man->io_reserve_fastpath = false;
686 man->use_io_reserve_lru = true;
687 } else {
688 man->func = &ttm_bo_manager_func;
689 }
690 break;
691 case TTM_PL_TT:
692 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA)
693 man->func = &nouveau_gart_manager;
694 else
695 if (!drm->agp.bridge)
696 man->func = &nv04_gart_manager;
697 else
698 man->func = &ttm_bo_manager_func;
699
700 if (drm->agp.bridge) {
701 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
702 man->available_caching = TTM_PL_FLAG_UNCACHED |
703 TTM_PL_FLAG_WC;
704 man->default_caching = TTM_PL_FLAG_WC;
705 } else {
706 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
707 TTM_MEMTYPE_FLAG_CMA;
708 man->available_caching = TTM_PL_MASK_CACHING;
709 man->default_caching = TTM_PL_FLAG_CACHED;
710 }
711
712 break;
713 default:
714 return -EINVAL;
715 }
716 return 0;
717}
718
719static void
720nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
721{
722 struct nouveau_bo *nvbo = nouveau_bo(bo);
723
724 switch (bo->mem.mem_type) {
725 case TTM_PL_VRAM:
726 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
727 TTM_PL_FLAG_SYSTEM);
728 break;
729 default:
730 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
731 break;
732 }
733
734 *pl = nvbo->placement;
735}
736
737
738static int
739nve0_bo_move_init(struct nouveau_channel *chan, u32 handle)
740{
741 int ret = RING_SPACE(chan, 2);
742 if (ret == 0) {
743 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
744 OUT_RING (chan, handle & 0x0000ffff);
745 FIRE_RING (chan);
746 }
747 return ret;
748}
749
750static int
751nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
752 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
753{
754 struct nouveau_mem *mem = nouveau_mem(old_reg);
755 int ret = RING_SPACE(chan, 10);
756 if (ret == 0) {
757 BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8);
758 OUT_RING (chan, upper_32_bits(mem->vma[0].addr));
759 OUT_RING (chan, lower_32_bits(mem->vma[0].addr));
760 OUT_RING (chan, upper_32_bits(mem->vma[1].addr));
761 OUT_RING (chan, lower_32_bits(mem->vma[1].addr));
762 OUT_RING (chan, PAGE_SIZE);
763 OUT_RING (chan, PAGE_SIZE);
764 OUT_RING (chan, PAGE_SIZE);
765 OUT_RING (chan, new_reg->num_pages);
766 BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386);
767 }
768 return ret;
769}
770
771static int
772nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle)
773{
774 int ret = RING_SPACE(chan, 2);
775 if (ret == 0) {
776 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
777 OUT_RING (chan, handle);
778 }
779 return ret;
780}
781
782static int
783nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
784 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
785{
786 struct nouveau_mem *mem = nouveau_mem(old_reg);
787 u64 src_offset = mem->vma[0].addr;
788 u64 dst_offset = mem->vma[1].addr;
789 u32 page_count = new_reg->num_pages;
790 int ret;
791
792 page_count = new_reg->num_pages;
793 while (page_count) {
794 int line_count = (page_count > 8191) ? 8191 : page_count;
795
796 ret = RING_SPACE(chan, 11);
797 if (ret)
798 return ret;
799
800 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8);
801 OUT_RING (chan, upper_32_bits(src_offset));
802 OUT_RING (chan, lower_32_bits(src_offset));
803 OUT_RING (chan, upper_32_bits(dst_offset));
804 OUT_RING (chan, lower_32_bits(dst_offset));
805 OUT_RING (chan, PAGE_SIZE);
806 OUT_RING (chan, PAGE_SIZE);
807 OUT_RING (chan, PAGE_SIZE);
808 OUT_RING (chan, line_count);
809 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
810 OUT_RING (chan, 0x00000110);
811
812 page_count -= line_count;
813 src_offset += (PAGE_SIZE * line_count);
814 dst_offset += (PAGE_SIZE * line_count);
815 }
816
817 return 0;
818}
819
820static int
821nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
822 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
823{
824 struct nouveau_mem *mem = nouveau_mem(old_reg);
825 u64 src_offset = mem->vma[0].addr;
826 u64 dst_offset = mem->vma[1].addr;
827 u32 page_count = new_reg->num_pages;
828 int ret;
829
830 page_count = new_reg->num_pages;
831 while (page_count) {
832 int line_count = (page_count > 2047) ? 2047 : page_count;
833
834 ret = RING_SPACE(chan, 12);
835 if (ret)
836 return ret;
837
838 BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2);
839 OUT_RING (chan, upper_32_bits(dst_offset));
840 OUT_RING (chan, lower_32_bits(dst_offset));
841 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6);
842 OUT_RING (chan, upper_32_bits(src_offset));
843 OUT_RING (chan, lower_32_bits(src_offset));
844 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
845 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
846 OUT_RING (chan, PAGE_SIZE); /* line_length */
847 OUT_RING (chan, line_count);
848 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
849 OUT_RING (chan, 0x00100110);
850
851 page_count -= line_count;
852 src_offset += (PAGE_SIZE * line_count);
853 dst_offset += (PAGE_SIZE * line_count);
854 }
855
856 return 0;
857}
858
859static int
860nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
861 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
862{
863 struct nouveau_mem *mem = nouveau_mem(old_reg);
864 u64 src_offset = mem->vma[0].addr;
865 u64 dst_offset = mem->vma[1].addr;
866 u32 page_count = new_reg->num_pages;
867 int ret;
868
869 page_count = new_reg->num_pages;
870 while (page_count) {
871 int line_count = (page_count > 8191) ? 8191 : page_count;
872
873 ret = RING_SPACE(chan, 11);
874 if (ret)
875 return ret;
876
877 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
878 OUT_RING (chan, upper_32_bits(src_offset));
879 OUT_RING (chan, lower_32_bits(src_offset));
880 OUT_RING (chan, upper_32_bits(dst_offset));
881 OUT_RING (chan, lower_32_bits(dst_offset));
882 OUT_RING (chan, PAGE_SIZE);
883 OUT_RING (chan, PAGE_SIZE);
884 OUT_RING (chan, PAGE_SIZE);
885 OUT_RING (chan, line_count);
886 BEGIN_NV04(chan, NvSubCopy, 0x0300, 1);
887 OUT_RING (chan, 0x00000110);
888
889 page_count -= line_count;
890 src_offset += (PAGE_SIZE * line_count);
891 dst_offset += (PAGE_SIZE * line_count);
892 }
893
894 return 0;
895}
896
897static int
898nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
899 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
900{
901 struct nouveau_mem *mem = nouveau_mem(old_reg);
902 int ret = RING_SPACE(chan, 7);
903 if (ret == 0) {
904 BEGIN_NV04(chan, NvSubCopy, 0x0320, 6);
905 OUT_RING (chan, upper_32_bits(mem->vma[0].addr));
906 OUT_RING (chan, lower_32_bits(mem->vma[0].addr));
907 OUT_RING (chan, upper_32_bits(mem->vma[1].addr));
908 OUT_RING (chan, lower_32_bits(mem->vma[1].addr));
909 OUT_RING (chan, 0x00000000 /* COPY */);
910 OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT);
911 }
912 return ret;
913}
914
915static int
916nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
917 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
918{
919 struct nouveau_mem *mem = nouveau_mem(old_reg);
920 int ret = RING_SPACE(chan, 7);
921 if (ret == 0) {
922 BEGIN_NV04(chan, NvSubCopy, 0x0304, 6);
923 OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT);
924 OUT_RING (chan, upper_32_bits(mem->vma[0].addr));
925 OUT_RING (chan, lower_32_bits(mem->vma[0].addr));
926 OUT_RING (chan, upper_32_bits(mem->vma[1].addr));
927 OUT_RING (chan, lower_32_bits(mem->vma[1].addr));
928 OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */);
929 }
930 return ret;
931}
932
933static int
934nv50_bo_move_init(struct nouveau_channel *chan, u32 handle)
935{
936 int ret = RING_SPACE(chan, 6);
937 if (ret == 0) {
938 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
939 OUT_RING (chan, handle);
940 BEGIN_NV04(chan, NvSubCopy, 0x0180, 3);
941 OUT_RING (chan, chan->drm->ntfy.handle);
942 OUT_RING (chan, chan->vram.handle);
943 OUT_RING (chan, chan->vram.handle);
944 }
945
946 return ret;
947}
948
949static int
950nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
951 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
952{
953 struct nouveau_mem *mem = nouveau_mem(old_reg);
954 u64 length = (new_reg->num_pages << PAGE_SHIFT);
955 u64 src_offset = mem->vma[0].addr;
956 u64 dst_offset = mem->vma[1].addr;
957 int src_tiled = !!mem->kind;
958 int dst_tiled = !!nouveau_mem(new_reg)->kind;
959 int ret;
960
961 while (length) {
962 u32 amount, stride, height;
963
964 ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled));
965 if (ret)
966 return ret;
967
968 amount = min(length, (u64)(4 * 1024 * 1024));
969 stride = 16 * 4;
970 height = amount / stride;
971
972 if (src_tiled) {
973 BEGIN_NV04(chan, NvSubCopy, 0x0200, 7);
974 OUT_RING (chan, 0);
975 OUT_RING (chan, 0);
976 OUT_RING (chan, stride);
977 OUT_RING (chan, height);
978 OUT_RING (chan, 1);
979 OUT_RING (chan, 0);
980 OUT_RING (chan, 0);
981 } else {
982 BEGIN_NV04(chan, NvSubCopy, 0x0200, 1);
983 OUT_RING (chan, 1);
984 }
985 if (dst_tiled) {
986 BEGIN_NV04(chan, NvSubCopy, 0x021c, 7);
987 OUT_RING (chan, 0);
988 OUT_RING (chan, 0);
989 OUT_RING (chan, stride);
990 OUT_RING (chan, height);
991 OUT_RING (chan, 1);
992 OUT_RING (chan, 0);
993 OUT_RING (chan, 0);
994 } else {
995 BEGIN_NV04(chan, NvSubCopy, 0x021c, 1);
996 OUT_RING (chan, 1);
997 }
998
999 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2);
1000 OUT_RING (chan, upper_32_bits(src_offset));
1001 OUT_RING (chan, upper_32_bits(dst_offset));
1002 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
1003 OUT_RING (chan, lower_32_bits(src_offset));
1004 OUT_RING (chan, lower_32_bits(dst_offset));
1005 OUT_RING (chan, stride);
1006 OUT_RING (chan, stride);
1007 OUT_RING (chan, stride);
1008 OUT_RING (chan, height);
1009 OUT_RING (chan, 0x00000101);
1010 OUT_RING (chan, 0x00000000);
1011 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
1012 OUT_RING (chan, 0);
1013
1014 length -= amount;
1015 src_offset += amount;
1016 dst_offset += amount;
1017 }
1018
1019 return 0;
1020}
1021
1022static int
1023nv04_bo_move_init(struct nouveau_channel *chan, u32 handle)
1024{
1025 int ret = RING_SPACE(chan, 4);
1026 if (ret == 0) {
1027 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
1028 OUT_RING (chan, handle);
1029 BEGIN_NV04(chan, NvSubCopy, 0x0180, 1);
1030 OUT_RING (chan, chan->drm->ntfy.handle);
1031 }
1032
1033 return ret;
1034}
1035
1036static inline uint32_t
1037nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
1038 struct nouveau_channel *chan, struct ttm_mem_reg *reg)
1039{
1040 if (reg->mem_type == TTM_PL_TT)
1041 return NvDmaTT;
1042 return chan->vram.handle;
1043}
1044
1045static int
1046nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
1047 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
1048{
1049 u32 src_offset = old_reg->start << PAGE_SHIFT;
1050 u32 dst_offset = new_reg->start << PAGE_SHIFT;
1051 u32 page_count = new_reg->num_pages;
1052 int ret;
1053
1054 ret = RING_SPACE(chan, 3);
1055 if (ret)
1056 return ret;
1057
1058 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
1059 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_reg));
1060 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_reg));
1061
1062 page_count = new_reg->num_pages;
1063 while (page_count) {
1064 int line_count = (page_count > 2047) ? 2047 : page_count;
1065
1066 ret = RING_SPACE(chan, 11);
1067 if (ret)
1068 return ret;
1069
1070 BEGIN_NV04(chan, NvSubCopy,
1071 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
1072 OUT_RING (chan, src_offset);
1073 OUT_RING (chan, dst_offset);
1074 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
1075 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
1076 OUT_RING (chan, PAGE_SIZE); /* line_length */
1077 OUT_RING (chan, line_count);
1078 OUT_RING (chan, 0x00000101);
1079 OUT_RING (chan, 0x00000000);
1080 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
1081 OUT_RING (chan, 0);
1082
1083 page_count -= line_count;
1084 src_offset += (PAGE_SIZE * line_count);
1085 dst_offset += (PAGE_SIZE * line_count);
1086 }
1087
1088 return 0;
1089}
1090
1091static int
1092nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
1093 struct ttm_mem_reg *reg)
1094{
1095 struct nouveau_mem *old_mem = nouveau_mem(&bo->mem);
1096 struct nouveau_mem *new_mem = nouveau_mem(reg);
1097 struct nvif_vmm *vmm = &drm->client.vmm.vmm;
1098 int ret;
1099
1100 ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0,
1101 old_mem->mem.size, &old_mem->vma[0]);
1102 if (ret)
1103 return ret;
1104
1105 ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0,
1106 new_mem->mem.size, &old_mem->vma[1]);
1107 if (ret)
1108 goto done;
1109
1110 ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]);
1111 if (ret)
1112 goto done;
1113
1114 ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]);
1115done:
1116 if (ret) {
1117 nvif_vmm_put(vmm, &old_mem->vma[1]);
1118 nvif_vmm_put(vmm, &old_mem->vma[0]);
1119 }
1120 return 0;
1121}
1122
1123static int
1124nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
1125 bool no_wait_gpu, struct ttm_mem_reg *new_reg)
1126{
1127 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1128 struct nouveau_channel *chan = drm->ttm.chan;
1129 struct nouveau_cli *cli = (void *)chan->user.client;
1130 struct nouveau_fence *fence;
1131 int ret;
1132
1133 /* create temporary vmas for the transfer and attach them to the
1134 * old nvkm_mem node, these will get cleaned up after ttm has
1135 * destroyed the ttm_mem_reg
1136 */
1137 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
1138 ret = nouveau_bo_move_prep(drm, bo, new_reg);
1139 if (ret)
1140 return ret;
1141 }
1142
1143 mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING);
1144 ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, intr);
1145 if (ret == 0) {
1146 ret = drm->ttm.move(chan, bo, &bo->mem, new_reg);
1147 if (ret == 0) {
1148 ret = nouveau_fence_new(chan, false, &fence);
1149 if (ret == 0) {
1150 ret = ttm_bo_move_accel_cleanup(bo,
1151 &fence->base,
1152 evict,
1153 new_reg);
1154 nouveau_fence_unref(&fence);
1155 }
1156 }
1157 }
1158 mutex_unlock(&cli->mutex);
1159 return ret;
1160}
1161
1162void
1163nouveau_bo_move_init(struct nouveau_drm *drm)
1164{
1165 static const struct {
1166 const char *name;
1167 int engine;
1168 s32 oclass;
1169 int (*exec)(struct nouveau_channel *,
1170 struct ttm_buffer_object *,
1171 struct ttm_mem_reg *, struct ttm_mem_reg *);
1172 int (*init)(struct nouveau_channel *, u32 handle);
1173 } _methods[] = {
1174 { "COPY", 4, 0xc5b5, nve0_bo_move_copy, nve0_bo_move_init },
1175 { "GRCE", 0, 0xc5b5, nve0_bo_move_copy, nvc0_bo_move_init },
1176 { "COPY", 4, 0xc3b5, nve0_bo_move_copy, nve0_bo_move_init },
1177 { "GRCE", 0, 0xc3b5, nve0_bo_move_copy, nvc0_bo_move_init },
1178 { "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init },
1179 { "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init },
1180 { "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init },
1181 { "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init },
1182 { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init },
1183 { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init },
1184 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
1185 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
1186 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
1187 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
1188 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
1189 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
1190 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
1191 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
1192 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
1193 {},
1194 { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init },
1195 }, *mthd = _methods;
1196 const char *name = "CPU";
1197 int ret;
1198
1199 do {
1200 struct nouveau_channel *chan;
1201
1202 if (mthd->engine)
1203 chan = drm->cechan;
1204 else
1205 chan = drm->channel;
1206 if (chan == NULL)
1207 continue;
1208
1209 ret = nvif_object_init(&chan->user,
1210 mthd->oclass | (mthd->engine << 16),
1211 mthd->oclass, NULL, 0,
1212 &drm->ttm.copy);
1213 if (ret == 0) {
1214 ret = mthd->init(chan, drm->ttm.copy.handle);
1215 if (ret) {
1216 nvif_object_fini(&drm->ttm.copy);
1217 continue;
1218 }
1219
1220 drm->ttm.move = mthd->exec;
1221 drm->ttm.chan = chan;
1222 name = mthd->name;
1223 break;
1224 }
1225 } while ((++mthd)->exec);
1226
1227 NV_INFO(drm, "MM: using %s for buffer copies\n", name);
1228}
1229
1230static int
1231nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
1232 bool no_wait_gpu, struct ttm_mem_reg *new_reg)
1233{
1234 struct ttm_operation_ctx ctx = { intr, no_wait_gpu };
1235 struct ttm_place placement_memtype = {
1236 .fpfn = 0,
1237 .lpfn = 0,
1238 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING
1239 };
1240 struct ttm_placement placement;
1241 struct ttm_mem_reg tmp_reg;
1242 int ret;
1243
1244 placement.num_placement = placement.num_busy_placement = 1;
1245 placement.placement = placement.busy_placement = &placement_memtype;
1246
1247 tmp_reg = *new_reg;
1248 tmp_reg.mm_node = NULL;
1249 ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx);
1250 if (ret)
1251 return ret;
1252
1253 ret = ttm_tt_bind(bo->ttm, &tmp_reg, &ctx);
1254 if (ret)
1255 goto out;
1256
1257 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_reg);
1258 if (ret)
1259 goto out;
1260
1261 ret = ttm_bo_move_ttm(bo, &ctx, new_reg);
1262out:
1263 ttm_bo_mem_put(bo, &tmp_reg);
1264 return ret;
1265}
1266
1267static int
1268nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
1269 bool no_wait_gpu, struct ttm_mem_reg *new_reg)
1270{
1271 struct ttm_operation_ctx ctx = { intr, no_wait_gpu };
1272 struct ttm_place placement_memtype = {
1273 .fpfn = 0,
1274 .lpfn = 0,
1275 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING
1276 };
1277 struct ttm_placement placement;
1278 struct ttm_mem_reg tmp_reg;
1279 int ret;
1280
1281 placement.num_placement = placement.num_busy_placement = 1;
1282 placement.placement = placement.busy_placement = &placement_memtype;
1283
1284 tmp_reg = *new_reg;
1285 tmp_reg.mm_node = NULL;
1286 ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx);
1287 if (ret)
1288 return ret;
1289
1290 ret = ttm_bo_move_ttm(bo, &ctx, &tmp_reg);
1291 if (ret)
1292 goto out;
1293
1294 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_reg);
1295 if (ret)
1296 goto out;
1297
1298out:
1299 ttm_bo_mem_put(bo, &tmp_reg);
1300 return ret;
1301}
1302
1303static void
1304nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, bool evict,
1305 struct ttm_mem_reg *new_reg)
1306{
1307 struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL;
1308 struct nouveau_bo *nvbo = nouveau_bo(bo);
1309 struct nouveau_vma *vma;
1310
1311 /* ttm can now (stupidly) pass the driver bos it didn't create... */
1312 if (bo->destroy != nouveau_bo_del_ttm)
1313 return;
1314
1315 if (mem && new_reg->mem_type != TTM_PL_SYSTEM &&
1316 mem->mem.page == nvbo->page) {
1317 list_for_each_entry(vma, &nvbo->vma_list, head) {
1318 nouveau_vma_map(vma, mem);
1319 }
1320 } else {
1321 list_for_each_entry(vma, &nvbo->vma_list, head) {
1322 WARN_ON(ttm_bo_wait(bo, false, false));
1323 nouveau_vma_unmap(vma);
1324 }
1325 }
1326}
1327
1328static int
1329nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_reg,
1330 struct nouveau_drm_tile **new_tile)
1331{
1332 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1333 struct drm_device *dev = drm->dev;
1334 struct nouveau_bo *nvbo = nouveau_bo(bo);
1335 u64 offset = new_reg->start << PAGE_SHIFT;
1336
1337 *new_tile = NULL;
1338 if (new_reg->mem_type != TTM_PL_VRAM)
1339 return 0;
1340
1341 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
1342 *new_tile = nv10_bo_set_tiling(dev, offset, new_reg->size,
1343 nvbo->mode, nvbo->zeta);
1344 }
1345
1346 return 0;
1347}
1348
1349static void
1350nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1351 struct nouveau_drm_tile *new_tile,
1352 struct nouveau_drm_tile **old_tile)
1353{
1354 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1355 struct drm_device *dev = drm->dev;
1356 struct dma_fence *fence = dma_resv_get_excl(bo->base.resv);
1357
1358 nv10_bo_put_tile_region(dev, *old_tile, fence);
1359 *old_tile = new_tile;
1360}
1361
1362static int
1363nouveau_bo_move(struct ttm_buffer_object *bo, bool evict,
1364 struct ttm_operation_ctx *ctx,
1365 struct ttm_mem_reg *new_reg)
1366{
1367 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1368 struct nouveau_bo *nvbo = nouveau_bo(bo);
1369 struct ttm_mem_reg *old_reg = &bo->mem;
1370 struct nouveau_drm_tile *new_tile = NULL;
1371 int ret = 0;
1372
1373 ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
1374 if (ret)
1375 return ret;
1376
1377 if (nvbo->pin_refcnt)
1378 NV_WARN(drm, "Moving pinned object %p!\n", nvbo);
1379
1380 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1381 ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile);
1382 if (ret)
1383 return ret;
1384 }
1385
1386 /* Fake bo copy. */
1387 if (old_reg->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
1388 BUG_ON(bo->mem.mm_node != NULL);
1389 bo->mem = *new_reg;
1390 new_reg->mm_node = NULL;
1391 goto out;
1392 }
1393
1394 /* Hardware assisted copy. */
1395 if (drm->ttm.move) {
1396 if (new_reg->mem_type == TTM_PL_SYSTEM)
1397 ret = nouveau_bo_move_flipd(bo, evict,
1398 ctx->interruptible,
1399 ctx->no_wait_gpu, new_reg);
1400 else if (old_reg->mem_type == TTM_PL_SYSTEM)
1401 ret = nouveau_bo_move_flips(bo, evict,
1402 ctx->interruptible,
1403 ctx->no_wait_gpu, new_reg);
1404 else
1405 ret = nouveau_bo_move_m2mf(bo, evict,
1406 ctx->interruptible,
1407 ctx->no_wait_gpu, new_reg);
1408 if (!ret)
1409 goto out;
1410 }
1411
1412 /* Fallback to software copy. */
1413 ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
1414 if (ret == 0)
1415 ret = ttm_bo_move_memcpy(bo, ctx, new_reg);
1416
1417out:
1418 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1419 if (ret)
1420 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1421 else
1422 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1423 }
1424
1425 return ret;
1426}
1427
1428static int
1429nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
1430{
1431 struct nouveau_bo *nvbo = nouveau_bo(bo);
1432
1433 return drm_vma_node_verify_access(&nvbo->bo.base.vma_node,
1434 filp->private_data);
1435}
1436
1437static int
1438nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg)
1439{
1440 struct ttm_mem_type_manager *man = &bdev->man[reg->mem_type];
1441 struct nouveau_drm *drm = nouveau_bdev(bdev);
1442 struct nvkm_device *device = nvxx_device(&drm->client.device);
1443 struct nouveau_mem *mem = nouveau_mem(reg);
1444
1445 reg->bus.addr = NULL;
1446 reg->bus.offset = 0;
1447 reg->bus.size = reg->num_pages << PAGE_SHIFT;
1448 reg->bus.base = 0;
1449 reg->bus.is_iomem = false;
1450 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
1451 return -EINVAL;
1452 switch (reg->mem_type) {
1453 case TTM_PL_SYSTEM:
1454 /* System memory */
1455 return 0;
1456 case TTM_PL_TT:
1457#if IS_ENABLED(CONFIG_AGP)
1458 if (drm->agp.bridge) {
1459 reg->bus.offset = reg->start << PAGE_SHIFT;
1460 reg->bus.base = drm->agp.base;
1461 reg->bus.is_iomem = !drm->agp.cma;
1462 }
1463#endif
1464 if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 || !mem->kind)
1465 /* untiled */
1466 break;
1467 /* fall through - tiled memory */
1468 case TTM_PL_VRAM:
1469 reg->bus.offset = reg->start << PAGE_SHIFT;
1470 reg->bus.base = device->func->resource_addr(device, 1);
1471 reg->bus.is_iomem = true;
1472 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1473 union {
1474 struct nv50_mem_map_v0 nv50;
1475 struct gf100_mem_map_v0 gf100;
1476 } args;
1477 u64 handle, length;
1478 u32 argc = 0;
1479 int ret;
1480
1481 switch (mem->mem.object.oclass) {
1482 case NVIF_CLASS_MEM_NV50:
1483 args.nv50.version = 0;
1484 args.nv50.ro = 0;
1485 args.nv50.kind = mem->kind;
1486 args.nv50.comp = mem->comp;
1487 argc = sizeof(args.nv50);
1488 break;
1489 case NVIF_CLASS_MEM_GF100:
1490 args.gf100.version = 0;
1491 args.gf100.ro = 0;
1492 args.gf100.kind = mem->kind;
1493 argc = sizeof(args.gf100);
1494 break;
1495 default:
1496 WARN_ON(1);
1497 break;
1498 }
1499
1500 ret = nvif_object_map_handle(&mem->mem.object,
1501 &args, argc,
1502 &handle, &length);
1503 if (ret != 1)
1504 return ret ? ret : -EINVAL;
1505
1506 reg->bus.base = 0;
1507 reg->bus.offset = handle;
1508 }
1509 break;
1510 default:
1511 return -EINVAL;
1512 }
1513 return 0;
1514}
1515
1516static void
1517nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg)
1518{
1519 struct nouveau_drm *drm = nouveau_bdev(bdev);
1520 struct nouveau_mem *mem = nouveau_mem(reg);
1521
1522 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1523 switch (reg->mem_type) {
1524 case TTM_PL_TT:
1525 if (mem->kind)
1526 nvif_object_unmap_handle(&mem->mem.object);
1527 break;
1528 case TTM_PL_VRAM:
1529 nvif_object_unmap_handle(&mem->mem.object);
1530 break;
1531 default:
1532 break;
1533 }
1534 }
1535}
1536
1537static int
1538nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1539{
1540 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1541 struct nouveau_bo *nvbo = nouveau_bo(bo);
1542 struct nvkm_device *device = nvxx_device(&drm->client.device);
1543 u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT;
1544 int i, ret;
1545
1546 /* as long as the bo isn't in vram, and isn't tiled, we've got
1547 * nothing to do here.
1548 */
1549 if (bo->mem.mem_type != TTM_PL_VRAM) {
1550 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA ||
1551 !nvbo->kind)
1552 return 0;
1553
1554 if (bo->mem.mem_type == TTM_PL_SYSTEM) {
1555 nouveau_bo_placement_set(nvbo, TTM_PL_TT, 0);
1556
1557 ret = nouveau_bo_validate(nvbo, false, false);
1558 if (ret)
1559 return ret;
1560 }
1561 return 0;
1562 }
1563
1564 /* make sure bo is in mappable vram */
1565 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
1566 bo->mem.start + bo->mem.num_pages < mappable)
1567 return 0;
1568
1569 for (i = 0; i < nvbo->placement.num_placement; ++i) {
1570 nvbo->placements[i].fpfn = 0;
1571 nvbo->placements[i].lpfn = mappable;
1572 }
1573
1574 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
1575 nvbo->busy_placements[i].fpfn = 0;
1576 nvbo->busy_placements[i].lpfn = mappable;
1577 }
1578
1579 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0);
1580 return nouveau_bo_validate(nvbo, false, false);
1581}
1582
1583static int
1584nouveau_ttm_tt_populate(struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
1585{
1586 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1587 struct nouveau_drm *drm;
1588 struct device *dev;
1589 unsigned i;
1590 int r;
1591 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1592
1593 if (ttm->state != tt_unpopulated)
1594 return 0;
1595
1596 if (slave && ttm->sg) {
1597 /* make userspace faulting work */
1598 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1599 ttm_dma->dma_address, ttm->num_pages);
1600 ttm->state = tt_unbound;
1601 return 0;
1602 }
1603
1604 drm = nouveau_bdev(ttm->bdev);
1605 dev = drm->dev->dev;
1606
1607#if IS_ENABLED(CONFIG_AGP)
1608 if (drm->agp.bridge) {
1609 return ttm_agp_tt_populate(ttm, ctx);
1610 }
1611#endif
1612
1613#if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
1614 if (swiotlb_nr_tbl()) {
1615 return ttm_dma_populate((void *)ttm, dev, ctx);
1616 }
1617#endif
1618
1619 r = ttm_pool_populate(ttm, ctx);
1620 if (r) {
1621 return r;
1622 }
1623
1624 for (i = 0; i < ttm->num_pages; i++) {
1625 dma_addr_t addr;
1626
1627 addr = dma_map_page(dev, ttm->pages[i], 0, PAGE_SIZE,
1628 DMA_BIDIRECTIONAL);
1629
1630 if (dma_mapping_error(dev, addr)) {
1631 while (i--) {
1632 dma_unmap_page(dev, ttm_dma->dma_address[i],
1633 PAGE_SIZE, DMA_BIDIRECTIONAL);
1634 ttm_dma->dma_address[i] = 0;
1635 }
1636 ttm_pool_unpopulate(ttm);
1637 return -EFAULT;
1638 }
1639
1640 ttm_dma->dma_address[i] = addr;
1641 }
1642 return 0;
1643}
1644
1645static void
1646nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
1647{
1648 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1649 struct nouveau_drm *drm;
1650 struct device *dev;
1651 unsigned i;
1652 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1653
1654 if (slave)
1655 return;
1656
1657 drm = nouveau_bdev(ttm->bdev);
1658 dev = drm->dev->dev;
1659
1660#if IS_ENABLED(CONFIG_AGP)
1661 if (drm->agp.bridge) {
1662 ttm_agp_tt_unpopulate(ttm);
1663 return;
1664 }
1665#endif
1666
1667#if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
1668 if (swiotlb_nr_tbl()) {
1669 ttm_dma_unpopulate((void *)ttm, dev);
1670 return;
1671 }
1672#endif
1673
1674 for (i = 0; i < ttm->num_pages; i++) {
1675 if (ttm_dma->dma_address[i]) {
1676 dma_unmap_page(dev, ttm_dma->dma_address[i], PAGE_SIZE,
1677 DMA_BIDIRECTIONAL);
1678 }
1679 }
1680
1681 ttm_pool_unpopulate(ttm);
1682}
1683
1684void
1685nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
1686{
1687 struct dma_resv *resv = nvbo->bo.base.resv;
1688
1689 if (exclusive)
1690 dma_resv_add_excl_fence(resv, &fence->base);
1691 else if (fence)
1692 dma_resv_add_shared_fence(resv, &fence->base);
1693}
1694
1695struct ttm_bo_driver nouveau_bo_driver = {
1696 .ttm_tt_create = &nouveau_ttm_tt_create,
1697 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1698 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1699 .invalidate_caches = nouveau_bo_invalidate_caches,
1700 .init_mem_type = nouveau_bo_init_mem_type,
1701 .eviction_valuable = ttm_bo_eviction_valuable,
1702 .evict_flags = nouveau_bo_evict_flags,
1703 .move_notify = nouveau_bo_move_ntfy,
1704 .move = nouveau_bo_move,
1705 .verify_access = nouveau_bo_verify_access,
1706 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1707 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1708 .io_mem_free = &nouveau_ttm_io_mem_free,
1709};
1/*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24/*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30#include <linux/dma-mapping.h>
31#include <drm/ttm/ttm_tt.h>
32
33#include "nouveau_drv.h"
34#include "nouveau_chan.h"
35#include "nouveau_fence.h"
36
37#include "nouveau_bo.h"
38#include "nouveau_ttm.h"
39#include "nouveau_gem.h"
40#include "nouveau_mem.h"
41#include "nouveau_vmm.h"
42
43#include <nvif/class.h>
44#include <nvif/if500b.h>
45#include <nvif/if900b.h>
46
47static int nouveau_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm,
48 struct ttm_resource *reg);
49static void nouveau_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm);
50
51/*
52 * NV10-NV40 tiling helpers
53 */
54
55static void
56nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
57 u32 addr, u32 size, u32 pitch, u32 flags)
58{
59 struct nouveau_drm *drm = nouveau_drm(dev);
60 int i = reg - drm->tile.reg;
61 struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
62 struct nvkm_fb_tile *tile = &fb->tile.region[i];
63
64 nouveau_fence_unref(®->fence);
65
66 if (tile->pitch)
67 nvkm_fb_tile_fini(fb, i, tile);
68
69 if (pitch)
70 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
71
72 nvkm_fb_tile_prog(fb, i, tile);
73}
74
75static struct nouveau_drm_tile *
76nv10_bo_get_tile_region(struct drm_device *dev, int i)
77{
78 struct nouveau_drm *drm = nouveau_drm(dev);
79 struct nouveau_drm_tile *tile = &drm->tile.reg[i];
80
81 spin_lock(&drm->tile.lock);
82
83 if (!tile->used &&
84 (!tile->fence || nouveau_fence_done(tile->fence)))
85 tile->used = true;
86 else
87 tile = NULL;
88
89 spin_unlock(&drm->tile.lock);
90 return tile;
91}
92
93static void
94nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
95 struct dma_fence *fence)
96{
97 struct nouveau_drm *drm = nouveau_drm(dev);
98
99 if (tile) {
100 spin_lock(&drm->tile.lock);
101 tile->fence = (struct nouveau_fence *)dma_fence_get(fence);
102 tile->used = false;
103 spin_unlock(&drm->tile.lock);
104 }
105}
106
107static struct nouveau_drm_tile *
108nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
109 u32 size, u32 pitch, u32 zeta)
110{
111 struct nouveau_drm *drm = nouveau_drm(dev);
112 struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
113 struct nouveau_drm_tile *tile, *found = NULL;
114 int i;
115
116 for (i = 0; i < fb->tile.regions; i++) {
117 tile = nv10_bo_get_tile_region(dev, i);
118
119 if (pitch && !found) {
120 found = tile;
121 continue;
122
123 } else if (tile && fb->tile.region[i].pitch) {
124 /* Kill an unused tile region. */
125 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
126 }
127
128 nv10_bo_put_tile_region(dev, tile, NULL);
129 }
130
131 if (found)
132 nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta);
133 return found;
134}
135
136static void
137nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
138{
139 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
140 struct drm_device *dev = drm->dev;
141 struct nouveau_bo *nvbo = nouveau_bo(bo);
142
143 WARN_ON(nvbo->bo.pin_count > 0);
144 nouveau_bo_del_io_reserve_lru(bo);
145 nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
146
147 /*
148 * If nouveau_bo_new() allocated this buffer, the GEM object was never
149 * initialized, so don't attempt to release it.
150 */
151 if (bo->base.dev) {
152 /* Gem objects not being shared with other VMs get their
153 * dma_resv from a root GEM object.
154 */
155 if (nvbo->no_share)
156 drm_gem_object_put(nvbo->r_obj);
157
158 drm_gem_object_release(&bo->base);
159 } else {
160 dma_resv_fini(&bo->base._resv);
161 }
162
163 kfree(nvbo);
164}
165
166static inline u64
167roundup_64(u64 x, u32 y)
168{
169 x += y - 1;
170 do_div(x, y);
171 return x * y;
172}
173
174static void
175nouveau_bo_fixup_align(struct nouveau_bo *nvbo, int *align, u64 *size)
176{
177 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
178 struct nvif_device *device = &drm->client.device;
179
180 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
181 if (nvbo->mode) {
182 if (device->info.chipset >= 0x40) {
183 *align = 65536;
184 *size = roundup_64(*size, 64 * nvbo->mode);
185
186 } else if (device->info.chipset >= 0x30) {
187 *align = 32768;
188 *size = roundup_64(*size, 64 * nvbo->mode);
189
190 } else if (device->info.chipset >= 0x20) {
191 *align = 16384;
192 *size = roundup_64(*size, 64 * nvbo->mode);
193
194 } else if (device->info.chipset >= 0x10) {
195 *align = 16384;
196 *size = roundup_64(*size, 32 * nvbo->mode);
197 }
198 }
199 } else {
200 *size = roundup_64(*size, (1 << nvbo->page));
201 *align = max((1 << nvbo->page), *align);
202 }
203
204 *size = roundup_64(*size, PAGE_SIZE);
205}
206
207struct nouveau_bo *
208nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 domain,
209 u32 tile_mode, u32 tile_flags, bool internal)
210{
211 struct nouveau_drm *drm = cli->drm;
212 struct nouveau_bo *nvbo;
213 struct nvif_mmu *mmu = &cli->mmu;
214 struct nvif_vmm *vmm = &nouveau_cli_vmm(cli)->vmm;
215 int i, pi = -1;
216
217 if (!*size) {
218 NV_WARN(drm, "skipped size %016llx\n", *size);
219 return ERR_PTR(-EINVAL);
220 }
221
222 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
223 if (!nvbo)
224 return ERR_PTR(-ENOMEM);
225
226 INIT_LIST_HEAD(&nvbo->head);
227 INIT_LIST_HEAD(&nvbo->entry);
228 INIT_LIST_HEAD(&nvbo->vma_list);
229 nvbo->bo.bdev = &drm->ttm.bdev;
230
231 /* This is confusing, and doesn't actually mean we want an uncached
232 * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated
233 * into in nouveau_gem_new().
234 */
235 if (domain & NOUVEAU_GEM_DOMAIN_COHERENT) {
236 /* Determine if we can get a cache-coherent map, forcing
237 * uncached mapping if we can't.
238 */
239 if (!nouveau_drm_use_coherent_gpu_mapping(drm))
240 nvbo->force_coherent = true;
241 }
242
243 nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG);
244
245 if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) {
246 nvbo->kind = (tile_flags & 0x0000ff00) >> 8;
247 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
248 kfree(nvbo);
249 return ERR_PTR(-EINVAL);
250 }
251
252 nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind;
253 } else if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
254 nvbo->kind = (tile_flags & 0x00007f00) >> 8;
255 nvbo->comp = (tile_flags & 0x00030000) >> 16;
256 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
257 kfree(nvbo);
258 return ERR_PTR(-EINVAL);
259 }
260 } else {
261 nvbo->zeta = (tile_flags & 0x00000007);
262 }
263 nvbo->mode = tile_mode;
264
265 if (!nouveau_cli_uvmm(cli) || internal) {
266 /* Determine the desirable target GPU page size for the buffer. */
267 for (i = 0; i < vmm->page_nr; i++) {
268 /* Because we cannot currently allow VMM maps to fail
269 * during buffer migration, we need to determine page
270 * size for the buffer up-front, and pre-allocate its
271 * page tables.
272 *
273 * Skip page sizes that can't support needed domains.
274 */
275 if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE &&
276 (domain & NOUVEAU_GEM_DOMAIN_VRAM) && !vmm->page[i].vram)
277 continue;
278 if ((domain & NOUVEAU_GEM_DOMAIN_GART) &&
279 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))
280 continue;
281
282 /* Select this page size if it's the first that supports
283 * the potential memory domains, or when it's compatible
284 * with the requested compression settings.
285 */
286 if (pi < 0 || !nvbo->comp || vmm->page[i].comp)
287 pi = i;
288
289 /* Stop once the buffer is larger than the current page size. */
290 if (*size >= 1ULL << vmm->page[i].shift)
291 break;
292 }
293
294 if (WARN_ON(pi < 0)) {
295 kfree(nvbo);
296 return ERR_PTR(-EINVAL);
297 }
298
299 /* Disable compression if suitable settings couldn't be found. */
300 if (nvbo->comp && !vmm->page[pi].comp) {
301 if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100)
302 nvbo->kind = mmu->kind[nvbo->kind];
303 nvbo->comp = 0;
304 }
305 nvbo->page = vmm->page[pi].shift;
306 } else {
307 /* Determine the desirable target GPU page size for the buffer. */
308 for (i = 0; i < vmm->page_nr; i++) {
309 /* Because we cannot currently allow VMM maps to fail
310 * during buffer migration, we need to determine page
311 * size for the buffer up-front, and pre-allocate its
312 * page tables.
313 *
314 * Skip page sizes that can't support needed domains.
315 */
316 if ((domain & NOUVEAU_GEM_DOMAIN_VRAM) && !vmm->page[i].vram)
317 continue;
318 if ((domain & NOUVEAU_GEM_DOMAIN_GART) &&
319 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))
320 continue;
321
322 /* pick the last one as it will be smallest. */
323 pi = i;
324
325 /* Stop once the buffer is larger than the current page size. */
326 if (*size >= 1ULL << vmm->page[i].shift)
327 break;
328 }
329 if (WARN_ON(pi < 0)) {
330 kfree(nvbo);
331 return ERR_PTR(-EINVAL);
332 }
333 nvbo->page = vmm->page[pi].shift;
334 }
335
336 nouveau_bo_fixup_align(nvbo, align, size);
337
338 return nvbo;
339}
340
341int
342nouveau_bo_init(struct nouveau_bo *nvbo, u64 size, int align, u32 domain,
343 struct sg_table *sg, struct dma_resv *robj)
344{
345 int type = sg ? ttm_bo_type_sg : ttm_bo_type_device;
346 int ret;
347 struct ttm_operation_ctx ctx = {
348 .interruptible = false,
349 .no_wait_gpu = false,
350 .resv = robj,
351 };
352
353 nouveau_bo_placement_set(nvbo, domain, 0);
354 INIT_LIST_HEAD(&nvbo->io_reserve_lru);
355
356 ret = ttm_bo_init_reserved(nvbo->bo.bdev, &nvbo->bo, type,
357 &nvbo->placement, align >> PAGE_SHIFT, &ctx,
358 sg, robj, nouveau_bo_del_ttm);
359 if (ret) {
360 /* ttm will call nouveau_bo_del_ttm if it fails.. */
361 return ret;
362 }
363
364 if (!robj)
365 ttm_bo_unreserve(&nvbo->bo);
366
367 return 0;
368}
369
370int
371nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align,
372 uint32_t domain, uint32_t tile_mode, uint32_t tile_flags,
373 struct sg_table *sg, struct dma_resv *robj,
374 struct nouveau_bo **pnvbo)
375{
376 struct nouveau_bo *nvbo;
377 int ret;
378
379 nvbo = nouveau_bo_alloc(cli, &size, &align, domain, tile_mode,
380 tile_flags, true);
381 if (IS_ERR(nvbo))
382 return PTR_ERR(nvbo);
383
384 nvbo->bo.base.size = size;
385 dma_resv_init(&nvbo->bo.base._resv);
386 drm_vma_node_reset(&nvbo->bo.base.vma_node);
387
388 /* This must be called before ttm_bo_init_reserved(). Subsequent
389 * bo_move() callbacks might already iterate the GEMs GPUVA list.
390 */
391 drm_gem_gpuva_init(&nvbo->bo.base);
392
393 ret = nouveau_bo_init(nvbo, size, align, domain, sg, robj);
394 if (ret)
395 return ret;
396
397 *pnvbo = nvbo;
398 return 0;
399}
400
401static void
402set_placement_range(struct nouveau_bo *nvbo, uint32_t domain)
403{
404 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
405 u64 vram_size = drm->client.device.info.ram_size;
406 unsigned i, fpfn, lpfn;
407
408 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
409 nvbo->mode && (domain & NOUVEAU_GEM_DOMAIN_VRAM) &&
410 nvbo->bo.base.size < vram_size / 4) {
411 /*
412 * Make sure that the color and depth buffers are handled
413 * by independent memory controller units. Up to a 9x
414 * speed up when alpha-blending and depth-test are enabled
415 * at the same time.
416 */
417 if (nvbo->zeta) {
418 fpfn = (vram_size / 2) >> PAGE_SHIFT;
419 lpfn = ~0;
420 } else {
421 fpfn = 0;
422 lpfn = (vram_size / 2) >> PAGE_SHIFT;
423 }
424 for (i = 0; i < nvbo->placement.num_placement; ++i) {
425 nvbo->placements[i].fpfn = fpfn;
426 nvbo->placements[i].lpfn = lpfn;
427 }
428 }
429}
430
431void
432nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t domain,
433 uint32_t busy)
434{
435 unsigned int *n = &nvbo->placement.num_placement;
436 struct ttm_place *pl = nvbo->placements;
437
438 domain |= busy;
439
440 *n = 0;
441 if (domain & NOUVEAU_GEM_DOMAIN_VRAM) {
442 pl[*n].mem_type = TTM_PL_VRAM;
443 pl[*n].flags = busy & NOUVEAU_GEM_DOMAIN_VRAM ?
444 TTM_PL_FLAG_FALLBACK : 0;
445 (*n)++;
446 }
447 if (domain & NOUVEAU_GEM_DOMAIN_GART) {
448 pl[*n].mem_type = TTM_PL_TT;
449 pl[*n].flags = busy & NOUVEAU_GEM_DOMAIN_GART ?
450 TTM_PL_FLAG_FALLBACK : 0;
451 (*n)++;
452 }
453 if (domain & NOUVEAU_GEM_DOMAIN_CPU) {
454 pl[*n].mem_type = TTM_PL_SYSTEM;
455 pl[*n].flags = busy & NOUVEAU_GEM_DOMAIN_CPU ?
456 TTM_PL_FLAG_FALLBACK : 0;
457 (*n)++;
458 }
459
460 nvbo->placement.placement = nvbo->placements;
461 set_placement_range(nvbo, domain);
462}
463
464int
465nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t domain, bool contig)
466{
467 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
468 struct ttm_buffer_object *bo = &nvbo->bo;
469 bool force = false, evict = false;
470 int ret;
471
472 ret = ttm_bo_reserve(bo, false, false, NULL);
473 if (ret)
474 return ret;
475
476 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
477 domain == NOUVEAU_GEM_DOMAIN_VRAM && contig) {
478 if (!nvbo->contig) {
479 nvbo->contig = true;
480 force = true;
481 evict = true;
482 }
483 }
484
485 if (nvbo->bo.pin_count) {
486 bool error = evict;
487
488 switch (bo->resource->mem_type) {
489 case TTM_PL_VRAM:
490 error |= !(domain & NOUVEAU_GEM_DOMAIN_VRAM);
491 break;
492 case TTM_PL_TT:
493 error |= !(domain & NOUVEAU_GEM_DOMAIN_GART);
494 break;
495 default:
496 break;
497 }
498
499 if (error) {
500 NV_ERROR(drm, "bo %p pinned elsewhere: "
501 "0x%08x vs 0x%08x\n", bo,
502 bo->resource->mem_type, domain);
503 ret = -EBUSY;
504 }
505 ttm_bo_pin(&nvbo->bo);
506 goto out;
507 }
508
509 if (evict) {
510 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
511 ret = nouveau_bo_validate(nvbo, false, false);
512 if (ret)
513 goto out;
514 }
515
516 nouveau_bo_placement_set(nvbo, domain, 0);
517 ret = nouveau_bo_validate(nvbo, false, false);
518 if (ret)
519 goto out;
520
521 ttm_bo_pin(&nvbo->bo);
522
523 switch (bo->resource->mem_type) {
524 case TTM_PL_VRAM:
525 drm->gem.vram_available -= bo->base.size;
526 break;
527 case TTM_PL_TT:
528 drm->gem.gart_available -= bo->base.size;
529 break;
530 default:
531 break;
532 }
533
534out:
535 if (force && ret)
536 nvbo->contig = false;
537 ttm_bo_unreserve(bo);
538 return ret;
539}
540
541int
542nouveau_bo_unpin(struct nouveau_bo *nvbo)
543{
544 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
545 struct ttm_buffer_object *bo = &nvbo->bo;
546 int ret;
547
548 ret = ttm_bo_reserve(bo, false, false, NULL);
549 if (ret)
550 return ret;
551
552 ttm_bo_unpin(&nvbo->bo);
553 if (!nvbo->bo.pin_count) {
554 switch (bo->resource->mem_type) {
555 case TTM_PL_VRAM:
556 drm->gem.vram_available += bo->base.size;
557 break;
558 case TTM_PL_TT:
559 drm->gem.gart_available += bo->base.size;
560 break;
561 default:
562 break;
563 }
564 }
565
566 ttm_bo_unreserve(bo);
567 return 0;
568}
569
570int
571nouveau_bo_map(struct nouveau_bo *nvbo)
572{
573 int ret;
574
575 ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL);
576 if (ret)
577 return ret;
578
579 ret = ttm_bo_kmap(&nvbo->bo, 0, PFN_UP(nvbo->bo.base.size), &nvbo->kmap);
580
581 ttm_bo_unreserve(&nvbo->bo);
582 return ret;
583}
584
585void
586nouveau_bo_unmap(struct nouveau_bo *nvbo)
587{
588 if (!nvbo)
589 return;
590
591 ttm_bo_kunmap(&nvbo->kmap);
592}
593
594void
595nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
596{
597 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
598 struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm;
599 int i, j;
600
601 if (!ttm_dma || !ttm_dma->dma_address)
602 return;
603 if (!ttm_dma->pages) {
604 NV_DEBUG(drm, "ttm_dma 0x%p: pages NULL\n", ttm_dma);
605 return;
606 }
607
608 /* Don't waste time looping if the object is coherent */
609 if (nvbo->force_coherent)
610 return;
611
612 i = 0;
613 while (i < ttm_dma->num_pages) {
614 struct page *p = ttm_dma->pages[i];
615 size_t num_pages = 1;
616
617 for (j = i + 1; j < ttm_dma->num_pages; ++j) {
618 if (++p != ttm_dma->pages[j])
619 break;
620
621 ++num_pages;
622 }
623 dma_sync_single_for_device(drm->dev->dev,
624 ttm_dma->dma_address[i],
625 num_pages * PAGE_SIZE, DMA_TO_DEVICE);
626 i += num_pages;
627 }
628}
629
630void
631nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
632{
633 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
634 struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm;
635 int i, j;
636
637 if (!ttm_dma || !ttm_dma->dma_address)
638 return;
639 if (!ttm_dma->pages) {
640 NV_DEBUG(drm, "ttm_dma 0x%p: pages NULL\n", ttm_dma);
641 return;
642 }
643
644 /* Don't waste time looping if the object is coherent */
645 if (nvbo->force_coherent)
646 return;
647
648 i = 0;
649 while (i < ttm_dma->num_pages) {
650 struct page *p = ttm_dma->pages[i];
651 size_t num_pages = 1;
652
653 for (j = i + 1; j < ttm_dma->num_pages; ++j) {
654 if (++p != ttm_dma->pages[j])
655 break;
656
657 ++num_pages;
658 }
659
660 dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i],
661 num_pages * PAGE_SIZE, DMA_FROM_DEVICE);
662 i += num_pages;
663 }
664}
665
666void nouveau_bo_add_io_reserve_lru(struct ttm_buffer_object *bo)
667{
668 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
669 struct nouveau_bo *nvbo = nouveau_bo(bo);
670
671 mutex_lock(&drm->ttm.io_reserve_mutex);
672 list_move_tail(&nvbo->io_reserve_lru, &drm->ttm.io_reserve_lru);
673 mutex_unlock(&drm->ttm.io_reserve_mutex);
674}
675
676void nouveau_bo_del_io_reserve_lru(struct ttm_buffer_object *bo)
677{
678 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
679 struct nouveau_bo *nvbo = nouveau_bo(bo);
680
681 mutex_lock(&drm->ttm.io_reserve_mutex);
682 list_del_init(&nvbo->io_reserve_lru);
683 mutex_unlock(&drm->ttm.io_reserve_mutex);
684}
685
686int
687nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
688 bool no_wait_gpu)
689{
690 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
691 int ret;
692
693 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx);
694 if (ret)
695 return ret;
696
697 nouveau_bo_sync_for_device(nvbo);
698
699 return 0;
700}
701
702void
703nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
704{
705 bool is_iomem;
706 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
707
708 mem += index;
709
710 if (is_iomem)
711 iowrite16_native(val, (void __force __iomem *)mem);
712 else
713 *mem = val;
714}
715
716u32
717nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
718{
719 bool is_iomem;
720 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
721
722 mem += index;
723
724 if (is_iomem)
725 return ioread32_native((void __force __iomem *)mem);
726 else
727 return *mem;
728}
729
730void
731nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
732{
733 bool is_iomem;
734 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
735
736 mem += index;
737
738 if (is_iomem)
739 iowrite32_native(val, (void __force __iomem *)mem);
740 else
741 *mem = val;
742}
743
744static struct ttm_tt *
745nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags)
746{
747#if IS_ENABLED(CONFIG_AGP)
748 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
749
750 if (drm->agp.bridge) {
751 return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags);
752 }
753#endif
754
755 return nouveau_sgdma_create_ttm(bo, page_flags);
756}
757
758static int
759nouveau_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm,
760 struct ttm_resource *reg)
761{
762#if IS_ENABLED(CONFIG_AGP)
763 struct nouveau_drm *drm = nouveau_bdev(bdev);
764#endif
765 if (!reg)
766 return -EINVAL;
767#if IS_ENABLED(CONFIG_AGP)
768 if (drm->agp.bridge)
769 return ttm_agp_bind(ttm, reg);
770#endif
771 return nouveau_sgdma_bind(bdev, ttm, reg);
772}
773
774static void
775nouveau_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm)
776{
777#if IS_ENABLED(CONFIG_AGP)
778 struct nouveau_drm *drm = nouveau_bdev(bdev);
779
780 if (drm->agp.bridge) {
781 ttm_agp_unbind(ttm);
782 return;
783 }
784#endif
785 nouveau_sgdma_unbind(bdev, ttm);
786}
787
788static void
789nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
790{
791 struct nouveau_bo *nvbo = nouveau_bo(bo);
792
793 switch (bo->resource->mem_type) {
794 case TTM_PL_VRAM:
795 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART,
796 NOUVEAU_GEM_DOMAIN_CPU);
797 break;
798 default:
799 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_CPU, 0);
800 break;
801 }
802
803 *pl = nvbo->placement;
804}
805
806static int
807nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
808 struct ttm_resource *reg)
809{
810 struct nouveau_mem *old_mem = nouveau_mem(bo->resource);
811 struct nouveau_mem *new_mem = nouveau_mem(reg);
812 struct nvif_vmm *vmm = &drm->client.vmm.vmm;
813 int ret;
814
815 ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0,
816 old_mem->mem.size, &old_mem->vma[0]);
817 if (ret)
818 return ret;
819
820 ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0,
821 new_mem->mem.size, &old_mem->vma[1]);
822 if (ret)
823 goto done;
824
825 ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]);
826 if (ret)
827 goto done;
828
829 ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]);
830done:
831 if (ret) {
832 nvif_vmm_put(vmm, &old_mem->vma[1]);
833 nvif_vmm_put(vmm, &old_mem->vma[0]);
834 }
835 return 0;
836}
837
838static int
839nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict,
840 struct ttm_operation_ctx *ctx,
841 struct ttm_resource *new_reg)
842{
843 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
844 struct nouveau_channel *chan = drm->ttm.chan;
845 struct nouveau_cli *cli = (void *)chan->user.client;
846 struct nouveau_fence *fence;
847 int ret;
848
849 /* create temporary vmas for the transfer and attach them to the
850 * old nvkm_mem node, these will get cleaned up after ttm has
851 * destroyed the ttm_resource
852 */
853 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
854 ret = nouveau_bo_move_prep(drm, bo, new_reg);
855 if (ret)
856 return ret;
857 }
858
859 if (drm_drv_uses_atomic_modeset(drm->dev))
860 mutex_lock(&cli->mutex);
861 else
862 mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING);
863
864 ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, ctx->interruptible);
865 if (ret)
866 goto out_unlock;
867
868 ret = drm->ttm.move(chan, bo, bo->resource, new_reg);
869 if (ret)
870 goto out_unlock;
871
872 ret = nouveau_fence_new(&fence, chan);
873 if (ret)
874 goto out_unlock;
875
876 /* TODO: figure out a better solution here
877 *
878 * wait on the fence here explicitly as going through
879 * ttm_bo_move_accel_cleanup somehow doesn't seem to do it.
880 *
881 * Without this the operation can timeout and we'll fallback to a
882 * software copy, which might take several minutes to finish.
883 */
884 nouveau_fence_wait(fence, false, false);
885 ret = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, false,
886 new_reg);
887 nouveau_fence_unref(&fence);
888
889out_unlock:
890 mutex_unlock(&cli->mutex);
891 return ret;
892}
893
894void
895nouveau_bo_move_init(struct nouveau_drm *drm)
896{
897 static const struct _method_table {
898 const char *name;
899 int engine;
900 s32 oclass;
901 int (*exec)(struct nouveau_channel *,
902 struct ttm_buffer_object *,
903 struct ttm_resource *, struct ttm_resource *);
904 int (*init)(struct nouveau_channel *, u32 handle);
905 } _methods[] = {
906 { "COPY", 4, 0xc7b5, nve0_bo_move_copy, nve0_bo_move_init },
907 { "GRCE", 0, 0xc7b5, nve0_bo_move_copy, nvc0_bo_move_init },
908 { "COPY", 4, 0xc6b5, nve0_bo_move_copy, nve0_bo_move_init },
909 { "GRCE", 0, 0xc6b5, nve0_bo_move_copy, nvc0_bo_move_init },
910 { "COPY", 4, 0xc5b5, nve0_bo_move_copy, nve0_bo_move_init },
911 { "GRCE", 0, 0xc5b5, nve0_bo_move_copy, nvc0_bo_move_init },
912 { "COPY", 4, 0xc3b5, nve0_bo_move_copy, nve0_bo_move_init },
913 { "GRCE", 0, 0xc3b5, nve0_bo_move_copy, nvc0_bo_move_init },
914 { "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init },
915 { "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init },
916 { "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init },
917 { "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init },
918 { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init },
919 { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init },
920 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
921 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
922 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
923 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
924 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
925 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
926 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
927 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
928 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
929 {},
930 };
931 const struct _method_table *mthd = _methods;
932 const char *name = "CPU";
933 int ret;
934
935 do {
936 struct nouveau_channel *chan;
937
938 if (mthd->engine)
939 chan = drm->cechan;
940 else
941 chan = drm->channel;
942 if (chan == NULL)
943 continue;
944
945 ret = nvif_object_ctor(&chan->user, "ttmBoMove",
946 mthd->oclass | (mthd->engine << 16),
947 mthd->oclass, NULL, 0,
948 &drm->ttm.copy);
949 if (ret == 0) {
950 ret = mthd->init(chan, drm->ttm.copy.handle);
951 if (ret) {
952 nvif_object_dtor(&drm->ttm.copy);
953 continue;
954 }
955
956 drm->ttm.move = mthd->exec;
957 drm->ttm.chan = chan;
958 name = mthd->name;
959 break;
960 }
961 } while ((++mthd)->exec);
962
963 NV_INFO(drm, "MM: using %s for buffer copies\n", name);
964}
965
966static void nouveau_bo_move_ntfy(struct ttm_buffer_object *bo,
967 struct ttm_resource *new_reg)
968{
969 struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL;
970 struct nouveau_bo *nvbo = nouveau_bo(bo);
971 struct nouveau_vma *vma;
972 long ret;
973
974 /* ttm can now (stupidly) pass the driver bos it didn't create... */
975 if (bo->destroy != nouveau_bo_del_ttm)
976 return;
977
978 nouveau_bo_del_io_reserve_lru(bo);
979
980 if (mem && new_reg->mem_type != TTM_PL_SYSTEM &&
981 mem->mem.page == nvbo->page) {
982 list_for_each_entry(vma, &nvbo->vma_list, head) {
983 nouveau_vma_map(vma, mem);
984 }
985 nouveau_uvmm_bo_map_all(nvbo, mem);
986 } else {
987 list_for_each_entry(vma, &nvbo->vma_list, head) {
988 ret = dma_resv_wait_timeout(bo->base.resv,
989 DMA_RESV_USAGE_BOOKKEEP,
990 false, 15 * HZ);
991 WARN_ON(ret <= 0);
992 nouveau_vma_unmap(vma);
993 }
994 nouveau_uvmm_bo_unmap_all(nvbo);
995 }
996
997 if (new_reg)
998 nvbo->offset = (new_reg->start << PAGE_SHIFT);
999
1000}
1001
1002static int
1003nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_resource *new_reg,
1004 struct nouveau_drm_tile **new_tile)
1005{
1006 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1007 struct drm_device *dev = drm->dev;
1008 struct nouveau_bo *nvbo = nouveau_bo(bo);
1009 u64 offset = new_reg->start << PAGE_SHIFT;
1010
1011 *new_tile = NULL;
1012 if (new_reg->mem_type != TTM_PL_VRAM)
1013 return 0;
1014
1015 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
1016 *new_tile = nv10_bo_set_tiling(dev, offset, bo->base.size,
1017 nvbo->mode, nvbo->zeta);
1018 }
1019
1020 return 0;
1021}
1022
1023static void
1024nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1025 struct nouveau_drm_tile *new_tile,
1026 struct nouveau_drm_tile **old_tile)
1027{
1028 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1029 struct drm_device *dev = drm->dev;
1030 struct dma_fence *fence;
1031 int ret;
1032
1033 ret = dma_resv_get_singleton(bo->base.resv, DMA_RESV_USAGE_WRITE,
1034 &fence);
1035 if (ret)
1036 dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_WRITE,
1037 false, MAX_SCHEDULE_TIMEOUT);
1038
1039 nv10_bo_put_tile_region(dev, *old_tile, fence);
1040 *old_tile = new_tile;
1041}
1042
1043static int
1044nouveau_bo_move(struct ttm_buffer_object *bo, bool evict,
1045 struct ttm_operation_ctx *ctx,
1046 struct ttm_resource *new_reg,
1047 struct ttm_place *hop)
1048{
1049 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1050 struct nouveau_bo *nvbo = nouveau_bo(bo);
1051 struct drm_gem_object *obj = &bo->base;
1052 struct ttm_resource *old_reg = bo->resource;
1053 struct nouveau_drm_tile *new_tile = NULL;
1054 int ret = 0;
1055
1056 if (new_reg->mem_type == TTM_PL_TT) {
1057 ret = nouveau_ttm_tt_bind(bo->bdev, bo->ttm, new_reg);
1058 if (ret)
1059 return ret;
1060 }
1061
1062 drm_gpuvm_bo_gem_evict(obj, evict);
1063 nouveau_bo_move_ntfy(bo, new_reg);
1064 ret = ttm_bo_wait_ctx(bo, ctx);
1065 if (ret)
1066 goto out_ntfy;
1067
1068 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1069 ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile);
1070 if (ret)
1071 goto out_ntfy;
1072 }
1073
1074 /* Fake bo copy. */
1075 if (!old_reg || (old_reg->mem_type == TTM_PL_SYSTEM &&
1076 !bo->ttm)) {
1077 ttm_bo_move_null(bo, new_reg);
1078 goto out;
1079 }
1080
1081 if (old_reg->mem_type == TTM_PL_SYSTEM &&
1082 new_reg->mem_type == TTM_PL_TT) {
1083 ttm_bo_move_null(bo, new_reg);
1084 goto out;
1085 }
1086
1087 if (old_reg->mem_type == TTM_PL_TT &&
1088 new_reg->mem_type == TTM_PL_SYSTEM) {
1089 nouveau_ttm_tt_unbind(bo->bdev, bo->ttm);
1090 ttm_resource_free(bo, &bo->resource);
1091 ttm_bo_assign_mem(bo, new_reg);
1092 goto out;
1093 }
1094
1095 /* Hardware assisted copy. */
1096 if (drm->ttm.move) {
1097 if ((old_reg->mem_type == TTM_PL_SYSTEM &&
1098 new_reg->mem_type == TTM_PL_VRAM) ||
1099 (old_reg->mem_type == TTM_PL_VRAM &&
1100 new_reg->mem_type == TTM_PL_SYSTEM)) {
1101 hop->fpfn = 0;
1102 hop->lpfn = 0;
1103 hop->mem_type = TTM_PL_TT;
1104 hop->flags = 0;
1105 return -EMULTIHOP;
1106 }
1107 ret = nouveau_bo_move_m2mf(bo, evict, ctx,
1108 new_reg);
1109 } else
1110 ret = -ENODEV;
1111
1112 if (ret) {
1113 /* Fallback to software copy. */
1114 ret = ttm_bo_move_memcpy(bo, ctx, new_reg);
1115 }
1116
1117out:
1118 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1119 if (ret)
1120 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1121 else
1122 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1123 }
1124out_ntfy:
1125 if (ret) {
1126 nouveau_bo_move_ntfy(bo, bo->resource);
1127 drm_gpuvm_bo_gem_evict(obj, !evict);
1128 }
1129 return ret;
1130}
1131
1132static void
1133nouveau_ttm_io_mem_free_locked(struct nouveau_drm *drm,
1134 struct ttm_resource *reg)
1135{
1136 struct nouveau_mem *mem = nouveau_mem(reg);
1137
1138 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1139 switch (reg->mem_type) {
1140 case TTM_PL_TT:
1141 if (mem->kind)
1142 nvif_object_unmap_handle(&mem->mem.object);
1143 break;
1144 case TTM_PL_VRAM:
1145 nvif_object_unmap_handle(&mem->mem.object);
1146 break;
1147 default:
1148 break;
1149 }
1150 }
1151}
1152
1153static int
1154nouveau_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *reg)
1155{
1156 struct nouveau_drm *drm = nouveau_bdev(bdev);
1157 struct nvkm_device *device = nvxx_device(&drm->client.device);
1158 struct nouveau_mem *mem = nouveau_mem(reg);
1159 struct nvif_mmu *mmu = &drm->client.mmu;
1160 int ret;
1161
1162 mutex_lock(&drm->ttm.io_reserve_mutex);
1163retry:
1164 switch (reg->mem_type) {
1165 case TTM_PL_SYSTEM:
1166 /* System memory */
1167 ret = 0;
1168 goto out;
1169 case TTM_PL_TT:
1170#if IS_ENABLED(CONFIG_AGP)
1171 if (drm->agp.bridge) {
1172 reg->bus.offset = (reg->start << PAGE_SHIFT) +
1173 drm->agp.base;
1174 reg->bus.is_iomem = !drm->agp.cma;
1175 reg->bus.caching = ttm_write_combined;
1176 }
1177#endif
1178 if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 ||
1179 !mem->kind) {
1180 /* untiled */
1181 ret = 0;
1182 break;
1183 }
1184 fallthrough; /* tiled memory */
1185 case TTM_PL_VRAM:
1186 reg->bus.offset = (reg->start << PAGE_SHIFT) +
1187 device->func->resource_addr(device, 1);
1188 reg->bus.is_iomem = true;
1189
1190 /* Some BARs do not support being ioremapped WC */
1191 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
1192 mmu->type[drm->ttm.type_vram].type & NVIF_MEM_UNCACHED)
1193 reg->bus.caching = ttm_uncached;
1194 else
1195 reg->bus.caching = ttm_write_combined;
1196
1197 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1198 union {
1199 struct nv50_mem_map_v0 nv50;
1200 struct gf100_mem_map_v0 gf100;
1201 } args;
1202 u64 handle, length;
1203 u32 argc = 0;
1204
1205 switch (mem->mem.object.oclass) {
1206 case NVIF_CLASS_MEM_NV50:
1207 args.nv50.version = 0;
1208 args.nv50.ro = 0;
1209 args.nv50.kind = mem->kind;
1210 args.nv50.comp = mem->comp;
1211 argc = sizeof(args.nv50);
1212 break;
1213 case NVIF_CLASS_MEM_GF100:
1214 args.gf100.version = 0;
1215 args.gf100.ro = 0;
1216 args.gf100.kind = mem->kind;
1217 argc = sizeof(args.gf100);
1218 break;
1219 default:
1220 WARN_ON(1);
1221 break;
1222 }
1223
1224 ret = nvif_object_map_handle(&mem->mem.object,
1225 &args, argc,
1226 &handle, &length);
1227 if (ret != 1) {
1228 if (WARN_ON(ret == 0))
1229 ret = -EINVAL;
1230 goto out;
1231 }
1232
1233 reg->bus.offset = handle;
1234 }
1235 ret = 0;
1236 break;
1237 default:
1238 ret = -EINVAL;
1239 }
1240
1241out:
1242 if (ret == -ENOSPC) {
1243 struct nouveau_bo *nvbo;
1244
1245 nvbo = list_first_entry_or_null(&drm->ttm.io_reserve_lru,
1246 typeof(*nvbo),
1247 io_reserve_lru);
1248 if (nvbo) {
1249 list_del_init(&nvbo->io_reserve_lru);
1250 drm_vma_node_unmap(&nvbo->bo.base.vma_node,
1251 bdev->dev_mapping);
1252 nouveau_ttm_io_mem_free_locked(drm, nvbo->bo.resource);
1253 nvbo->bo.resource->bus.offset = 0;
1254 nvbo->bo.resource->bus.addr = NULL;
1255 goto retry;
1256 }
1257
1258 }
1259 mutex_unlock(&drm->ttm.io_reserve_mutex);
1260 return ret;
1261}
1262
1263static void
1264nouveau_ttm_io_mem_free(struct ttm_device *bdev, struct ttm_resource *reg)
1265{
1266 struct nouveau_drm *drm = nouveau_bdev(bdev);
1267
1268 mutex_lock(&drm->ttm.io_reserve_mutex);
1269 nouveau_ttm_io_mem_free_locked(drm, reg);
1270 mutex_unlock(&drm->ttm.io_reserve_mutex);
1271}
1272
1273vm_fault_t nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1274{
1275 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1276 struct nouveau_bo *nvbo = nouveau_bo(bo);
1277 struct nvkm_device *device = nvxx_device(&drm->client.device);
1278 u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT;
1279 int i, ret;
1280
1281 /* as long as the bo isn't in vram, and isn't tiled, we've got
1282 * nothing to do here.
1283 */
1284 if (bo->resource->mem_type != TTM_PL_VRAM) {
1285 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA ||
1286 !nvbo->kind)
1287 return 0;
1288
1289 if (bo->resource->mem_type != TTM_PL_SYSTEM)
1290 return 0;
1291
1292 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
1293
1294 } else {
1295 /* make sure bo is in mappable vram */
1296 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
1297 bo->resource->start + PFN_UP(bo->resource->size) < mappable)
1298 return 0;
1299
1300 for (i = 0; i < nvbo->placement.num_placement; ++i) {
1301 nvbo->placements[i].fpfn = 0;
1302 nvbo->placements[i].lpfn = mappable;
1303 }
1304
1305 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, 0);
1306 }
1307
1308 ret = nouveau_bo_validate(nvbo, false, false);
1309 if (unlikely(ret == -EBUSY || ret == -ERESTARTSYS))
1310 return VM_FAULT_NOPAGE;
1311 else if (unlikely(ret))
1312 return VM_FAULT_SIGBUS;
1313
1314 ttm_bo_move_to_lru_tail_unlocked(bo);
1315 return 0;
1316}
1317
1318static int
1319nouveau_ttm_tt_populate(struct ttm_device *bdev,
1320 struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
1321{
1322 struct ttm_tt *ttm_dma = (void *)ttm;
1323 struct nouveau_drm *drm;
1324 bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL);
1325
1326 if (ttm_tt_is_populated(ttm))
1327 return 0;
1328
1329 if (slave && ttm->sg) {
1330 drm_prime_sg_to_dma_addr_array(ttm->sg, ttm_dma->dma_address,
1331 ttm->num_pages);
1332 return 0;
1333 }
1334
1335 drm = nouveau_bdev(bdev);
1336
1337 return ttm_pool_alloc(&drm->ttm.bdev.pool, ttm, ctx);
1338}
1339
1340static void
1341nouveau_ttm_tt_unpopulate(struct ttm_device *bdev,
1342 struct ttm_tt *ttm)
1343{
1344 struct nouveau_drm *drm;
1345 bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL);
1346
1347 if (slave)
1348 return;
1349
1350 nouveau_ttm_tt_unbind(bdev, ttm);
1351
1352 drm = nouveau_bdev(bdev);
1353
1354 return ttm_pool_free(&drm->ttm.bdev.pool, ttm);
1355}
1356
1357static void
1358nouveau_ttm_tt_destroy(struct ttm_device *bdev,
1359 struct ttm_tt *ttm)
1360{
1361#if IS_ENABLED(CONFIG_AGP)
1362 struct nouveau_drm *drm = nouveau_bdev(bdev);
1363 if (drm->agp.bridge) {
1364 ttm_agp_destroy(ttm);
1365 return;
1366 }
1367#endif
1368 nouveau_sgdma_destroy(bdev, ttm);
1369}
1370
1371void
1372nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
1373{
1374 struct dma_resv *resv = nvbo->bo.base.resv;
1375
1376 if (!fence)
1377 return;
1378
1379 dma_resv_add_fence(resv, &fence->base, exclusive ?
1380 DMA_RESV_USAGE_WRITE : DMA_RESV_USAGE_READ);
1381}
1382
1383static void
1384nouveau_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1385{
1386 nouveau_bo_move_ntfy(bo, NULL);
1387}
1388
1389struct ttm_device_funcs nouveau_bo_driver = {
1390 .ttm_tt_create = &nouveau_ttm_tt_create,
1391 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1392 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1393 .ttm_tt_destroy = &nouveau_ttm_tt_destroy,
1394 .eviction_valuable = ttm_bo_eviction_valuable,
1395 .evict_flags = nouveau_bo_evict_flags,
1396 .delete_mem_notify = nouveau_bo_delete_mem_notify,
1397 .move = nouveau_bo_move,
1398 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1399 .io_mem_free = &nouveau_ttm_io_mem_free,
1400};