1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Defines for the MSP interrupt controller.
  4 *
  5 * Copyright (C) 1999 MIPS Technologies, Inc.  All rights reserved.
  6 * Author: Carsten Langgaard, carstenl@mips.com
  7 *
  8 * ########################################################################
  9 *
 10 * ########################################################################
 11 */
 12
 13#ifndef _MSP_SLP_INT_H
 14#define _MSP_SLP_INT_H
 15
 16/*
 17 * The PMC-Sierra SLP interrupts are arranged in a 3 level cascaded
 18 * hierarchical system.	 The first level are the direct MIPS interrupts
 19 * and are assigned the interrupt range 0-7.  The second level is the SLM
 20 * interrupt controller and is assigned the range 8-39.	 The third level
 21 * comprises the Peripherial block, the PCI block, the PCI MSI block and
 22 * the SLP.  The PCI interrupts and the SLP errors are handled by the
 23 * relevant subsystems so the core interrupt code needs only concern
 24 * itself with the Peripheral block.  These are assigned interrupts in
 25 * the range 40-71.
 26 */
 27
 28/*
 29 * IRQs directly connected to CPU
 30 */
 31#define MSP_MIPS_INTBASE	0
 32#define MSP_INT_SW0		0  /* IRQ for swint0,	      C_SW0  */
 33#define MSP_INT_SW1		1  /* IRQ for swint1,	      C_SW1  */
 34#define MSP_INT_MAC0		2  /* IRQ for MAC 0,	      C_IRQ0 */
 35#define MSP_INT_MAC1		3  /* IRQ for MAC 1,	      C_IRQ1 */
 36#define MSP_INT_C_IRQ2		4  /* Wired off,	      C_IRQ2 */
 37#define MSP_INT_VE		5  /* IRQ for Voice Engine,   C_IRQ3 */
 38#define MSP_INT_SLP		6  /* IRQ for SLM block,      C_IRQ4 */
 39#define MSP_INT_TIMER		7  /* IRQ for the MIPS timer, C_IRQ5 */
 40
 41/*
 42 * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
 43 * These defines should be tied to the register definition for the SLM
 44 * interrupt routine.  For now, just use hard-coded values.
 45 */
 46#define MSP_SLP_INTBASE		(MSP_MIPS_INTBASE + 8)
 47#define MSP_INT_EXT0		(MSP_SLP_INTBASE + 0)
 48					/* External interrupt 0		*/
 49#define MSP_INT_EXT1		(MSP_SLP_INTBASE + 1)
 50					/* External interrupt 1		*/
 51#define MSP_INT_EXT2		(MSP_SLP_INTBASE + 2)
 52					/* External interrupt 2		*/
 53#define MSP_INT_EXT3		(MSP_SLP_INTBASE + 3)
 54					/* External interrupt 3		*/
 55/* Reserved					   4-7			*/
 56
 57/*
 58 *************************************************************************
 59 * DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER *
 60 * Some MSP produces have this interrupt labelled as Voice and some are	 *
 61 * SEC mbox ...								 *
 62 *************************************************************************
 63 */
 64#define MSP_INT_SLP_VE		(MSP_SLP_INTBASE + 8)
 65					/* Cascaded IRQ for Voice Engine*/
 66#define MSP_INT_SLP_TDM		(MSP_SLP_INTBASE + 9)
 67					/* TDM interrupt		*/
 68#define MSP_INT_SLP_MAC0	(MSP_SLP_INTBASE + 10)
 69					/* Cascaded IRQ for MAC 0	*/
 70#define MSP_INT_SLP_MAC1	(MSP_SLP_INTBASE + 11)
 71					/* Cascaded IRQ for MAC 1	*/
 72#define MSP_INT_SEC		(MSP_SLP_INTBASE + 12)
 73					/* IRQ for security engine	*/
 74#define MSP_INT_PER		(MSP_SLP_INTBASE + 13)
 75					/* Peripheral interrupt		*/
 76#define MSP_INT_TIMER0		(MSP_SLP_INTBASE + 14)
 77					/* SLP timer 0			*/
 78#define MSP_INT_TIMER1		(MSP_SLP_INTBASE + 15)
 79					/* SLP timer 1			*/
 80#define MSP_INT_TIMER2		(MSP_SLP_INTBASE + 16)
 81					/* SLP timer 2			*/
 82#define MSP_INT_SLP_TIMER	(MSP_SLP_INTBASE + 17)
 83					/* Cascaded MIPS timer		*/
 84#define MSP_INT_BLKCP		(MSP_SLP_INTBASE + 18)
 85					/* Block Copy			*/
 86#define MSP_INT_UART0		(MSP_SLP_INTBASE + 19)
 87					/* UART 0			*/
 88#define MSP_INT_PCI		(MSP_SLP_INTBASE + 20)
 89					/* PCI subsystem		*/
 90#define MSP_INT_PCI_DBELL	(MSP_SLP_INTBASE + 21)
 91					/* PCI doorbell			*/
 92#define MSP_INT_PCI_MSI		(MSP_SLP_INTBASE + 22)
 93					/* PCI Message Signal		*/
 94#define MSP_INT_PCI_BC0		(MSP_SLP_INTBASE + 23)
 95					/* PCI Block Copy 0		*/
 96#define MSP_INT_PCI_BC1		(MSP_SLP_INTBASE + 24)
 97					/* PCI Block Copy 1		*/
 98#define MSP_INT_SLP_ERR		(MSP_SLP_INTBASE + 25)
 99					/* SLP error condition		*/
100#define MSP_INT_MAC2		(MSP_SLP_INTBASE + 26)
101					/* IRQ for MAC2			*/
102/* Reserved					   26-31		*/
103
104/*
105 * IRQs cascaded on SLP PER interrupt (MSP_INT_PER)
106 */
107#define MSP_PER_INTBASE		(MSP_SLP_INTBASE + 32)
108/* Reserved					   0-1			*/
109#define MSP_INT_UART1		(MSP_PER_INTBASE + 2)
110					/* UART 1			*/
111/* Reserved					   3-5			*/
112#define MSP_INT_2WIRE		(MSP_PER_INTBASE + 6)
113					/* 2-wire			*/
114#define MSP_INT_TM0		(MSP_PER_INTBASE + 7)
115					/* Peripheral timer block out 0 */
116#define MSP_INT_TM1		(MSP_PER_INTBASE + 8)
117					/* Peripheral timer block out 1 */
118/* Reserved					   9			*/
119#define MSP_INT_SPRX		(MSP_PER_INTBASE + 10)
120					/* SPI RX complete		*/
121#define MSP_INT_SPTX		(MSP_PER_INTBASE + 11)
122					/* SPI TX complete		*/
123#define MSP_INT_GPIO		(MSP_PER_INTBASE + 12)
124					/* GPIO				*/
125#define MSP_INT_PER_ERR		(MSP_PER_INTBASE + 13)
126					/* Peripheral error		*/
127/* Reserved					   14-31		*/
128
129#endif /* !_MSP_SLP_INT_H */