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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
4 *
5 * Copyright (C) 2009-2011 Nokia Corporation
6 * Copyright (C) 2012 Texas Instruments, Inc.
7 * Paul Walmsley
8 *
9 * XXX handle crossbar/shared link difference for L3?
10 * XXX these should be marked initdata for multi-OMAP kernels
11 */
12
13#include <linux/platform_data/i2c-omap.h>
14#include <linux/omap-dma.h>
15
16#include "omap_hwmod.h"
17#include "l3_2xxx.h"
18#include "l4_2xxx.h"
19
20#include "omap_hwmod_common_data.h"
21
22#include "cm-regbits-24xx.h"
23#include "prm-regbits-24xx.h"
24#include "i2c.h"
25#include "mmc.h"
26#include "serial.h"
27#include "wd_timer.h"
28
29/*
30 * OMAP2420 hardware module integration data
31 *
32 * All of the data in this section should be autogeneratable from the
33 * TI hardware database or other technical documentation. Data that
34 * is driver-specific or driver-kernel integration-specific belongs
35 * elsewhere.
36 */
37
38/*
39 * IP blocks
40 */
41
42/* IVA1 (IVA1) */
43static struct omap_hwmod_class iva1_hwmod_class = {
44 .name = "iva1",
45};
46
47static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
48 { .name = "iva", .rst_shift = 8 },
49};
50
51static struct omap_hwmod omap2420_iva_hwmod = {
52 .name = "iva",
53 .class = &iva1_hwmod_class,
54 .clkdm_name = "iva1_clkdm",
55 .rst_lines = omap2420_iva_resets,
56 .rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets),
57 .main_clk = "iva1_ifck",
58};
59
60/* DSP */
61static struct omap_hwmod_class dsp_hwmod_class = {
62 .name = "dsp",
63};
64
65static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
66 { .name = "logic", .rst_shift = 0 },
67 { .name = "mmu", .rst_shift = 1 },
68};
69
70static struct omap_hwmod omap2420_dsp_hwmod = {
71 .name = "dsp",
72 .class = &dsp_hwmod_class,
73 .clkdm_name = "dsp_clkdm",
74 .rst_lines = omap2420_dsp_resets,
75 .rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets),
76 .main_clk = "dsp_fck",
77};
78
79/* I2C common */
80static struct omap_hwmod_class_sysconfig i2c_sysc = {
81 .rev_offs = 0x00,
82 .sysc_offs = 0x20,
83 .syss_offs = 0x10,
84 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
85 .sysc_fields = &omap_hwmod_sysc_type1,
86};
87
88static struct omap_hwmod_class i2c_class = {
89 .name = "i2c",
90 .sysc = &i2c_sysc,
91 .reset = &omap_i2c_reset,
92};
93
94/* I2C1 */
95static struct omap_hwmod omap2420_i2c1_hwmod = {
96 .name = "i2c1",
97 .main_clk = "i2c1_fck",
98 .prcm = {
99 .omap2 = {
100 .module_offs = CORE_MOD,
101 .idlest_reg_id = 1,
102 .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
103 },
104 },
105 .class = &i2c_class,
106 /*
107 * From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
108 * while a transfer is active seems to cause the I2C block to
109 * timeout. Why? Good question."
110 */
111 .flags = (HWMOD_16BIT_REG | HWMOD_BLOCK_WFI),
112};
113
114/* I2C2 */
115static struct omap_hwmod omap2420_i2c2_hwmod = {
116 .name = "i2c2",
117 .main_clk = "i2c2_fck",
118 .prcm = {
119 .omap2 = {
120 .module_offs = CORE_MOD,
121 .idlest_reg_id = 1,
122 .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
123 },
124 },
125 .class = &i2c_class,
126 .flags = HWMOD_16BIT_REG,
127};
128
129/* dma attributes */
130static struct omap_dma_dev_attr dma_dev_attr = {
131 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
132 IS_CSSA_32 | IS_CDSA_32,
133 .lch_count = 32,
134};
135
136static struct omap_hwmod omap2420_dma_system_hwmod = {
137 .name = "dma",
138 .class = &omap2xxx_dma_hwmod_class,
139 .main_clk = "core_l3_ck",
140 .dev_attr = &dma_dev_attr,
141 .flags = HWMOD_NO_IDLEST,
142};
143
144/* mailbox */
145static struct omap_hwmod omap2420_mailbox_hwmod = {
146 .name = "mailbox",
147 .class = &omap2xxx_mailbox_hwmod_class,
148 .main_clk = "mailboxes_ick",
149 .prcm = {
150 .omap2 = {
151 .module_offs = CORE_MOD,
152 .idlest_reg_id = 1,
153 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
154 },
155 },
156};
157
158/*
159 * 'mcbsp' class
160 * multi channel buffered serial port controller
161 */
162
163static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
164 .name = "mcbsp",
165};
166
167static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
168 { .role = "pad_fck", .clk = "mcbsp_clks" },
169 { .role = "prcm_fck", .clk = "func_96m_ck" },
170};
171
172/* mcbsp1 */
173static struct omap_hwmod omap2420_mcbsp1_hwmod = {
174 .name = "mcbsp1",
175 .class = &omap2420_mcbsp_hwmod_class,
176 .main_clk = "mcbsp1_fck",
177 .prcm = {
178 .omap2 = {
179 .module_offs = CORE_MOD,
180 .idlest_reg_id = 1,
181 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
182 },
183 },
184 .opt_clks = mcbsp_opt_clks,
185 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
186};
187
188/* mcbsp2 */
189static struct omap_hwmod omap2420_mcbsp2_hwmod = {
190 .name = "mcbsp2",
191 .class = &omap2420_mcbsp_hwmod_class,
192 .main_clk = "mcbsp2_fck",
193 .prcm = {
194 .omap2 = {
195 .module_offs = CORE_MOD,
196 .idlest_reg_id = 1,
197 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
198 },
199 },
200 .opt_clks = mcbsp_opt_clks,
201 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
202};
203
204static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
205 .rev_offs = 0x3c,
206 .sysc_offs = 0x64,
207 .syss_offs = 0x68,
208 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
209 .sysc_fields = &omap_hwmod_sysc_type1,
210};
211
212static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
213 .name = "msdi",
214 .sysc = &omap2420_msdi_sysc,
215 .reset = &omap_msdi_reset,
216};
217
218/* msdi1 */
219static struct omap_hwmod omap2420_msdi1_hwmod = {
220 .name = "msdi1",
221 .class = &omap2420_msdi_hwmod_class,
222 .main_clk = "mmc_fck",
223 .prcm = {
224 .omap2 = {
225 .module_offs = CORE_MOD,
226 .idlest_reg_id = 1,
227 .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
228 },
229 },
230 .flags = HWMOD_16BIT_REG,
231};
232
233/* HDQ1W/1-wire */
234static struct omap_hwmod omap2420_hdq1w_hwmod = {
235 .name = "hdq1w",
236 .main_clk = "hdq_fck",
237 .prcm = {
238 .omap2 = {
239 .module_offs = CORE_MOD,
240 .idlest_reg_id = 1,
241 .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
242 },
243 },
244 .class = &omap2_hdq1w_class,
245};
246
247/*
248 * interfaces
249 */
250
251/* L4 CORE -> I2C1 interface */
252static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
253 .master = &omap2xxx_l4_core_hwmod,
254 .slave = &omap2420_i2c1_hwmod,
255 .clk = "i2c1_ick",
256 .user = OCP_USER_MPU | OCP_USER_SDMA,
257};
258
259/* L4 CORE -> I2C2 interface */
260static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
261 .master = &omap2xxx_l4_core_hwmod,
262 .slave = &omap2420_i2c2_hwmod,
263 .clk = "i2c2_ick",
264 .user = OCP_USER_MPU | OCP_USER_SDMA,
265};
266
267/* IVA <- L3 interface */
268static struct omap_hwmod_ocp_if omap2420_l3__iva = {
269 .master = &omap2xxx_l3_main_hwmod,
270 .slave = &omap2420_iva_hwmod,
271 .clk = "core_l3_ck",
272 .user = OCP_USER_MPU | OCP_USER_SDMA,
273};
274
275/* DSP <- L3 interface */
276static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
277 .master = &omap2xxx_l3_main_hwmod,
278 .slave = &omap2420_dsp_hwmod,
279 .clk = "dsp_ick",
280 .user = OCP_USER_MPU | OCP_USER_SDMA,
281};
282
283/* l4_wkup -> timer1 */
284static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
285 .master = &omap2xxx_l4_wkup_hwmod,
286 .slave = &omap2xxx_timer1_hwmod,
287 .clk = "gpt1_ick",
288 .user = OCP_USER_MPU | OCP_USER_SDMA,
289};
290
291/* l4_wkup -> wd_timer2 */
292static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
293 .master = &omap2xxx_l4_wkup_hwmod,
294 .slave = &omap2xxx_wd_timer2_hwmod,
295 .clk = "mpu_wdt_ick",
296 .user = OCP_USER_MPU | OCP_USER_SDMA,
297};
298
299/* l4_wkup -> gpio1 */
300static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
301 .master = &omap2xxx_l4_wkup_hwmod,
302 .slave = &omap2xxx_gpio1_hwmod,
303 .clk = "gpios_ick",
304 .user = OCP_USER_MPU | OCP_USER_SDMA,
305};
306
307/* l4_wkup -> gpio2 */
308static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
309 .master = &omap2xxx_l4_wkup_hwmod,
310 .slave = &omap2xxx_gpio2_hwmod,
311 .clk = "gpios_ick",
312 .user = OCP_USER_MPU | OCP_USER_SDMA,
313};
314
315/* l4_wkup -> gpio3 */
316static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
317 .master = &omap2xxx_l4_wkup_hwmod,
318 .slave = &omap2xxx_gpio3_hwmod,
319 .clk = "gpios_ick",
320 .user = OCP_USER_MPU | OCP_USER_SDMA,
321};
322
323/* l4_wkup -> gpio4 */
324static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
325 .master = &omap2xxx_l4_wkup_hwmod,
326 .slave = &omap2xxx_gpio4_hwmod,
327 .clk = "gpios_ick",
328 .user = OCP_USER_MPU | OCP_USER_SDMA,
329};
330
331/* dma_system -> L3 */
332static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
333 .master = &omap2420_dma_system_hwmod,
334 .slave = &omap2xxx_l3_main_hwmod,
335 .clk = "core_l3_ck",
336 .user = OCP_USER_MPU | OCP_USER_SDMA,
337};
338
339/* l4_core -> dma_system */
340static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
341 .master = &omap2xxx_l4_core_hwmod,
342 .slave = &omap2420_dma_system_hwmod,
343 .clk = "sdma_ick",
344 .user = OCP_USER_MPU | OCP_USER_SDMA,
345};
346
347/* l4_core -> mailbox */
348static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
349 .master = &omap2xxx_l4_core_hwmod,
350 .slave = &omap2420_mailbox_hwmod,
351 .user = OCP_USER_MPU | OCP_USER_SDMA,
352};
353
354/* l4_core -> mcbsp1 */
355static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
356 .master = &omap2xxx_l4_core_hwmod,
357 .slave = &omap2420_mcbsp1_hwmod,
358 .clk = "mcbsp1_ick",
359 .user = OCP_USER_MPU | OCP_USER_SDMA,
360};
361
362/* l4_core -> mcbsp2 */
363static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
364 .master = &omap2xxx_l4_core_hwmod,
365 .slave = &omap2420_mcbsp2_hwmod,
366 .clk = "mcbsp2_ick",
367 .user = OCP_USER_MPU | OCP_USER_SDMA,
368};
369
370/* l4_core -> msdi1 */
371static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
372 .master = &omap2xxx_l4_core_hwmod,
373 .slave = &omap2420_msdi1_hwmod,
374 .clk = "mmc_ick",
375 .user = OCP_USER_MPU | OCP_USER_SDMA,
376};
377
378/* l4_core -> hdq1w interface */
379static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
380 .master = &omap2xxx_l4_core_hwmod,
381 .slave = &omap2420_hdq1w_hwmod,
382 .clk = "hdq_ick",
383 .user = OCP_USER_MPU | OCP_USER_SDMA,
384 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
385};
386
387
388/* l4_wkup -> 32ksync_counter */
389static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
390 .master = &omap2xxx_l4_wkup_hwmod,
391 .slave = &omap2xxx_counter_32k_hwmod,
392 .clk = "sync_32k_ick",
393 .user = OCP_USER_MPU | OCP_USER_SDMA,
394};
395
396static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
397 .master = &omap2xxx_l3_main_hwmod,
398 .slave = &omap2xxx_gpmc_hwmod,
399 .clk = "core_l3_ck",
400 .user = OCP_USER_MPU | OCP_USER_SDMA,
401};
402
403static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
404 &omap2xxx_l3_main__l4_core,
405 &omap2xxx_mpu__l3_main,
406 &omap2xxx_dss__l3,
407 &omap2xxx_l4_core__mcspi1,
408 &omap2xxx_l4_core__mcspi2,
409 &omap2xxx_l4_core__l4_wkup,
410 &omap2_l4_core__uart1,
411 &omap2_l4_core__uart2,
412 &omap2_l4_core__uart3,
413 &omap2420_l4_core__i2c1,
414 &omap2420_l4_core__i2c2,
415 &omap2420_l3__iva,
416 &omap2420_l3__dsp,
417 &omap2420_l4_wkup__timer1,
418 &omap2xxx_l4_core__timer2,
419 &omap2xxx_l4_core__timer3,
420 &omap2xxx_l4_core__timer4,
421 &omap2xxx_l4_core__timer5,
422 &omap2xxx_l4_core__timer6,
423 &omap2xxx_l4_core__timer7,
424 &omap2xxx_l4_core__timer8,
425 &omap2xxx_l4_core__timer9,
426 &omap2xxx_l4_core__timer10,
427 &omap2xxx_l4_core__timer11,
428 &omap2xxx_l4_core__timer12,
429 &omap2420_l4_wkup__wd_timer2,
430 &omap2xxx_l4_core__dss,
431 &omap2xxx_l4_core__dss_dispc,
432 &omap2xxx_l4_core__dss_rfbi,
433 &omap2xxx_l4_core__dss_venc,
434 &omap2420_l4_wkup__gpio1,
435 &omap2420_l4_wkup__gpio2,
436 &omap2420_l4_wkup__gpio3,
437 &omap2420_l4_wkup__gpio4,
438 &omap2420_dma_system__l3,
439 &omap2420_l4_core__dma_system,
440 &omap2420_l4_core__mailbox,
441 &omap2420_l4_core__mcbsp1,
442 &omap2420_l4_core__mcbsp2,
443 &omap2420_l4_core__msdi1,
444 &omap2xxx_l4_core__rng,
445 &omap2xxx_l4_core__sham,
446 &omap2xxx_l4_core__aes,
447 &omap2420_l4_core__hdq1w,
448 &omap2420_l4_wkup__counter_32k,
449 &omap2420_l3__gpmc,
450 NULL,
451};
452
453int __init omap2420_hwmod_init(void)
454{
455 omap_hwmod_init();
456 return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
457}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
4 *
5 * Copyright (C) 2009-2011 Nokia Corporation
6 * Copyright (C) 2012 Texas Instruments, Inc.
7 * Paul Walmsley
8 *
9 * XXX handle crossbar/shared link difference for L3?
10 * XXX these should be marked initdata for multi-OMAP kernels
11 */
12
13#include <linux/platform_data/i2c-omap.h>
14
15#include "omap_hwmod.h"
16#include "l3_2xxx.h"
17#include "l4_2xxx.h"
18
19#include "omap_hwmod_common_data.h"
20
21#include "cm-regbits-24xx.h"
22#include "prm-regbits-24xx.h"
23#include "i2c.h"
24#include "mmc.h"
25#include "wd_timer.h"
26
27/*
28 * OMAP2420 hardware module integration data
29 *
30 * All of the data in this section should be autogeneratable from the
31 * TI hardware database or other technical documentation. Data that
32 * is driver-specific or driver-kernel integration-specific belongs
33 * elsewhere.
34 */
35
36/*
37 * IP blocks
38 */
39
40/* IVA1 (IVA1) */
41static struct omap_hwmod_class iva1_hwmod_class = {
42 .name = "iva1",
43};
44
45static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
46 { .name = "iva", .rst_shift = 8 },
47};
48
49static struct omap_hwmod omap2420_iva_hwmod = {
50 .name = "iva",
51 .class = &iva1_hwmod_class,
52 .clkdm_name = "iva1_clkdm",
53 .rst_lines = omap2420_iva_resets,
54 .rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets),
55 .main_clk = "iva1_ifck",
56};
57
58/* DSP */
59static struct omap_hwmod_class dsp_hwmod_class = {
60 .name = "dsp",
61};
62
63static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
64 { .name = "logic", .rst_shift = 0 },
65 { .name = "mmu", .rst_shift = 1 },
66};
67
68static struct omap_hwmod omap2420_dsp_hwmod = {
69 .name = "dsp",
70 .class = &dsp_hwmod_class,
71 .clkdm_name = "dsp_clkdm",
72 .rst_lines = omap2420_dsp_resets,
73 .rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets),
74 .main_clk = "dsp_fck",
75};
76
77/* I2C common */
78static struct omap_hwmod_class_sysconfig i2c_sysc = {
79 .rev_offs = 0x00,
80 .sysc_offs = 0x20,
81 .syss_offs = 0x10,
82 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
83 .sysc_fields = &omap_hwmod_sysc_type1,
84};
85
86static struct omap_hwmod_class i2c_class = {
87 .name = "i2c",
88 .sysc = &i2c_sysc,
89 .reset = &omap_i2c_reset,
90};
91
92/* I2C1 */
93static struct omap_hwmod omap2420_i2c1_hwmod = {
94 .name = "i2c1",
95 .main_clk = "i2c1_fck",
96 .prcm = {
97 .omap2 = {
98 .module_offs = CORE_MOD,
99 .idlest_reg_id = 1,
100 .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
101 },
102 },
103 .class = &i2c_class,
104 /*
105 * From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
106 * while a transfer is active seems to cause the I2C block to
107 * timeout. Why? Good question."
108 */
109 .flags = (HWMOD_16BIT_REG | HWMOD_BLOCK_WFI),
110};
111
112/* I2C2 */
113static struct omap_hwmod omap2420_i2c2_hwmod = {
114 .name = "i2c2",
115 .main_clk = "i2c2_fck",
116 .prcm = {
117 .omap2 = {
118 .module_offs = CORE_MOD,
119 .idlest_reg_id = 1,
120 .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
121 },
122 },
123 .class = &i2c_class,
124 .flags = HWMOD_16BIT_REG,
125};
126
127/* mailbox */
128static struct omap_hwmod omap2420_mailbox_hwmod = {
129 .name = "mailbox",
130 .class = &omap2xxx_mailbox_hwmod_class,
131 .main_clk = "mailboxes_ick",
132 .prcm = {
133 .omap2 = {
134 .module_offs = CORE_MOD,
135 .idlest_reg_id = 1,
136 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
137 },
138 },
139};
140
141/*
142 * 'mcbsp' class
143 * multi channel buffered serial port controller
144 */
145
146static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
147 .name = "mcbsp",
148};
149
150static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
151 { .role = "pad_fck", .clk = "mcbsp_clks" },
152 { .role = "prcm_fck", .clk = "func_96m_ck" },
153};
154
155/* mcbsp1 */
156static struct omap_hwmod omap2420_mcbsp1_hwmod = {
157 .name = "mcbsp1",
158 .class = &omap2420_mcbsp_hwmod_class,
159 .main_clk = "mcbsp1_fck",
160 .prcm = {
161 .omap2 = {
162 .module_offs = CORE_MOD,
163 .idlest_reg_id = 1,
164 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
165 },
166 },
167 .opt_clks = mcbsp_opt_clks,
168 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
169};
170
171/* mcbsp2 */
172static struct omap_hwmod omap2420_mcbsp2_hwmod = {
173 .name = "mcbsp2",
174 .class = &omap2420_mcbsp_hwmod_class,
175 .main_clk = "mcbsp2_fck",
176 .prcm = {
177 .omap2 = {
178 .module_offs = CORE_MOD,
179 .idlest_reg_id = 1,
180 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
181 },
182 },
183 .opt_clks = mcbsp_opt_clks,
184 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
185};
186
187static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
188 .rev_offs = 0x3c,
189 .sysc_offs = 0x64,
190 .syss_offs = 0x68,
191 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
192 .sysc_fields = &omap_hwmod_sysc_type1,
193};
194
195static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
196 .name = "msdi",
197 .sysc = &omap2420_msdi_sysc,
198 .reset = &omap_msdi_reset,
199};
200
201/* msdi1 */
202static struct omap_hwmod omap2420_msdi1_hwmod = {
203 .name = "msdi1",
204 .class = &omap2420_msdi_hwmod_class,
205 .main_clk = "mmc_fck",
206 .prcm = {
207 .omap2 = {
208 .module_offs = CORE_MOD,
209 .idlest_reg_id = 1,
210 .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
211 },
212 },
213 .flags = HWMOD_16BIT_REG,
214};
215
216/* HDQ1W/1-wire */
217static struct omap_hwmod omap2420_hdq1w_hwmod = {
218 .name = "hdq1w",
219 .main_clk = "hdq_fck",
220 .prcm = {
221 .omap2 = {
222 .module_offs = CORE_MOD,
223 .idlest_reg_id = 1,
224 .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
225 },
226 },
227 .class = &omap2_hdq1w_class,
228};
229
230/*
231 * interfaces
232 */
233
234/* L4 CORE -> I2C1 interface */
235static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
236 .master = &omap2xxx_l4_core_hwmod,
237 .slave = &omap2420_i2c1_hwmod,
238 .clk = "i2c1_ick",
239 .user = OCP_USER_MPU | OCP_USER_SDMA,
240};
241
242/* L4 CORE -> I2C2 interface */
243static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
244 .master = &omap2xxx_l4_core_hwmod,
245 .slave = &omap2420_i2c2_hwmod,
246 .clk = "i2c2_ick",
247 .user = OCP_USER_MPU | OCP_USER_SDMA,
248};
249
250/* IVA <- L3 interface */
251static struct omap_hwmod_ocp_if omap2420_l3__iva = {
252 .master = &omap2xxx_l3_main_hwmod,
253 .slave = &omap2420_iva_hwmod,
254 .clk = "core_l3_ck",
255 .user = OCP_USER_MPU | OCP_USER_SDMA,
256};
257
258/* DSP <- L3 interface */
259static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
260 .master = &omap2xxx_l3_main_hwmod,
261 .slave = &omap2420_dsp_hwmod,
262 .clk = "dsp_ick",
263 .user = OCP_USER_MPU | OCP_USER_SDMA,
264};
265
266/* l4_wkup -> wd_timer2 */
267static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
268 .master = &omap2xxx_l4_wkup_hwmod,
269 .slave = &omap2xxx_wd_timer2_hwmod,
270 .clk = "mpu_wdt_ick",
271 .user = OCP_USER_MPU | OCP_USER_SDMA,
272};
273
274/* l4_wkup -> gpio1 */
275static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
276 .master = &omap2xxx_l4_wkup_hwmod,
277 .slave = &omap2xxx_gpio1_hwmod,
278 .clk = "gpios_ick",
279 .user = OCP_USER_MPU | OCP_USER_SDMA,
280};
281
282/* l4_wkup -> gpio2 */
283static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
284 .master = &omap2xxx_l4_wkup_hwmod,
285 .slave = &omap2xxx_gpio2_hwmod,
286 .clk = "gpios_ick",
287 .user = OCP_USER_MPU | OCP_USER_SDMA,
288};
289
290/* l4_wkup -> gpio3 */
291static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
292 .master = &omap2xxx_l4_wkup_hwmod,
293 .slave = &omap2xxx_gpio3_hwmod,
294 .clk = "gpios_ick",
295 .user = OCP_USER_MPU | OCP_USER_SDMA,
296};
297
298/* l4_wkup -> gpio4 */
299static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
300 .master = &omap2xxx_l4_wkup_hwmod,
301 .slave = &omap2xxx_gpio4_hwmod,
302 .clk = "gpios_ick",
303 .user = OCP_USER_MPU | OCP_USER_SDMA,
304};
305
306/* l4_core -> mailbox */
307static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
308 .master = &omap2xxx_l4_core_hwmod,
309 .slave = &omap2420_mailbox_hwmod,
310 .user = OCP_USER_MPU | OCP_USER_SDMA,
311};
312
313/* l4_core -> mcbsp1 */
314static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
315 .master = &omap2xxx_l4_core_hwmod,
316 .slave = &omap2420_mcbsp1_hwmod,
317 .clk = "mcbsp1_ick",
318 .user = OCP_USER_MPU | OCP_USER_SDMA,
319};
320
321/* l4_core -> mcbsp2 */
322static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
323 .master = &omap2xxx_l4_core_hwmod,
324 .slave = &omap2420_mcbsp2_hwmod,
325 .clk = "mcbsp2_ick",
326 .user = OCP_USER_MPU | OCP_USER_SDMA,
327};
328
329/* l4_core -> msdi1 */
330static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
331 .master = &omap2xxx_l4_core_hwmod,
332 .slave = &omap2420_msdi1_hwmod,
333 .clk = "mmc_ick",
334 .user = OCP_USER_MPU | OCP_USER_SDMA,
335};
336
337/* l4_core -> hdq1w interface */
338static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
339 .master = &omap2xxx_l4_core_hwmod,
340 .slave = &omap2420_hdq1w_hwmod,
341 .clk = "hdq_ick",
342 .user = OCP_USER_MPU | OCP_USER_SDMA,
343 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
344};
345
346static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
347 .master = &omap2xxx_l3_main_hwmod,
348 .slave = &omap2xxx_gpmc_hwmod,
349 .clk = "core_l3_ck",
350 .user = OCP_USER_MPU | OCP_USER_SDMA,
351};
352
353static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
354 &omap2xxx_l3_main__l4_core,
355 &omap2xxx_mpu__l3_main,
356 &omap2xxx_dss__l3,
357 &omap2xxx_l4_core__mcspi1,
358 &omap2xxx_l4_core__mcspi2,
359 &omap2xxx_l4_core__l4_wkup,
360 &omap2_l4_core__uart1,
361 &omap2_l4_core__uart2,
362 &omap2_l4_core__uart3,
363 &omap2420_l4_core__i2c1,
364 &omap2420_l4_core__i2c2,
365 &omap2420_l3__iva,
366 &omap2420_l3__dsp,
367 &omap2xxx_l4_core__timer3,
368 &omap2xxx_l4_core__timer4,
369 &omap2xxx_l4_core__timer5,
370 &omap2xxx_l4_core__timer6,
371 &omap2xxx_l4_core__timer7,
372 &omap2xxx_l4_core__timer8,
373 &omap2xxx_l4_core__timer9,
374 &omap2xxx_l4_core__timer10,
375 &omap2xxx_l4_core__timer11,
376 &omap2xxx_l4_core__timer12,
377 &omap2420_l4_wkup__wd_timer2,
378 &omap2xxx_l4_core__dss,
379 &omap2xxx_l4_core__dss_dispc,
380 &omap2xxx_l4_core__dss_rfbi,
381 &omap2xxx_l4_core__dss_venc,
382 &omap2420_l4_wkup__gpio1,
383 &omap2420_l4_wkup__gpio2,
384 &omap2420_l4_wkup__gpio3,
385 &omap2420_l4_wkup__gpio4,
386 &omap2420_l4_core__mailbox,
387 &omap2420_l4_core__mcbsp1,
388 &omap2420_l4_core__mcbsp2,
389 &omap2420_l4_core__msdi1,
390 &omap2xxx_l4_core__rng,
391 &omap2xxx_l4_core__sham,
392 &omap2xxx_l4_core__aes,
393 &omap2420_l4_core__hdq1w,
394 &omap2420_l3__gpmc,
395 NULL,
396};
397
398int __init omap2420_hwmod_init(void)
399{
400 omap_hwmod_init();
401 return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
402}