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1// SPDX-License-Identifier: GPL-2.0
2
3/*
4 * xHCI host controller driver
5 *
6 * Copyright (C) 2008 Intel Corp.
7 *
8 * Author: Sarah Sharp
9 * Some code borrowed from the Linux EHCI driver.
10 */
11
12#ifndef __LINUX_XHCI_HCD_H
13#define __LINUX_XHCI_HCD_H
14
15#include <linux/usb.h>
16#include <linux/timer.h>
17#include <linux/kernel.h>
18#include <linux/usb/hcd.h>
19#include <linux/io-64-nonatomic-lo-hi.h>
20
21/* Code sharing between pci-quirks and xhci hcd */
22#include "xhci-ext-caps.h"
23#include "pci-quirks.h"
24
25/* xHCI PCI Configuration Registers */
26#define XHCI_SBRN_OFFSET (0x60)
27
28/* Max number of USB devices for any host controller - limit in section 6.1 */
29#define MAX_HC_SLOTS 256
30/* Section 5.3.3 - MaxPorts */
31#define MAX_HC_PORTS 127
32
33/*
34 * xHCI register interface.
35 * This corresponds to the eXtensible Host Controller Interface (xHCI)
36 * Revision 0.95 specification
37 */
38
39/**
40 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
41 * @hc_capbase: length of the capabilities register and HC version number
42 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
43 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
44 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
45 * @hcc_params: HCCPARAMS - Capability Parameters
46 * @db_off: DBOFF - Doorbell array offset
47 * @run_regs_off: RTSOFF - Runtime register space offset
48 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only
49 */
50struct xhci_cap_regs {
51 __le32 hc_capbase;
52 __le32 hcs_params1;
53 __le32 hcs_params2;
54 __le32 hcs_params3;
55 __le32 hcc_params;
56 __le32 db_off;
57 __le32 run_regs_off;
58 __le32 hcc_params2; /* xhci 1.1 */
59 /* Reserved up to (CAPLENGTH - 0x1C) */
60};
61
62/* hc_capbase bitmasks */
63/* bits 7:0 - how long is the Capabilities register */
64#define HC_LENGTH(p) XHCI_HC_LENGTH(p)
65/* bits 31:16 */
66#define HC_VERSION(p) (((p) >> 16) & 0xffff)
67
68/* HCSPARAMS1 - hcs_params1 - bitmasks */
69/* bits 0:7, Max Device Slots */
70#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
71#define HCS_SLOTS_MASK 0xff
72/* bits 8:18, Max Interrupters */
73#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
74/* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
75#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
76
77/* HCSPARAMS2 - hcs_params2 - bitmasks */
78/* bits 0:3, frames or uframes that SW needs to queue transactions
79 * ahead of the HW to meet periodic deadlines */
80#define HCS_IST(p) (((p) >> 0) & 0xf)
81/* bits 4:7, max number of Event Ring segments */
82#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
83/* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */
84/* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
85/* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */
86#define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
87
88/* HCSPARAMS3 - hcs_params3 - bitmasks */
89/* bits 0:7, Max U1 to U0 latency for the roothub ports */
90#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
91/* bits 16:31, Max U2 to U0 latency for the roothub ports */
92#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
93
94/* HCCPARAMS - hcc_params - bitmasks */
95/* true: HC can use 64-bit address pointers */
96#define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
97/* true: HC can do bandwidth negotiation */
98#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
99/* true: HC uses 64-byte Device Context structures
100 * FIXME 64-byte context structures aren't supported yet.
101 */
102#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
103/* true: HC has port power switches */
104#define HCC_PPC(p) ((p) & (1 << 3))
105/* true: HC has port indicators */
106#define HCS_INDICATOR(p) ((p) & (1 << 4))
107/* true: HC has Light HC Reset Capability */
108#define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
109/* true: HC supports latency tolerance messaging */
110#define HCC_LTC(p) ((p) & (1 << 6))
111/* true: no secondary Stream ID Support */
112#define HCC_NSS(p) ((p) & (1 << 7))
113/* true: HC supports Stopped - Short Packet */
114#define HCC_SPC(p) ((p) & (1 << 9))
115/* true: HC has Contiguous Frame ID Capability */
116#define HCC_CFC(p) ((p) & (1 << 11))
117/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
118#define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
119/* Extended Capabilities pointer from PCI base - section 5.3.6 */
120#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
121
122#define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
123
124/* db_off bitmask - bits 0:1 reserved */
125#define DBOFF_MASK (~0x3)
126
127/* run_regs_off bitmask - bits 0:4 reserved */
128#define RTSOFF_MASK (~0x1f)
129
130/* HCCPARAMS2 - hcc_params2 - bitmasks */
131/* true: HC supports U3 entry Capability */
132#define HCC2_U3C(p) ((p) & (1 << 0))
133/* true: HC supports Configure endpoint command Max exit latency too large */
134#define HCC2_CMC(p) ((p) & (1 << 1))
135/* true: HC supports Force Save context Capability */
136#define HCC2_FSC(p) ((p) & (1 << 2))
137/* true: HC supports Compliance Transition Capability */
138#define HCC2_CTC(p) ((p) & (1 << 3))
139/* true: HC support Large ESIT payload Capability > 48k */
140#define HCC2_LEC(p) ((p) & (1 << 4))
141/* true: HC support Configuration Information Capability */
142#define HCC2_CIC(p) ((p) & (1 << 5))
143/* true: HC support Extended TBC Capability, Isoc burst count > 65535 */
144#define HCC2_ETC(p) ((p) & (1 << 6))
145
146/* Number of registers per port */
147#define NUM_PORT_REGS 4
148
149#define PORTSC 0
150#define PORTPMSC 1
151#define PORTLI 2
152#define PORTHLPMC 3
153
154/**
155 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
156 * @command: USBCMD - xHC command register
157 * @status: USBSTS - xHC status register
158 * @page_size: This indicates the page size that the host controller
159 * supports. If bit n is set, the HC supports a page size
160 * of 2^(n+12), up to a 128MB page size.
161 * 4K is the minimum page size.
162 * @cmd_ring: CRP - 64-bit Command Ring Pointer
163 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
164 * @config_reg: CONFIG - Configure Register
165 * @port_status_base: PORTSCn - base address for Port Status and Control
166 * Each port has a Port Status and Control register,
167 * followed by a Port Power Management Status and Control
168 * register, a Port Link Info register, and a reserved
169 * register.
170 * @port_power_base: PORTPMSCn - base address for
171 * Port Power Management Status and Control
172 * @port_link_base: PORTLIn - base address for Port Link Info (current
173 * Link PM state and control) for USB 2.1 and USB 3.0
174 * devices.
175 */
176struct xhci_op_regs {
177 __le32 command;
178 __le32 status;
179 __le32 page_size;
180 __le32 reserved1;
181 __le32 reserved2;
182 __le32 dev_notification;
183 __le64 cmd_ring;
184 /* rsvd: offset 0x20-2F */
185 __le32 reserved3[4];
186 __le64 dcbaa_ptr;
187 __le32 config_reg;
188 /* rsvd: offset 0x3C-3FF */
189 __le32 reserved4[241];
190 /* port 1 registers, which serve as a base address for other ports */
191 __le32 port_status_base;
192 __le32 port_power_base;
193 __le32 port_link_base;
194 __le32 reserved5;
195 /* registers for ports 2-255 */
196 __le32 reserved6[NUM_PORT_REGS*254];
197};
198
199/* USBCMD - USB command - command bitmasks */
200/* start/stop HC execution - do not write unless HC is halted*/
201#define CMD_RUN XHCI_CMD_RUN
202/* Reset HC - resets internal HC state machine and all registers (except
203 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
204 * The xHCI driver must reinitialize the xHC after setting this bit.
205 */
206#define CMD_RESET (1 << 1)
207/* Event Interrupt Enable - a '1' allows interrupts from the host controller */
208#define CMD_EIE XHCI_CMD_EIE
209/* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
210#define CMD_HSEIE XHCI_CMD_HSEIE
211/* bits 4:6 are reserved (and should be preserved on writes). */
212/* light reset (port status stays unchanged) - reset completed when this is 0 */
213#define CMD_LRESET (1 << 7)
214/* host controller save/restore state. */
215#define CMD_CSS (1 << 8)
216#define CMD_CRS (1 << 9)
217/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
218#define CMD_EWE XHCI_CMD_EWE
219/* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
220 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
221 * '0' means the xHC can power it off if all ports are in the disconnect,
222 * disabled, or powered-off state.
223 */
224#define CMD_PM_INDEX (1 << 11)
225/* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */
226#define CMD_ETE (1 << 14)
227/* bits 15:31 are reserved (and should be preserved on writes). */
228
229/* IMAN - Interrupt Management Register */
230#define IMAN_IE (1 << 1)
231#define IMAN_IP (1 << 0)
232
233/* USBSTS - USB status - status bitmasks */
234/* HC not running - set to 1 when run/stop bit is cleared. */
235#define STS_HALT XHCI_STS_HALT
236/* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
237#define STS_FATAL (1 << 2)
238/* event interrupt - clear this prior to clearing any IP flags in IR set*/
239#define STS_EINT (1 << 3)
240/* port change detect */
241#define STS_PORT (1 << 4)
242/* bits 5:7 reserved and zeroed */
243/* save state status - '1' means xHC is saving state */
244#define STS_SAVE (1 << 8)
245/* restore state status - '1' means xHC is restoring state */
246#define STS_RESTORE (1 << 9)
247/* true: save or restore error */
248#define STS_SRE (1 << 10)
249/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
250#define STS_CNR XHCI_STS_CNR
251/* true: internal Host Controller Error - SW needs to reset and reinitialize */
252#define STS_HCE (1 << 12)
253/* bits 13:31 reserved and should be preserved */
254
255/*
256 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
257 * Generate a device notification event when the HC sees a transaction with a
258 * notification type that matches a bit set in this bit field.
259 */
260#define DEV_NOTE_MASK (0xffff)
261#define ENABLE_DEV_NOTE(x) (1 << (x))
262/* Most of the device notification types should only be used for debug.
263 * SW does need to pay attention to function wake notifications.
264 */
265#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
266
267/* CRCR - Command Ring Control Register - cmd_ring bitmasks */
268/* bit 0 is the command ring cycle state */
269/* stop ring operation after completion of the currently executing command */
270#define CMD_RING_PAUSE (1 << 1)
271/* stop ring immediately - abort the currently executing command */
272#define CMD_RING_ABORT (1 << 2)
273/* true: command ring is running */
274#define CMD_RING_RUNNING (1 << 3)
275/* bits 4:5 reserved and should be preserved */
276/* Command Ring pointer - bit mask for the lower 32 bits. */
277#define CMD_RING_RSVD_BITS (0x3f)
278
279/* CONFIG - Configure Register - config_reg bitmasks */
280/* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
281#define MAX_DEVS(p) ((p) & 0xff)
282/* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */
283#define CONFIG_U3E (1 << 8)
284/* bit 9: Configuration Information Enable, xhci 1.1 */
285#define CONFIG_CIE (1 << 9)
286/* bits 10:31 - reserved and should be preserved */
287
288/* PORTSC - Port Status and Control Register - port_status_base bitmasks */
289/* true: device connected */
290#define PORT_CONNECT (1 << 0)
291/* true: port enabled */
292#define PORT_PE (1 << 1)
293/* bit 2 reserved and zeroed */
294/* true: port has an over-current condition */
295#define PORT_OC (1 << 3)
296/* true: port reset signaling asserted */
297#define PORT_RESET (1 << 4)
298/* Port Link State - bits 5:8
299 * A read gives the current link PM state of the port,
300 * a write with Link State Write Strobe set sets the link state.
301 */
302#define PORT_PLS_MASK (0xf << 5)
303#define XDEV_U0 (0x0 << 5)
304#define XDEV_U1 (0x1 << 5)
305#define XDEV_U2 (0x2 << 5)
306#define XDEV_U3 (0x3 << 5)
307#define XDEV_DISABLED (0x4 << 5)
308#define XDEV_RXDETECT (0x5 << 5)
309#define XDEV_INACTIVE (0x6 << 5)
310#define XDEV_POLLING (0x7 << 5)
311#define XDEV_RECOVERY (0x8 << 5)
312#define XDEV_HOT_RESET (0x9 << 5)
313#define XDEV_COMP_MODE (0xa << 5)
314#define XDEV_TEST_MODE (0xb << 5)
315#define XDEV_RESUME (0xf << 5)
316
317/* true: port has power (see HCC_PPC) */
318#define PORT_POWER (1 << 9)
319/* bits 10:13 indicate device speed:
320 * 0 - undefined speed - port hasn't be initialized by a reset yet
321 * 1 - full speed
322 * 2 - low speed
323 * 3 - high speed
324 * 4 - super speed
325 * 5-15 reserved
326 */
327#define DEV_SPEED_MASK (0xf << 10)
328#define XDEV_FS (0x1 << 10)
329#define XDEV_LS (0x2 << 10)
330#define XDEV_HS (0x3 << 10)
331#define XDEV_SS (0x4 << 10)
332#define XDEV_SSP (0x5 << 10)
333#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
334#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
335#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
336#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
337#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
338#define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP)
339#define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS)
340#define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f)
341
342/* Bits 20:23 in the Slot Context are the speed for the device */
343#define SLOT_SPEED_FS (XDEV_FS << 10)
344#define SLOT_SPEED_LS (XDEV_LS << 10)
345#define SLOT_SPEED_HS (XDEV_HS << 10)
346#define SLOT_SPEED_SS (XDEV_SS << 10)
347#define SLOT_SPEED_SSP (XDEV_SSP << 10)
348/* Port Indicator Control */
349#define PORT_LED_OFF (0 << 14)
350#define PORT_LED_AMBER (1 << 14)
351#define PORT_LED_GREEN (2 << 14)
352#define PORT_LED_MASK (3 << 14)
353/* Port Link State Write Strobe - set this when changing link state */
354#define PORT_LINK_STROBE (1 << 16)
355/* true: connect status change */
356#define PORT_CSC (1 << 17)
357/* true: port enable change */
358#define PORT_PEC (1 << 18)
359/* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
360 * into an enabled state, and the device into the default state. A "warm" reset
361 * also resets the link, forcing the device through the link training sequence.
362 * SW can also look at the Port Reset register to see when warm reset is done.
363 */
364#define PORT_WRC (1 << 19)
365/* true: over-current change */
366#define PORT_OCC (1 << 20)
367/* true: reset change - 1 to 0 transition of PORT_RESET */
368#define PORT_RC (1 << 21)
369/* port link status change - set on some port link state transitions:
370 * Transition Reason
371 * ------------------------------------------------------------------------------
372 * - U3 to Resume Wakeup signaling from a device
373 * - Resume to Recovery to U0 USB 3.0 device resume
374 * - Resume to U0 USB 2.0 device resume
375 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
376 * - U3 to U0 Software resume of USB 2.0 device complete
377 * - U2 to U0 L1 resume of USB 2.1 device complete
378 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
379 * - U0 to disabled L1 entry error with USB 2.1 device
380 * - Any state to inactive Error on USB 3.0 port
381 */
382#define PORT_PLC (1 << 22)
383/* port configure error change - port failed to configure its link partner */
384#define PORT_CEC (1 << 23)
385#define PORT_CHANGE_MASK (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
386 PORT_RC | PORT_PLC | PORT_CEC)
387
388
389/* Cold Attach Status - xHC can set this bit to report device attached during
390 * Sx state. Warm port reset should be perfomed to clear this bit and move port
391 * to connected state.
392 */
393#define PORT_CAS (1 << 24)
394/* wake on connect (enable) */
395#define PORT_WKCONN_E (1 << 25)
396/* wake on disconnect (enable) */
397#define PORT_WKDISC_E (1 << 26)
398/* wake on over-current (enable) */
399#define PORT_WKOC_E (1 << 27)
400/* bits 28:29 reserved */
401/* true: device is non-removable - for USB 3.0 roothub emulation */
402#define PORT_DEV_REMOVE (1 << 30)
403/* Initiate a warm port reset - complete when PORT_WRC is '1' */
404#define PORT_WR (1 << 31)
405
406/* We mark duplicate entries with -1 */
407#define DUPLICATE_ENTRY ((u8)(-1))
408
409/* Port Power Management Status and Control - port_power_base bitmasks */
410/* Inactivity timer value for transitions into U1, in microseconds.
411 * Timeout can be up to 127us. 0xFF means an infinite timeout.
412 */
413#define PORT_U1_TIMEOUT(p) ((p) & 0xff)
414#define PORT_U1_TIMEOUT_MASK 0xff
415/* Inactivity timer value for transitions into U2 */
416#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
417#define PORT_U2_TIMEOUT_MASK (0xff << 8)
418/* Bits 24:31 for port testing */
419
420/* USB2 Protocol PORTSPMSC */
421#define PORT_L1S_MASK 7
422#define PORT_L1S_SUCCESS 1
423#define PORT_RWE (1 << 3)
424#define PORT_HIRD(p) (((p) & 0xf) << 4)
425#define PORT_HIRD_MASK (0xf << 4)
426#define PORT_L1DS_MASK (0xff << 8)
427#define PORT_L1DS(p) (((p) & 0xff) << 8)
428#define PORT_HLE (1 << 16)
429#define PORT_TEST_MODE_SHIFT 28
430
431/* USB3 Protocol PORTLI Port Link Information */
432#define PORT_RX_LANES(p) (((p) >> 16) & 0xf)
433#define PORT_TX_LANES(p) (((p) >> 20) & 0xf)
434
435/* USB2 Protocol PORTHLPMC */
436#define PORT_HIRDM(p)((p) & 3)
437#define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
438#define PORT_BESLD(p)(((p) & 0xf) << 10)
439
440/* use 512 microseconds as USB2 LPM L1 default timeout. */
441#define XHCI_L1_TIMEOUT 512
442
443/* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency.
444 * Safe to use with mixed HIRD and BESL systems (host and device) and is used
445 * by other operating systems.
446 *
447 * XHCI 1.0 errata 8/14/12 Table 13 notes:
448 * "Software should choose xHC BESL/BESLD field values that do not violate a
449 * device's resume latency requirements,
450 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached,
451 * or not program values < '4' if BLC = '0' and a BESL device is attached.
452 */
453#define XHCI_DEFAULT_BESL 4
454
455/*
456 * USB3 specification define a 360ms tPollingLFPSTiemout for USB3 ports
457 * to complete link training. usually link trainig completes much faster
458 * so check status 10 times with 36ms sleep in places we need to wait for
459 * polling to complete.
460 */
461#define XHCI_PORT_POLLING_LFPS_TIME 36
462
463/**
464 * struct xhci_intr_reg - Interrupt Register Set
465 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
466 * interrupts and check for pending interrupts.
467 * @irq_control: IMOD - Interrupt Moderation Register.
468 * Used to throttle interrupts.
469 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
470 * @erst_base: ERST base address.
471 * @erst_dequeue: Event ring dequeue pointer.
472 *
473 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
474 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
475 * multiple segments of the same size. The HC places events on the ring and
476 * "updates the Cycle bit in the TRBs to indicate to software the current
477 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
478 * updates the dequeue pointer.
479 */
480struct xhci_intr_reg {
481 __le32 irq_pending;
482 __le32 irq_control;
483 __le32 erst_size;
484 __le32 rsvd;
485 __le64 erst_base;
486 __le64 erst_dequeue;
487};
488
489/* irq_pending bitmasks */
490#define ER_IRQ_PENDING(p) ((p) & 0x1)
491/* bits 2:31 need to be preserved */
492/* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
493#define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
494#define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
495#define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
496
497/* irq_control bitmasks */
498/* Minimum interval between interrupts (in 250ns intervals). The interval
499 * between interrupts will be longer if there are no events on the event ring.
500 * Default is 4000 (1 ms).
501 */
502#define ER_IRQ_INTERVAL_MASK (0xffff)
503/* Counter used to count down the time to the next interrupt - HW use only */
504#define ER_IRQ_COUNTER_MASK (0xffff << 16)
505
506/* erst_size bitmasks */
507/* Preserve bits 16:31 of erst_size */
508#define ERST_SIZE_MASK (0xffff << 16)
509
510/* erst_dequeue bitmasks */
511/* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
512 * where the current dequeue pointer lies. This is an optional HW hint.
513 */
514#define ERST_DESI_MASK (0x7)
515/* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
516 * a work queue (or delayed service routine)?
517 */
518#define ERST_EHB (1 << 3)
519#define ERST_PTR_MASK (0xf)
520
521/**
522 * struct xhci_run_regs
523 * @microframe_index:
524 * MFINDEX - current microframe number
525 *
526 * Section 5.5 Host Controller Runtime Registers:
527 * "Software should read and write these registers using only Dword (32 bit)
528 * or larger accesses"
529 */
530struct xhci_run_regs {
531 __le32 microframe_index;
532 __le32 rsvd[7];
533 struct xhci_intr_reg ir_set[128];
534};
535
536/**
537 * struct doorbell_array
538 *
539 * Bits 0 - 7: Endpoint target
540 * Bits 8 - 15: RsvdZ
541 * Bits 16 - 31: Stream ID
542 *
543 * Section 5.6
544 */
545struct xhci_doorbell_array {
546 __le32 doorbell[256];
547};
548
549#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
550#define DB_VALUE_HOST 0x00000000
551
552/**
553 * struct xhci_protocol_caps
554 * @revision: major revision, minor revision, capability ID,
555 * and next capability pointer.
556 * @name_string: Four ASCII characters to say which spec this xHC
557 * follows, typically "USB ".
558 * @port_info: Port offset, count, and protocol-defined information.
559 */
560struct xhci_protocol_caps {
561 u32 revision;
562 u32 name_string;
563 u32 port_info;
564};
565
566#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
567#define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff)
568#define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f)
569#define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
570#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
571
572#define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f)
573#define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03)
574#define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03)
575#define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01)
576#define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03)
577#define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff)
578
579#define PLT_MASK (0x03 << 6)
580#define PLT_SYM (0x00 << 6)
581#define PLT_ASYM_RX (0x02 << 6)
582#define PLT_ASYM_TX (0x03 << 6)
583
584/**
585 * struct xhci_container_ctx
586 * @type: Type of context. Used to calculated offsets to contained contexts.
587 * @size: Size of the context data
588 * @bytes: The raw context data given to HW
589 * @dma: dma address of the bytes
590 *
591 * Represents either a Device or Input context. Holds a pointer to the raw
592 * memory used for the context (bytes) and dma address of it (dma).
593 */
594struct xhci_container_ctx {
595 unsigned type;
596#define XHCI_CTX_TYPE_DEVICE 0x1
597#define XHCI_CTX_TYPE_INPUT 0x2
598
599 int size;
600
601 u8 *bytes;
602 dma_addr_t dma;
603};
604
605/**
606 * struct xhci_slot_ctx
607 * @dev_info: Route string, device speed, hub info, and last valid endpoint
608 * @dev_info2: Max exit latency for device number, root hub port number
609 * @tt_info: tt_info is used to construct split transaction tokens
610 * @dev_state: slot state and device address
611 *
612 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
613 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
614 * reserved at the end of the slot context for HC internal use.
615 */
616struct xhci_slot_ctx {
617 __le32 dev_info;
618 __le32 dev_info2;
619 __le32 tt_info;
620 __le32 dev_state;
621 /* offset 0x10 to 0x1f reserved for HC internal use */
622 __le32 reserved[4];
623};
624
625/* dev_info bitmasks */
626/* Route String - 0:19 */
627#define ROUTE_STRING_MASK (0xfffff)
628/* Device speed - values defined by PORTSC Device Speed field - 20:23 */
629#define DEV_SPEED (0xf << 20)
630#define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20)
631/* bit 24 reserved */
632/* Is this LS/FS device connected through a HS hub? - bit 25 */
633#define DEV_MTT (0x1 << 25)
634/* Set if the device is a hub - bit 26 */
635#define DEV_HUB (0x1 << 26)
636/* Index of the last valid endpoint context in this device context - 27:31 */
637#define LAST_CTX_MASK (0x1f << 27)
638#define LAST_CTX(p) ((p) << 27)
639#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
640#define SLOT_FLAG (1 << 0)
641#define EP0_FLAG (1 << 1)
642
643/* dev_info2 bitmasks */
644/* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
645#define MAX_EXIT (0xffff)
646/* Root hub port number that is needed to access the USB device */
647#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
648#define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
649/* Maximum number of ports under a hub device */
650#define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
651#define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24)
652
653/* tt_info bitmasks */
654/*
655 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
656 * The Slot ID of the hub that isolates the high speed signaling from
657 * this low or full-speed device. '0' if attached to root hub port.
658 */
659#define TT_SLOT (0xff)
660/*
661 * The number of the downstream facing port of the high-speed hub
662 * '0' if the device is not low or full speed.
663 */
664#define TT_PORT (0xff << 8)
665#define TT_THINK_TIME(p) (((p) & 0x3) << 16)
666#define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16)
667
668/* dev_state bitmasks */
669/* USB device address - assigned by the HC */
670#define DEV_ADDR_MASK (0xff)
671/* bits 8:26 reserved */
672/* Slot state */
673#define SLOT_STATE (0x1f << 27)
674#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
675
676#define SLOT_STATE_DISABLED 0
677#define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
678#define SLOT_STATE_DEFAULT 1
679#define SLOT_STATE_ADDRESSED 2
680#define SLOT_STATE_CONFIGURED 3
681
682/**
683 * struct xhci_ep_ctx
684 * @ep_info: endpoint state, streams, mult, and interval information.
685 * @ep_info2: information on endpoint type, max packet size, max burst size,
686 * error count, and whether the HC will force an event for all
687 * transactions.
688 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
689 * defines one stream, this points to the endpoint transfer ring.
690 * Otherwise, it points to a stream context array, which has a
691 * ring pointer for each flow.
692 * @tx_info:
693 * Average TRB lengths for the endpoint ring and
694 * max payload within an Endpoint Service Interval Time (ESIT).
695 *
696 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
697 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
698 * reserved at the end of the endpoint context for HC internal use.
699 */
700struct xhci_ep_ctx {
701 __le32 ep_info;
702 __le32 ep_info2;
703 __le64 deq;
704 __le32 tx_info;
705 /* offset 0x14 - 0x1f reserved for HC internal use */
706 __le32 reserved[3];
707};
708
709/* ep_info bitmasks */
710/*
711 * Endpoint State - bits 0:2
712 * 0 - disabled
713 * 1 - running
714 * 2 - halted due to halt condition - ok to manipulate endpoint ring
715 * 3 - stopped
716 * 4 - TRB error
717 * 5-7 - reserved
718 */
719#define EP_STATE_MASK (0xf)
720#define EP_STATE_DISABLED 0
721#define EP_STATE_RUNNING 1
722#define EP_STATE_HALTED 2
723#define EP_STATE_STOPPED 3
724#define EP_STATE_ERROR 4
725#define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
726
727/* Mult - Max number of burtst within an interval, in EP companion desc. */
728#define EP_MULT(p) (((p) & 0x3) << 8)
729#define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
730/* bits 10:14 are Max Primary Streams */
731/* bit 15 is Linear Stream Array */
732/* Interval - period between requests to an endpoint - 125u increments. */
733#define EP_INTERVAL(p) (((p) & 0xff) << 16)
734#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
735#define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
736#define EP_MAXPSTREAMS_MASK (0x1f << 10)
737#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
738#define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10)
739/* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
740#define EP_HAS_LSA (1 << 15)
741/* hosts with LEC=1 use bits 31:24 as ESIT high bits. */
742#define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff)
743
744/* ep_info2 bitmasks */
745/*
746 * Force Event - generate transfer events for all TRBs for this endpoint
747 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
748 */
749#define FORCE_EVENT (0x1)
750#define ERROR_COUNT(p) (((p) & 0x3) << 1)
751#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
752#define EP_TYPE(p) ((p) << 3)
753#define ISOC_OUT_EP 1
754#define BULK_OUT_EP 2
755#define INT_OUT_EP 3
756#define CTRL_EP 4
757#define ISOC_IN_EP 5
758#define BULK_IN_EP 6
759#define INT_IN_EP 7
760/* bit 6 reserved */
761/* bit 7 is Host Initiate Disable - for disabling stream selection */
762#define MAX_BURST(p) (((p)&0xff) << 8)
763#define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
764#define MAX_PACKET(p) (((p)&0xffff) << 16)
765#define MAX_PACKET_MASK (0xffff << 16)
766#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
767
768/* tx_info bitmasks */
769#define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff)
770#define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16)
771#define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24)
772#define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
773
774/* deq bitmasks */
775#define EP_CTX_CYCLE_MASK (1 << 0)
776#define SCTX_DEQ_MASK (~0xfL)
777
778
779/**
780 * struct xhci_input_control_context
781 * Input control context; see section 6.2.5.
782 *
783 * @drop_context: set the bit of the endpoint context you want to disable
784 * @add_context: set the bit of the endpoint context you want to enable
785 */
786struct xhci_input_control_ctx {
787 __le32 drop_flags;
788 __le32 add_flags;
789 __le32 rsvd2[6];
790};
791
792#define EP_IS_ADDED(ctrl_ctx, i) \
793 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
794#define EP_IS_DROPPED(ctrl_ctx, i) \
795 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
796
797/* Represents everything that is needed to issue a command on the command ring.
798 * It's useful to pre-allocate these for commands that cannot fail due to
799 * out-of-memory errors, like freeing streams.
800 */
801struct xhci_command {
802 /* Input context for changing device state */
803 struct xhci_container_ctx *in_ctx;
804 u32 status;
805 int slot_id;
806 /* If completion is null, no one is waiting on this command
807 * and the structure can be freed after the command completes.
808 */
809 struct completion *completion;
810 union xhci_trb *command_trb;
811 struct list_head cmd_list;
812};
813
814/* drop context bitmasks */
815#define DROP_EP(x) (0x1 << x)
816/* add context bitmasks */
817#define ADD_EP(x) (0x1 << x)
818
819struct xhci_stream_ctx {
820 /* 64-bit stream ring address, cycle state, and stream type */
821 __le64 stream_ring;
822 /* offset 0x14 - 0x1f reserved for HC internal use */
823 __le32 reserved[2];
824};
825
826/* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
827#define SCT_FOR_CTX(p) (((p) & 0x7) << 1)
828/* Secondary stream array type, dequeue pointer is to a transfer ring */
829#define SCT_SEC_TR 0
830/* Primary stream array type, dequeue pointer is to a transfer ring */
831#define SCT_PRI_TR 1
832/* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
833#define SCT_SSA_8 2
834#define SCT_SSA_16 3
835#define SCT_SSA_32 4
836#define SCT_SSA_64 5
837#define SCT_SSA_128 6
838#define SCT_SSA_256 7
839
840/* Assume no secondary streams for now */
841struct xhci_stream_info {
842 struct xhci_ring **stream_rings;
843 /* Number of streams, including stream 0 (which drivers can't use) */
844 unsigned int num_streams;
845 /* The stream context array may be bigger than
846 * the number of streams the driver asked for
847 */
848 struct xhci_stream_ctx *stream_ctx_array;
849 unsigned int num_stream_ctxs;
850 dma_addr_t ctx_array_dma;
851 /* For mapping physical TRB addresses to segments in stream rings */
852 struct radix_tree_root trb_address_map;
853 struct xhci_command *free_streams_command;
854};
855
856#define SMALL_STREAM_ARRAY_SIZE 256
857#define MEDIUM_STREAM_ARRAY_SIZE 1024
858
859/* Some Intel xHCI host controllers need software to keep track of the bus
860 * bandwidth. Keep track of endpoint info here. Each root port is allocated
861 * the full bus bandwidth. We must also treat TTs (including each port under a
862 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
863 * (DMI) also limits the total bandwidth (across all domains) that can be used.
864 */
865struct xhci_bw_info {
866 /* ep_interval is zero-based */
867 unsigned int ep_interval;
868 /* mult and num_packets are one-based */
869 unsigned int mult;
870 unsigned int num_packets;
871 unsigned int max_packet_size;
872 unsigned int max_esit_payload;
873 unsigned int type;
874};
875
876/* "Block" sizes in bytes the hardware uses for different device speeds.
877 * The logic in this part of the hardware limits the number of bits the hardware
878 * can use, so must represent bandwidth in a less precise manner to mimic what
879 * the scheduler hardware computes.
880 */
881#define FS_BLOCK 1
882#define HS_BLOCK 4
883#define SS_BLOCK 16
884#define DMI_BLOCK 32
885
886/* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
887 * with each byte transferred. SuperSpeed devices have an initial overhead to
888 * set up bursts. These are in blocks, see above. LS overhead has already been
889 * translated into FS blocks.
890 */
891#define DMI_OVERHEAD 8
892#define DMI_OVERHEAD_BURST 4
893#define SS_OVERHEAD 8
894#define SS_OVERHEAD_BURST 32
895#define HS_OVERHEAD 26
896#define FS_OVERHEAD 20
897#define LS_OVERHEAD 128
898/* The TTs need to claim roughly twice as much bandwidth (94 bytes per
899 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
900 * of overhead associated with split transfers crossing microframe boundaries.
901 * 31 blocks is pure protocol overhead.
902 */
903#define TT_HS_OVERHEAD (31 + 94)
904#define TT_DMI_OVERHEAD (25 + 12)
905
906/* Bandwidth limits in blocks */
907#define FS_BW_LIMIT 1285
908#define TT_BW_LIMIT 1320
909#define HS_BW_LIMIT 1607
910#define SS_BW_LIMIT_IN 3906
911#define DMI_BW_LIMIT_IN 3906
912#define SS_BW_LIMIT_OUT 3906
913#define DMI_BW_LIMIT_OUT 3906
914
915/* Percentage of bus bandwidth reserved for non-periodic transfers */
916#define FS_BW_RESERVED 10
917#define HS_BW_RESERVED 20
918#define SS_BW_RESERVED 10
919
920struct xhci_virt_ep {
921 struct xhci_ring *ring;
922 /* Related to endpoints that are configured to use stream IDs only */
923 struct xhci_stream_info *stream_info;
924 /* Temporary storage in case the configure endpoint command fails and we
925 * have to restore the device state to the previous state
926 */
927 struct xhci_ring *new_ring;
928 unsigned int ep_state;
929#define SET_DEQ_PENDING (1 << 0)
930#define EP_HALTED (1 << 1) /* For stall handling */
931#define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */
932/* Transitioning the endpoint to using streams, don't enqueue URBs */
933#define EP_GETTING_STREAMS (1 << 3)
934#define EP_HAS_STREAMS (1 << 4)
935/* Transitioning the endpoint to not using streams, don't enqueue URBs */
936#define EP_GETTING_NO_STREAMS (1 << 5)
937#define EP_HARD_CLEAR_TOGGLE (1 << 6)
938#define EP_SOFT_CLEAR_TOGGLE (1 << 7)
939/* usb_hub_clear_tt_buffer is in progress */
940#define EP_CLEARING_TT (1 << 8)
941 /* ---- Related to URB cancellation ---- */
942 struct list_head cancelled_td_list;
943 /* Watchdog timer for stop endpoint command to cancel URBs */
944 struct timer_list stop_cmd_timer;
945 struct xhci_hcd *xhci;
946 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
947 * command. We'll need to update the ring's dequeue segment and dequeue
948 * pointer after the command completes.
949 */
950 struct xhci_segment *queued_deq_seg;
951 union xhci_trb *queued_deq_ptr;
952 /*
953 * Sometimes the xHC can not process isochronous endpoint ring quickly
954 * enough, and it will miss some isoc tds on the ring and generate
955 * a Missed Service Error Event.
956 * Set skip flag when receive a Missed Service Error Event and
957 * process the missed tds on the endpoint ring.
958 */
959 bool skip;
960 /* Bandwidth checking storage */
961 struct xhci_bw_info bw_info;
962 struct list_head bw_endpoint_list;
963 /* Isoch Frame ID checking storage */
964 int next_frame_id;
965 /* Use new Isoch TRB layout needed for extended TBC support */
966 bool use_extended_tbc;
967};
968
969enum xhci_overhead_type {
970 LS_OVERHEAD_TYPE = 0,
971 FS_OVERHEAD_TYPE,
972 HS_OVERHEAD_TYPE,
973};
974
975struct xhci_interval_bw {
976 unsigned int num_packets;
977 /* Sorted by max packet size.
978 * Head of the list is the greatest max packet size.
979 */
980 struct list_head endpoints;
981 /* How many endpoints of each speed are present. */
982 unsigned int overhead[3];
983};
984
985#define XHCI_MAX_INTERVAL 16
986
987struct xhci_interval_bw_table {
988 unsigned int interval0_esit_payload;
989 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
990 /* Includes reserved bandwidth for async endpoints */
991 unsigned int bw_used;
992 unsigned int ss_bw_in;
993 unsigned int ss_bw_out;
994};
995
996
997struct xhci_virt_device {
998 struct usb_device *udev;
999 /*
1000 * Commands to the hardware are passed an "input context" that
1001 * tells the hardware what to change in its data structures.
1002 * The hardware will return changes in an "output context" that
1003 * software must allocate for the hardware. We need to keep
1004 * track of input and output contexts separately because
1005 * these commands might fail and we don't trust the hardware.
1006 */
1007 struct xhci_container_ctx *out_ctx;
1008 /* Used for addressing devices and configuration changes */
1009 struct xhci_container_ctx *in_ctx;
1010 struct xhci_virt_ep eps[31];
1011 u8 fake_port;
1012 u8 real_port;
1013 struct xhci_interval_bw_table *bw_table;
1014 struct xhci_tt_bw_info *tt_info;
1015 /*
1016 * flags for state tracking based on events and issued commands.
1017 * Software can not rely on states from output contexts because of
1018 * latency between events and xHC updating output context values.
1019 * See xhci 1.1 section 4.8.3 for more details
1020 */
1021 unsigned long flags;
1022#define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */
1023
1024 /* The current max exit latency for the enabled USB3 link states. */
1025 u16 current_mel;
1026 /* Used for the debugfs interfaces. */
1027 void *debugfs_private;
1028};
1029
1030/*
1031 * For each roothub, keep track of the bandwidth information for each periodic
1032 * interval.
1033 *
1034 * If a high speed hub is attached to the roothub, each TT associated with that
1035 * hub is a separate bandwidth domain. The interval information for the
1036 * endpoints on the devices under that TT will appear in the TT structure.
1037 */
1038struct xhci_root_port_bw_info {
1039 struct list_head tts;
1040 unsigned int num_active_tts;
1041 struct xhci_interval_bw_table bw_table;
1042};
1043
1044struct xhci_tt_bw_info {
1045 struct list_head tt_list;
1046 int slot_id;
1047 int ttport;
1048 struct xhci_interval_bw_table bw_table;
1049 int active_eps;
1050};
1051
1052
1053/**
1054 * struct xhci_device_context_array
1055 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
1056 */
1057struct xhci_device_context_array {
1058 /* 64-bit device addresses; we only write 32-bit addresses */
1059 __le64 dev_context_ptrs[MAX_HC_SLOTS];
1060 /* private xHCD pointers */
1061 dma_addr_t dma;
1062};
1063/* TODO: write function to set the 64-bit device DMA address */
1064/*
1065 * TODO: change this to be dynamically sized at HC mem init time since the HC
1066 * might not be able to handle the maximum number of devices possible.
1067 */
1068
1069
1070struct xhci_transfer_event {
1071 /* 64-bit buffer address, or immediate data */
1072 __le64 buffer;
1073 __le32 transfer_len;
1074 /* This field is interpreted differently based on the type of TRB */
1075 __le32 flags;
1076};
1077
1078/* Transfer event TRB length bit mask */
1079/* bits 0:23 */
1080#define EVENT_TRB_LEN(p) ((p) & 0xffffff)
1081
1082/** Transfer Event bit fields **/
1083#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
1084
1085/* Completion Code - only applicable for some types of TRBs */
1086#define COMP_CODE_MASK (0xff << 24)
1087#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
1088#define COMP_INVALID 0
1089#define COMP_SUCCESS 1
1090#define COMP_DATA_BUFFER_ERROR 2
1091#define COMP_BABBLE_DETECTED_ERROR 3
1092#define COMP_USB_TRANSACTION_ERROR 4
1093#define COMP_TRB_ERROR 5
1094#define COMP_STALL_ERROR 6
1095#define COMP_RESOURCE_ERROR 7
1096#define COMP_BANDWIDTH_ERROR 8
1097#define COMP_NO_SLOTS_AVAILABLE_ERROR 9
1098#define COMP_INVALID_STREAM_TYPE_ERROR 10
1099#define COMP_SLOT_NOT_ENABLED_ERROR 11
1100#define COMP_ENDPOINT_NOT_ENABLED_ERROR 12
1101#define COMP_SHORT_PACKET 13
1102#define COMP_RING_UNDERRUN 14
1103#define COMP_RING_OVERRUN 15
1104#define COMP_VF_EVENT_RING_FULL_ERROR 16
1105#define COMP_PARAMETER_ERROR 17
1106#define COMP_BANDWIDTH_OVERRUN_ERROR 18
1107#define COMP_CONTEXT_STATE_ERROR 19
1108#define COMP_NO_PING_RESPONSE_ERROR 20
1109#define COMP_EVENT_RING_FULL_ERROR 21
1110#define COMP_INCOMPATIBLE_DEVICE_ERROR 22
1111#define COMP_MISSED_SERVICE_ERROR 23
1112#define COMP_COMMAND_RING_STOPPED 24
1113#define COMP_COMMAND_ABORTED 25
1114#define COMP_STOPPED 26
1115#define COMP_STOPPED_LENGTH_INVALID 27
1116#define COMP_STOPPED_SHORT_PACKET 28
1117#define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29
1118#define COMP_ISOCH_BUFFER_OVERRUN 31
1119#define COMP_EVENT_LOST_ERROR 32
1120#define COMP_UNDEFINED_ERROR 33
1121#define COMP_INVALID_STREAM_ID_ERROR 34
1122#define COMP_SECONDARY_BANDWIDTH_ERROR 35
1123#define COMP_SPLIT_TRANSACTION_ERROR 36
1124
1125static inline const char *xhci_trb_comp_code_string(u8 status)
1126{
1127 switch (status) {
1128 case COMP_INVALID:
1129 return "Invalid";
1130 case COMP_SUCCESS:
1131 return "Success";
1132 case COMP_DATA_BUFFER_ERROR:
1133 return "Data Buffer Error";
1134 case COMP_BABBLE_DETECTED_ERROR:
1135 return "Babble Detected";
1136 case COMP_USB_TRANSACTION_ERROR:
1137 return "USB Transaction Error";
1138 case COMP_TRB_ERROR:
1139 return "TRB Error";
1140 case COMP_STALL_ERROR:
1141 return "Stall Error";
1142 case COMP_RESOURCE_ERROR:
1143 return "Resource Error";
1144 case COMP_BANDWIDTH_ERROR:
1145 return "Bandwidth Error";
1146 case COMP_NO_SLOTS_AVAILABLE_ERROR:
1147 return "No Slots Available Error";
1148 case COMP_INVALID_STREAM_TYPE_ERROR:
1149 return "Invalid Stream Type Error";
1150 case COMP_SLOT_NOT_ENABLED_ERROR:
1151 return "Slot Not Enabled Error";
1152 case COMP_ENDPOINT_NOT_ENABLED_ERROR:
1153 return "Endpoint Not Enabled Error";
1154 case COMP_SHORT_PACKET:
1155 return "Short Packet";
1156 case COMP_RING_UNDERRUN:
1157 return "Ring Underrun";
1158 case COMP_RING_OVERRUN:
1159 return "Ring Overrun";
1160 case COMP_VF_EVENT_RING_FULL_ERROR:
1161 return "VF Event Ring Full Error";
1162 case COMP_PARAMETER_ERROR:
1163 return "Parameter Error";
1164 case COMP_BANDWIDTH_OVERRUN_ERROR:
1165 return "Bandwidth Overrun Error";
1166 case COMP_CONTEXT_STATE_ERROR:
1167 return "Context State Error";
1168 case COMP_NO_PING_RESPONSE_ERROR:
1169 return "No Ping Response Error";
1170 case COMP_EVENT_RING_FULL_ERROR:
1171 return "Event Ring Full Error";
1172 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1173 return "Incompatible Device Error";
1174 case COMP_MISSED_SERVICE_ERROR:
1175 return "Missed Service Error";
1176 case COMP_COMMAND_RING_STOPPED:
1177 return "Command Ring Stopped";
1178 case COMP_COMMAND_ABORTED:
1179 return "Command Aborted";
1180 case COMP_STOPPED:
1181 return "Stopped";
1182 case COMP_STOPPED_LENGTH_INVALID:
1183 return "Stopped - Length Invalid";
1184 case COMP_STOPPED_SHORT_PACKET:
1185 return "Stopped - Short Packet";
1186 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
1187 return "Max Exit Latency Too Large Error";
1188 case COMP_ISOCH_BUFFER_OVERRUN:
1189 return "Isoch Buffer Overrun";
1190 case COMP_EVENT_LOST_ERROR:
1191 return "Event Lost Error";
1192 case COMP_UNDEFINED_ERROR:
1193 return "Undefined Error";
1194 case COMP_INVALID_STREAM_ID_ERROR:
1195 return "Invalid Stream ID Error";
1196 case COMP_SECONDARY_BANDWIDTH_ERROR:
1197 return "Secondary Bandwidth Error";
1198 case COMP_SPLIT_TRANSACTION_ERROR:
1199 return "Split Transaction Error";
1200 default:
1201 return "Unknown!!";
1202 }
1203}
1204
1205struct xhci_link_trb {
1206 /* 64-bit segment pointer*/
1207 __le64 segment_ptr;
1208 __le32 intr_target;
1209 __le32 control;
1210};
1211
1212/* control bitfields */
1213#define LINK_TOGGLE (0x1<<1)
1214
1215/* Command completion event TRB */
1216struct xhci_event_cmd {
1217 /* Pointer to command TRB, or the value passed by the event data trb */
1218 __le64 cmd_trb;
1219 __le32 status;
1220 __le32 flags;
1221};
1222
1223/* flags bitmasks */
1224
1225/* Address device - disable SetAddress */
1226#define TRB_BSR (1<<9)
1227
1228/* Configure Endpoint - Deconfigure */
1229#define TRB_DC (1<<9)
1230
1231/* Stop Ring - Transfer State Preserve */
1232#define TRB_TSP (1<<9)
1233
1234enum xhci_ep_reset_type {
1235 EP_HARD_RESET,
1236 EP_SOFT_RESET,
1237};
1238
1239/* Force Event */
1240#define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22)
1241#define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16)
1242
1243/* Set Latency Tolerance Value */
1244#define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16)
1245
1246/* Get Port Bandwidth */
1247#define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16)
1248
1249/* Force Header */
1250#define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f)
1251#define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24)
1252
1253enum xhci_setup_dev {
1254 SETUP_CONTEXT_ONLY,
1255 SETUP_CONTEXT_ADDRESS,
1256};
1257
1258/* bits 16:23 are the virtual function ID */
1259/* bits 24:31 are the slot ID */
1260#define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1261#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
1262
1263/* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1264#define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1265#define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1266
1267#define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1268#define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1269#define LAST_EP_INDEX 30
1270
1271/* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */
1272#define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1273#define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1274#define SCT_FOR_TRB(p) (((p) << 1) & 0x7)
1275
1276/* Link TRB specific fields */
1277#define TRB_TC (1<<1)
1278
1279/* Port Status Change Event TRB fields */
1280/* Port ID - bits 31:24 */
1281#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1282
1283#define EVENT_DATA (1 << 2)
1284
1285/* Normal TRB fields */
1286/* transfer_len bitmasks - bits 0:16 */
1287#define TRB_LEN(p) ((p) & 0x1ffff)
1288/* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */
1289#define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
1290#define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17)
1291/* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */
1292#define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17)
1293/* Interrupter Target - which MSI-X vector to target the completion event at */
1294#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1295#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1296/* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */
1297#define TRB_TBC(p) (((p) & 0x3) << 7)
1298#define TRB_TLBPC(p) (((p) & 0xf) << 16)
1299
1300/* Cycle bit - indicates TRB ownership by HC or HCD */
1301#define TRB_CYCLE (1<<0)
1302/*
1303 * Force next event data TRB to be evaluated before task switch.
1304 * Used to pass OS data back after a TD completes.
1305 */
1306#define TRB_ENT (1<<1)
1307/* Interrupt on short packet */
1308#define TRB_ISP (1<<2)
1309/* Set PCIe no snoop attribute */
1310#define TRB_NO_SNOOP (1<<3)
1311/* Chain multiple TRBs into a TD */
1312#define TRB_CHAIN (1<<4)
1313/* Interrupt on completion */
1314#define TRB_IOC (1<<5)
1315/* The buffer pointer contains immediate data */
1316#define TRB_IDT (1<<6)
1317/* TDs smaller than this might use IDT */
1318#define TRB_IDT_MAX_SIZE 8
1319
1320/* Block Event Interrupt */
1321#define TRB_BEI (1<<9)
1322
1323/* Control transfer TRB specific fields */
1324#define TRB_DIR_IN (1<<16)
1325#define TRB_TX_TYPE(p) ((p) << 16)
1326#define TRB_DATA_OUT 2
1327#define TRB_DATA_IN 3
1328
1329/* Isochronous TRB specific fields */
1330#define TRB_SIA (1<<31)
1331#define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
1332
1333struct xhci_generic_trb {
1334 __le32 field[4];
1335};
1336
1337union xhci_trb {
1338 struct xhci_link_trb link;
1339 struct xhci_transfer_event trans_event;
1340 struct xhci_event_cmd event_cmd;
1341 struct xhci_generic_trb generic;
1342};
1343
1344/* TRB bit mask */
1345#define TRB_TYPE_BITMASK (0xfc00)
1346#define TRB_TYPE(p) ((p) << 10)
1347#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1348/* TRB type IDs */
1349/* bulk, interrupt, isoc scatter/gather, and control data stage */
1350#define TRB_NORMAL 1
1351/* setup stage for control transfers */
1352#define TRB_SETUP 2
1353/* data stage for control transfers */
1354#define TRB_DATA 3
1355/* status stage for control transfers */
1356#define TRB_STATUS 4
1357/* isoc transfers */
1358#define TRB_ISOC 5
1359/* TRB for linking ring segments */
1360#define TRB_LINK 6
1361#define TRB_EVENT_DATA 7
1362/* Transfer Ring No-op (not for the command ring) */
1363#define TRB_TR_NOOP 8
1364/* Command TRBs */
1365/* Enable Slot Command */
1366#define TRB_ENABLE_SLOT 9
1367/* Disable Slot Command */
1368#define TRB_DISABLE_SLOT 10
1369/* Address Device Command */
1370#define TRB_ADDR_DEV 11
1371/* Configure Endpoint Command */
1372#define TRB_CONFIG_EP 12
1373/* Evaluate Context Command */
1374#define TRB_EVAL_CONTEXT 13
1375/* Reset Endpoint Command */
1376#define TRB_RESET_EP 14
1377/* Stop Transfer Ring Command */
1378#define TRB_STOP_RING 15
1379/* Set Transfer Ring Dequeue Pointer Command */
1380#define TRB_SET_DEQ 16
1381/* Reset Device Command */
1382#define TRB_RESET_DEV 17
1383/* Force Event Command (opt) */
1384#define TRB_FORCE_EVENT 18
1385/* Negotiate Bandwidth Command (opt) */
1386#define TRB_NEG_BANDWIDTH 19
1387/* Set Latency Tolerance Value Command (opt) */
1388#define TRB_SET_LT 20
1389/* Get port bandwidth Command */
1390#define TRB_GET_BW 21
1391/* Force Header Command - generate a transaction or link management packet */
1392#define TRB_FORCE_HEADER 22
1393/* No-op Command - not for transfer rings */
1394#define TRB_CMD_NOOP 23
1395/* TRB IDs 24-31 reserved */
1396/* Event TRBS */
1397/* Transfer Event */
1398#define TRB_TRANSFER 32
1399/* Command Completion Event */
1400#define TRB_COMPLETION 33
1401/* Port Status Change Event */
1402#define TRB_PORT_STATUS 34
1403/* Bandwidth Request Event (opt) */
1404#define TRB_BANDWIDTH_EVENT 35
1405/* Doorbell Event (opt) */
1406#define TRB_DOORBELL 36
1407/* Host Controller Event */
1408#define TRB_HC_EVENT 37
1409/* Device Notification Event - device sent function wake notification */
1410#define TRB_DEV_NOTE 38
1411/* MFINDEX Wrap Event - microframe counter wrapped */
1412#define TRB_MFINDEX_WRAP 39
1413/* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1414
1415/* Nec vendor-specific command completion event. */
1416#define TRB_NEC_CMD_COMP 48
1417/* Get NEC firmware revision. */
1418#define TRB_NEC_GET_FW 49
1419
1420static inline const char *xhci_trb_type_string(u8 type)
1421{
1422 switch (type) {
1423 case TRB_NORMAL:
1424 return "Normal";
1425 case TRB_SETUP:
1426 return "Setup Stage";
1427 case TRB_DATA:
1428 return "Data Stage";
1429 case TRB_STATUS:
1430 return "Status Stage";
1431 case TRB_ISOC:
1432 return "Isoch";
1433 case TRB_LINK:
1434 return "Link";
1435 case TRB_EVENT_DATA:
1436 return "Event Data";
1437 case TRB_TR_NOOP:
1438 return "No-Op";
1439 case TRB_ENABLE_SLOT:
1440 return "Enable Slot Command";
1441 case TRB_DISABLE_SLOT:
1442 return "Disable Slot Command";
1443 case TRB_ADDR_DEV:
1444 return "Address Device Command";
1445 case TRB_CONFIG_EP:
1446 return "Configure Endpoint Command";
1447 case TRB_EVAL_CONTEXT:
1448 return "Evaluate Context Command";
1449 case TRB_RESET_EP:
1450 return "Reset Endpoint Command";
1451 case TRB_STOP_RING:
1452 return "Stop Ring Command";
1453 case TRB_SET_DEQ:
1454 return "Set TR Dequeue Pointer Command";
1455 case TRB_RESET_DEV:
1456 return "Reset Device Command";
1457 case TRB_FORCE_EVENT:
1458 return "Force Event Command";
1459 case TRB_NEG_BANDWIDTH:
1460 return "Negotiate Bandwidth Command";
1461 case TRB_SET_LT:
1462 return "Set Latency Tolerance Value Command";
1463 case TRB_GET_BW:
1464 return "Get Port Bandwidth Command";
1465 case TRB_FORCE_HEADER:
1466 return "Force Header Command";
1467 case TRB_CMD_NOOP:
1468 return "No-Op Command";
1469 case TRB_TRANSFER:
1470 return "Transfer Event";
1471 case TRB_COMPLETION:
1472 return "Command Completion Event";
1473 case TRB_PORT_STATUS:
1474 return "Port Status Change Event";
1475 case TRB_BANDWIDTH_EVENT:
1476 return "Bandwidth Request Event";
1477 case TRB_DOORBELL:
1478 return "Doorbell Event";
1479 case TRB_HC_EVENT:
1480 return "Host Controller Event";
1481 case TRB_DEV_NOTE:
1482 return "Device Notification Event";
1483 case TRB_MFINDEX_WRAP:
1484 return "MFINDEX Wrap Event";
1485 case TRB_NEC_CMD_COMP:
1486 return "NEC Command Completion Event";
1487 case TRB_NEC_GET_FW:
1488 return "NET Get Firmware Revision Command";
1489 default:
1490 return "UNKNOWN";
1491 }
1492}
1493
1494#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1495/* Above, but for __le32 types -- can avoid work by swapping constants: */
1496#define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1497 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1498#define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1499 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1500
1501#define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1502#define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1503
1504/*
1505 * TRBS_PER_SEGMENT must be a multiple of 4,
1506 * since the command ring is 64-byte aligned.
1507 * It must also be greater than 16.
1508 */
1509#define TRBS_PER_SEGMENT 256
1510/* Allow two commands + a link TRB, along with any reserved command TRBs */
1511#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1512#define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1513#define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1514/* TRB buffer pointers can't cross 64KB boundaries */
1515#define TRB_MAX_BUFF_SHIFT 16
1516#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1517/* How much data is left before the 64KB boundary? */
1518#define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1519 (addr & (TRB_MAX_BUFF_SIZE - 1)))
1520#define MAX_SOFT_RETRY 3
1521
1522struct xhci_segment {
1523 union xhci_trb *trbs;
1524 /* private to HCD */
1525 struct xhci_segment *next;
1526 dma_addr_t dma;
1527 /* Max packet sized bounce buffer for td-fragmant alignment */
1528 dma_addr_t bounce_dma;
1529 void *bounce_buf;
1530 unsigned int bounce_offs;
1531 unsigned int bounce_len;
1532};
1533
1534struct xhci_td {
1535 struct list_head td_list;
1536 struct list_head cancelled_td_list;
1537 struct urb *urb;
1538 struct xhci_segment *start_seg;
1539 union xhci_trb *first_trb;
1540 union xhci_trb *last_trb;
1541 struct xhci_segment *bounce_seg;
1542 /* actual_length of the URB has already been set */
1543 bool urb_length_set;
1544};
1545
1546/* xHCI command default timeout value */
1547#define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ)
1548
1549/* command descriptor */
1550struct xhci_cd {
1551 struct xhci_command *command;
1552 union xhci_trb *cmd_trb;
1553};
1554
1555struct xhci_dequeue_state {
1556 struct xhci_segment *new_deq_seg;
1557 union xhci_trb *new_deq_ptr;
1558 int new_cycle_state;
1559 unsigned int stream_id;
1560};
1561
1562enum xhci_ring_type {
1563 TYPE_CTRL = 0,
1564 TYPE_ISOC,
1565 TYPE_BULK,
1566 TYPE_INTR,
1567 TYPE_STREAM,
1568 TYPE_COMMAND,
1569 TYPE_EVENT,
1570};
1571
1572static inline const char *xhci_ring_type_string(enum xhci_ring_type type)
1573{
1574 switch (type) {
1575 case TYPE_CTRL:
1576 return "CTRL";
1577 case TYPE_ISOC:
1578 return "ISOC";
1579 case TYPE_BULK:
1580 return "BULK";
1581 case TYPE_INTR:
1582 return "INTR";
1583 case TYPE_STREAM:
1584 return "STREAM";
1585 case TYPE_COMMAND:
1586 return "CMD";
1587 case TYPE_EVENT:
1588 return "EVENT";
1589 }
1590
1591 return "UNKNOWN";
1592}
1593
1594struct xhci_ring {
1595 struct xhci_segment *first_seg;
1596 struct xhci_segment *last_seg;
1597 union xhci_trb *enqueue;
1598 struct xhci_segment *enq_seg;
1599 union xhci_trb *dequeue;
1600 struct xhci_segment *deq_seg;
1601 struct list_head td_list;
1602 /*
1603 * Write the cycle state into the TRB cycle field to give ownership of
1604 * the TRB to the host controller (if we are the producer), or to check
1605 * if we own the TRB (if we are the consumer). See section 4.9.1.
1606 */
1607 u32 cycle_state;
1608 unsigned int err_count;
1609 unsigned int stream_id;
1610 unsigned int num_segs;
1611 unsigned int num_trbs_free;
1612 unsigned int num_trbs_free_temp;
1613 unsigned int bounce_buf_len;
1614 enum xhci_ring_type type;
1615 bool last_td_was_short;
1616 struct radix_tree_root *trb_address_map;
1617};
1618
1619struct xhci_erst_entry {
1620 /* 64-bit event ring segment address */
1621 __le64 seg_addr;
1622 __le32 seg_size;
1623 /* Set to zero */
1624 __le32 rsvd;
1625};
1626
1627struct xhci_erst {
1628 struct xhci_erst_entry *entries;
1629 unsigned int num_entries;
1630 /* xhci->event_ring keeps track of segment dma addresses */
1631 dma_addr_t erst_dma_addr;
1632 /* Num entries the ERST can contain */
1633 unsigned int erst_size;
1634};
1635
1636struct xhci_scratchpad {
1637 u64 *sp_array;
1638 dma_addr_t sp_dma;
1639 void **sp_buffers;
1640};
1641
1642struct urb_priv {
1643 int num_tds;
1644 int num_tds_done;
1645 struct xhci_td td[0];
1646};
1647
1648/*
1649 * Each segment table entry is 4*32bits long. 1K seems like an ok size:
1650 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
1651 * meaning 64 ring segments.
1652 * Initial allocated size of the ERST, in number of entries */
1653#define ERST_NUM_SEGS 1
1654/* Initial allocated size of the ERST, in number of entries */
1655#define ERST_SIZE 64
1656/* Initial number of event segment rings allocated */
1657#define ERST_ENTRIES 1
1658/* Poll every 60 seconds */
1659#define POLL_TIMEOUT 60
1660/* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1661#define XHCI_STOP_EP_CMD_TIMEOUT 5
1662/* XXX: Make these module parameters */
1663
1664struct s3_save {
1665 u32 command;
1666 u32 dev_nt;
1667 u64 dcbaa_ptr;
1668 u32 config_reg;
1669 u32 irq_pending;
1670 u32 irq_control;
1671 u32 erst_size;
1672 u64 erst_base;
1673 u64 erst_dequeue;
1674};
1675
1676/* Use for lpm */
1677struct dev_info {
1678 u32 dev_id;
1679 struct list_head list;
1680};
1681
1682struct xhci_bus_state {
1683 unsigned long bus_suspended;
1684 unsigned long next_statechange;
1685
1686 /* Port suspend arrays are indexed by the portnum of the fake roothub */
1687 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1688 u32 port_c_suspend;
1689 u32 suspended_ports;
1690 u32 port_remote_wakeup;
1691 unsigned long resume_done[USB_MAXCHILDREN];
1692 /* which ports have started to resume */
1693 unsigned long resuming_ports;
1694 /* Which ports are waiting on RExit to U0 transition. */
1695 unsigned long rexit_ports;
1696 struct completion rexit_done[USB_MAXCHILDREN];
1697};
1698
1699
1700/*
1701 * It can take up to 20 ms to transition from RExit to U0 on the
1702 * Intel Lynx Point LP xHCI host.
1703 */
1704#define XHCI_MAX_REXIT_TIMEOUT_MS 20
1705
1706struct xhci_port {
1707 __le32 __iomem *addr;
1708 int hw_portnum;
1709 int hcd_portnum;
1710 struct xhci_hub *rhub;
1711};
1712
1713struct xhci_hub {
1714 struct xhci_port **ports;
1715 unsigned int num_ports;
1716 struct usb_hcd *hcd;
1717 /* keep track of bus suspend info */
1718 struct xhci_bus_state bus_state;
1719 /* supported prococol extended capabiliy values */
1720 u8 maj_rev;
1721 u8 min_rev;
1722 u32 *psi; /* array of protocol speed ID entries */
1723 u8 psi_count;
1724 u8 psi_uid_count;
1725};
1726
1727/* There is one xhci_hcd structure per controller */
1728struct xhci_hcd {
1729 struct usb_hcd *main_hcd;
1730 struct usb_hcd *shared_hcd;
1731 /* glue to PCI and HCD framework */
1732 struct xhci_cap_regs __iomem *cap_regs;
1733 struct xhci_op_regs __iomem *op_regs;
1734 struct xhci_run_regs __iomem *run_regs;
1735 struct xhci_doorbell_array __iomem *dba;
1736 /* Our HCD's current interrupter register set */
1737 struct xhci_intr_reg __iomem *ir_set;
1738
1739 /* Cached register copies of read-only HC data */
1740 __u32 hcs_params1;
1741 __u32 hcs_params2;
1742 __u32 hcs_params3;
1743 __u32 hcc_params;
1744 __u32 hcc_params2;
1745
1746 spinlock_t lock;
1747
1748 /* packed release number */
1749 u8 sbrn;
1750 u16 hci_version;
1751 u8 max_slots;
1752 u8 max_interrupters;
1753 u8 max_ports;
1754 u8 isoc_threshold;
1755 /* imod_interval in ns (I * 250ns) */
1756 u32 imod_interval;
1757 int event_ring_max;
1758 /* 4KB min, 128MB max */
1759 int page_size;
1760 /* Valid values are 12 to 20, inclusive */
1761 int page_shift;
1762 /* msi-x vectors */
1763 int msix_count;
1764 /* optional clocks */
1765 struct clk *clk;
1766 struct clk *reg_clk;
1767 /* data structures */
1768 struct xhci_device_context_array *dcbaa;
1769 struct xhci_ring *cmd_ring;
1770 unsigned int cmd_ring_state;
1771#define CMD_RING_STATE_RUNNING (1 << 0)
1772#define CMD_RING_STATE_ABORTED (1 << 1)
1773#define CMD_RING_STATE_STOPPED (1 << 2)
1774 struct list_head cmd_list;
1775 unsigned int cmd_ring_reserved_trbs;
1776 struct delayed_work cmd_timer;
1777 struct completion cmd_ring_stop_completion;
1778 struct xhci_command *current_cmd;
1779 struct xhci_ring *event_ring;
1780 struct xhci_erst erst;
1781 /* Scratchpad */
1782 struct xhci_scratchpad *scratchpad;
1783 /* Store LPM test failed devices' information */
1784 struct list_head lpm_failed_devs;
1785
1786 /* slot enabling and address device helpers */
1787 /* these are not thread safe so use mutex */
1788 struct mutex mutex;
1789 /* For USB 3.0 LPM enable/disable. */
1790 struct xhci_command *lpm_command;
1791 /* Internal mirror of the HW's dcbaa */
1792 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1793 /* For keeping track of bandwidth domains per roothub. */
1794 struct xhci_root_port_bw_info *rh_bw;
1795
1796 /* DMA pools */
1797 struct dma_pool *device_pool;
1798 struct dma_pool *segment_pool;
1799 struct dma_pool *small_streams_pool;
1800 struct dma_pool *medium_streams_pool;
1801
1802 /* Host controller watchdog timer structures */
1803 unsigned int xhc_state;
1804
1805 u32 command;
1806 struct s3_save s3;
1807/* Host controller is dying - not responding to commands. "I'm not dead yet!"
1808 *
1809 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1810 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1811 * that sees this status (other than the timer that set it) should stop touching
1812 * hardware immediately. Interrupt handlers should return immediately when
1813 * they see this status (any time they drop and re-acquire xhci->lock).
1814 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1815 * putting the TD on the canceled list, etc.
1816 *
1817 * There are no reports of xHCI host controllers that display this issue.
1818 */
1819#define XHCI_STATE_DYING (1 << 0)
1820#define XHCI_STATE_HALTED (1 << 1)
1821#define XHCI_STATE_REMOVING (1 << 2)
1822 unsigned long long quirks;
1823#define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
1824#define XHCI_RESET_EP_QUIRK BIT_ULL(1)
1825#define XHCI_NEC_HOST BIT_ULL(2)
1826#define XHCI_AMD_PLL_FIX BIT_ULL(3)
1827#define XHCI_SPURIOUS_SUCCESS BIT_ULL(4)
1828/*
1829 * Certain Intel host controllers have a limit to the number of endpoint
1830 * contexts they can handle. Ideally, they would signal that they can't handle
1831 * anymore endpoint contexts by returning a Resource Error for the Configure
1832 * Endpoint command, but they don't. Instead they expect software to keep track
1833 * of the number of active endpoints for them, across configure endpoint
1834 * commands, reset device commands, disable slot commands, and address device
1835 * commands.
1836 */
1837#define XHCI_EP_LIMIT_QUIRK BIT_ULL(5)
1838#define XHCI_BROKEN_MSI BIT_ULL(6)
1839#define XHCI_RESET_ON_RESUME BIT_ULL(7)
1840#define XHCI_SW_BW_CHECKING BIT_ULL(8)
1841#define XHCI_AMD_0x96_HOST BIT_ULL(9)
1842#define XHCI_TRUST_TX_LENGTH BIT_ULL(10)
1843#define XHCI_LPM_SUPPORT BIT_ULL(11)
1844#define XHCI_INTEL_HOST BIT_ULL(12)
1845#define XHCI_SPURIOUS_REBOOT BIT_ULL(13)
1846#define XHCI_COMP_MODE_QUIRK BIT_ULL(14)
1847#define XHCI_AVOID_BEI BIT_ULL(15)
1848#define XHCI_PLAT BIT_ULL(16)
1849#define XHCI_SLOW_SUSPEND BIT_ULL(17)
1850#define XHCI_SPURIOUS_WAKEUP BIT_ULL(18)
1851/* For controllers with a broken beyond repair streams implementation */
1852#define XHCI_BROKEN_STREAMS BIT_ULL(19)
1853#define XHCI_PME_STUCK_QUIRK BIT_ULL(20)
1854#define XHCI_MTK_HOST BIT_ULL(21)
1855#define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
1856#define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
1857#define XHCI_MISSING_CAS BIT_ULL(24)
1858/* For controller with a broken Port Disable implementation */
1859#define XHCI_BROKEN_PORT_PED BIT_ULL(25)
1860#define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
1861#define XHCI_U2_DISABLE_WAKE BIT_ULL(27)
1862#define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28)
1863#define XHCI_HW_LPM_DISABLE BIT_ULL(29)
1864#define XHCI_SUSPEND_DELAY BIT_ULL(30)
1865#define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
1866#define XHCI_ZERO_64B_REGS BIT_ULL(32)
1867#define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33)
1868#define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
1869#define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
1870
1871 unsigned int num_active_eps;
1872 unsigned int limit_active_eps;
1873 struct xhci_port *hw_ports;
1874 struct xhci_hub usb2_rhub;
1875 struct xhci_hub usb3_rhub;
1876 /* support xHCI 1.0 spec USB2 hardware LPM */
1877 unsigned hw_lpm_support:1;
1878 /* Broken Suspend flag for SNPS Suspend resume issue */
1879 unsigned broken_suspend:1;
1880 /* cached usb2 extened protocol capabilites */
1881 u32 *ext_caps;
1882 unsigned int num_ext_caps;
1883 /* Compliance Mode Recovery Data */
1884 struct timer_list comp_mode_recovery_timer;
1885 u32 port_status_u0;
1886 u16 test_mode;
1887/* Compliance Mode Timer Triggered every 2 seconds */
1888#define COMP_MODE_RCVRY_MSECS 2000
1889
1890 struct dentry *debugfs_root;
1891 struct dentry *debugfs_slots;
1892 struct list_head regset_list;
1893
1894 void *dbc;
1895 /* platform-specific data -- must come last */
1896 unsigned long priv[0] __aligned(sizeof(s64));
1897};
1898
1899/* Platform specific overrides to generic XHCI hc_driver ops */
1900struct xhci_driver_overrides {
1901 size_t extra_priv_size;
1902 int (*reset)(struct usb_hcd *hcd);
1903 int (*start)(struct usb_hcd *hcd);
1904};
1905
1906#define XHCI_CFC_DELAY 10
1907
1908/* convert between an HCD pointer and the corresponding EHCI_HCD */
1909static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1910{
1911 struct usb_hcd *primary_hcd;
1912
1913 if (usb_hcd_is_primary_hcd(hcd))
1914 primary_hcd = hcd;
1915 else
1916 primary_hcd = hcd->primary_hcd;
1917
1918 return (struct xhci_hcd *) (primary_hcd->hcd_priv);
1919}
1920
1921static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1922{
1923 return xhci->main_hcd;
1924}
1925
1926#define xhci_dbg(xhci, fmt, args...) \
1927 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1928#define xhci_err(xhci, fmt, args...) \
1929 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1930#define xhci_warn(xhci, fmt, args...) \
1931 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1932#define xhci_warn_ratelimited(xhci, fmt, args...) \
1933 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1934#define xhci_info(xhci, fmt, args...) \
1935 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1936
1937/*
1938 * Registers should always be accessed with double word or quad word accesses.
1939 *
1940 * Some xHCI implementations may support 64-bit address pointers. Registers
1941 * with 64-bit address pointers should be written to with dword accesses by
1942 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1943 * xHCI implementations that do not support 64-bit address pointers will ignore
1944 * the high dword, and write order is irrelevant.
1945 */
1946static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1947 __le64 __iomem *regs)
1948{
1949 return lo_hi_readq(regs);
1950}
1951static inline void xhci_write_64(struct xhci_hcd *xhci,
1952 const u64 val, __le64 __iomem *regs)
1953{
1954 lo_hi_writeq(val, regs);
1955}
1956
1957static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1958{
1959 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
1960}
1961
1962/* xHCI debugging */
1963char *xhci_get_slot_state(struct xhci_hcd *xhci,
1964 struct xhci_container_ctx *ctx);
1965void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
1966 const char *fmt, ...);
1967
1968/* xHCI memory management */
1969void xhci_mem_cleanup(struct xhci_hcd *xhci);
1970int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1971void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1972int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1973int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1974void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1975 struct usb_device *udev);
1976unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1977unsigned int xhci_get_endpoint_address(unsigned int ep_index);
1978unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1979void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1980void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1981 struct xhci_virt_device *virt_dev,
1982 int old_active_eps);
1983void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1984void xhci_update_bw_info(struct xhci_hcd *xhci,
1985 struct xhci_container_ctx *in_ctx,
1986 struct xhci_input_control_ctx *ctrl_ctx,
1987 struct xhci_virt_device *virt_dev);
1988void xhci_endpoint_copy(struct xhci_hcd *xhci,
1989 struct xhci_container_ctx *in_ctx,
1990 struct xhci_container_ctx *out_ctx,
1991 unsigned int ep_index);
1992void xhci_slot_copy(struct xhci_hcd *xhci,
1993 struct xhci_container_ctx *in_ctx,
1994 struct xhci_container_ctx *out_ctx);
1995int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1996 struct usb_device *udev, struct usb_host_endpoint *ep,
1997 gfp_t mem_flags);
1998struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
1999 unsigned int num_segs, unsigned int cycle_state,
2000 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags);
2001void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
2002int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
2003 unsigned int num_trbs, gfp_t flags);
2004int xhci_alloc_erst(struct xhci_hcd *xhci,
2005 struct xhci_ring *evt_ring,
2006 struct xhci_erst *erst,
2007 gfp_t flags);
2008void xhci_free_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
2009void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
2010 struct xhci_virt_device *virt_dev,
2011 unsigned int ep_index);
2012struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
2013 unsigned int num_stream_ctxs,
2014 unsigned int num_streams,
2015 unsigned int max_packet, gfp_t flags);
2016void xhci_free_stream_info(struct xhci_hcd *xhci,
2017 struct xhci_stream_info *stream_info);
2018void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
2019 struct xhci_ep_ctx *ep_ctx,
2020 struct xhci_stream_info *stream_info);
2021void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
2022 struct xhci_virt_ep *ep);
2023void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
2024 struct xhci_virt_device *virt_dev, bool drop_control_ep);
2025struct xhci_ring *xhci_dma_to_transfer_ring(
2026 struct xhci_virt_ep *ep,
2027 u64 address);
2028struct xhci_ring *xhci_stream_id_to_ring(
2029 struct xhci_virt_device *dev,
2030 unsigned int ep_index,
2031 unsigned int stream_id);
2032struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
2033 bool allocate_completion, gfp_t mem_flags);
2034struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
2035 bool allocate_completion, gfp_t mem_flags);
2036void xhci_urb_free_priv(struct urb_priv *urb_priv);
2037void xhci_free_command(struct xhci_hcd *xhci,
2038 struct xhci_command *command);
2039struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
2040 int type, gfp_t flags);
2041void xhci_free_container_ctx(struct xhci_hcd *xhci,
2042 struct xhci_container_ctx *ctx);
2043
2044/* xHCI host controller glue */
2045typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
2046int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec);
2047void xhci_quiesce(struct xhci_hcd *xhci);
2048int xhci_halt(struct xhci_hcd *xhci);
2049int xhci_start(struct xhci_hcd *xhci);
2050int xhci_reset(struct xhci_hcd *xhci);
2051int xhci_run(struct usb_hcd *hcd);
2052int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
2053void xhci_init_driver(struct hc_driver *drv,
2054 const struct xhci_driver_overrides *over);
2055int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id);
2056int xhci_ext_cap_init(struct xhci_hcd *xhci);
2057
2058int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
2059int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
2060
2061irqreturn_t xhci_irq(struct usb_hcd *hcd);
2062irqreturn_t xhci_msi_irq(int irq, void *hcd);
2063int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
2064int xhci_alloc_tt_info(struct xhci_hcd *xhci,
2065 struct xhci_virt_device *virt_dev,
2066 struct usb_device *hdev,
2067 struct usb_tt *tt, gfp_t mem_flags);
2068
2069/* xHCI ring, segment, TRB, and TD functions */
2070dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
2071struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
2072 struct xhci_segment *start_seg, union xhci_trb *start_trb,
2073 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug);
2074int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
2075void xhci_ring_cmd_db(struct xhci_hcd *xhci);
2076int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
2077 u32 trb_type, u32 slot_id);
2078int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2079 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev);
2080int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
2081 u32 field1, u32 field2, u32 field3, u32 field4);
2082int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
2083 int slot_id, unsigned int ep_index, int suspend);
2084int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2085 int slot_id, unsigned int ep_index);
2086int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2087 int slot_id, unsigned int ep_index);
2088int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2089 int slot_id, unsigned int ep_index);
2090int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
2091 struct urb *urb, int slot_id, unsigned int ep_index);
2092int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
2093 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id,
2094 bool command_must_succeed);
2095int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
2096 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed);
2097int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
2098 int slot_id, unsigned int ep_index,
2099 enum xhci_ep_reset_type reset_type);
2100int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2101 u32 slot_id);
2102void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
2103 unsigned int slot_id, unsigned int ep_index,
2104 unsigned int stream_id, struct xhci_td *cur_td,
2105 struct xhci_dequeue_state *state);
2106void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
2107 unsigned int slot_id, unsigned int ep_index,
2108 struct xhci_dequeue_state *deq_state);
2109void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int ep_index,
2110 unsigned int stream_id, struct xhci_td *td);
2111void xhci_stop_endpoint_command_watchdog(struct timer_list *t);
2112void xhci_handle_command_timeout(struct work_struct *work);
2113
2114void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
2115 unsigned int ep_index, unsigned int stream_id);
2116void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
2117 unsigned int slot_id,
2118 unsigned int ep_index);
2119void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
2120void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring);
2121unsigned int count_trbs(u64 addr, u64 len);
2122
2123/* xHCI roothub code */
2124void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
2125 u32 link_state);
2126void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
2127 u32 port_bit);
2128int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
2129 char *buf, u16 wLength);
2130int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
2131int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
2132struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd);
2133
2134void xhci_hc_died(struct xhci_hcd *xhci);
2135
2136#ifdef CONFIG_PM
2137int xhci_bus_suspend(struct usb_hcd *hcd);
2138int xhci_bus_resume(struct usb_hcd *hcd);
2139unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd);
2140#else
2141#define xhci_bus_suspend NULL
2142#define xhci_bus_resume NULL
2143#define xhci_get_resuming_ports NULL
2144#endif /* CONFIG_PM */
2145
2146u32 xhci_port_state_to_neutral(u32 state);
2147int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
2148 u16 port);
2149void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
2150
2151/* xHCI contexts */
2152struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
2153struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
2154struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
2155
2156struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
2157 unsigned int slot_id, unsigned int ep_index,
2158 unsigned int stream_id);
2159
2160static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
2161 struct urb *urb)
2162{
2163 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
2164 xhci_get_endpoint_index(&urb->ep->desc),
2165 urb->stream_id);
2166}
2167
2168/*
2169 * TODO: As per spec Isochronous IDT transmissions are supported. We bypass
2170 * them anyways as we where unable to find a device that matches the
2171 * constraints.
2172 */
2173static inline bool xhci_urb_suitable_for_idt(struct urb *urb)
2174{
2175 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) &&
2176 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE &&
2177 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE &&
2178 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) &&
2179 !urb->num_sgs)
2180 return true;
2181
2182 return false;
2183}
2184
2185static inline char *xhci_slot_state_string(u32 state)
2186{
2187 switch (state) {
2188 case SLOT_STATE_ENABLED:
2189 return "enabled/disabled";
2190 case SLOT_STATE_DEFAULT:
2191 return "default";
2192 case SLOT_STATE_ADDRESSED:
2193 return "addressed";
2194 case SLOT_STATE_CONFIGURED:
2195 return "configured";
2196 default:
2197 return "reserved";
2198 }
2199}
2200
2201static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2,
2202 u32 field3)
2203{
2204 static char str[256];
2205 int type = TRB_FIELD_TO_TYPE(field3);
2206
2207 switch (type) {
2208 case TRB_LINK:
2209 sprintf(str,
2210 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c",
2211 field1, field0, GET_INTR_TARGET(field2),
2212 xhci_trb_type_string(type),
2213 field3 & TRB_IOC ? 'I' : 'i',
2214 field3 & TRB_CHAIN ? 'C' : 'c',
2215 field3 & TRB_TC ? 'T' : 't',
2216 field3 & TRB_CYCLE ? 'C' : 'c');
2217 break;
2218 case TRB_TRANSFER:
2219 case TRB_COMPLETION:
2220 case TRB_PORT_STATUS:
2221 case TRB_BANDWIDTH_EVENT:
2222 case TRB_DOORBELL:
2223 case TRB_HC_EVENT:
2224 case TRB_DEV_NOTE:
2225 case TRB_MFINDEX_WRAP:
2226 sprintf(str,
2227 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c",
2228 field1, field0,
2229 xhci_trb_comp_code_string(GET_COMP_CODE(field2)),
2230 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3),
2231 /* Macro decrements 1, maybe it shouldn't?!? */
2232 TRB_TO_EP_INDEX(field3) + 1,
2233 xhci_trb_type_string(type),
2234 field3 & EVENT_DATA ? 'E' : 'e',
2235 field3 & TRB_CYCLE ? 'C' : 'c');
2236
2237 break;
2238 case TRB_SETUP:
2239 sprintf(str, "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c",
2240 field0 & 0xff,
2241 (field0 & 0xff00) >> 8,
2242 (field0 & 0xff000000) >> 24,
2243 (field0 & 0xff0000) >> 16,
2244 (field1 & 0xff00) >> 8,
2245 field1 & 0xff,
2246 (field1 & 0xff000000) >> 16 |
2247 (field1 & 0xff0000) >> 16,
2248 TRB_LEN(field2), GET_TD_SIZE(field2),
2249 GET_INTR_TARGET(field2),
2250 xhci_trb_type_string(type),
2251 field3 & TRB_IDT ? 'I' : 'i',
2252 field3 & TRB_IOC ? 'I' : 'i',
2253 field3 & TRB_CYCLE ? 'C' : 'c');
2254 break;
2255 case TRB_DATA:
2256 sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c",
2257 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2258 GET_INTR_TARGET(field2),
2259 xhci_trb_type_string(type),
2260 field3 & TRB_IDT ? 'I' : 'i',
2261 field3 & TRB_IOC ? 'I' : 'i',
2262 field3 & TRB_CHAIN ? 'C' : 'c',
2263 field3 & TRB_NO_SNOOP ? 'S' : 's',
2264 field3 & TRB_ISP ? 'I' : 'i',
2265 field3 & TRB_ENT ? 'E' : 'e',
2266 field3 & TRB_CYCLE ? 'C' : 'c');
2267 break;
2268 case TRB_STATUS:
2269 sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c",
2270 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2271 GET_INTR_TARGET(field2),
2272 xhci_trb_type_string(type),
2273 field3 & TRB_IOC ? 'I' : 'i',
2274 field3 & TRB_CHAIN ? 'C' : 'c',
2275 field3 & TRB_ENT ? 'E' : 'e',
2276 field3 & TRB_CYCLE ? 'C' : 'c');
2277 break;
2278 case TRB_NORMAL:
2279 case TRB_ISOC:
2280 case TRB_EVENT_DATA:
2281 case TRB_TR_NOOP:
2282 sprintf(str,
2283 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c",
2284 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2285 GET_INTR_TARGET(field2),
2286 xhci_trb_type_string(type),
2287 field3 & TRB_BEI ? 'B' : 'b',
2288 field3 & TRB_IDT ? 'I' : 'i',
2289 field3 & TRB_IOC ? 'I' : 'i',
2290 field3 & TRB_CHAIN ? 'C' : 'c',
2291 field3 & TRB_NO_SNOOP ? 'S' : 's',
2292 field3 & TRB_ISP ? 'I' : 'i',
2293 field3 & TRB_ENT ? 'E' : 'e',
2294 field3 & TRB_CYCLE ? 'C' : 'c');
2295 break;
2296
2297 case TRB_CMD_NOOP:
2298 case TRB_ENABLE_SLOT:
2299 sprintf(str,
2300 "%s: flags %c",
2301 xhci_trb_type_string(type),
2302 field3 & TRB_CYCLE ? 'C' : 'c');
2303 break;
2304 case TRB_DISABLE_SLOT:
2305 case TRB_NEG_BANDWIDTH:
2306 sprintf(str,
2307 "%s: slot %d flags %c",
2308 xhci_trb_type_string(type),
2309 TRB_TO_SLOT_ID(field3),
2310 field3 & TRB_CYCLE ? 'C' : 'c');
2311 break;
2312 case TRB_ADDR_DEV:
2313 sprintf(str,
2314 "%s: ctx %08x%08x slot %d flags %c:%c",
2315 xhci_trb_type_string(type),
2316 field1, field0,
2317 TRB_TO_SLOT_ID(field3),
2318 field3 & TRB_BSR ? 'B' : 'b',
2319 field3 & TRB_CYCLE ? 'C' : 'c');
2320 break;
2321 case TRB_CONFIG_EP:
2322 sprintf(str,
2323 "%s: ctx %08x%08x slot %d flags %c:%c",
2324 xhci_trb_type_string(type),
2325 field1, field0,
2326 TRB_TO_SLOT_ID(field3),
2327 field3 & TRB_DC ? 'D' : 'd',
2328 field3 & TRB_CYCLE ? 'C' : 'c');
2329 break;
2330 case TRB_EVAL_CONTEXT:
2331 sprintf(str,
2332 "%s: ctx %08x%08x slot %d flags %c",
2333 xhci_trb_type_string(type),
2334 field1, field0,
2335 TRB_TO_SLOT_ID(field3),
2336 field3 & TRB_CYCLE ? 'C' : 'c');
2337 break;
2338 case TRB_RESET_EP:
2339 sprintf(str,
2340 "%s: ctx %08x%08x slot %d ep %d flags %c:%c",
2341 xhci_trb_type_string(type),
2342 field1, field0,
2343 TRB_TO_SLOT_ID(field3),
2344 /* Macro decrements 1, maybe it shouldn't?!? */
2345 TRB_TO_EP_INDEX(field3) + 1,
2346 field3 & TRB_TSP ? 'T' : 't',
2347 field3 & TRB_CYCLE ? 'C' : 'c');
2348 break;
2349 case TRB_STOP_RING:
2350 sprintf(str,
2351 "%s: slot %d sp %d ep %d flags %c",
2352 xhci_trb_type_string(type),
2353 TRB_TO_SLOT_ID(field3),
2354 TRB_TO_SUSPEND_PORT(field3),
2355 /* Macro decrements 1, maybe it shouldn't?!? */
2356 TRB_TO_EP_INDEX(field3) + 1,
2357 field3 & TRB_CYCLE ? 'C' : 'c');
2358 break;
2359 case TRB_SET_DEQ:
2360 sprintf(str,
2361 "%s: deq %08x%08x stream %d slot %d ep %d flags %c",
2362 xhci_trb_type_string(type),
2363 field1, field0,
2364 TRB_TO_STREAM_ID(field2),
2365 TRB_TO_SLOT_ID(field3),
2366 /* Macro decrements 1, maybe it shouldn't?!? */
2367 TRB_TO_EP_INDEX(field3) + 1,
2368 field3 & TRB_CYCLE ? 'C' : 'c');
2369 break;
2370 case TRB_RESET_DEV:
2371 sprintf(str,
2372 "%s: slot %d flags %c",
2373 xhci_trb_type_string(type),
2374 TRB_TO_SLOT_ID(field3),
2375 field3 & TRB_CYCLE ? 'C' : 'c');
2376 break;
2377 case TRB_FORCE_EVENT:
2378 sprintf(str,
2379 "%s: event %08x%08x vf intr %d vf id %d flags %c",
2380 xhci_trb_type_string(type),
2381 field1, field0,
2382 TRB_TO_VF_INTR_TARGET(field2),
2383 TRB_TO_VF_ID(field3),
2384 field3 & TRB_CYCLE ? 'C' : 'c');
2385 break;
2386 case TRB_SET_LT:
2387 sprintf(str,
2388 "%s: belt %d flags %c",
2389 xhci_trb_type_string(type),
2390 TRB_TO_BELT(field3),
2391 field3 & TRB_CYCLE ? 'C' : 'c');
2392 break;
2393 case TRB_GET_BW:
2394 sprintf(str,
2395 "%s: ctx %08x%08x slot %d speed %d flags %c",
2396 xhci_trb_type_string(type),
2397 field1, field0,
2398 TRB_TO_SLOT_ID(field3),
2399 TRB_TO_DEV_SPEED(field3),
2400 field3 & TRB_CYCLE ? 'C' : 'c');
2401 break;
2402 case TRB_FORCE_HEADER:
2403 sprintf(str,
2404 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c",
2405 xhci_trb_type_string(type),
2406 field2, field1, field0 & 0xffffffe0,
2407 TRB_TO_PACKET_TYPE(field0),
2408 TRB_TO_ROOTHUB_PORT(field3),
2409 field3 & TRB_CYCLE ? 'C' : 'c');
2410 break;
2411 default:
2412 sprintf(str,
2413 "type '%s' -> raw %08x %08x %08x %08x",
2414 xhci_trb_type_string(type),
2415 field0, field1, field2, field3);
2416 }
2417
2418 return str;
2419}
2420
2421static inline const char *xhci_decode_ctrl_ctx(unsigned long drop,
2422 unsigned long add)
2423{
2424 static char str[1024];
2425 unsigned int bit;
2426 int ret = 0;
2427
2428 if (drop) {
2429 ret = sprintf(str, "Drop:");
2430 for_each_set_bit(bit, &drop, 32)
2431 ret += sprintf(str + ret, " %d%s",
2432 bit / 2,
2433 bit % 2 ? "in":"out");
2434 ret += sprintf(str + ret, ", ");
2435 }
2436
2437 if (add) {
2438 ret += sprintf(str + ret, "Add:%s%s",
2439 (add & SLOT_FLAG) ? " slot":"",
2440 (add & EP0_FLAG) ? " ep0":"");
2441 add &= ~(SLOT_FLAG | EP0_FLAG);
2442 for_each_set_bit(bit, &add, 32)
2443 ret += sprintf(str + ret, " %d%s",
2444 bit / 2,
2445 bit % 2 ? "in":"out");
2446 }
2447 return str;
2448}
2449
2450static inline const char *xhci_decode_slot_context(u32 info, u32 info2,
2451 u32 tt_info, u32 state)
2452{
2453 static char str[1024];
2454 u32 speed;
2455 u32 hub;
2456 u32 mtt;
2457 int ret = 0;
2458
2459 speed = info & DEV_SPEED;
2460 hub = info & DEV_HUB;
2461 mtt = info & DEV_MTT;
2462
2463 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d",
2464 info & ROUTE_STRING_MASK,
2465 ({ char *s;
2466 switch (speed) {
2467 case SLOT_SPEED_FS:
2468 s = "full-speed";
2469 break;
2470 case SLOT_SPEED_LS:
2471 s = "low-speed";
2472 break;
2473 case SLOT_SPEED_HS:
2474 s = "high-speed";
2475 break;
2476 case SLOT_SPEED_SS:
2477 s = "super-speed";
2478 break;
2479 case SLOT_SPEED_SSP:
2480 s = "super-speed plus";
2481 break;
2482 default:
2483 s = "UNKNOWN speed";
2484 } s; }),
2485 mtt ? " multi-TT" : "",
2486 hub ? " Hub" : "",
2487 (info & LAST_CTX_MASK) >> 27,
2488 info2 & MAX_EXIT,
2489 DEVINFO_TO_ROOT_HUB_PORT(info2),
2490 DEVINFO_TO_MAX_PORTS(info2));
2491
2492 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s",
2493 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8,
2494 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info),
2495 state & DEV_ADDR_MASK,
2496 xhci_slot_state_string(GET_SLOT_STATE(state)));
2497
2498 return str;
2499}
2500
2501
2502static inline const char *xhci_portsc_link_state_string(u32 portsc)
2503{
2504 switch (portsc & PORT_PLS_MASK) {
2505 case XDEV_U0:
2506 return "U0";
2507 case XDEV_U1:
2508 return "U1";
2509 case XDEV_U2:
2510 return "U2";
2511 case XDEV_U3:
2512 return "U3";
2513 case XDEV_DISABLED:
2514 return "Disabled";
2515 case XDEV_RXDETECT:
2516 return "RxDetect";
2517 case XDEV_INACTIVE:
2518 return "Inactive";
2519 case XDEV_POLLING:
2520 return "Polling";
2521 case XDEV_RECOVERY:
2522 return "Recovery";
2523 case XDEV_HOT_RESET:
2524 return "Hot Reset";
2525 case XDEV_COMP_MODE:
2526 return "Compliance mode";
2527 case XDEV_TEST_MODE:
2528 return "Test mode";
2529 case XDEV_RESUME:
2530 return "Resume";
2531 default:
2532 break;
2533 }
2534 return "Unknown";
2535}
2536
2537static inline const char *xhci_decode_portsc(u32 portsc)
2538{
2539 static char str[256];
2540 int ret;
2541
2542 ret = sprintf(str, "%s %s %s Link:%s PortSpeed:%d ",
2543 portsc & PORT_POWER ? "Powered" : "Powered-off",
2544 portsc & PORT_CONNECT ? "Connected" : "Not-connected",
2545 portsc & PORT_PE ? "Enabled" : "Disabled",
2546 xhci_portsc_link_state_string(portsc),
2547 DEV_PORT_SPEED(portsc));
2548
2549 if (portsc & PORT_OC)
2550 ret += sprintf(str + ret, "OverCurrent ");
2551 if (portsc & PORT_RESET)
2552 ret += sprintf(str + ret, "In-Reset ");
2553
2554 ret += sprintf(str + ret, "Change: ");
2555 if (portsc & PORT_CSC)
2556 ret += sprintf(str + ret, "CSC ");
2557 if (portsc & PORT_PEC)
2558 ret += sprintf(str + ret, "PEC ");
2559 if (portsc & PORT_WRC)
2560 ret += sprintf(str + ret, "WRC ");
2561 if (portsc & PORT_OCC)
2562 ret += sprintf(str + ret, "OCC ");
2563 if (portsc & PORT_RC)
2564 ret += sprintf(str + ret, "PRC ");
2565 if (portsc & PORT_PLC)
2566 ret += sprintf(str + ret, "PLC ");
2567 if (portsc & PORT_CEC)
2568 ret += sprintf(str + ret, "CEC ");
2569 if (portsc & PORT_CAS)
2570 ret += sprintf(str + ret, "CAS ");
2571
2572 ret += sprintf(str + ret, "Wake: ");
2573 if (portsc & PORT_WKCONN_E)
2574 ret += sprintf(str + ret, "WCE ");
2575 if (portsc & PORT_WKDISC_E)
2576 ret += sprintf(str + ret, "WDE ");
2577 if (portsc & PORT_WKOC_E)
2578 ret += sprintf(str + ret, "WOE ");
2579
2580 return str;
2581}
2582
2583static inline const char *xhci_ep_state_string(u8 state)
2584{
2585 switch (state) {
2586 case EP_STATE_DISABLED:
2587 return "disabled";
2588 case EP_STATE_RUNNING:
2589 return "running";
2590 case EP_STATE_HALTED:
2591 return "halted";
2592 case EP_STATE_STOPPED:
2593 return "stopped";
2594 case EP_STATE_ERROR:
2595 return "error";
2596 default:
2597 return "INVALID";
2598 }
2599}
2600
2601static inline const char *xhci_ep_type_string(u8 type)
2602{
2603 switch (type) {
2604 case ISOC_OUT_EP:
2605 return "Isoc OUT";
2606 case BULK_OUT_EP:
2607 return "Bulk OUT";
2608 case INT_OUT_EP:
2609 return "Int OUT";
2610 case CTRL_EP:
2611 return "Ctrl";
2612 case ISOC_IN_EP:
2613 return "Isoc IN";
2614 case BULK_IN_EP:
2615 return "Bulk IN";
2616 case INT_IN_EP:
2617 return "Int IN";
2618 default:
2619 return "INVALID";
2620 }
2621}
2622
2623static inline const char *xhci_decode_ep_context(u32 info, u32 info2, u64 deq,
2624 u32 tx_info)
2625{
2626 static char str[1024];
2627 int ret;
2628
2629 u32 esit;
2630 u16 maxp;
2631 u16 avg;
2632
2633 u8 max_pstr;
2634 u8 ep_state;
2635 u8 interval;
2636 u8 ep_type;
2637 u8 burst;
2638 u8 cerr;
2639 u8 mult;
2640
2641 bool lsa;
2642 bool hid;
2643
2644 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 |
2645 CTX_TO_MAX_ESIT_PAYLOAD(tx_info);
2646
2647 ep_state = info & EP_STATE_MASK;
2648 max_pstr = CTX_TO_EP_MAXPSTREAMS(info);
2649 interval = CTX_TO_EP_INTERVAL(info);
2650 mult = CTX_TO_EP_MULT(info) + 1;
2651 lsa = !!(info & EP_HAS_LSA);
2652
2653 cerr = (info2 & (3 << 1)) >> 1;
2654 ep_type = CTX_TO_EP_TYPE(info2);
2655 hid = !!(info2 & (1 << 7));
2656 burst = CTX_TO_MAX_BURST(info2);
2657 maxp = MAX_PACKET_DECODED(info2);
2658
2659 avg = EP_AVG_TRB_LENGTH(tx_info);
2660
2661 ret = sprintf(str, "State %s mult %d max P. Streams %d %s",
2662 xhci_ep_state_string(ep_state), mult,
2663 max_pstr, lsa ? "LSA " : "");
2664
2665 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ",
2666 (1 << interval) * 125, esit, cerr);
2667
2668 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ",
2669 xhci_ep_type_string(ep_type), hid ? "HID" : "",
2670 burst, maxp, deq);
2671
2672 ret += sprintf(str + ret, "avg trb len %d", avg);
2673
2674 return str;
2675}
2676
2677#endif /* __LINUX_XHCI_HCD_H */
1/* SPDX-License-Identifier: GPL-2.0 */
2
3/*
4 * xHCI host controller driver
5 *
6 * Copyright (C) 2008 Intel Corp.
7 *
8 * Author: Sarah Sharp
9 * Some code borrowed from the Linux EHCI driver.
10 */
11
12#ifndef __LINUX_XHCI_HCD_H
13#define __LINUX_XHCI_HCD_H
14
15#include <linux/usb.h>
16#include <linux/timer.h>
17#include <linux/kernel.h>
18#include <linux/usb/hcd.h>
19#include <linux/io-64-nonatomic-lo-hi.h>
20
21/* Code sharing between pci-quirks and xhci hcd */
22#include "xhci-ext-caps.h"
23#include "pci-quirks.h"
24
25#include "xhci-port.h"
26#include "xhci-caps.h"
27
28/* max buffer size for trace and debug messages */
29#define XHCI_MSG_MAX 500
30
31/* xHCI PCI Configuration Registers */
32#define XHCI_SBRN_OFFSET (0x60)
33
34/* Max number of USB devices for any host controller - limit in section 6.1 */
35#define MAX_HC_SLOTS 256
36/* Section 5.3.3 - MaxPorts */
37#define MAX_HC_PORTS 127
38
39/*
40 * xHCI register interface.
41 * This corresponds to the eXtensible Host Controller Interface (xHCI)
42 * Revision 0.95 specification
43 */
44
45/**
46 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
47 * @hc_capbase: length of the capabilities register and HC version number
48 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
49 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
50 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
51 * @hcc_params: HCCPARAMS - Capability Parameters
52 * @db_off: DBOFF - Doorbell array offset
53 * @run_regs_off: RTSOFF - Runtime register space offset
54 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only
55 */
56struct xhci_cap_regs {
57 __le32 hc_capbase;
58 __le32 hcs_params1;
59 __le32 hcs_params2;
60 __le32 hcs_params3;
61 __le32 hcc_params;
62 __le32 db_off;
63 __le32 run_regs_off;
64 __le32 hcc_params2; /* xhci 1.1 */
65 /* Reserved up to (CAPLENGTH - 0x1C) */
66};
67
68/* Number of registers per port */
69#define NUM_PORT_REGS 4
70
71#define PORTSC 0
72#define PORTPMSC 1
73#define PORTLI 2
74#define PORTHLPMC 3
75
76/**
77 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
78 * @command: USBCMD - xHC command register
79 * @status: USBSTS - xHC status register
80 * @page_size: This indicates the page size that the host controller
81 * supports. If bit n is set, the HC supports a page size
82 * of 2^(n+12), up to a 128MB page size.
83 * 4K is the minimum page size.
84 * @cmd_ring: CRP - 64-bit Command Ring Pointer
85 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
86 * @config_reg: CONFIG - Configure Register
87 * @port_status_base: PORTSCn - base address for Port Status and Control
88 * Each port has a Port Status and Control register,
89 * followed by a Port Power Management Status and Control
90 * register, a Port Link Info register, and a reserved
91 * register.
92 * @port_power_base: PORTPMSCn - base address for
93 * Port Power Management Status and Control
94 * @port_link_base: PORTLIn - base address for Port Link Info (current
95 * Link PM state and control) for USB 2.1 and USB 3.0
96 * devices.
97 */
98struct xhci_op_regs {
99 __le32 command;
100 __le32 status;
101 __le32 page_size;
102 __le32 reserved1;
103 __le32 reserved2;
104 __le32 dev_notification;
105 __le64 cmd_ring;
106 /* rsvd: offset 0x20-2F */
107 __le32 reserved3[4];
108 __le64 dcbaa_ptr;
109 __le32 config_reg;
110 /* rsvd: offset 0x3C-3FF */
111 __le32 reserved4[241];
112 /* port 1 registers, which serve as a base address for other ports */
113 __le32 port_status_base;
114 __le32 port_power_base;
115 __le32 port_link_base;
116 __le32 reserved5;
117 /* registers for ports 2-255 */
118 __le32 reserved6[NUM_PORT_REGS*254];
119};
120
121/* USBCMD - USB command - command bitmasks */
122/* start/stop HC execution - do not write unless HC is halted*/
123#define CMD_RUN XHCI_CMD_RUN
124/* Reset HC - resets internal HC state machine and all registers (except
125 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
126 * The xHCI driver must reinitialize the xHC after setting this bit.
127 */
128#define CMD_RESET (1 << 1)
129/* Event Interrupt Enable - a '1' allows interrupts from the host controller */
130#define CMD_EIE XHCI_CMD_EIE
131/* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
132#define CMD_HSEIE XHCI_CMD_HSEIE
133/* bits 4:6 are reserved (and should be preserved on writes). */
134/* light reset (port status stays unchanged) - reset completed when this is 0 */
135#define CMD_LRESET (1 << 7)
136/* host controller save/restore state. */
137#define CMD_CSS (1 << 8)
138#define CMD_CRS (1 << 9)
139/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
140#define CMD_EWE XHCI_CMD_EWE
141/* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
142 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
143 * '0' means the xHC can power it off if all ports are in the disconnect,
144 * disabled, or powered-off state.
145 */
146#define CMD_PM_INDEX (1 << 11)
147/* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */
148#define CMD_ETE (1 << 14)
149/* bits 15:31 are reserved (and should be preserved on writes). */
150
151#define XHCI_RESET_LONG_USEC (10 * 1000 * 1000)
152#define XHCI_RESET_SHORT_USEC (250 * 1000)
153
154/* IMAN - Interrupt Management Register */
155#define IMAN_IE (1 << 1)
156#define IMAN_IP (1 << 0)
157
158/* USBSTS - USB status - status bitmasks */
159/* HC not running - set to 1 when run/stop bit is cleared. */
160#define STS_HALT XHCI_STS_HALT
161/* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
162#define STS_FATAL (1 << 2)
163/* event interrupt - clear this prior to clearing any IP flags in IR set*/
164#define STS_EINT (1 << 3)
165/* port change detect */
166#define STS_PORT (1 << 4)
167/* bits 5:7 reserved and zeroed */
168/* save state status - '1' means xHC is saving state */
169#define STS_SAVE (1 << 8)
170/* restore state status - '1' means xHC is restoring state */
171#define STS_RESTORE (1 << 9)
172/* true: save or restore error */
173#define STS_SRE (1 << 10)
174/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
175#define STS_CNR XHCI_STS_CNR
176/* true: internal Host Controller Error - SW needs to reset and reinitialize */
177#define STS_HCE (1 << 12)
178/* bits 13:31 reserved and should be preserved */
179
180/*
181 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
182 * Generate a device notification event when the HC sees a transaction with a
183 * notification type that matches a bit set in this bit field.
184 */
185#define DEV_NOTE_MASK (0xffff)
186#define ENABLE_DEV_NOTE(x) (1 << (x))
187/* Most of the device notification types should only be used for debug.
188 * SW does need to pay attention to function wake notifications.
189 */
190#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
191
192/* CRCR - Command Ring Control Register - cmd_ring bitmasks */
193/* bit 0 is the command ring cycle state */
194/* stop ring operation after completion of the currently executing command */
195#define CMD_RING_PAUSE (1 << 1)
196/* stop ring immediately - abort the currently executing command */
197#define CMD_RING_ABORT (1 << 2)
198/* true: command ring is running */
199#define CMD_RING_RUNNING (1 << 3)
200/* bits 4:5 reserved and should be preserved */
201/* Command Ring pointer - bit mask for the lower 32 bits. */
202#define CMD_RING_RSVD_BITS (0x3f)
203
204/* CONFIG - Configure Register - config_reg bitmasks */
205/* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
206#define MAX_DEVS(p) ((p) & 0xff)
207/* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */
208#define CONFIG_U3E (1 << 8)
209/* bit 9: Configuration Information Enable, xhci 1.1 */
210#define CONFIG_CIE (1 << 9)
211/* bits 10:31 - reserved and should be preserved */
212
213/**
214 * struct xhci_intr_reg - Interrupt Register Set
215 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
216 * interrupts and check for pending interrupts.
217 * @irq_control: IMOD - Interrupt Moderation Register.
218 * Used to throttle interrupts.
219 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
220 * @erst_base: ERST base address.
221 * @erst_dequeue: Event ring dequeue pointer.
222 *
223 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
224 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
225 * multiple segments of the same size. The HC places events on the ring and
226 * "updates the Cycle bit in the TRBs to indicate to software the current
227 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
228 * updates the dequeue pointer.
229 */
230struct xhci_intr_reg {
231 __le32 irq_pending;
232 __le32 irq_control;
233 __le32 erst_size;
234 __le32 rsvd;
235 __le64 erst_base;
236 __le64 erst_dequeue;
237};
238
239/* irq_pending bitmasks */
240#define ER_IRQ_PENDING(p) ((p) & 0x1)
241/* bits 2:31 need to be preserved */
242/* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
243#define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
244#define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
245#define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
246
247/* irq_control bitmasks */
248/* Minimum interval between interrupts (in 250ns intervals). The interval
249 * between interrupts will be longer if there are no events on the event ring.
250 * Default is 4000 (1 ms).
251 */
252#define ER_IRQ_INTERVAL_MASK (0xffff)
253/* Counter used to count down the time to the next interrupt - HW use only */
254#define ER_IRQ_COUNTER_MASK (0xffff << 16)
255
256/* erst_size bitmasks */
257/* Preserve bits 16:31 of erst_size */
258#define ERST_SIZE_MASK (0xffff << 16)
259
260/* erst_base bitmasks */
261#define ERST_BASE_RSVDP (GENMASK_ULL(5, 0))
262
263/* erst_dequeue bitmasks */
264/* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
265 * where the current dequeue pointer lies. This is an optional HW hint.
266 */
267#define ERST_DESI_MASK (0x7)
268/* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
269 * a work queue (or delayed service routine)?
270 */
271#define ERST_EHB (1 << 3)
272#define ERST_PTR_MASK (GENMASK_ULL(63, 4))
273
274/**
275 * struct xhci_run_regs
276 * @microframe_index:
277 * MFINDEX - current microframe number
278 *
279 * Section 5.5 Host Controller Runtime Registers:
280 * "Software should read and write these registers using only Dword (32 bit)
281 * or larger accesses"
282 */
283struct xhci_run_regs {
284 __le32 microframe_index;
285 __le32 rsvd[7];
286 struct xhci_intr_reg ir_set[128];
287};
288
289/**
290 * struct doorbell_array
291 *
292 * Bits 0 - 7: Endpoint target
293 * Bits 8 - 15: RsvdZ
294 * Bits 16 - 31: Stream ID
295 *
296 * Section 5.6
297 */
298struct xhci_doorbell_array {
299 __le32 doorbell[256];
300};
301
302#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
303#define DB_VALUE_HOST 0x00000000
304
305#define PLT_MASK (0x03 << 6)
306#define PLT_SYM (0x00 << 6)
307#define PLT_ASYM_RX (0x02 << 6)
308#define PLT_ASYM_TX (0x03 << 6)
309
310/**
311 * struct xhci_container_ctx
312 * @type: Type of context. Used to calculated offsets to contained contexts.
313 * @size: Size of the context data
314 * @bytes: The raw context data given to HW
315 * @dma: dma address of the bytes
316 *
317 * Represents either a Device or Input context. Holds a pointer to the raw
318 * memory used for the context (bytes) and dma address of it (dma).
319 */
320struct xhci_container_ctx {
321 unsigned type;
322#define XHCI_CTX_TYPE_DEVICE 0x1
323#define XHCI_CTX_TYPE_INPUT 0x2
324
325 int size;
326
327 u8 *bytes;
328 dma_addr_t dma;
329};
330
331/**
332 * struct xhci_slot_ctx
333 * @dev_info: Route string, device speed, hub info, and last valid endpoint
334 * @dev_info2: Max exit latency for device number, root hub port number
335 * @tt_info: tt_info is used to construct split transaction tokens
336 * @dev_state: slot state and device address
337 *
338 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
339 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
340 * reserved at the end of the slot context for HC internal use.
341 */
342struct xhci_slot_ctx {
343 __le32 dev_info;
344 __le32 dev_info2;
345 __le32 tt_info;
346 __le32 dev_state;
347 /* offset 0x10 to 0x1f reserved for HC internal use */
348 __le32 reserved[4];
349};
350
351/* dev_info bitmasks */
352/* Route String - 0:19 */
353#define ROUTE_STRING_MASK (0xfffff)
354/* Device speed - values defined by PORTSC Device Speed field - 20:23 */
355#define DEV_SPEED (0xf << 20)
356#define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20)
357/* bit 24 reserved */
358/* Is this LS/FS device connected through a HS hub? - bit 25 */
359#define DEV_MTT (0x1 << 25)
360/* Set if the device is a hub - bit 26 */
361#define DEV_HUB (0x1 << 26)
362/* Index of the last valid endpoint context in this device context - 27:31 */
363#define LAST_CTX_MASK (0x1f << 27)
364#define LAST_CTX(p) ((p) << 27)
365#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
366#define SLOT_FLAG (1 << 0)
367#define EP0_FLAG (1 << 1)
368
369/* dev_info2 bitmasks */
370/* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
371#define MAX_EXIT (0xffff)
372/* Root hub port number that is needed to access the USB device */
373#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
374#define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
375/* Maximum number of ports under a hub device */
376#define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
377#define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24)
378
379/* tt_info bitmasks */
380/*
381 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
382 * The Slot ID of the hub that isolates the high speed signaling from
383 * this low or full-speed device. '0' if attached to root hub port.
384 */
385#define TT_SLOT (0xff)
386/*
387 * The number of the downstream facing port of the high-speed hub
388 * '0' if the device is not low or full speed.
389 */
390#define TT_PORT (0xff << 8)
391#define TT_THINK_TIME(p) (((p) & 0x3) << 16)
392#define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16)
393
394/* dev_state bitmasks */
395/* USB device address - assigned by the HC */
396#define DEV_ADDR_MASK (0xff)
397/* bits 8:26 reserved */
398/* Slot state */
399#define SLOT_STATE (0x1f << 27)
400#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
401
402#define SLOT_STATE_DISABLED 0
403#define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
404#define SLOT_STATE_DEFAULT 1
405#define SLOT_STATE_ADDRESSED 2
406#define SLOT_STATE_CONFIGURED 3
407
408/**
409 * struct xhci_ep_ctx
410 * @ep_info: endpoint state, streams, mult, and interval information.
411 * @ep_info2: information on endpoint type, max packet size, max burst size,
412 * error count, and whether the HC will force an event for all
413 * transactions.
414 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
415 * defines one stream, this points to the endpoint transfer ring.
416 * Otherwise, it points to a stream context array, which has a
417 * ring pointer for each flow.
418 * @tx_info:
419 * Average TRB lengths for the endpoint ring and
420 * max payload within an Endpoint Service Interval Time (ESIT).
421 *
422 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
423 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
424 * reserved at the end of the endpoint context for HC internal use.
425 */
426struct xhci_ep_ctx {
427 __le32 ep_info;
428 __le32 ep_info2;
429 __le64 deq;
430 __le32 tx_info;
431 /* offset 0x14 - 0x1f reserved for HC internal use */
432 __le32 reserved[3];
433};
434
435/* ep_info bitmasks */
436/*
437 * Endpoint State - bits 0:2
438 * 0 - disabled
439 * 1 - running
440 * 2 - halted due to halt condition - ok to manipulate endpoint ring
441 * 3 - stopped
442 * 4 - TRB error
443 * 5-7 - reserved
444 */
445#define EP_STATE_MASK (0x7)
446#define EP_STATE_DISABLED 0
447#define EP_STATE_RUNNING 1
448#define EP_STATE_HALTED 2
449#define EP_STATE_STOPPED 3
450#define EP_STATE_ERROR 4
451#define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
452
453/* Mult - Max number of burtst within an interval, in EP companion desc. */
454#define EP_MULT(p) (((p) & 0x3) << 8)
455#define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
456/* bits 10:14 are Max Primary Streams */
457/* bit 15 is Linear Stream Array */
458/* Interval - period between requests to an endpoint - 125u increments. */
459#define EP_INTERVAL(p) (((p) & 0xff) << 16)
460#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
461#define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
462#define EP_MAXPSTREAMS_MASK (0x1f << 10)
463#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
464#define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10)
465/* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
466#define EP_HAS_LSA (1 << 15)
467/* hosts with LEC=1 use bits 31:24 as ESIT high bits. */
468#define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff)
469
470/* ep_info2 bitmasks */
471/*
472 * Force Event - generate transfer events for all TRBs for this endpoint
473 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
474 */
475#define FORCE_EVENT (0x1)
476#define ERROR_COUNT(p) (((p) & 0x3) << 1)
477#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
478#define EP_TYPE(p) ((p) << 3)
479#define ISOC_OUT_EP 1
480#define BULK_OUT_EP 2
481#define INT_OUT_EP 3
482#define CTRL_EP 4
483#define ISOC_IN_EP 5
484#define BULK_IN_EP 6
485#define INT_IN_EP 7
486/* bit 6 reserved */
487/* bit 7 is Host Initiate Disable - for disabling stream selection */
488#define MAX_BURST(p) (((p)&0xff) << 8)
489#define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
490#define MAX_PACKET(p) (((p)&0xffff) << 16)
491#define MAX_PACKET_MASK (0xffff << 16)
492#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
493
494/* tx_info bitmasks */
495#define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff)
496#define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16)
497#define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24)
498#define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
499
500/* deq bitmasks */
501#define EP_CTX_CYCLE_MASK (1 << 0)
502#define SCTX_DEQ_MASK (~0xfL)
503
504
505/**
506 * struct xhci_input_control_context
507 * Input control context; see section 6.2.5.
508 *
509 * @drop_context: set the bit of the endpoint context you want to disable
510 * @add_context: set the bit of the endpoint context you want to enable
511 */
512struct xhci_input_control_ctx {
513 __le32 drop_flags;
514 __le32 add_flags;
515 __le32 rsvd2[6];
516};
517
518#define EP_IS_ADDED(ctrl_ctx, i) \
519 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
520#define EP_IS_DROPPED(ctrl_ctx, i) \
521 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
522
523/* Represents everything that is needed to issue a command on the command ring.
524 * It's useful to pre-allocate these for commands that cannot fail due to
525 * out-of-memory errors, like freeing streams.
526 */
527struct xhci_command {
528 /* Input context for changing device state */
529 struct xhci_container_ctx *in_ctx;
530 u32 status;
531 int slot_id;
532 /* If completion is null, no one is waiting on this command
533 * and the structure can be freed after the command completes.
534 */
535 struct completion *completion;
536 union xhci_trb *command_trb;
537 struct list_head cmd_list;
538 /* xHCI command response timeout in milliseconds */
539 unsigned int timeout_ms;
540};
541
542/* drop context bitmasks */
543#define DROP_EP(x) (0x1 << x)
544/* add context bitmasks */
545#define ADD_EP(x) (0x1 << x)
546
547struct xhci_stream_ctx {
548 /* 64-bit stream ring address, cycle state, and stream type */
549 __le64 stream_ring;
550 /* offset 0x14 - 0x1f reserved for HC internal use */
551 __le32 reserved[2];
552};
553
554/* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
555#define SCT_FOR_CTX(p) (((p) & 0x7) << 1)
556/* Secondary stream array type, dequeue pointer is to a transfer ring */
557#define SCT_SEC_TR 0
558/* Primary stream array type, dequeue pointer is to a transfer ring */
559#define SCT_PRI_TR 1
560/* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
561#define SCT_SSA_8 2
562#define SCT_SSA_16 3
563#define SCT_SSA_32 4
564#define SCT_SSA_64 5
565#define SCT_SSA_128 6
566#define SCT_SSA_256 7
567
568/* Assume no secondary streams for now */
569struct xhci_stream_info {
570 struct xhci_ring **stream_rings;
571 /* Number of streams, including stream 0 (which drivers can't use) */
572 unsigned int num_streams;
573 /* The stream context array may be bigger than
574 * the number of streams the driver asked for
575 */
576 struct xhci_stream_ctx *stream_ctx_array;
577 unsigned int num_stream_ctxs;
578 dma_addr_t ctx_array_dma;
579 /* For mapping physical TRB addresses to segments in stream rings */
580 struct radix_tree_root trb_address_map;
581 struct xhci_command *free_streams_command;
582};
583
584#define SMALL_STREAM_ARRAY_SIZE 256
585#define MEDIUM_STREAM_ARRAY_SIZE 1024
586
587/* Some Intel xHCI host controllers need software to keep track of the bus
588 * bandwidth. Keep track of endpoint info here. Each root port is allocated
589 * the full bus bandwidth. We must also treat TTs (including each port under a
590 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
591 * (DMI) also limits the total bandwidth (across all domains) that can be used.
592 */
593struct xhci_bw_info {
594 /* ep_interval is zero-based */
595 unsigned int ep_interval;
596 /* mult and num_packets are one-based */
597 unsigned int mult;
598 unsigned int num_packets;
599 unsigned int max_packet_size;
600 unsigned int max_esit_payload;
601 unsigned int type;
602};
603
604/* "Block" sizes in bytes the hardware uses for different device speeds.
605 * The logic in this part of the hardware limits the number of bits the hardware
606 * can use, so must represent bandwidth in a less precise manner to mimic what
607 * the scheduler hardware computes.
608 */
609#define FS_BLOCK 1
610#define HS_BLOCK 4
611#define SS_BLOCK 16
612#define DMI_BLOCK 32
613
614/* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
615 * with each byte transferred. SuperSpeed devices have an initial overhead to
616 * set up bursts. These are in blocks, see above. LS overhead has already been
617 * translated into FS blocks.
618 */
619#define DMI_OVERHEAD 8
620#define DMI_OVERHEAD_BURST 4
621#define SS_OVERHEAD 8
622#define SS_OVERHEAD_BURST 32
623#define HS_OVERHEAD 26
624#define FS_OVERHEAD 20
625#define LS_OVERHEAD 128
626/* The TTs need to claim roughly twice as much bandwidth (94 bytes per
627 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
628 * of overhead associated with split transfers crossing microframe boundaries.
629 * 31 blocks is pure protocol overhead.
630 */
631#define TT_HS_OVERHEAD (31 + 94)
632#define TT_DMI_OVERHEAD (25 + 12)
633
634/* Bandwidth limits in blocks */
635#define FS_BW_LIMIT 1285
636#define TT_BW_LIMIT 1320
637#define HS_BW_LIMIT 1607
638#define SS_BW_LIMIT_IN 3906
639#define DMI_BW_LIMIT_IN 3906
640#define SS_BW_LIMIT_OUT 3906
641#define DMI_BW_LIMIT_OUT 3906
642
643/* Percentage of bus bandwidth reserved for non-periodic transfers */
644#define FS_BW_RESERVED 10
645#define HS_BW_RESERVED 20
646#define SS_BW_RESERVED 10
647
648struct xhci_virt_ep {
649 struct xhci_virt_device *vdev; /* parent */
650 unsigned int ep_index;
651 struct xhci_ring *ring;
652 /* Related to endpoints that are configured to use stream IDs only */
653 struct xhci_stream_info *stream_info;
654 /* Temporary storage in case the configure endpoint command fails and we
655 * have to restore the device state to the previous state
656 */
657 struct xhci_ring *new_ring;
658 unsigned int err_count;
659 unsigned int ep_state;
660#define SET_DEQ_PENDING (1 << 0)
661#define EP_HALTED (1 << 1) /* For stall handling */
662#define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */
663/* Transitioning the endpoint to using streams, don't enqueue URBs */
664#define EP_GETTING_STREAMS (1 << 3)
665#define EP_HAS_STREAMS (1 << 4)
666/* Transitioning the endpoint to not using streams, don't enqueue URBs */
667#define EP_GETTING_NO_STREAMS (1 << 5)
668#define EP_HARD_CLEAR_TOGGLE (1 << 6)
669#define EP_SOFT_CLEAR_TOGGLE (1 << 7)
670/* usb_hub_clear_tt_buffer is in progress */
671#define EP_CLEARING_TT (1 << 8)
672 /* ---- Related to URB cancellation ---- */
673 struct list_head cancelled_td_list;
674 struct xhci_hcd *xhci;
675 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
676 * command. We'll need to update the ring's dequeue segment and dequeue
677 * pointer after the command completes.
678 */
679 struct xhci_segment *queued_deq_seg;
680 union xhci_trb *queued_deq_ptr;
681 /*
682 * Sometimes the xHC can not process isochronous endpoint ring quickly
683 * enough, and it will miss some isoc tds on the ring and generate
684 * a Missed Service Error Event.
685 * Set skip flag when receive a Missed Service Error Event and
686 * process the missed tds on the endpoint ring.
687 */
688 bool skip;
689 /* Bandwidth checking storage */
690 struct xhci_bw_info bw_info;
691 struct list_head bw_endpoint_list;
692 /* Isoch Frame ID checking storage */
693 int next_frame_id;
694 /* Use new Isoch TRB layout needed for extended TBC support */
695 bool use_extended_tbc;
696};
697
698enum xhci_overhead_type {
699 LS_OVERHEAD_TYPE = 0,
700 FS_OVERHEAD_TYPE,
701 HS_OVERHEAD_TYPE,
702};
703
704struct xhci_interval_bw {
705 unsigned int num_packets;
706 /* Sorted by max packet size.
707 * Head of the list is the greatest max packet size.
708 */
709 struct list_head endpoints;
710 /* How many endpoints of each speed are present. */
711 unsigned int overhead[3];
712};
713
714#define XHCI_MAX_INTERVAL 16
715
716struct xhci_interval_bw_table {
717 unsigned int interval0_esit_payload;
718 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
719 /* Includes reserved bandwidth for async endpoints */
720 unsigned int bw_used;
721 unsigned int ss_bw_in;
722 unsigned int ss_bw_out;
723};
724
725#define EP_CTX_PER_DEV 31
726
727struct xhci_virt_device {
728 int slot_id;
729 struct usb_device *udev;
730 /*
731 * Commands to the hardware are passed an "input context" that
732 * tells the hardware what to change in its data structures.
733 * The hardware will return changes in an "output context" that
734 * software must allocate for the hardware. We need to keep
735 * track of input and output contexts separately because
736 * these commands might fail and we don't trust the hardware.
737 */
738 struct xhci_container_ctx *out_ctx;
739 /* Used for addressing devices and configuration changes */
740 struct xhci_container_ctx *in_ctx;
741 struct xhci_virt_ep eps[EP_CTX_PER_DEV];
742 struct xhci_port *rhub_port;
743 struct xhci_interval_bw_table *bw_table;
744 struct xhci_tt_bw_info *tt_info;
745 /*
746 * flags for state tracking based on events and issued commands.
747 * Software can not rely on states from output contexts because of
748 * latency between events and xHC updating output context values.
749 * See xhci 1.1 section 4.8.3 for more details
750 */
751 unsigned long flags;
752#define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */
753
754 /* The current max exit latency for the enabled USB3 link states. */
755 u16 current_mel;
756 /* Used for the debugfs interfaces. */
757 void *debugfs_private;
758};
759
760/*
761 * For each roothub, keep track of the bandwidth information for each periodic
762 * interval.
763 *
764 * If a high speed hub is attached to the roothub, each TT associated with that
765 * hub is a separate bandwidth domain. The interval information for the
766 * endpoints on the devices under that TT will appear in the TT structure.
767 */
768struct xhci_root_port_bw_info {
769 struct list_head tts;
770 unsigned int num_active_tts;
771 struct xhci_interval_bw_table bw_table;
772};
773
774struct xhci_tt_bw_info {
775 struct list_head tt_list;
776 int slot_id;
777 int ttport;
778 struct xhci_interval_bw_table bw_table;
779 int active_eps;
780};
781
782
783/**
784 * struct xhci_device_context_array
785 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
786 */
787struct xhci_device_context_array {
788 /* 64-bit device addresses; we only write 32-bit addresses */
789 __le64 dev_context_ptrs[MAX_HC_SLOTS];
790 /* private xHCD pointers */
791 dma_addr_t dma;
792};
793/* TODO: write function to set the 64-bit device DMA address */
794/*
795 * TODO: change this to be dynamically sized at HC mem init time since the HC
796 * might not be able to handle the maximum number of devices possible.
797 */
798
799
800struct xhci_transfer_event {
801 /* 64-bit buffer address, or immediate data */
802 __le64 buffer;
803 __le32 transfer_len;
804 /* This field is interpreted differently based on the type of TRB */
805 __le32 flags;
806};
807
808/* Transfer event TRB length bit mask */
809/* bits 0:23 */
810#define EVENT_TRB_LEN(p) ((p) & 0xffffff)
811
812/** Transfer Event bit fields **/
813#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
814
815/* Completion Code - only applicable for some types of TRBs */
816#define COMP_CODE_MASK (0xff << 24)
817#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
818#define COMP_INVALID 0
819#define COMP_SUCCESS 1
820#define COMP_DATA_BUFFER_ERROR 2
821#define COMP_BABBLE_DETECTED_ERROR 3
822#define COMP_USB_TRANSACTION_ERROR 4
823#define COMP_TRB_ERROR 5
824#define COMP_STALL_ERROR 6
825#define COMP_RESOURCE_ERROR 7
826#define COMP_BANDWIDTH_ERROR 8
827#define COMP_NO_SLOTS_AVAILABLE_ERROR 9
828#define COMP_INVALID_STREAM_TYPE_ERROR 10
829#define COMP_SLOT_NOT_ENABLED_ERROR 11
830#define COMP_ENDPOINT_NOT_ENABLED_ERROR 12
831#define COMP_SHORT_PACKET 13
832#define COMP_RING_UNDERRUN 14
833#define COMP_RING_OVERRUN 15
834#define COMP_VF_EVENT_RING_FULL_ERROR 16
835#define COMP_PARAMETER_ERROR 17
836#define COMP_BANDWIDTH_OVERRUN_ERROR 18
837#define COMP_CONTEXT_STATE_ERROR 19
838#define COMP_NO_PING_RESPONSE_ERROR 20
839#define COMP_EVENT_RING_FULL_ERROR 21
840#define COMP_INCOMPATIBLE_DEVICE_ERROR 22
841#define COMP_MISSED_SERVICE_ERROR 23
842#define COMP_COMMAND_RING_STOPPED 24
843#define COMP_COMMAND_ABORTED 25
844#define COMP_STOPPED 26
845#define COMP_STOPPED_LENGTH_INVALID 27
846#define COMP_STOPPED_SHORT_PACKET 28
847#define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29
848#define COMP_ISOCH_BUFFER_OVERRUN 31
849#define COMP_EVENT_LOST_ERROR 32
850#define COMP_UNDEFINED_ERROR 33
851#define COMP_INVALID_STREAM_ID_ERROR 34
852#define COMP_SECONDARY_BANDWIDTH_ERROR 35
853#define COMP_SPLIT_TRANSACTION_ERROR 36
854
855static inline const char *xhci_trb_comp_code_string(u8 status)
856{
857 switch (status) {
858 case COMP_INVALID:
859 return "Invalid";
860 case COMP_SUCCESS:
861 return "Success";
862 case COMP_DATA_BUFFER_ERROR:
863 return "Data Buffer Error";
864 case COMP_BABBLE_DETECTED_ERROR:
865 return "Babble Detected";
866 case COMP_USB_TRANSACTION_ERROR:
867 return "USB Transaction Error";
868 case COMP_TRB_ERROR:
869 return "TRB Error";
870 case COMP_STALL_ERROR:
871 return "Stall Error";
872 case COMP_RESOURCE_ERROR:
873 return "Resource Error";
874 case COMP_BANDWIDTH_ERROR:
875 return "Bandwidth Error";
876 case COMP_NO_SLOTS_AVAILABLE_ERROR:
877 return "No Slots Available Error";
878 case COMP_INVALID_STREAM_TYPE_ERROR:
879 return "Invalid Stream Type Error";
880 case COMP_SLOT_NOT_ENABLED_ERROR:
881 return "Slot Not Enabled Error";
882 case COMP_ENDPOINT_NOT_ENABLED_ERROR:
883 return "Endpoint Not Enabled Error";
884 case COMP_SHORT_PACKET:
885 return "Short Packet";
886 case COMP_RING_UNDERRUN:
887 return "Ring Underrun";
888 case COMP_RING_OVERRUN:
889 return "Ring Overrun";
890 case COMP_VF_EVENT_RING_FULL_ERROR:
891 return "VF Event Ring Full Error";
892 case COMP_PARAMETER_ERROR:
893 return "Parameter Error";
894 case COMP_BANDWIDTH_OVERRUN_ERROR:
895 return "Bandwidth Overrun Error";
896 case COMP_CONTEXT_STATE_ERROR:
897 return "Context State Error";
898 case COMP_NO_PING_RESPONSE_ERROR:
899 return "No Ping Response Error";
900 case COMP_EVENT_RING_FULL_ERROR:
901 return "Event Ring Full Error";
902 case COMP_INCOMPATIBLE_DEVICE_ERROR:
903 return "Incompatible Device Error";
904 case COMP_MISSED_SERVICE_ERROR:
905 return "Missed Service Error";
906 case COMP_COMMAND_RING_STOPPED:
907 return "Command Ring Stopped";
908 case COMP_COMMAND_ABORTED:
909 return "Command Aborted";
910 case COMP_STOPPED:
911 return "Stopped";
912 case COMP_STOPPED_LENGTH_INVALID:
913 return "Stopped - Length Invalid";
914 case COMP_STOPPED_SHORT_PACKET:
915 return "Stopped - Short Packet";
916 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
917 return "Max Exit Latency Too Large Error";
918 case COMP_ISOCH_BUFFER_OVERRUN:
919 return "Isoch Buffer Overrun";
920 case COMP_EVENT_LOST_ERROR:
921 return "Event Lost Error";
922 case COMP_UNDEFINED_ERROR:
923 return "Undefined Error";
924 case COMP_INVALID_STREAM_ID_ERROR:
925 return "Invalid Stream ID Error";
926 case COMP_SECONDARY_BANDWIDTH_ERROR:
927 return "Secondary Bandwidth Error";
928 case COMP_SPLIT_TRANSACTION_ERROR:
929 return "Split Transaction Error";
930 default:
931 return "Unknown!!";
932 }
933}
934
935struct xhci_link_trb {
936 /* 64-bit segment pointer*/
937 __le64 segment_ptr;
938 __le32 intr_target;
939 __le32 control;
940};
941
942/* control bitfields */
943#define LINK_TOGGLE (0x1<<1)
944
945/* Command completion event TRB */
946struct xhci_event_cmd {
947 /* Pointer to command TRB, or the value passed by the event data trb */
948 __le64 cmd_trb;
949 __le32 status;
950 __le32 flags;
951};
952
953/* flags bitmasks */
954
955/* Address device - disable SetAddress */
956#define TRB_BSR (1<<9)
957
958/* Configure Endpoint - Deconfigure */
959#define TRB_DC (1<<9)
960
961/* Stop Ring - Transfer State Preserve */
962#define TRB_TSP (1<<9)
963
964enum xhci_ep_reset_type {
965 EP_HARD_RESET,
966 EP_SOFT_RESET,
967};
968
969/* Force Event */
970#define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22)
971#define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16)
972
973/* Set Latency Tolerance Value */
974#define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16)
975
976/* Get Port Bandwidth */
977#define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16)
978
979/* Force Header */
980#define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f)
981#define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24)
982
983enum xhci_setup_dev {
984 SETUP_CONTEXT_ONLY,
985 SETUP_CONTEXT_ADDRESS,
986};
987
988/* bits 16:23 are the virtual function ID */
989/* bits 24:31 are the slot ID */
990#define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
991#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
992
993/* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
994#define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
995#define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
996
997#define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
998#define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
999#define LAST_EP_INDEX 30
1000
1001/* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */
1002#define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1003#define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1004#define SCT_FOR_TRB(p) (((p) << 1) & 0x7)
1005
1006/* Link TRB specific fields */
1007#define TRB_TC (1<<1)
1008
1009/* Port Status Change Event TRB fields */
1010/* Port ID - bits 31:24 */
1011#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1012
1013#define EVENT_DATA (1 << 2)
1014
1015/* Normal TRB fields */
1016/* transfer_len bitmasks - bits 0:16 */
1017#define TRB_LEN(p) ((p) & 0x1ffff)
1018/* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */
1019#define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
1020#define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17)
1021/* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */
1022#define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17)
1023/* Interrupter Target - which MSI-X vector to target the completion event at */
1024#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1025#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1026/* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */
1027#define TRB_TBC(p) (((p) & 0x3) << 7)
1028#define TRB_TLBPC(p) (((p) & 0xf) << 16)
1029
1030/* Cycle bit - indicates TRB ownership by HC or HCD */
1031#define TRB_CYCLE (1<<0)
1032/*
1033 * Force next event data TRB to be evaluated before task switch.
1034 * Used to pass OS data back after a TD completes.
1035 */
1036#define TRB_ENT (1<<1)
1037/* Interrupt on short packet */
1038#define TRB_ISP (1<<2)
1039/* Set PCIe no snoop attribute */
1040#define TRB_NO_SNOOP (1<<3)
1041/* Chain multiple TRBs into a TD */
1042#define TRB_CHAIN (1<<4)
1043/* Interrupt on completion */
1044#define TRB_IOC (1<<5)
1045/* The buffer pointer contains immediate data */
1046#define TRB_IDT (1<<6)
1047/* TDs smaller than this might use IDT */
1048#define TRB_IDT_MAX_SIZE 8
1049
1050/* Block Event Interrupt */
1051#define TRB_BEI (1<<9)
1052
1053/* Control transfer TRB specific fields */
1054#define TRB_DIR_IN (1<<16)
1055#define TRB_TX_TYPE(p) ((p) << 16)
1056#define TRB_DATA_OUT 2
1057#define TRB_DATA_IN 3
1058
1059/* Isochronous TRB specific fields */
1060#define TRB_SIA (1<<31)
1061#define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
1062
1063/* TRB cache size for xHC with TRB cache */
1064#define TRB_CACHE_SIZE_HS 8
1065#define TRB_CACHE_SIZE_SS 16
1066
1067struct xhci_generic_trb {
1068 __le32 field[4];
1069};
1070
1071union xhci_trb {
1072 struct xhci_link_trb link;
1073 struct xhci_transfer_event trans_event;
1074 struct xhci_event_cmd event_cmd;
1075 struct xhci_generic_trb generic;
1076};
1077
1078/* TRB bit mask */
1079#define TRB_TYPE_BITMASK (0xfc00)
1080#define TRB_TYPE(p) ((p) << 10)
1081#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1082/* TRB type IDs */
1083/* bulk, interrupt, isoc scatter/gather, and control data stage */
1084#define TRB_NORMAL 1
1085/* setup stage for control transfers */
1086#define TRB_SETUP 2
1087/* data stage for control transfers */
1088#define TRB_DATA 3
1089/* status stage for control transfers */
1090#define TRB_STATUS 4
1091/* isoc transfers */
1092#define TRB_ISOC 5
1093/* TRB for linking ring segments */
1094#define TRB_LINK 6
1095#define TRB_EVENT_DATA 7
1096/* Transfer Ring No-op (not for the command ring) */
1097#define TRB_TR_NOOP 8
1098/* Command TRBs */
1099/* Enable Slot Command */
1100#define TRB_ENABLE_SLOT 9
1101/* Disable Slot Command */
1102#define TRB_DISABLE_SLOT 10
1103/* Address Device Command */
1104#define TRB_ADDR_DEV 11
1105/* Configure Endpoint Command */
1106#define TRB_CONFIG_EP 12
1107/* Evaluate Context Command */
1108#define TRB_EVAL_CONTEXT 13
1109/* Reset Endpoint Command */
1110#define TRB_RESET_EP 14
1111/* Stop Transfer Ring Command */
1112#define TRB_STOP_RING 15
1113/* Set Transfer Ring Dequeue Pointer Command */
1114#define TRB_SET_DEQ 16
1115/* Reset Device Command */
1116#define TRB_RESET_DEV 17
1117/* Force Event Command (opt) */
1118#define TRB_FORCE_EVENT 18
1119/* Negotiate Bandwidth Command (opt) */
1120#define TRB_NEG_BANDWIDTH 19
1121/* Set Latency Tolerance Value Command (opt) */
1122#define TRB_SET_LT 20
1123/* Get port bandwidth Command */
1124#define TRB_GET_BW 21
1125/* Force Header Command - generate a transaction or link management packet */
1126#define TRB_FORCE_HEADER 22
1127/* No-op Command - not for transfer rings */
1128#define TRB_CMD_NOOP 23
1129/* TRB IDs 24-31 reserved */
1130/* Event TRBS */
1131/* Transfer Event */
1132#define TRB_TRANSFER 32
1133/* Command Completion Event */
1134#define TRB_COMPLETION 33
1135/* Port Status Change Event */
1136#define TRB_PORT_STATUS 34
1137/* Bandwidth Request Event (opt) */
1138#define TRB_BANDWIDTH_EVENT 35
1139/* Doorbell Event (opt) */
1140#define TRB_DOORBELL 36
1141/* Host Controller Event */
1142#define TRB_HC_EVENT 37
1143/* Device Notification Event - device sent function wake notification */
1144#define TRB_DEV_NOTE 38
1145/* MFINDEX Wrap Event - microframe counter wrapped */
1146#define TRB_MFINDEX_WRAP 39
1147/* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1148#define TRB_VENDOR_DEFINED_LOW 48
1149/* Nec vendor-specific command completion event. */
1150#define TRB_NEC_CMD_COMP 48
1151/* Get NEC firmware revision. */
1152#define TRB_NEC_GET_FW 49
1153
1154static inline const char *xhci_trb_type_string(u8 type)
1155{
1156 switch (type) {
1157 case TRB_NORMAL:
1158 return "Normal";
1159 case TRB_SETUP:
1160 return "Setup Stage";
1161 case TRB_DATA:
1162 return "Data Stage";
1163 case TRB_STATUS:
1164 return "Status Stage";
1165 case TRB_ISOC:
1166 return "Isoch";
1167 case TRB_LINK:
1168 return "Link";
1169 case TRB_EVENT_DATA:
1170 return "Event Data";
1171 case TRB_TR_NOOP:
1172 return "No-Op";
1173 case TRB_ENABLE_SLOT:
1174 return "Enable Slot Command";
1175 case TRB_DISABLE_SLOT:
1176 return "Disable Slot Command";
1177 case TRB_ADDR_DEV:
1178 return "Address Device Command";
1179 case TRB_CONFIG_EP:
1180 return "Configure Endpoint Command";
1181 case TRB_EVAL_CONTEXT:
1182 return "Evaluate Context Command";
1183 case TRB_RESET_EP:
1184 return "Reset Endpoint Command";
1185 case TRB_STOP_RING:
1186 return "Stop Ring Command";
1187 case TRB_SET_DEQ:
1188 return "Set TR Dequeue Pointer Command";
1189 case TRB_RESET_DEV:
1190 return "Reset Device Command";
1191 case TRB_FORCE_EVENT:
1192 return "Force Event Command";
1193 case TRB_NEG_BANDWIDTH:
1194 return "Negotiate Bandwidth Command";
1195 case TRB_SET_LT:
1196 return "Set Latency Tolerance Value Command";
1197 case TRB_GET_BW:
1198 return "Get Port Bandwidth Command";
1199 case TRB_FORCE_HEADER:
1200 return "Force Header Command";
1201 case TRB_CMD_NOOP:
1202 return "No-Op Command";
1203 case TRB_TRANSFER:
1204 return "Transfer Event";
1205 case TRB_COMPLETION:
1206 return "Command Completion Event";
1207 case TRB_PORT_STATUS:
1208 return "Port Status Change Event";
1209 case TRB_BANDWIDTH_EVENT:
1210 return "Bandwidth Request Event";
1211 case TRB_DOORBELL:
1212 return "Doorbell Event";
1213 case TRB_HC_EVENT:
1214 return "Host Controller Event";
1215 case TRB_DEV_NOTE:
1216 return "Device Notification Event";
1217 case TRB_MFINDEX_WRAP:
1218 return "MFINDEX Wrap Event";
1219 case TRB_NEC_CMD_COMP:
1220 return "NEC Command Completion Event";
1221 case TRB_NEC_GET_FW:
1222 return "NET Get Firmware Revision Command";
1223 default:
1224 return "UNKNOWN";
1225 }
1226}
1227
1228#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1229/* Above, but for __le32 types -- can avoid work by swapping constants: */
1230#define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1231 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1232#define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1233 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1234
1235#define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1236#define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1237
1238/*
1239 * TRBS_PER_SEGMENT must be a multiple of 4,
1240 * since the command ring is 64-byte aligned.
1241 * It must also be greater than 16.
1242 */
1243#define TRBS_PER_SEGMENT 256
1244/* Allow two commands + a link TRB, along with any reserved command TRBs */
1245#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1246#define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1247#define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1248/* TRB buffer pointers can't cross 64KB boundaries */
1249#define TRB_MAX_BUFF_SHIFT 16
1250#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1251/* How much data is left before the 64KB boundary? */
1252#define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1253 (addr & (TRB_MAX_BUFF_SIZE - 1)))
1254#define MAX_SOFT_RETRY 3
1255/*
1256 * Limits of consecutive isoc trbs that can Block Event Interrupt (BEI) if
1257 * XHCI_AVOID_BEI quirk is in use.
1258 */
1259#define AVOID_BEI_INTERVAL_MIN 8
1260#define AVOID_BEI_INTERVAL_MAX 32
1261
1262struct xhci_segment {
1263 union xhci_trb *trbs;
1264 /* private to HCD */
1265 struct xhci_segment *next;
1266 unsigned int num;
1267 dma_addr_t dma;
1268 /* Max packet sized bounce buffer for td-fragmant alignment */
1269 dma_addr_t bounce_dma;
1270 void *bounce_buf;
1271 unsigned int bounce_offs;
1272 unsigned int bounce_len;
1273};
1274
1275enum xhci_cancelled_td_status {
1276 TD_DIRTY = 0,
1277 TD_HALTED,
1278 TD_CLEARING_CACHE,
1279 TD_CLEARED,
1280};
1281
1282struct xhci_td {
1283 struct list_head td_list;
1284 struct list_head cancelled_td_list;
1285 int status;
1286 enum xhci_cancelled_td_status cancel_status;
1287 struct urb *urb;
1288 struct xhci_segment *start_seg;
1289 union xhci_trb *first_trb;
1290 union xhci_trb *last_trb;
1291 struct xhci_segment *last_trb_seg;
1292 struct xhci_segment *bounce_seg;
1293 /* actual_length of the URB has already been set */
1294 bool urb_length_set;
1295 bool error_mid_td;
1296 unsigned int num_trbs;
1297};
1298
1299/*
1300 * xHCI command default timeout value in milliseconds.
1301 * USB 3.2 spec, section 9.2.6.1
1302 */
1303#define XHCI_CMD_DEFAULT_TIMEOUT 5000
1304
1305/* command descriptor */
1306struct xhci_cd {
1307 struct xhci_command *command;
1308 union xhci_trb *cmd_trb;
1309};
1310
1311enum xhci_ring_type {
1312 TYPE_CTRL = 0,
1313 TYPE_ISOC,
1314 TYPE_BULK,
1315 TYPE_INTR,
1316 TYPE_STREAM,
1317 TYPE_COMMAND,
1318 TYPE_EVENT,
1319};
1320
1321static inline const char *xhci_ring_type_string(enum xhci_ring_type type)
1322{
1323 switch (type) {
1324 case TYPE_CTRL:
1325 return "CTRL";
1326 case TYPE_ISOC:
1327 return "ISOC";
1328 case TYPE_BULK:
1329 return "BULK";
1330 case TYPE_INTR:
1331 return "INTR";
1332 case TYPE_STREAM:
1333 return "STREAM";
1334 case TYPE_COMMAND:
1335 return "CMD";
1336 case TYPE_EVENT:
1337 return "EVENT";
1338 }
1339
1340 return "UNKNOWN";
1341}
1342
1343struct xhci_ring {
1344 struct xhci_segment *first_seg;
1345 struct xhci_segment *last_seg;
1346 union xhci_trb *enqueue;
1347 struct xhci_segment *enq_seg;
1348 union xhci_trb *dequeue;
1349 struct xhci_segment *deq_seg;
1350 struct list_head td_list;
1351 /*
1352 * Write the cycle state into the TRB cycle field to give ownership of
1353 * the TRB to the host controller (if we are the producer), or to check
1354 * if we own the TRB (if we are the consumer). See section 4.9.1.
1355 */
1356 u32 cycle_state;
1357 unsigned int stream_id;
1358 unsigned int num_segs;
1359 unsigned int num_trbs_free; /* used only by xhci DbC */
1360 unsigned int bounce_buf_len;
1361 enum xhci_ring_type type;
1362 bool last_td_was_short;
1363 struct radix_tree_root *trb_address_map;
1364};
1365
1366struct xhci_erst_entry {
1367 /* 64-bit event ring segment address */
1368 __le64 seg_addr;
1369 __le32 seg_size;
1370 /* Set to zero */
1371 __le32 rsvd;
1372};
1373
1374struct xhci_erst {
1375 struct xhci_erst_entry *entries;
1376 unsigned int num_entries;
1377 /* xhci->event_ring keeps track of segment dma addresses */
1378 dma_addr_t erst_dma_addr;
1379 /* Num entries the ERST can contain */
1380 unsigned int erst_size;
1381};
1382
1383struct xhci_scratchpad {
1384 u64 *sp_array;
1385 dma_addr_t sp_dma;
1386 void **sp_buffers;
1387};
1388
1389struct urb_priv {
1390 int num_tds;
1391 int num_tds_done;
1392 struct xhci_td td[] __counted_by(num_tds);
1393};
1394
1395/* Number of Event Ring segments to allocate, when amount is not specified. (spec allows 32k) */
1396#define ERST_DEFAULT_SEGS 2
1397/* Poll every 60 seconds */
1398#define POLL_TIMEOUT 60
1399/* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1400#define XHCI_STOP_EP_CMD_TIMEOUT 5
1401/* XXX: Make these module parameters */
1402
1403struct s3_save {
1404 u32 command;
1405 u32 dev_nt;
1406 u64 dcbaa_ptr;
1407 u32 config_reg;
1408};
1409
1410/* Use for lpm */
1411struct dev_info {
1412 u32 dev_id;
1413 struct list_head list;
1414};
1415
1416struct xhci_bus_state {
1417 unsigned long bus_suspended;
1418 unsigned long next_statechange;
1419
1420 /* Port suspend arrays are indexed by the portnum of the fake roothub */
1421 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1422 u32 port_c_suspend;
1423 u32 suspended_ports;
1424 u32 port_remote_wakeup;
1425 /* which ports have started to resume */
1426 unsigned long resuming_ports;
1427};
1428
1429struct xhci_interrupter {
1430 struct xhci_ring *event_ring;
1431 struct xhci_erst erst;
1432 struct xhci_intr_reg __iomem *ir_set;
1433 unsigned int intr_num;
1434 bool ip_autoclear;
1435 u32 isoc_bei_interval;
1436 /* For interrupter registers save and restore over suspend/resume */
1437 u32 s3_irq_pending;
1438 u32 s3_irq_control;
1439 u32 s3_erst_size;
1440 u64 s3_erst_base;
1441 u64 s3_erst_dequeue;
1442};
1443/*
1444 * It can take up to 20 ms to transition from RExit to U0 on the
1445 * Intel Lynx Point LP xHCI host.
1446 */
1447#define XHCI_MAX_REXIT_TIMEOUT_MS 20
1448struct xhci_port_cap {
1449 u32 *psi; /* array of protocol speed ID entries */
1450 u8 psi_count;
1451 u8 psi_uid_count;
1452 u8 maj_rev;
1453 u8 min_rev;
1454};
1455
1456struct xhci_port {
1457 __le32 __iomem *addr;
1458 int hw_portnum;
1459 int hcd_portnum;
1460 struct xhci_hub *rhub;
1461 struct xhci_port_cap *port_cap;
1462 unsigned int lpm_incapable:1;
1463 unsigned long resume_timestamp;
1464 bool rexit_active;
1465 /* Slot ID is the index of the device directly connected to the port */
1466 int slot_id;
1467 struct completion rexit_done;
1468 struct completion u3exit_done;
1469};
1470
1471struct xhci_hub {
1472 struct xhci_port **ports;
1473 unsigned int num_ports;
1474 struct usb_hcd *hcd;
1475 /* keep track of bus suspend info */
1476 struct xhci_bus_state bus_state;
1477 /* supported prococol extended capabiliy values */
1478 u8 maj_rev;
1479 u8 min_rev;
1480};
1481
1482/* There is one xhci_hcd structure per controller */
1483struct xhci_hcd {
1484 struct usb_hcd *main_hcd;
1485 struct usb_hcd *shared_hcd;
1486 /* glue to PCI and HCD framework */
1487 struct xhci_cap_regs __iomem *cap_regs;
1488 struct xhci_op_regs __iomem *op_regs;
1489 struct xhci_run_regs __iomem *run_regs;
1490 struct xhci_doorbell_array __iomem *dba;
1491
1492 /* Cached register copies of read-only HC data */
1493 __u32 hcs_params1;
1494 __u32 hcs_params2;
1495 __u32 hcs_params3;
1496 __u32 hcc_params;
1497 __u32 hcc_params2;
1498
1499 spinlock_t lock;
1500
1501 /* packed release number */
1502 u8 sbrn;
1503 u16 hci_version;
1504 u8 max_slots;
1505 u16 max_interrupters;
1506 u8 max_ports;
1507 u8 isoc_threshold;
1508 /* imod_interval in ns (I * 250ns) */
1509 u32 imod_interval;
1510 int event_ring_max;
1511 /* 4KB min, 128MB max */
1512 int page_size;
1513 /* Valid values are 12 to 20, inclusive */
1514 int page_shift;
1515 /* MSI-X/MSI vectors */
1516 int nvecs;
1517 /* optional clocks */
1518 struct clk *clk;
1519 struct clk *reg_clk;
1520 /* optional reset controller */
1521 struct reset_control *reset;
1522 /* data structures */
1523 struct xhci_device_context_array *dcbaa;
1524 struct xhci_interrupter **interrupters;
1525 struct xhci_ring *cmd_ring;
1526 unsigned int cmd_ring_state;
1527#define CMD_RING_STATE_RUNNING (1 << 0)
1528#define CMD_RING_STATE_ABORTED (1 << 1)
1529#define CMD_RING_STATE_STOPPED (1 << 2)
1530 struct list_head cmd_list;
1531 unsigned int cmd_ring_reserved_trbs;
1532 struct delayed_work cmd_timer;
1533 struct completion cmd_ring_stop_completion;
1534 struct xhci_command *current_cmd;
1535
1536 /* Scratchpad */
1537 struct xhci_scratchpad *scratchpad;
1538
1539 /* slot enabling and address device helpers */
1540 /* these are not thread safe so use mutex */
1541 struct mutex mutex;
1542 /* Internal mirror of the HW's dcbaa */
1543 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1544 /* For keeping track of bandwidth domains per roothub. */
1545 struct xhci_root_port_bw_info *rh_bw;
1546
1547 /* DMA pools */
1548 struct dma_pool *device_pool;
1549 struct dma_pool *segment_pool;
1550 struct dma_pool *small_streams_pool;
1551 struct dma_pool *medium_streams_pool;
1552
1553 /* Host controller watchdog timer structures */
1554 unsigned int xhc_state;
1555 unsigned long run_graceperiod;
1556 struct s3_save s3;
1557/* Host controller is dying - not responding to commands. "I'm not dead yet!"
1558 *
1559 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1560 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1561 * that sees this status (other than the timer that set it) should stop touching
1562 * hardware immediately. Interrupt handlers should return immediately when
1563 * they see this status (any time they drop and re-acquire xhci->lock).
1564 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1565 * putting the TD on the canceled list, etc.
1566 *
1567 * There are no reports of xHCI host controllers that display this issue.
1568 */
1569#define XHCI_STATE_DYING (1 << 0)
1570#define XHCI_STATE_HALTED (1 << 1)
1571#define XHCI_STATE_REMOVING (1 << 2)
1572 unsigned long long quirks;
1573#define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
1574#define XHCI_RESET_EP_QUIRK BIT_ULL(1) /* Deprecated */
1575#define XHCI_NEC_HOST BIT_ULL(2)
1576#define XHCI_AMD_PLL_FIX BIT_ULL(3)
1577#define XHCI_SPURIOUS_SUCCESS BIT_ULL(4)
1578/*
1579 * Certain Intel host controllers have a limit to the number of endpoint
1580 * contexts they can handle. Ideally, they would signal that they can't handle
1581 * anymore endpoint contexts by returning a Resource Error for the Configure
1582 * Endpoint command, but they don't. Instead they expect software to keep track
1583 * of the number of active endpoints for them, across configure endpoint
1584 * commands, reset device commands, disable slot commands, and address device
1585 * commands.
1586 */
1587#define XHCI_EP_LIMIT_QUIRK BIT_ULL(5)
1588#define XHCI_BROKEN_MSI BIT_ULL(6)
1589#define XHCI_RESET_ON_RESUME BIT_ULL(7)
1590#define XHCI_SW_BW_CHECKING BIT_ULL(8)
1591#define XHCI_AMD_0x96_HOST BIT_ULL(9)
1592#define XHCI_TRUST_TX_LENGTH BIT_ULL(10)
1593#define XHCI_LPM_SUPPORT BIT_ULL(11)
1594#define XHCI_INTEL_HOST BIT_ULL(12)
1595#define XHCI_SPURIOUS_REBOOT BIT_ULL(13)
1596#define XHCI_COMP_MODE_QUIRK BIT_ULL(14)
1597#define XHCI_AVOID_BEI BIT_ULL(15)
1598#define XHCI_PLAT BIT_ULL(16) /* Deprecated */
1599#define XHCI_SLOW_SUSPEND BIT_ULL(17)
1600#define XHCI_SPURIOUS_WAKEUP BIT_ULL(18)
1601/* For controllers with a broken beyond repair streams implementation */
1602#define XHCI_BROKEN_STREAMS BIT_ULL(19)
1603#define XHCI_PME_STUCK_QUIRK BIT_ULL(20)
1604#define XHCI_MTK_HOST BIT_ULL(21)
1605#define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
1606#define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
1607#define XHCI_MISSING_CAS BIT_ULL(24)
1608/* For controller with a broken Port Disable implementation */
1609#define XHCI_BROKEN_PORT_PED BIT_ULL(25)
1610#define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
1611#define XHCI_U2_DISABLE_WAKE BIT_ULL(27)
1612#define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28)
1613#define XHCI_HW_LPM_DISABLE BIT_ULL(29)
1614#define XHCI_SUSPEND_DELAY BIT_ULL(30)
1615#define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
1616#define XHCI_ZERO_64B_REGS BIT_ULL(32)
1617#define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33)
1618#define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
1619#define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
1620#define XHCI_RENESAS_FW_QUIRK BIT_ULL(36)
1621#define XHCI_SKIP_PHY_INIT BIT_ULL(37)
1622#define XHCI_DISABLE_SPARSE BIT_ULL(38)
1623#define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39)
1624#define XHCI_NO_SOFT_RETRY BIT_ULL(40)
1625#define XHCI_BROKEN_D3COLD_S2I BIT_ULL(41)
1626#define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42)
1627#define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43)
1628#define XHCI_RESET_TO_DEFAULT BIT_ULL(44)
1629#define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45)
1630#define XHCI_ZHAOXIN_HOST BIT_ULL(46)
1631
1632 unsigned int num_active_eps;
1633 unsigned int limit_active_eps;
1634 struct xhci_port *hw_ports;
1635 struct xhci_hub usb2_rhub;
1636 struct xhci_hub usb3_rhub;
1637 /* support xHCI 1.0 spec USB2 hardware LPM */
1638 unsigned hw_lpm_support:1;
1639 /* Broken Suspend flag for SNPS Suspend resume issue */
1640 unsigned broken_suspend:1;
1641 /* Indicates that omitting hcd is supported if root hub has no ports */
1642 unsigned allow_single_roothub:1;
1643 /* cached usb2 extened protocol capabilites */
1644 u32 *ext_caps;
1645 unsigned int num_ext_caps;
1646 /* cached extended protocol port capabilities */
1647 struct xhci_port_cap *port_caps;
1648 unsigned int num_port_caps;
1649 /* Compliance Mode Recovery Data */
1650 struct timer_list comp_mode_recovery_timer;
1651 u32 port_status_u0;
1652 u16 test_mode;
1653/* Compliance Mode Timer Triggered every 2 seconds */
1654#define COMP_MODE_RCVRY_MSECS 2000
1655
1656 struct dentry *debugfs_root;
1657 struct dentry *debugfs_slots;
1658 struct list_head regset_list;
1659
1660 void *dbc;
1661 /* platform-specific data -- must come last */
1662 unsigned long priv[] __aligned(sizeof(s64));
1663};
1664
1665/* Platform specific overrides to generic XHCI hc_driver ops */
1666struct xhci_driver_overrides {
1667 size_t extra_priv_size;
1668 int (*reset)(struct usb_hcd *hcd);
1669 int (*start)(struct usb_hcd *hcd);
1670 int (*add_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
1671 struct usb_host_endpoint *ep);
1672 int (*drop_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
1673 struct usb_host_endpoint *ep);
1674 int (*check_bandwidth)(struct usb_hcd *, struct usb_device *);
1675 void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);
1676 int (*update_hub_device)(struct usb_hcd *hcd, struct usb_device *hdev,
1677 struct usb_tt *tt, gfp_t mem_flags);
1678 int (*hub_control)(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1679 u16 wIndex, char *buf, u16 wLength);
1680};
1681
1682#define XHCI_CFC_DELAY 10
1683
1684/* convert between an HCD pointer and the corresponding EHCI_HCD */
1685static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1686{
1687 struct usb_hcd *primary_hcd;
1688
1689 if (usb_hcd_is_primary_hcd(hcd))
1690 primary_hcd = hcd;
1691 else
1692 primary_hcd = hcd->primary_hcd;
1693
1694 return (struct xhci_hcd *) (primary_hcd->hcd_priv);
1695}
1696
1697static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1698{
1699 return xhci->main_hcd;
1700}
1701
1702static inline struct usb_hcd *xhci_get_usb3_hcd(struct xhci_hcd *xhci)
1703{
1704 if (xhci->shared_hcd)
1705 return xhci->shared_hcd;
1706
1707 if (!xhci->usb2_rhub.num_ports)
1708 return xhci->main_hcd;
1709
1710 return NULL;
1711}
1712
1713static inline bool xhci_hcd_is_usb3(struct usb_hcd *hcd)
1714{
1715 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1716
1717 return hcd == xhci_get_usb3_hcd(xhci);
1718}
1719
1720static inline bool xhci_has_one_roothub(struct xhci_hcd *xhci)
1721{
1722 return xhci->allow_single_roothub &&
1723 (!xhci->usb2_rhub.num_ports || !xhci->usb3_rhub.num_ports);
1724}
1725
1726#define xhci_dbg(xhci, fmt, args...) \
1727 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1728#define xhci_err(xhci, fmt, args...) \
1729 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1730#define xhci_warn(xhci, fmt, args...) \
1731 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1732#define xhci_warn_ratelimited(xhci, fmt, args...) \
1733 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1734#define xhci_info(xhci, fmt, args...) \
1735 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1736
1737/*
1738 * Registers should always be accessed with double word or quad word accesses.
1739 *
1740 * Some xHCI implementations may support 64-bit address pointers. Registers
1741 * with 64-bit address pointers should be written to with dword accesses by
1742 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1743 * xHCI implementations that do not support 64-bit address pointers will ignore
1744 * the high dword, and write order is irrelevant.
1745 */
1746static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1747 __le64 __iomem *regs)
1748{
1749 return lo_hi_readq(regs);
1750}
1751static inline void xhci_write_64(struct xhci_hcd *xhci,
1752 const u64 val, __le64 __iomem *regs)
1753{
1754 lo_hi_writeq(val, regs);
1755}
1756
1757static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1758{
1759 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
1760}
1761
1762/* xHCI debugging */
1763char *xhci_get_slot_state(struct xhci_hcd *xhci,
1764 struct xhci_container_ctx *ctx);
1765void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
1766 const char *fmt, ...);
1767
1768/* xHCI memory management */
1769void xhci_mem_cleanup(struct xhci_hcd *xhci);
1770int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1771void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1772int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1773int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1774void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1775 struct usb_device *udev);
1776unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1777unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1778void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1779void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1780 struct xhci_virt_device *virt_dev,
1781 int old_active_eps);
1782void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1783void xhci_update_bw_info(struct xhci_hcd *xhci,
1784 struct xhci_container_ctx *in_ctx,
1785 struct xhci_input_control_ctx *ctrl_ctx,
1786 struct xhci_virt_device *virt_dev);
1787void xhci_endpoint_copy(struct xhci_hcd *xhci,
1788 struct xhci_container_ctx *in_ctx,
1789 struct xhci_container_ctx *out_ctx,
1790 unsigned int ep_index);
1791void xhci_slot_copy(struct xhci_hcd *xhci,
1792 struct xhci_container_ctx *in_ctx,
1793 struct xhci_container_ctx *out_ctx);
1794int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1795 struct usb_device *udev, struct usb_host_endpoint *ep,
1796 gfp_t mem_flags);
1797struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
1798 unsigned int num_segs, unsigned int cycle_state,
1799 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags);
1800void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1801int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
1802 unsigned int num_trbs, gfp_t flags);
1803void xhci_initialize_ring_info(struct xhci_ring *ring,
1804 unsigned int cycle_state);
1805void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
1806 struct xhci_virt_device *virt_dev,
1807 unsigned int ep_index);
1808struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1809 unsigned int num_stream_ctxs,
1810 unsigned int num_streams,
1811 unsigned int max_packet, gfp_t flags);
1812void xhci_free_stream_info(struct xhci_hcd *xhci,
1813 struct xhci_stream_info *stream_info);
1814void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1815 struct xhci_ep_ctx *ep_ctx,
1816 struct xhci_stream_info *stream_info);
1817void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
1818 struct xhci_virt_ep *ep);
1819void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
1820 struct xhci_virt_device *virt_dev, bool drop_control_ep);
1821struct xhci_ring *xhci_dma_to_transfer_ring(
1822 struct xhci_virt_ep *ep,
1823 u64 address);
1824struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1825 bool allocate_completion, gfp_t mem_flags);
1826struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
1827 bool allocate_completion, gfp_t mem_flags);
1828void xhci_urb_free_priv(struct urb_priv *urb_priv);
1829void xhci_free_command(struct xhci_hcd *xhci,
1830 struct xhci_command *command);
1831struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
1832 int type, gfp_t flags);
1833void xhci_free_container_ctx(struct xhci_hcd *xhci,
1834 struct xhci_container_ctx *ctx);
1835struct xhci_interrupter *
1836xhci_create_secondary_interrupter(struct usb_hcd *hcd, unsigned int segs);
1837void xhci_remove_secondary_interrupter(struct usb_hcd
1838 *hcd, struct xhci_interrupter *ir);
1839
1840/* xHCI host controller glue */
1841typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
1842int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us);
1843int xhci_handshake_check_state(struct xhci_hcd *xhci, void __iomem *ptr,
1844 u32 mask, u32 done, int usec, unsigned int exit_state);
1845void xhci_quiesce(struct xhci_hcd *xhci);
1846int xhci_halt(struct xhci_hcd *xhci);
1847int xhci_start(struct xhci_hcd *xhci);
1848int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us);
1849int xhci_run(struct usb_hcd *hcd);
1850int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
1851void xhci_shutdown(struct usb_hcd *hcd);
1852void xhci_stop(struct usb_hcd *hcd);
1853void xhci_init_driver(struct hc_driver *drv,
1854 const struct xhci_driver_overrides *over);
1855int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1856 struct usb_host_endpoint *ep);
1857int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1858 struct usb_host_endpoint *ep);
1859int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1860void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1861int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
1862 struct usb_tt *tt, gfp_t mem_flags);
1863int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id);
1864int xhci_ext_cap_init(struct xhci_hcd *xhci);
1865
1866int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
1867int xhci_resume(struct xhci_hcd *xhci, pm_message_t msg);
1868
1869irqreturn_t xhci_irq(struct usb_hcd *hcd);
1870irqreturn_t xhci_msi_irq(int irq, void *hcd);
1871int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1872int xhci_alloc_tt_info(struct xhci_hcd *xhci,
1873 struct xhci_virt_device *virt_dev,
1874 struct usb_device *hdev,
1875 struct usb_tt *tt, gfp_t mem_flags);
1876
1877/* xHCI ring, segment, TRB, and TD functions */
1878dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
1879struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1880 struct xhci_segment *start_seg, union xhci_trb *start_trb,
1881 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug);
1882int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
1883void xhci_ring_cmd_db(struct xhci_hcd *xhci);
1884int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
1885 u32 trb_type, u32 slot_id);
1886int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
1887 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev);
1888int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
1889 u32 field1, u32 field2, u32 field3, u32 field4);
1890int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
1891 int slot_id, unsigned int ep_index, int suspend);
1892int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1893 int slot_id, unsigned int ep_index);
1894int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1895 int slot_id, unsigned int ep_index);
1896int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1897 int slot_id, unsigned int ep_index);
1898int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
1899 struct urb *urb, int slot_id, unsigned int ep_index);
1900int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
1901 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id,
1902 bool command_must_succeed);
1903int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
1904 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed);
1905int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
1906 int slot_id, unsigned int ep_index,
1907 enum xhci_ep_reset_type reset_type);
1908int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
1909 u32 slot_id);
1910void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int slot_id,
1911 unsigned int ep_index, unsigned int stream_id,
1912 struct xhci_td *td);
1913void xhci_stop_endpoint_command_watchdog(struct timer_list *t);
1914void xhci_handle_command_timeout(struct work_struct *work);
1915
1916void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
1917 unsigned int ep_index, unsigned int stream_id);
1918void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
1919 unsigned int slot_id,
1920 unsigned int ep_index);
1921void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
1922void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring);
1923unsigned int count_trbs(u64 addr, u64 len);
1924
1925/* xHCI roothub code */
1926void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
1927 u32 link_state);
1928void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
1929 u32 port_bit);
1930int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1931 char *buf, u16 wLength);
1932int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
1933int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
1934struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd);
1935
1936void xhci_hc_died(struct xhci_hcd *xhci);
1937
1938#ifdef CONFIG_PM
1939int xhci_bus_suspend(struct usb_hcd *hcd);
1940int xhci_bus_resume(struct usb_hcd *hcd);
1941unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd);
1942#else
1943#define xhci_bus_suspend NULL
1944#define xhci_bus_resume NULL
1945#define xhci_get_resuming_ports NULL
1946#endif /* CONFIG_PM */
1947
1948u32 xhci_port_state_to_neutral(u32 state);
1949void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
1950
1951/* xHCI contexts */
1952struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
1953struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1954struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1955
1956struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
1957 unsigned int slot_id, unsigned int ep_index,
1958 unsigned int stream_id);
1959
1960static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
1961 struct urb *urb)
1962{
1963 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
1964 xhci_get_endpoint_index(&urb->ep->desc),
1965 urb->stream_id);
1966}
1967
1968/*
1969 * TODO: As per spec Isochronous IDT transmissions are supported. We bypass
1970 * them anyways as we where unable to find a device that matches the
1971 * constraints.
1972 */
1973static inline bool xhci_urb_suitable_for_idt(struct urb *urb)
1974{
1975 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) &&
1976 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE &&
1977 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE &&
1978 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) &&
1979 !urb->num_sgs)
1980 return true;
1981
1982 return false;
1983}
1984
1985static inline char *xhci_slot_state_string(u32 state)
1986{
1987 switch (state) {
1988 case SLOT_STATE_ENABLED:
1989 return "enabled/disabled";
1990 case SLOT_STATE_DEFAULT:
1991 return "default";
1992 case SLOT_STATE_ADDRESSED:
1993 return "addressed";
1994 case SLOT_STATE_CONFIGURED:
1995 return "configured";
1996 default:
1997 return "reserved";
1998 }
1999}
2000
2001static inline const char *xhci_decode_trb(char *str, size_t size,
2002 u32 field0, u32 field1, u32 field2, u32 field3)
2003{
2004 int type = TRB_FIELD_TO_TYPE(field3);
2005
2006 switch (type) {
2007 case TRB_LINK:
2008 snprintf(str, size,
2009 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c",
2010 field1, field0, GET_INTR_TARGET(field2),
2011 xhci_trb_type_string(type),
2012 field3 & TRB_IOC ? 'I' : 'i',
2013 field3 & TRB_CHAIN ? 'C' : 'c',
2014 field3 & TRB_TC ? 'T' : 't',
2015 field3 & TRB_CYCLE ? 'C' : 'c');
2016 break;
2017 case TRB_TRANSFER:
2018 case TRB_COMPLETION:
2019 case TRB_PORT_STATUS:
2020 case TRB_BANDWIDTH_EVENT:
2021 case TRB_DOORBELL:
2022 case TRB_HC_EVENT:
2023 case TRB_DEV_NOTE:
2024 case TRB_MFINDEX_WRAP:
2025 snprintf(str, size,
2026 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c",
2027 field1, field0,
2028 xhci_trb_comp_code_string(GET_COMP_CODE(field2)),
2029 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3),
2030 /* Macro decrements 1, maybe it shouldn't?!? */
2031 TRB_TO_EP_INDEX(field3) + 1,
2032 xhci_trb_type_string(type),
2033 field3 & EVENT_DATA ? 'E' : 'e',
2034 field3 & TRB_CYCLE ? 'C' : 'c');
2035
2036 break;
2037 case TRB_SETUP:
2038 snprintf(str, size,
2039 "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c",
2040 field0 & 0xff,
2041 (field0 & 0xff00) >> 8,
2042 (field0 & 0xff000000) >> 24,
2043 (field0 & 0xff0000) >> 16,
2044 (field1 & 0xff00) >> 8,
2045 field1 & 0xff,
2046 (field1 & 0xff000000) >> 16 |
2047 (field1 & 0xff0000) >> 16,
2048 TRB_LEN(field2), GET_TD_SIZE(field2),
2049 GET_INTR_TARGET(field2),
2050 xhci_trb_type_string(type),
2051 field3 & TRB_IDT ? 'I' : 'i',
2052 field3 & TRB_IOC ? 'I' : 'i',
2053 field3 & TRB_CYCLE ? 'C' : 'c');
2054 break;
2055 case TRB_DATA:
2056 snprintf(str, size,
2057 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c",
2058 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2059 GET_INTR_TARGET(field2),
2060 xhci_trb_type_string(type),
2061 field3 & TRB_IDT ? 'I' : 'i',
2062 field3 & TRB_IOC ? 'I' : 'i',
2063 field3 & TRB_CHAIN ? 'C' : 'c',
2064 field3 & TRB_NO_SNOOP ? 'S' : 's',
2065 field3 & TRB_ISP ? 'I' : 'i',
2066 field3 & TRB_ENT ? 'E' : 'e',
2067 field3 & TRB_CYCLE ? 'C' : 'c');
2068 break;
2069 case TRB_STATUS:
2070 snprintf(str, size,
2071 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c",
2072 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2073 GET_INTR_TARGET(field2),
2074 xhci_trb_type_string(type),
2075 field3 & TRB_IOC ? 'I' : 'i',
2076 field3 & TRB_CHAIN ? 'C' : 'c',
2077 field3 & TRB_ENT ? 'E' : 'e',
2078 field3 & TRB_CYCLE ? 'C' : 'c');
2079 break;
2080 case TRB_NORMAL:
2081 case TRB_ISOC:
2082 case TRB_EVENT_DATA:
2083 case TRB_TR_NOOP:
2084 snprintf(str, size,
2085 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c",
2086 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2087 GET_INTR_TARGET(field2),
2088 xhci_trb_type_string(type),
2089 field3 & TRB_BEI ? 'B' : 'b',
2090 field3 & TRB_IDT ? 'I' : 'i',
2091 field3 & TRB_IOC ? 'I' : 'i',
2092 field3 & TRB_CHAIN ? 'C' : 'c',
2093 field3 & TRB_NO_SNOOP ? 'S' : 's',
2094 field3 & TRB_ISP ? 'I' : 'i',
2095 field3 & TRB_ENT ? 'E' : 'e',
2096 field3 & TRB_CYCLE ? 'C' : 'c');
2097 break;
2098
2099 case TRB_CMD_NOOP:
2100 case TRB_ENABLE_SLOT:
2101 snprintf(str, size,
2102 "%s: flags %c",
2103 xhci_trb_type_string(type),
2104 field3 & TRB_CYCLE ? 'C' : 'c');
2105 break;
2106 case TRB_DISABLE_SLOT:
2107 case TRB_NEG_BANDWIDTH:
2108 snprintf(str, size,
2109 "%s: slot %d flags %c",
2110 xhci_trb_type_string(type),
2111 TRB_TO_SLOT_ID(field3),
2112 field3 & TRB_CYCLE ? 'C' : 'c');
2113 break;
2114 case TRB_ADDR_DEV:
2115 snprintf(str, size,
2116 "%s: ctx %08x%08x slot %d flags %c:%c",
2117 xhci_trb_type_string(type),
2118 field1, field0,
2119 TRB_TO_SLOT_ID(field3),
2120 field3 & TRB_BSR ? 'B' : 'b',
2121 field3 & TRB_CYCLE ? 'C' : 'c');
2122 break;
2123 case TRB_CONFIG_EP:
2124 snprintf(str, size,
2125 "%s: ctx %08x%08x slot %d flags %c:%c",
2126 xhci_trb_type_string(type),
2127 field1, field0,
2128 TRB_TO_SLOT_ID(field3),
2129 field3 & TRB_DC ? 'D' : 'd',
2130 field3 & TRB_CYCLE ? 'C' : 'c');
2131 break;
2132 case TRB_EVAL_CONTEXT:
2133 snprintf(str, size,
2134 "%s: ctx %08x%08x slot %d flags %c",
2135 xhci_trb_type_string(type),
2136 field1, field0,
2137 TRB_TO_SLOT_ID(field3),
2138 field3 & TRB_CYCLE ? 'C' : 'c');
2139 break;
2140 case TRB_RESET_EP:
2141 snprintf(str, size,
2142 "%s: ctx %08x%08x slot %d ep %d flags %c:%c",
2143 xhci_trb_type_string(type),
2144 field1, field0,
2145 TRB_TO_SLOT_ID(field3),
2146 /* Macro decrements 1, maybe it shouldn't?!? */
2147 TRB_TO_EP_INDEX(field3) + 1,
2148 field3 & TRB_TSP ? 'T' : 't',
2149 field3 & TRB_CYCLE ? 'C' : 'c');
2150 break;
2151 case TRB_STOP_RING:
2152 snprintf(str, size,
2153 "%s: slot %d sp %d ep %d flags %c",
2154 xhci_trb_type_string(type),
2155 TRB_TO_SLOT_ID(field3),
2156 TRB_TO_SUSPEND_PORT(field3),
2157 /* Macro decrements 1, maybe it shouldn't?!? */
2158 TRB_TO_EP_INDEX(field3) + 1,
2159 field3 & TRB_CYCLE ? 'C' : 'c');
2160 break;
2161 case TRB_SET_DEQ:
2162 snprintf(str, size,
2163 "%s: deq %08x%08x stream %d slot %d ep %d flags %c",
2164 xhci_trb_type_string(type),
2165 field1, field0,
2166 TRB_TO_STREAM_ID(field2),
2167 TRB_TO_SLOT_ID(field3),
2168 /* Macro decrements 1, maybe it shouldn't?!? */
2169 TRB_TO_EP_INDEX(field3) + 1,
2170 field3 & TRB_CYCLE ? 'C' : 'c');
2171 break;
2172 case TRB_RESET_DEV:
2173 snprintf(str, size,
2174 "%s: slot %d flags %c",
2175 xhci_trb_type_string(type),
2176 TRB_TO_SLOT_ID(field3),
2177 field3 & TRB_CYCLE ? 'C' : 'c');
2178 break;
2179 case TRB_FORCE_EVENT:
2180 snprintf(str, size,
2181 "%s: event %08x%08x vf intr %d vf id %d flags %c",
2182 xhci_trb_type_string(type),
2183 field1, field0,
2184 TRB_TO_VF_INTR_TARGET(field2),
2185 TRB_TO_VF_ID(field3),
2186 field3 & TRB_CYCLE ? 'C' : 'c');
2187 break;
2188 case TRB_SET_LT:
2189 snprintf(str, size,
2190 "%s: belt %d flags %c",
2191 xhci_trb_type_string(type),
2192 TRB_TO_BELT(field3),
2193 field3 & TRB_CYCLE ? 'C' : 'c');
2194 break;
2195 case TRB_GET_BW:
2196 snprintf(str, size,
2197 "%s: ctx %08x%08x slot %d speed %d flags %c",
2198 xhci_trb_type_string(type),
2199 field1, field0,
2200 TRB_TO_SLOT_ID(field3),
2201 TRB_TO_DEV_SPEED(field3),
2202 field3 & TRB_CYCLE ? 'C' : 'c');
2203 break;
2204 case TRB_FORCE_HEADER:
2205 snprintf(str, size,
2206 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c",
2207 xhci_trb_type_string(type),
2208 field2, field1, field0 & 0xffffffe0,
2209 TRB_TO_PACKET_TYPE(field0),
2210 TRB_TO_ROOTHUB_PORT(field3),
2211 field3 & TRB_CYCLE ? 'C' : 'c');
2212 break;
2213 default:
2214 snprintf(str, size,
2215 "type '%s' -> raw %08x %08x %08x %08x",
2216 xhci_trb_type_string(type),
2217 field0, field1, field2, field3);
2218 }
2219
2220 return str;
2221}
2222
2223static inline const char *xhci_decode_ctrl_ctx(char *str,
2224 unsigned long drop, unsigned long add)
2225{
2226 unsigned int bit;
2227 int ret = 0;
2228
2229 str[0] = '\0';
2230
2231 if (drop) {
2232 ret = sprintf(str, "Drop:");
2233 for_each_set_bit(bit, &drop, 32)
2234 ret += sprintf(str + ret, " %d%s",
2235 bit / 2,
2236 bit % 2 ? "in":"out");
2237 ret += sprintf(str + ret, ", ");
2238 }
2239
2240 if (add) {
2241 ret += sprintf(str + ret, "Add:%s%s",
2242 (add & SLOT_FLAG) ? " slot":"",
2243 (add & EP0_FLAG) ? " ep0":"");
2244 add &= ~(SLOT_FLAG | EP0_FLAG);
2245 for_each_set_bit(bit, &add, 32)
2246 ret += sprintf(str + ret, " %d%s",
2247 bit / 2,
2248 bit % 2 ? "in":"out");
2249 }
2250 return str;
2251}
2252
2253static inline const char *xhci_decode_slot_context(char *str,
2254 u32 info, u32 info2, u32 tt_info, u32 state)
2255{
2256 u32 speed;
2257 u32 hub;
2258 u32 mtt;
2259 int ret = 0;
2260
2261 speed = info & DEV_SPEED;
2262 hub = info & DEV_HUB;
2263 mtt = info & DEV_MTT;
2264
2265 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d",
2266 info & ROUTE_STRING_MASK,
2267 ({ char *s;
2268 switch (speed) {
2269 case SLOT_SPEED_FS:
2270 s = "full-speed";
2271 break;
2272 case SLOT_SPEED_LS:
2273 s = "low-speed";
2274 break;
2275 case SLOT_SPEED_HS:
2276 s = "high-speed";
2277 break;
2278 case SLOT_SPEED_SS:
2279 s = "super-speed";
2280 break;
2281 case SLOT_SPEED_SSP:
2282 s = "super-speed plus";
2283 break;
2284 default:
2285 s = "UNKNOWN speed";
2286 } s; }),
2287 mtt ? " multi-TT" : "",
2288 hub ? " Hub" : "",
2289 (info & LAST_CTX_MASK) >> 27,
2290 info2 & MAX_EXIT,
2291 DEVINFO_TO_ROOT_HUB_PORT(info2),
2292 DEVINFO_TO_MAX_PORTS(info2));
2293
2294 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s",
2295 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8,
2296 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info),
2297 state & DEV_ADDR_MASK,
2298 xhci_slot_state_string(GET_SLOT_STATE(state)));
2299
2300 return str;
2301}
2302
2303
2304static inline const char *xhci_portsc_link_state_string(u32 portsc)
2305{
2306 switch (portsc & PORT_PLS_MASK) {
2307 case XDEV_U0:
2308 return "U0";
2309 case XDEV_U1:
2310 return "U1";
2311 case XDEV_U2:
2312 return "U2";
2313 case XDEV_U3:
2314 return "U3";
2315 case XDEV_DISABLED:
2316 return "Disabled";
2317 case XDEV_RXDETECT:
2318 return "RxDetect";
2319 case XDEV_INACTIVE:
2320 return "Inactive";
2321 case XDEV_POLLING:
2322 return "Polling";
2323 case XDEV_RECOVERY:
2324 return "Recovery";
2325 case XDEV_HOT_RESET:
2326 return "Hot Reset";
2327 case XDEV_COMP_MODE:
2328 return "Compliance mode";
2329 case XDEV_TEST_MODE:
2330 return "Test mode";
2331 case XDEV_RESUME:
2332 return "Resume";
2333 default:
2334 break;
2335 }
2336 return "Unknown";
2337}
2338
2339static inline const char *xhci_decode_portsc(char *str, u32 portsc)
2340{
2341 int ret;
2342
2343 ret = sprintf(str, "%s %s %s Link:%s PortSpeed:%d ",
2344 portsc & PORT_POWER ? "Powered" : "Powered-off",
2345 portsc & PORT_CONNECT ? "Connected" : "Not-connected",
2346 portsc & PORT_PE ? "Enabled" : "Disabled",
2347 xhci_portsc_link_state_string(portsc),
2348 DEV_PORT_SPEED(portsc));
2349
2350 if (portsc & PORT_OC)
2351 ret += sprintf(str + ret, "OverCurrent ");
2352 if (portsc & PORT_RESET)
2353 ret += sprintf(str + ret, "In-Reset ");
2354
2355 ret += sprintf(str + ret, "Change: ");
2356 if (portsc & PORT_CSC)
2357 ret += sprintf(str + ret, "CSC ");
2358 if (portsc & PORT_PEC)
2359 ret += sprintf(str + ret, "PEC ");
2360 if (portsc & PORT_WRC)
2361 ret += sprintf(str + ret, "WRC ");
2362 if (portsc & PORT_OCC)
2363 ret += sprintf(str + ret, "OCC ");
2364 if (portsc & PORT_RC)
2365 ret += sprintf(str + ret, "PRC ");
2366 if (portsc & PORT_PLC)
2367 ret += sprintf(str + ret, "PLC ");
2368 if (portsc & PORT_CEC)
2369 ret += sprintf(str + ret, "CEC ");
2370 if (portsc & PORT_CAS)
2371 ret += sprintf(str + ret, "CAS ");
2372
2373 ret += sprintf(str + ret, "Wake: ");
2374 if (portsc & PORT_WKCONN_E)
2375 ret += sprintf(str + ret, "WCE ");
2376 if (portsc & PORT_WKDISC_E)
2377 ret += sprintf(str + ret, "WDE ");
2378 if (portsc & PORT_WKOC_E)
2379 ret += sprintf(str + ret, "WOE ");
2380
2381 return str;
2382}
2383
2384static inline const char *xhci_decode_usbsts(char *str, u32 usbsts)
2385{
2386 int ret = 0;
2387
2388 ret = sprintf(str, " 0x%08x", usbsts);
2389
2390 if (usbsts == ~(u32)0)
2391 return str;
2392
2393 if (usbsts & STS_HALT)
2394 ret += sprintf(str + ret, " HCHalted");
2395 if (usbsts & STS_FATAL)
2396 ret += sprintf(str + ret, " HSE");
2397 if (usbsts & STS_EINT)
2398 ret += sprintf(str + ret, " EINT");
2399 if (usbsts & STS_PORT)
2400 ret += sprintf(str + ret, " PCD");
2401 if (usbsts & STS_SAVE)
2402 ret += sprintf(str + ret, " SSS");
2403 if (usbsts & STS_RESTORE)
2404 ret += sprintf(str + ret, " RSS");
2405 if (usbsts & STS_SRE)
2406 ret += sprintf(str + ret, " SRE");
2407 if (usbsts & STS_CNR)
2408 ret += sprintf(str + ret, " CNR");
2409 if (usbsts & STS_HCE)
2410 ret += sprintf(str + ret, " HCE");
2411
2412 return str;
2413}
2414
2415static inline const char *xhci_decode_doorbell(char *str, u32 slot, u32 doorbell)
2416{
2417 u8 ep;
2418 u16 stream;
2419 int ret;
2420
2421 ep = (doorbell & 0xff);
2422 stream = doorbell >> 16;
2423
2424 if (slot == 0) {
2425 sprintf(str, "Command Ring %d", doorbell);
2426 return str;
2427 }
2428 ret = sprintf(str, "Slot %d ", slot);
2429 if (ep > 0 && ep < 32)
2430 ret = sprintf(str + ret, "ep%d%s",
2431 ep / 2,
2432 ep % 2 ? "in" : "out");
2433 else if (ep == 0 || ep < 248)
2434 ret = sprintf(str + ret, "Reserved %d", ep);
2435 else
2436 ret = sprintf(str + ret, "Vendor Defined %d", ep);
2437 if (stream)
2438 ret = sprintf(str + ret, " Stream %d", stream);
2439
2440 return str;
2441}
2442
2443static inline const char *xhci_ep_state_string(u8 state)
2444{
2445 switch (state) {
2446 case EP_STATE_DISABLED:
2447 return "disabled";
2448 case EP_STATE_RUNNING:
2449 return "running";
2450 case EP_STATE_HALTED:
2451 return "halted";
2452 case EP_STATE_STOPPED:
2453 return "stopped";
2454 case EP_STATE_ERROR:
2455 return "error";
2456 default:
2457 return "INVALID";
2458 }
2459}
2460
2461static inline const char *xhci_ep_type_string(u8 type)
2462{
2463 switch (type) {
2464 case ISOC_OUT_EP:
2465 return "Isoc OUT";
2466 case BULK_OUT_EP:
2467 return "Bulk OUT";
2468 case INT_OUT_EP:
2469 return "Int OUT";
2470 case CTRL_EP:
2471 return "Ctrl";
2472 case ISOC_IN_EP:
2473 return "Isoc IN";
2474 case BULK_IN_EP:
2475 return "Bulk IN";
2476 case INT_IN_EP:
2477 return "Int IN";
2478 default:
2479 return "INVALID";
2480 }
2481}
2482
2483static inline const char *xhci_decode_ep_context(char *str, u32 info,
2484 u32 info2, u64 deq, u32 tx_info)
2485{
2486 int ret;
2487
2488 u32 esit;
2489 u16 maxp;
2490 u16 avg;
2491
2492 u8 max_pstr;
2493 u8 ep_state;
2494 u8 interval;
2495 u8 ep_type;
2496 u8 burst;
2497 u8 cerr;
2498 u8 mult;
2499
2500 bool lsa;
2501 bool hid;
2502
2503 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 |
2504 CTX_TO_MAX_ESIT_PAYLOAD(tx_info);
2505
2506 ep_state = info & EP_STATE_MASK;
2507 max_pstr = CTX_TO_EP_MAXPSTREAMS(info);
2508 interval = CTX_TO_EP_INTERVAL(info);
2509 mult = CTX_TO_EP_MULT(info) + 1;
2510 lsa = !!(info & EP_HAS_LSA);
2511
2512 cerr = (info2 & (3 << 1)) >> 1;
2513 ep_type = CTX_TO_EP_TYPE(info2);
2514 hid = !!(info2 & (1 << 7));
2515 burst = CTX_TO_MAX_BURST(info2);
2516 maxp = MAX_PACKET_DECODED(info2);
2517
2518 avg = EP_AVG_TRB_LENGTH(tx_info);
2519
2520 ret = sprintf(str, "State %s mult %d max P. Streams %d %s",
2521 xhci_ep_state_string(ep_state), mult,
2522 max_pstr, lsa ? "LSA " : "");
2523
2524 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ",
2525 (1 << interval) * 125, esit, cerr);
2526
2527 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ",
2528 xhci_ep_type_string(ep_type), hid ? "HID" : "",
2529 burst, maxp, deq);
2530
2531 ret += sprintf(str + ret, "avg trb len %d", avg);
2532
2533 return str;
2534}
2535
2536#endif /* __LINUX_XHCI_HCD_H */