Loading...
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Freescale linflexuart serial port driver
4 *
5 * Copyright 2012-2016 Freescale Semiconductor, Inc.
6 * Copyright 2017-2019 NXP
7 */
8
9#if defined(CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE) && \
10 defined(CONFIG_MAGIC_SYSRQ)
11#define SUPPORT_SYSRQ
12#endif
13
14#include <linux/console.h>
15#include <linux/io.h>
16#include <linux/irq.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/of_device.h>
20#include <linux/serial_core.h>
21#include <linux/slab.h>
22#include <linux/tty_flip.h>
23#include <linux/delay.h>
24
25/* All registers are 32-bit width */
26
27#define LINCR1 0x0000 /* LIN control register */
28#define LINIER 0x0004 /* LIN interrupt enable register */
29#define LINSR 0x0008 /* LIN status register */
30#define LINESR 0x000C /* LIN error status register */
31#define UARTCR 0x0010 /* UART mode control register */
32#define UARTSR 0x0014 /* UART mode status register */
33#define LINTCSR 0x0018 /* LIN timeout control status register */
34#define LINOCR 0x001C /* LIN output compare register */
35#define LINTOCR 0x0020 /* LIN timeout control register */
36#define LINFBRR 0x0024 /* LIN fractional baud rate register */
37#define LINIBRR 0x0028 /* LIN integer baud rate register */
38#define LINCFR 0x002C /* LIN checksum field register */
39#define LINCR2 0x0030 /* LIN control register 2 */
40#define BIDR 0x0034 /* Buffer identifier register */
41#define BDRL 0x0038 /* Buffer data register least significant */
42#define BDRM 0x003C /* Buffer data register most significant */
43#define IFER 0x0040 /* Identifier filter enable register */
44#define IFMI 0x0044 /* Identifier filter match index */
45#define IFMR 0x0048 /* Identifier filter mode register */
46#define GCR 0x004C /* Global control register */
47#define UARTPTO 0x0050 /* UART preset timeout register */
48#define UARTCTO 0x0054 /* UART current timeout register */
49
50/*
51 * Register field definitions
52 */
53
54#define LINFLEXD_LINCR1_INIT BIT(0)
55#define LINFLEXD_LINCR1_MME BIT(4)
56#define LINFLEXD_LINCR1_BF BIT(7)
57
58#define LINFLEXD_LINSR_LINS_INITMODE BIT(12)
59#define LINFLEXD_LINSR_LINS_MASK (0xF << 12)
60
61#define LINFLEXD_LINIER_SZIE BIT(15)
62#define LINFLEXD_LINIER_OCIE BIT(14)
63#define LINFLEXD_LINIER_BEIE BIT(13)
64#define LINFLEXD_LINIER_CEIE BIT(12)
65#define LINFLEXD_LINIER_HEIE BIT(11)
66#define LINFLEXD_LINIER_FEIE BIT(8)
67#define LINFLEXD_LINIER_BOIE BIT(7)
68#define LINFLEXD_LINIER_LSIE BIT(6)
69#define LINFLEXD_LINIER_WUIE BIT(5)
70#define LINFLEXD_LINIER_DBFIE BIT(4)
71#define LINFLEXD_LINIER_DBEIETOIE BIT(3)
72#define LINFLEXD_LINIER_DRIE BIT(2)
73#define LINFLEXD_LINIER_DTIE BIT(1)
74#define LINFLEXD_LINIER_HRIE BIT(0)
75
76#define LINFLEXD_UARTCR_OSR_MASK (0xF << 24)
77#define LINFLEXD_UARTCR_OSR(uartcr) (((uartcr) \
78 & LINFLEXD_UARTCR_OSR_MASK) >> 24)
79
80#define LINFLEXD_UARTCR_ROSE BIT(23)
81
82#define LINFLEXD_UARTCR_RFBM BIT(9)
83#define LINFLEXD_UARTCR_TFBM BIT(8)
84#define LINFLEXD_UARTCR_WL1 BIT(7)
85#define LINFLEXD_UARTCR_PC1 BIT(6)
86
87#define LINFLEXD_UARTCR_RXEN BIT(5)
88#define LINFLEXD_UARTCR_TXEN BIT(4)
89#define LINFLEXD_UARTCR_PC0 BIT(3)
90
91#define LINFLEXD_UARTCR_PCE BIT(2)
92#define LINFLEXD_UARTCR_WL0 BIT(1)
93#define LINFLEXD_UARTCR_UART BIT(0)
94
95#define LINFLEXD_UARTSR_SZF BIT(15)
96#define LINFLEXD_UARTSR_OCF BIT(14)
97#define LINFLEXD_UARTSR_PE3 BIT(13)
98#define LINFLEXD_UARTSR_PE2 BIT(12)
99#define LINFLEXD_UARTSR_PE1 BIT(11)
100#define LINFLEXD_UARTSR_PE0 BIT(10)
101#define LINFLEXD_UARTSR_RMB BIT(9)
102#define LINFLEXD_UARTSR_FEF BIT(8)
103#define LINFLEXD_UARTSR_BOF BIT(7)
104#define LINFLEXD_UARTSR_RPS BIT(6)
105#define LINFLEXD_UARTSR_WUF BIT(5)
106#define LINFLEXD_UARTSR_4 BIT(4)
107
108#define LINFLEXD_UARTSR_TO BIT(3)
109
110#define LINFLEXD_UARTSR_DRFRFE BIT(2)
111#define LINFLEXD_UARTSR_DTFTFF BIT(1)
112#define LINFLEXD_UARTSR_NF BIT(0)
113#define LINFLEXD_UARTSR_PE (LINFLEXD_UARTSR_PE0 |\
114 LINFLEXD_UARTSR_PE1 |\
115 LINFLEXD_UARTSR_PE2 |\
116 LINFLEXD_UARTSR_PE3)
117
118#define LINFLEX_LDIV_MULTIPLIER (16)
119
120#define DRIVER_NAME "fsl-linflexuart"
121#define DEV_NAME "ttyLF"
122#define UART_NR 4
123
124#define EARLYCON_BUFFER_INITIAL_CAP 8
125
126#define PREINIT_DELAY 2000 /* us */
127
128static const struct of_device_id linflex_dt_ids[] = {
129 {
130 .compatible = "fsl,s32v234-linflexuart",
131 },
132 { /* sentinel */ }
133};
134MODULE_DEVICE_TABLE(of, linflex_dt_ids);
135
136#ifdef CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE
137static struct uart_port *earlycon_port;
138static bool linflex_earlycon_same_instance;
139static DEFINE_SPINLOCK(init_lock);
140static bool during_init;
141
142static struct {
143 char *content;
144 unsigned int len, cap;
145} earlycon_buf;
146#endif
147
148static void linflex_stop_tx(struct uart_port *port)
149{
150 unsigned long ier;
151
152 ier = readl(port->membase + LINIER);
153 ier &= ~(LINFLEXD_LINIER_DTIE);
154 writel(ier, port->membase + LINIER);
155}
156
157static void linflex_stop_rx(struct uart_port *port)
158{
159 unsigned long ier;
160
161 ier = readl(port->membase + LINIER);
162 writel(ier & ~LINFLEXD_LINIER_DRIE, port->membase + LINIER);
163}
164
165static inline void linflex_transmit_buffer(struct uart_port *sport)
166{
167 struct circ_buf *xmit = &sport->state->xmit;
168 unsigned char c;
169 unsigned long status;
170
171 while (!uart_circ_empty(xmit)) {
172 c = xmit->buf[xmit->tail];
173 writeb(c, sport->membase + BDRL);
174
175 /* Waiting for data transmission completed. */
176 while (((status = readl(sport->membase + UARTSR)) &
177 LINFLEXD_UARTSR_DTFTFF) !=
178 LINFLEXD_UARTSR_DTFTFF)
179 ;
180
181 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
182 sport->icount.tx++;
183
184 writel(status | LINFLEXD_UARTSR_DTFTFF,
185 sport->membase + UARTSR);
186 }
187
188 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
189 uart_write_wakeup(sport);
190
191 if (uart_circ_empty(xmit))
192 linflex_stop_tx(sport);
193}
194
195static void linflex_start_tx(struct uart_port *port)
196{
197 unsigned long ier;
198
199 linflex_transmit_buffer(port);
200 ier = readl(port->membase + LINIER);
201 writel(ier | LINFLEXD_LINIER_DTIE, port->membase + LINIER);
202}
203
204static irqreturn_t linflex_txint(int irq, void *dev_id)
205{
206 struct uart_port *sport = dev_id;
207 struct circ_buf *xmit = &sport->state->xmit;
208 unsigned long flags;
209 unsigned long status;
210
211 spin_lock_irqsave(&sport->lock, flags);
212
213 if (sport->x_char) {
214 writeb(sport->x_char, sport->membase + BDRL);
215
216 /* waiting for data transmission completed */
217 while (((status = readl(sport->membase + UARTSR)) &
218 LINFLEXD_UARTSR_DTFTFF) != LINFLEXD_UARTSR_DTFTFF)
219 ;
220
221 writel(status | LINFLEXD_UARTSR_DTFTFF,
222 sport->membase + UARTSR);
223
224 goto out;
225 }
226
227 if (uart_circ_empty(xmit) || uart_tx_stopped(sport)) {
228 linflex_stop_tx(sport);
229 goto out;
230 }
231
232 linflex_transmit_buffer(sport);
233
234 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
235 uart_write_wakeup(sport);
236
237out:
238 spin_unlock_irqrestore(&sport->lock, flags);
239 return IRQ_HANDLED;
240}
241
242static irqreturn_t linflex_rxint(int irq, void *dev_id)
243{
244 struct uart_port *sport = dev_id;
245 unsigned int flg;
246 struct tty_port *port = &sport->state->port;
247 unsigned long flags, status;
248 unsigned char rx;
249 bool brk;
250
251 spin_lock_irqsave(&sport->lock, flags);
252
253 status = readl(sport->membase + UARTSR);
254 while (status & LINFLEXD_UARTSR_RMB) {
255 rx = readb(sport->membase + BDRM);
256 brk = false;
257 flg = TTY_NORMAL;
258 sport->icount.rx++;
259
260 if (status & (LINFLEXD_UARTSR_BOF | LINFLEXD_UARTSR_SZF |
261 LINFLEXD_UARTSR_FEF | LINFLEXD_UARTSR_PE)) {
262 if (status & LINFLEXD_UARTSR_SZF)
263 status |= LINFLEXD_UARTSR_SZF;
264 if (status & LINFLEXD_UARTSR_BOF)
265 status |= LINFLEXD_UARTSR_BOF;
266 if (status & LINFLEXD_UARTSR_FEF) {
267 if (!rx)
268 brk = true;
269 status |= LINFLEXD_UARTSR_FEF;
270 }
271 if (status & LINFLEXD_UARTSR_PE)
272 status |= LINFLEXD_UARTSR_PE;
273 }
274
275 writel(status | LINFLEXD_UARTSR_RMB | LINFLEXD_UARTSR_DRFRFE,
276 sport->membase + UARTSR);
277 status = readl(sport->membase + UARTSR);
278
279 if (brk) {
280 uart_handle_break(sport);
281 } else {
282#ifdef SUPPORT_SYSRQ
283 if (uart_handle_sysrq_char(sport, (unsigned char)rx))
284 continue;
285#endif
286 tty_insert_flip_char(port, rx, flg);
287 }
288 }
289
290 spin_unlock_irqrestore(&sport->lock, flags);
291
292 tty_flip_buffer_push(port);
293
294 return IRQ_HANDLED;
295}
296
297static irqreturn_t linflex_int(int irq, void *dev_id)
298{
299 struct uart_port *sport = dev_id;
300 unsigned long status;
301
302 status = readl(sport->membase + UARTSR);
303
304 if (status & LINFLEXD_UARTSR_DRFRFE)
305 linflex_rxint(irq, dev_id);
306 if (status & LINFLEXD_UARTSR_DTFTFF)
307 linflex_txint(irq, dev_id);
308
309 return IRQ_HANDLED;
310}
311
312/* return TIOCSER_TEMT when transmitter is not busy */
313static unsigned int linflex_tx_empty(struct uart_port *port)
314{
315 unsigned long status;
316
317 status = readl(port->membase + UARTSR) & LINFLEXD_UARTSR_DTFTFF;
318
319 return status ? TIOCSER_TEMT : 0;
320}
321
322static unsigned int linflex_get_mctrl(struct uart_port *port)
323{
324 return 0;
325}
326
327static void linflex_set_mctrl(struct uart_port *port, unsigned int mctrl)
328{
329}
330
331static void linflex_break_ctl(struct uart_port *port, int break_state)
332{
333}
334
335static void linflex_setup_watermark(struct uart_port *sport)
336{
337 unsigned long cr, ier, cr1;
338
339 /* Disable transmission/reception */
340 ier = readl(sport->membase + LINIER);
341 ier &= ~(LINFLEXD_LINIER_DRIE | LINFLEXD_LINIER_DTIE);
342 writel(ier, sport->membase + LINIER);
343
344 cr = readl(sport->membase + UARTCR);
345 cr &= ~(LINFLEXD_UARTCR_RXEN | LINFLEXD_UARTCR_TXEN);
346 writel(cr, sport->membase + UARTCR);
347
348 /* Enter initialization mode by setting INIT bit */
349
350 /* set the Linflex in master mode and activate by-pass filter */
351 cr1 = LINFLEXD_LINCR1_BF | LINFLEXD_LINCR1_MME
352 | LINFLEXD_LINCR1_INIT;
353 writel(cr1, sport->membase + LINCR1);
354
355 /* wait for init mode entry */
356 while ((readl(sport->membase + LINSR)
357 & LINFLEXD_LINSR_LINS_MASK)
358 != LINFLEXD_LINSR_LINS_INITMODE)
359 ;
360
361 /*
362 * UART = 0x1; - Linflex working in UART mode
363 * TXEN = 0x1; - Enable transmission of data now
364 * RXEn = 0x1; - Receiver enabled
365 * WL0 = 0x1; - 8 bit data
366 * PCE = 0x0; - No parity
367 */
368
369 /* set UART bit to allow writing other bits */
370 writel(LINFLEXD_UARTCR_UART, sport->membase + UARTCR);
371
372 cr = (LINFLEXD_UARTCR_RXEN | LINFLEXD_UARTCR_TXEN |
373 LINFLEXD_UARTCR_WL0 | LINFLEXD_UARTCR_UART);
374
375 writel(cr, sport->membase + UARTCR);
376
377 cr1 &= ~(LINFLEXD_LINCR1_INIT);
378
379 writel(cr1, sport->membase + LINCR1);
380
381 ier = readl(sport->membase + LINIER);
382 ier |= LINFLEXD_LINIER_DRIE;
383 ier |= LINFLEXD_LINIER_DTIE;
384
385 writel(ier, sport->membase + LINIER);
386}
387
388static int linflex_startup(struct uart_port *port)
389{
390 int ret = 0;
391 unsigned long flags;
392
393 spin_lock_irqsave(&port->lock, flags);
394
395 linflex_setup_watermark(port);
396
397 spin_unlock_irqrestore(&port->lock, flags);
398
399 ret = devm_request_irq(port->dev, port->irq, linflex_int, 0,
400 DRIVER_NAME, port);
401
402 return ret;
403}
404
405static void linflex_shutdown(struct uart_port *port)
406{
407 unsigned long ier;
408 unsigned long flags;
409
410 spin_lock_irqsave(&port->lock, flags);
411
412 /* disable interrupts */
413 ier = readl(port->membase + LINIER);
414 ier &= ~(LINFLEXD_LINIER_DRIE | LINFLEXD_LINIER_DTIE);
415 writel(ier, port->membase + LINIER);
416
417 spin_unlock_irqrestore(&port->lock, flags);
418
419 devm_free_irq(port->dev, port->irq, port);
420}
421
422static void
423linflex_set_termios(struct uart_port *port, struct ktermios *termios,
424 struct ktermios *old)
425{
426 unsigned long flags;
427 unsigned long cr, old_cr, cr1;
428 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
429
430 cr = readl(port->membase + UARTCR);
431 old_cr = cr;
432
433 /* Enter initialization mode by setting INIT bit */
434 cr1 = readl(port->membase + LINCR1);
435 cr1 |= LINFLEXD_LINCR1_INIT;
436 writel(cr1, port->membase + LINCR1);
437
438 /* wait for init mode entry */
439 while ((readl(port->membase + LINSR)
440 & LINFLEXD_LINSR_LINS_MASK)
441 != LINFLEXD_LINSR_LINS_INITMODE)
442 ;
443
444 /*
445 * only support CS8 and CS7, and for CS7 must enable PE.
446 * supported mode:
447 * - (7,e/o,1)
448 * - (8,n,1)
449 * - (8,e/o,1)
450 */
451 /* enter the UART into configuration mode */
452
453 while ((termios->c_cflag & CSIZE) != CS8 &&
454 (termios->c_cflag & CSIZE) != CS7) {
455 termios->c_cflag &= ~CSIZE;
456 termios->c_cflag |= old_csize;
457 old_csize = CS8;
458 }
459
460 if ((termios->c_cflag & CSIZE) == CS7) {
461 /* Word length: WL1WL0:00 */
462 cr = old_cr & ~LINFLEXD_UARTCR_WL1 & ~LINFLEXD_UARTCR_WL0;
463 }
464
465 if ((termios->c_cflag & CSIZE) == CS8) {
466 /* Word length: WL1WL0:01 */
467 cr = (old_cr | LINFLEXD_UARTCR_WL0) & ~LINFLEXD_UARTCR_WL1;
468 }
469
470 if (termios->c_cflag & CMSPAR) {
471 if ((termios->c_cflag & CSIZE) != CS8) {
472 termios->c_cflag &= ~CSIZE;
473 termios->c_cflag |= CS8;
474 }
475 /* has a space/sticky bit */
476 cr |= LINFLEXD_UARTCR_WL0;
477 }
478
479 if (termios->c_cflag & CSTOPB)
480 termios->c_cflag &= ~CSTOPB;
481
482 /* parity must be enabled when CS7 to match 8-bits format */
483 if ((termios->c_cflag & CSIZE) == CS7)
484 termios->c_cflag |= PARENB;
485
486 if ((termios->c_cflag & PARENB)) {
487 cr |= LINFLEXD_UARTCR_PCE;
488 if (termios->c_cflag & PARODD)
489 cr = (cr | LINFLEXD_UARTCR_PC0) &
490 (~LINFLEXD_UARTCR_PC1);
491 else
492 cr = cr & (~LINFLEXD_UARTCR_PC1 &
493 ~LINFLEXD_UARTCR_PC0);
494 } else {
495 cr &= ~LINFLEXD_UARTCR_PCE;
496 }
497
498 spin_lock_irqsave(&port->lock, flags);
499
500 port->read_status_mask = 0;
501
502 if (termios->c_iflag & INPCK)
503 port->read_status_mask |= (LINFLEXD_UARTSR_FEF |
504 LINFLEXD_UARTSR_PE0 |
505 LINFLEXD_UARTSR_PE1 |
506 LINFLEXD_UARTSR_PE2 |
507 LINFLEXD_UARTSR_PE3);
508 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
509 port->read_status_mask |= LINFLEXD_UARTSR_FEF;
510
511 /* characters to ignore */
512 port->ignore_status_mask = 0;
513 if (termios->c_iflag & IGNPAR)
514 port->ignore_status_mask |= LINFLEXD_UARTSR_PE;
515 if (termios->c_iflag & IGNBRK) {
516 port->ignore_status_mask |= LINFLEXD_UARTSR_PE;
517 /*
518 * if we're ignoring parity and break indicators,
519 * ignore overruns too (for real raw support).
520 */
521 if (termios->c_iflag & IGNPAR)
522 port->ignore_status_mask |= LINFLEXD_UARTSR_BOF;
523 }
524
525 writel(cr, port->membase + UARTCR);
526
527 cr1 &= ~(LINFLEXD_LINCR1_INIT);
528
529 writel(cr1, port->membase + LINCR1);
530
531 spin_unlock_irqrestore(&port->lock, flags);
532}
533
534static const char *linflex_type(struct uart_port *port)
535{
536 return "FSL_LINFLEX";
537}
538
539static void linflex_release_port(struct uart_port *port)
540{
541 /* nothing to do */
542}
543
544static int linflex_request_port(struct uart_port *port)
545{
546 return 0;
547}
548
549/* configure/auto-configure the port */
550static void linflex_config_port(struct uart_port *port, int flags)
551{
552 if (flags & UART_CONFIG_TYPE)
553 port->type = PORT_LINFLEXUART;
554}
555
556static const struct uart_ops linflex_pops = {
557 .tx_empty = linflex_tx_empty,
558 .set_mctrl = linflex_set_mctrl,
559 .get_mctrl = linflex_get_mctrl,
560 .stop_tx = linflex_stop_tx,
561 .start_tx = linflex_start_tx,
562 .stop_rx = linflex_stop_rx,
563 .break_ctl = linflex_break_ctl,
564 .startup = linflex_startup,
565 .shutdown = linflex_shutdown,
566 .set_termios = linflex_set_termios,
567 .type = linflex_type,
568 .request_port = linflex_request_port,
569 .release_port = linflex_release_port,
570 .config_port = linflex_config_port,
571};
572
573static struct uart_port *linflex_ports[UART_NR];
574
575#ifdef CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE
576static void linflex_console_putchar(struct uart_port *port, int ch)
577{
578 unsigned long cr;
579
580 cr = readl(port->membase + UARTCR);
581
582 writeb(ch, port->membase + BDRL);
583
584 if (!(cr & LINFLEXD_UARTCR_TFBM))
585 while ((readl(port->membase + UARTSR) &
586 LINFLEXD_UARTSR_DTFTFF)
587 != LINFLEXD_UARTSR_DTFTFF)
588 ;
589 else
590 while (readl(port->membase + UARTSR) &
591 LINFLEXD_UARTSR_DTFTFF)
592 ;
593
594 if (!(cr & LINFLEXD_UARTCR_TFBM)) {
595 writel((readl(port->membase + UARTSR) |
596 LINFLEXD_UARTSR_DTFTFF),
597 port->membase + UARTSR);
598 }
599}
600
601static void linflex_earlycon_putchar(struct uart_port *port, int ch)
602{
603 unsigned long flags;
604 char *ret;
605
606 if (!linflex_earlycon_same_instance) {
607 linflex_console_putchar(port, ch);
608 return;
609 }
610
611 spin_lock_irqsave(&init_lock, flags);
612 if (!during_init)
613 goto outside_init;
614
615 if (earlycon_buf.len >= 1 << CONFIG_LOG_BUF_SHIFT)
616 goto init_release;
617
618 if (!earlycon_buf.cap) {
619 earlycon_buf.content = kmalloc(EARLYCON_BUFFER_INITIAL_CAP,
620 GFP_ATOMIC);
621 earlycon_buf.cap = earlycon_buf.content ?
622 EARLYCON_BUFFER_INITIAL_CAP : 0;
623 } else if (earlycon_buf.len == earlycon_buf.cap) {
624 ret = krealloc(earlycon_buf.content, earlycon_buf.cap << 1,
625 GFP_ATOMIC);
626 if (ret) {
627 earlycon_buf.content = ret;
628 earlycon_buf.cap <<= 1;
629 }
630 }
631
632 if (earlycon_buf.len < earlycon_buf.cap)
633 earlycon_buf.content[earlycon_buf.len++] = ch;
634
635 goto init_release;
636
637outside_init:
638 linflex_console_putchar(port, ch);
639init_release:
640 spin_unlock_irqrestore(&init_lock, flags);
641}
642
643static void linflex_string_write(struct uart_port *sport, const char *s,
644 unsigned int count)
645{
646 unsigned long cr, ier = 0;
647
648 ier = readl(sport->membase + LINIER);
649 linflex_stop_tx(sport);
650
651 cr = readl(sport->membase + UARTCR);
652 cr |= (LINFLEXD_UARTCR_TXEN);
653 writel(cr, sport->membase + UARTCR);
654
655 uart_console_write(sport, s, count, linflex_console_putchar);
656
657 writel(ier, sport->membase + LINIER);
658}
659
660static void
661linflex_console_write(struct console *co, const char *s, unsigned int count)
662{
663 struct uart_port *sport = linflex_ports[co->index];
664 unsigned long flags;
665 int locked = 1;
666
667 if (sport->sysrq)
668 locked = 0;
669 else if (oops_in_progress)
670 locked = spin_trylock_irqsave(&sport->lock, flags);
671 else
672 spin_lock_irqsave(&sport->lock, flags);
673
674 linflex_string_write(sport, s, count);
675
676 if (locked)
677 spin_unlock_irqrestore(&sport->lock, flags);
678}
679
680/*
681 * if the port was already initialised (eg, by a boot loader),
682 * try to determine the current setup.
683 */
684static void __init
685linflex_console_get_options(struct uart_port *sport, int *parity, int *bits)
686{
687 unsigned long cr;
688
689 cr = readl(sport->membase + UARTCR);
690 cr &= LINFLEXD_UARTCR_RXEN | LINFLEXD_UARTCR_TXEN;
691
692 if (!cr)
693 return;
694
695 /* ok, the port was enabled */
696
697 *parity = 'n';
698 if (cr & LINFLEXD_UARTCR_PCE) {
699 if (cr & LINFLEXD_UARTCR_PC0)
700 *parity = 'o';
701 else
702 *parity = 'e';
703 }
704
705 if ((cr & LINFLEXD_UARTCR_WL0) && ((cr & LINFLEXD_UARTCR_WL1) == 0)) {
706 if (cr & LINFLEXD_UARTCR_PCE)
707 *bits = 9;
708 else
709 *bits = 8;
710 }
711}
712
713static int __init linflex_console_setup(struct console *co, char *options)
714{
715 struct uart_port *sport;
716 int baud = 115200;
717 int bits = 8;
718 int parity = 'n';
719 int flow = 'n';
720 int ret;
721 int i;
722 unsigned long flags;
723 /*
724 * check whether an invalid uart number has been specified, and
725 * if so, search for the first available port that does have
726 * console support.
727 */
728 if (co->index == -1 || co->index >= ARRAY_SIZE(linflex_ports))
729 co->index = 0;
730
731 sport = linflex_ports[co->index];
732 if (!sport)
733 return -ENODEV;
734
735 if (options)
736 uart_parse_options(options, &baud, &parity, &bits, &flow);
737 else
738 linflex_console_get_options(sport, &parity, &bits);
739
740 if (earlycon_port && sport->mapbase == earlycon_port->mapbase) {
741 linflex_earlycon_same_instance = true;
742
743 spin_lock_irqsave(&init_lock, flags);
744 during_init = true;
745 spin_unlock_irqrestore(&init_lock, flags);
746
747 /* Workaround for character loss or output of many invalid
748 * characters, when INIT mode is entered shortly after a
749 * character has just been printed.
750 */
751 udelay(PREINIT_DELAY);
752 }
753
754 linflex_setup_watermark(sport);
755
756 ret = uart_set_options(sport, co, baud, parity, bits, flow);
757
758 if (!linflex_earlycon_same_instance)
759 goto done;
760
761 spin_lock_irqsave(&init_lock, flags);
762
763 /* Emptying buffer */
764 if (earlycon_buf.len) {
765 for (i = 0; i < earlycon_buf.len; i++)
766 linflex_console_putchar(earlycon_port,
767 earlycon_buf.content[i]);
768
769 kfree(earlycon_buf.content);
770 earlycon_buf.len = 0;
771 }
772
773 during_init = false;
774 spin_unlock_irqrestore(&init_lock, flags);
775
776done:
777 return ret;
778}
779
780static struct uart_driver linflex_reg;
781static struct console linflex_console = {
782 .name = DEV_NAME,
783 .write = linflex_console_write,
784 .device = uart_console_device,
785 .setup = linflex_console_setup,
786 .flags = CON_PRINTBUFFER,
787 .index = -1,
788 .data = &linflex_reg,
789};
790
791static void linflex_earlycon_write(struct console *con, const char *s,
792 unsigned int n)
793{
794 struct earlycon_device *dev = con->data;
795
796 uart_console_write(&dev->port, s, n, linflex_earlycon_putchar);
797}
798
799static int __init linflex_early_console_setup(struct earlycon_device *device,
800 const char *options)
801{
802 if (!device->port.membase)
803 return -ENODEV;
804
805 device->con->write = linflex_earlycon_write;
806 earlycon_port = &device->port;
807
808 return 0;
809}
810
811OF_EARLYCON_DECLARE(linflex, "fsl,s32v234-linflexuart",
812 linflex_early_console_setup);
813
814#define LINFLEX_CONSOLE (&linflex_console)
815#else
816#define LINFLEX_CONSOLE NULL
817#endif
818
819static struct uart_driver linflex_reg = {
820 .owner = THIS_MODULE,
821 .driver_name = DRIVER_NAME,
822 .dev_name = DEV_NAME,
823 .nr = ARRAY_SIZE(linflex_ports),
824 .cons = LINFLEX_CONSOLE,
825};
826
827static int linflex_probe(struct platform_device *pdev)
828{
829 struct device_node *np = pdev->dev.of_node;
830 struct uart_port *sport;
831 struct resource *res;
832 int ret;
833
834 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
835 if (!sport)
836 return -ENOMEM;
837
838 ret = of_alias_get_id(np, "serial");
839 if (ret < 0) {
840 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
841 return ret;
842 }
843 if (ret >= UART_NR) {
844 dev_err(&pdev->dev, "driver limited to %d serial ports\n",
845 UART_NR);
846 return -ENOMEM;
847 }
848
849 sport->line = ret;
850
851 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
852 if (!res)
853 return -ENODEV;
854
855 sport->mapbase = res->start;
856 sport->membase = devm_ioremap_resource(&pdev->dev, res);
857 if (IS_ERR(sport->membase))
858 return PTR_ERR(sport->membase);
859
860 sport->dev = &pdev->dev;
861 sport->type = PORT_LINFLEXUART;
862 sport->iotype = UPIO_MEM;
863 sport->irq = platform_get_irq(pdev, 0);
864 sport->ops = &linflex_pops;
865 sport->flags = UPF_BOOT_AUTOCONF;
866
867 linflex_ports[sport->line] = sport;
868
869 platform_set_drvdata(pdev, sport);
870
871 ret = uart_add_one_port(&linflex_reg, sport);
872 if (ret)
873 return ret;
874
875 return 0;
876}
877
878static int linflex_remove(struct platform_device *pdev)
879{
880 struct uart_port *sport = platform_get_drvdata(pdev);
881
882 uart_remove_one_port(&linflex_reg, sport);
883
884 return 0;
885}
886
887#ifdef CONFIG_PM_SLEEP
888static int linflex_suspend(struct device *dev)
889{
890 struct uart_port *sport = dev_get_drvdata(dev);
891
892 uart_suspend_port(&linflex_reg, sport);
893
894 return 0;
895}
896
897static int linflex_resume(struct device *dev)
898{
899 struct uart_port *sport = dev_get_drvdata(dev);
900
901 uart_resume_port(&linflex_reg, sport);
902
903 return 0;
904}
905#endif
906
907static SIMPLE_DEV_PM_OPS(linflex_pm_ops, linflex_suspend, linflex_resume);
908
909static struct platform_driver linflex_driver = {
910 .probe = linflex_probe,
911 .remove = linflex_remove,
912 .driver = {
913 .name = DRIVER_NAME,
914 .of_match_table = linflex_dt_ids,
915 .pm = &linflex_pm_ops,
916 },
917};
918
919static int __init linflex_serial_init(void)
920{
921 int ret;
922
923 ret = uart_register_driver(&linflex_reg);
924 if (ret)
925 return ret;
926
927 ret = platform_driver_register(&linflex_driver);
928 if (ret)
929 uart_unregister_driver(&linflex_reg);
930
931 return ret;
932}
933
934static void __exit linflex_serial_exit(void)
935{
936 platform_driver_unregister(&linflex_driver);
937 uart_unregister_driver(&linflex_reg);
938}
939
940module_init(linflex_serial_init);
941module_exit(linflex_serial_exit);
942
943MODULE_DESCRIPTION("Freescale linflex serial port driver");
944MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Freescale LINFlexD UART serial port driver
4 *
5 * Copyright 2012-2016 Freescale Semiconductor, Inc.
6 * Copyright 2017-2019 NXP
7 */
8
9#include <linux/console.h>
10#include <linux/io.h>
11#include <linux/irq.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
15#include <linux/serial_core.h>
16#include <linux/slab.h>
17#include <linux/tty_flip.h>
18#include <linux/delay.h>
19
20/* All registers are 32-bit width */
21
22#define LINCR1 0x0000 /* LIN control register */
23#define LINIER 0x0004 /* LIN interrupt enable register */
24#define LINSR 0x0008 /* LIN status register */
25#define LINESR 0x000C /* LIN error status register */
26#define UARTCR 0x0010 /* UART mode control register */
27#define UARTSR 0x0014 /* UART mode status register */
28#define LINTCSR 0x0018 /* LIN timeout control status register */
29#define LINOCR 0x001C /* LIN output compare register */
30#define LINTOCR 0x0020 /* LIN timeout control register */
31#define LINFBRR 0x0024 /* LIN fractional baud rate register */
32#define LINIBRR 0x0028 /* LIN integer baud rate register */
33#define LINCFR 0x002C /* LIN checksum field register */
34#define LINCR2 0x0030 /* LIN control register 2 */
35#define BIDR 0x0034 /* Buffer identifier register */
36#define BDRL 0x0038 /* Buffer data register least significant */
37#define BDRM 0x003C /* Buffer data register most significant */
38#define IFER 0x0040 /* Identifier filter enable register */
39#define IFMI 0x0044 /* Identifier filter match index */
40#define IFMR 0x0048 /* Identifier filter mode register */
41#define GCR 0x004C /* Global control register */
42#define UARTPTO 0x0050 /* UART preset timeout register */
43#define UARTCTO 0x0054 /* UART current timeout register */
44
45/*
46 * Register field definitions
47 */
48
49#define LINFLEXD_LINCR1_INIT BIT(0)
50#define LINFLEXD_LINCR1_MME BIT(4)
51#define LINFLEXD_LINCR1_BF BIT(7)
52
53#define LINFLEXD_LINSR_LINS_INITMODE BIT(12)
54#define LINFLEXD_LINSR_LINS_MASK (0xF << 12)
55
56#define LINFLEXD_LINIER_SZIE BIT(15)
57#define LINFLEXD_LINIER_OCIE BIT(14)
58#define LINFLEXD_LINIER_BEIE BIT(13)
59#define LINFLEXD_LINIER_CEIE BIT(12)
60#define LINFLEXD_LINIER_HEIE BIT(11)
61#define LINFLEXD_LINIER_FEIE BIT(8)
62#define LINFLEXD_LINIER_BOIE BIT(7)
63#define LINFLEXD_LINIER_LSIE BIT(6)
64#define LINFLEXD_LINIER_WUIE BIT(5)
65#define LINFLEXD_LINIER_DBFIE BIT(4)
66#define LINFLEXD_LINIER_DBEIETOIE BIT(3)
67#define LINFLEXD_LINIER_DRIE BIT(2)
68#define LINFLEXD_LINIER_DTIE BIT(1)
69#define LINFLEXD_LINIER_HRIE BIT(0)
70
71#define LINFLEXD_UARTCR_OSR_MASK (0xF << 24)
72#define LINFLEXD_UARTCR_OSR(uartcr) (((uartcr) \
73 & LINFLEXD_UARTCR_OSR_MASK) >> 24)
74
75#define LINFLEXD_UARTCR_ROSE BIT(23)
76
77#define LINFLEXD_UARTCR_RFBM BIT(9)
78#define LINFLEXD_UARTCR_TFBM BIT(8)
79#define LINFLEXD_UARTCR_WL1 BIT(7)
80#define LINFLEXD_UARTCR_PC1 BIT(6)
81
82#define LINFLEXD_UARTCR_RXEN BIT(5)
83#define LINFLEXD_UARTCR_TXEN BIT(4)
84#define LINFLEXD_UARTCR_PC0 BIT(3)
85
86#define LINFLEXD_UARTCR_PCE BIT(2)
87#define LINFLEXD_UARTCR_WL0 BIT(1)
88#define LINFLEXD_UARTCR_UART BIT(0)
89
90#define LINFLEXD_UARTSR_SZF BIT(15)
91#define LINFLEXD_UARTSR_OCF BIT(14)
92#define LINFLEXD_UARTSR_PE3 BIT(13)
93#define LINFLEXD_UARTSR_PE2 BIT(12)
94#define LINFLEXD_UARTSR_PE1 BIT(11)
95#define LINFLEXD_UARTSR_PE0 BIT(10)
96#define LINFLEXD_UARTSR_RMB BIT(9)
97#define LINFLEXD_UARTSR_FEF BIT(8)
98#define LINFLEXD_UARTSR_BOF BIT(7)
99#define LINFLEXD_UARTSR_RPS BIT(6)
100#define LINFLEXD_UARTSR_WUF BIT(5)
101#define LINFLEXD_UARTSR_4 BIT(4)
102
103#define LINFLEXD_UARTSR_TO BIT(3)
104
105#define LINFLEXD_UARTSR_DRFRFE BIT(2)
106#define LINFLEXD_UARTSR_DTFTFF BIT(1)
107#define LINFLEXD_UARTSR_NF BIT(0)
108#define LINFLEXD_UARTSR_PE (LINFLEXD_UARTSR_PE0 |\
109 LINFLEXD_UARTSR_PE1 |\
110 LINFLEXD_UARTSR_PE2 |\
111 LINFLEXD_UARTSR_PE3)
112
113#define LINFLEX_LDIV_MULTIPLIER (16)
114
115#define DRIVER_NAME "fsl-linflexuart"
116#define DEV_NAME "ttyLF"
117#define UART_NR 4
118
119#define EARLYCON_BUFFER_INITIAL_CAP 8
120
121#define PREINIT_DELAY 2000 /* us */
122
123static const struct of_device_id linflex_dt_ids[] = {
124 {
125 .compatible = "fsl,s32v234-linflexuart",
126 },
127 { /* sentinel */ }
128};
129MODULE_DEVICE_TABLE(of, linflex_dt_ids);
130
131#ifdef CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE
132static struct uart_port *earlycon_port;
133static bool linflex_earlycon_same_instance;
134static DEFINE_SPINLOCK(init_lock);
135static bool during_init;
136
137static struct {
138 char *content;
139 unsigned int len, cap;
140} earlycon_buf;
141#endif
142
143static void linflex_stop_tx(struct uart_port *port)
144{
145 unsigned long ier;
146
147 ier = readl(port->membase + LINIER);
148 ier &= ~(LINFLEXD_LINIER_DTIE);
149 writel(ier, port->membase + LINIER);
150}
151
152static void linflex_stop_rx(struct uart_port *port)
153{
154 unsigned long ier;
155
156 ier = readl(port->membase + LINIER);
157 writel(ier & ~LINFLEXD_LINIER_DRIE, port->membase + LINIER);
158}
159
160static void linflex_put_char(struct uart_port *sport, unsigned char c)
161{
162 unsigned long status;
163
164 writeb(c, sport->membase + BDRL);
165
166 /* Waiting for data transmission completed. */
167 while (((status = readl(sport->membase + UARTSR)) &
168 LINFLEXD_UARTSR_DTFTFF) !=
169 LINFLEXD_UARTSR_DTFTFF)
170 ;
171
172 writel(status | LINFLEXD_UARTSR_DTFTFF, sport->membase + UARTSR);
173}
174
175static inline void linflex_transmit_buffer(struct uart_port *sport)
176{
177 struct circ_buf *xmit = &sport->state->xmit;
178
179 while (!uart_circ_empty(xmit)) {
180 linflex_put_char(sport, xmit->buf[xmit->tail]);
181 uart_xmit_advance(sport, 1);
182 }
183
184 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
185 uart_write_wakeup(sport);
186
187 if (uart_circ_empty(xmit))
188 linflex_stop_tx(sport);
189}
190
191static void linflex_start_tx(struct uart_port *port)
192{
193 unsigned long ier;
194
195 linflex_transmit_buffer(port);
196 ier = readl(port->membase + LINIER);
197 writel(ier | LINFLEXD_LINIER_DTIE, port->membase + LINIER);
198}
199
200static irqreturn_t linflex_txint(int irq, void *dev_id)
201{
202 struct uart_port *sport = dev_id;
203 struct circ_buf *xmit = &sport->state->xmit;
204 unsigned long flags;
205
206 uart_port_lock_irqsave(sport, &flags);
207
208 if (sport->x_char) {
209 linflex_put_char(sport, sport->x_char);
210 goto out;
211 }
212
213 if (uart_circ_empty(xmit) || uart_tx_stopped(sport)) {
214 linflex_stop_tx(sport);
215 goto out;
216 }
217
218 linflex_transmit_buffer(sport);
219out:
220 uart_port_unlock_irqrestore(sport, flags);
221 return IRQ_HANDLED;
222}
223
224static irqreturn_t linflex_rxint(int irq, void *dev_id)
225{
226 struct uart_port *sport = dev_id;
227 unsigned int flg;
228 struct tty_port *port = &sport->state->port;
229 unsigned long flags, status;
230 unsigned char rx;
231 bool brk;
232
233 uart_port_lock_irqsave(sport, &flags);
234
235 status = readl(sport->membase + UARTSR);
236 while (status & LINFLEXD_UARTSR_RMB) {
237 rx = readb(sport->membase + BDRM);
238 brk = false;
239 flg = TTY_NORMAL;
240 sport->icount.rx++;
241
242 if (status & (LINFLEXD_UARTSR_BOF | LINFLEXD_UARTSR_FEF |
243 LINFLEXD_UARTSR_PE)) {
244 if (status & LINFLEXD_UARTSR_BOF)
245 sport->icount.overrun++;
246 if (status & LINFLEXD_UARTSR_FEF) {
247 if (!rx) {
248 brk = true;
249 sport->icount.brk++;
250 } else
251 sport->icount.frame++;
252 }
253 if (status & LINFLEXD_UARTSR_PE)
254 sport->icount.parity++;
255 }
256
257 writel(status, sport->membase + UARTSR);
258 status = readl(sport->membase + UARTSR);
259
260 if (brk) {
261 uart_handle_break(sport);
262 } else {
263 if (uart_handle_sysrq_char(sport, (unsigned char)rx))
264 continue;
265 tty_insert_flip_char(port, rx, flg);
266 }
267 }
268
269 uart_port_unlock_irqrestore(sport, flags);
270
271 tty_flip_buffer_push(port);
272
273 return IRQ_HANDLED;
274}
275
276static irqreturn_t linflex_int(int irq, void *dev_id)
277{
278 struct uart_port *sport = dev_id;
279 unsigned long status;
280
281 status = readl(sport->membase + UARTSR);
282
283 if (status & LINFLEXD_UARTSR_DRFRFE)
284 linflex_rxint(irq, dev_id);
285 if (status & LINFLEXD_UARTSR_DTFTFF)
286 linflex_txint(irq, dev_id);
287
288 return IRQ_HANDLED;
289}
290
291/* return TIOCSER_TEMT when transmitter is not busy */
292static unsigned int linflex_tx_empty(struct uart_port *port)
293{
294 unsigned long status;
295
296 status = readl(port->membase + UARTSR) & LINFLEXD_UARTSR_DTFTFF;
297
298 return status ? TIOCSER_TEMT : 0;
299}
300
301static unsigned int linflex_get_mctrl(struct uart_port *port)
302{
303 return 0;
304}
305
306static void linflex_set_mctrl(struct uart_port *port, unsigned int mctrl)
307{
308}
309
310static void linflex_break_ctl(struct uart_port *port, int break_state)
311{
312}
313
314static void linflex_setup_watermark(struct uart_port *sport)
315{
316 unsigned long cr, ier, cr1;
317
318 /* Disable transmission/reception */
319 ier = readl(sport->membase + LINIER);
320 ier &= ~(LINFLEXD_LINIER_DRIE | LINFLEXD_LINIER_DTIE);
321 writel(ier, sport->membase + LINIER);
322
323 cr = readl(sport->membase + UARTCR);
324 cr &= ~(LINFLEXD_UARTCR_RXEN | LINFLEXD_UARTCR_TXEN);
325 writel(cr, sport->membase + UARTCR);
326
327 /* Enter initialization mode by setting INIT bit */
328
329 /* set the Linflex in master mode and activate by-pass filter */
330 cr1 = LINFLEXD_LINCR1_BF | LINFLEXD_LINCR1_MME
331 | LINFLEXD_LINCR1_INIT;
332 writel(cr1, sport->membase + LINCR1);
333
334 /* wait for init mode entry */
335 while ((readl(sport->membase + LINSR)
336 & LINFLEXD_LINSR_LINS_MASK)
337 != LINFLEXD_LINSR_LINS_INITMODE)
338 ;
339
340 /*
341 * UART = 0x1; - Linflex working in UART mode
342 * TXEN = 0x1; - Enable transmission of data now
343 * RXEn = 0x1; - Receiver enabled
344 * WL0 = 0x1; - 8 bit data
345 * PCE = 0x0; - No parity
346 */
347
348 /* set UART bit to allow writing other bits */
349 writel(LINFLEXD_UARTCR_UART, sport->membase + UARTCR);
350
351 cr = (LINFLEXD_UARTCR_RXEN | LINFLEXD_UARTCR_TXEN |
352 LINFLEXD_UARTCR_WL0 | LINFLEXD_UARTCR_UART);
353
354 writel(cr, sport->membase + UARTCR);
355
356 cr1 &= ~(LINFLEXD_LINCR1_INIT);
357
358 writel(cr1, sport->membase + LINCR1);
359
360 ier = readl(sport->membase + LINIER);
361 ier |= LINFLEXD_LINIER_DRIE;
362 ier |= LINFLEXD_LINIER_DTIE;
363
364 writel(ier, sport->membase + LINIER);
365}
366
367static int linflex_startup(struct uart_port *port)
368{
369 int ret = 0;
370 unsigned long flags;
371
372 uart_port_lock_irqsave(port, &flags);
373
374 linflex_setup_watermark(port);
375
376 uart_port_unlock_irqrestore(port, flags);
377
378 ret = devm_request_irq(port->dev, port->irq, linflex_int, 0,
379 DRIVER_NAME, port);
380
381 return ret;
382}
383
384static void linflex_shutdown(struct uart_port *port)
385{
386 unsigned long ier;
387 unsigned long flags;
388
389 uart_port_lock_irqsave(port, &flags);
390
391 /* disable interrupts */
392 ier = readl(port->membase + LINIER);
393 ier &= ~(LINFLEXD_LINIER_DRIE | LINFLEXD_LINIER_DTIE);
394 writel(ier, port->membase + LINIER);
395
396 uart_port_unlock_irqrestore(port, flags);
397
398 devm_free_irq(port->dev, port->irq, port);
399}
400
401static void
402linflex_set_termios(struct uart_port *port, struct ktermios *termios,
403 const struct ktermios *old)
404{
405 unsigned long flags;
406 unsigned long cr, old_cr, cr1;
407 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
408
409 cr = readl(port->membase + UARTCR);
410 old_cr = cr;
411
412 /* Enter initialization mode by setting INIT bit */
413 cr1 = readl(port->membase + LINCR1);
414 cr1 |= LINFLEXD_LINCR1_INIT;
415 writel(cr1, port->membase + LINCR1);
416
417 /* wait for init mode entry */
418 while ((readl(port->membase + LINSR)
419 & LINFLEXD_LINSR_LINS_MASK)
420 != LINFLEXD_LINSR_LINS_INITMODE)
421 ;
422
423 /*
424 * only support CS8 and CS7, and for CS7 must enable PE.
425 * supported mode:
426 * - (7,e/o,1)
427 * - (8,n,1)
428 * - (8,e/o,1)
429 */
430 /* enter the UART into configuration mode */
431
432 while ((termios->c_cflag & CSIZE) != CS8 &&
433 (termios->c_cflag & CSIZE) != CS7) {
434 termios->c_cflag &= ~CSIZE;
435 termios->c_cflag |= old_csize;
436 old_csize = CS8;
437 }
438
439 if ((termios->c_cflag & CSIZE) == CS7) {
440 /* Word length: WL1WL0:00 */
441 cr = old_cr & ~LINFLEXD_UARTCR_WL1 & ~LINFLEXD_UARTCR_WL0;
442 }
443
444 if ((termios->c_cflag & CSIZE) == CS8) {
445 /* Word length: WL1WL0:01 */
446 cr = (old_cr | LINFLEXD_UARTCR_WL0) & ~LINFLEXD_UARTCR_WL1;
447 }
448
449 if (termios->c_cflag & CMSPAR) {
450 if ((termios->c_cflag & CSIZE) != CS8) {
451 termios->c_cflag &= ~CSIZE;
452 termios->c_cflag |= CS8;
453 }
454 /* has a space/sticky bit */
455 cr |= LINFLEXD_UARTCR_WL0;
456 }
457
458 if (termios->c_cflag & CSTOPB)
459 termios->c_cflag &= ~CSTOPB;
460
461 /* parity must be enabled when CS7 to match 8-bits format */
462 if ((termios->c_cflag & CSIZE) == CS7)
463 termios->c_cflag |= PARENB;
464
465 if ((termios->c_cflag & PARENB)) {
466 cr |= LINFLEXD_UARTCR_PCE;
467 if (termios->c_cflag & PARODD)
468 cr = (cr | LINFLEXD_UARTCR_PC0) &
469 (~LINFLEXD_UARTCR_PC1);
470 else
471 cr = cr & (~LINFLEXD_UARTCR_PC1 &
472 ~LINFLEXD_UARTCR_PC0);
473 } else {
474 cr &= ~LINFLEXD_UARTCR_PCE;
475 }
476
477 uart_port_lock_irqsave(port, &flags);
478
479 port->read_status_mask = 0;
480
481 if (termios->c_iflag & INPCK)
482 port->read_status_mask |= (LINFLEXD_UARTSR_FEF |
483 LINFLEXD_UARTSR_PE0 |
484 LINFLEXD_UARTSR_PE1 |
485 LINFLEXD_UARTSR_PE2 |
486 LINFLEXD_UARTSR_PE3);
487 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
488 port->read_status_mask |= LINFLEXD_UARTSR_FEF;
489
490 /* characters to ignore */
491 port->ignore_status_mask = 0;
492 if (termios->c_iflag & IGNPAR)
493 port->ignore_status_mask |= LINFLEXD_UARTSR_PE;
494 if (termios->c_iflag & IGNBRK) {
495 port->ignore_status_mask |= LINFLEXD_UARTSR_PE;
496 /*
497 * if we're ignoring parity and break indicators,
498 * ignore overruns too (for real raw support).
499 */
500 if (termios->c_iflag & IGNPAR)
501 port->ignore_status_mask |= LINFLEXD_UARTSR_BOF;
502 }
503
504 writel(cr, port->membase + UARTCR);
505
506 cr1 &= ~(LINFLEXD_LINCR1_INIT);
507
508 writel(cr1, port->membase + LINCR1);
509
510 uart_port_unlock_irqrestore(port, flags);
511}
512
513static const char *linflex_type(struct uart_port *port)
514{
515 return "FSL_LINFLEX";
516}
517
518static void linflex_release_port(struct uart_port *port)
519{
520 /* nothing to do */
521}
522
523static int linflex_request_port(struct uart_port *port)
524{
525 return 0;
526}
527
528/* configure/auto-configure the port */
529static void linflex_config_port(struct uart_port *port, int flags)
530{
531 if (flags & UART_CONFIG_TYPE)
532 port->type = PORT_LINFLEXUART;
533}
534
535static const struct uart_ops linflex_pops = {
536 .tx_empty = linflex_tx_empty,
537 .set_mctrl = linflex_set_mctrl,
538 .get_mctrl = linflex_get_mctrl,
539 .stop_tx = linflex_stop_tx,
540 .start_tx = linflex_start_tx,
541 .stop_rx = linflex_stop_rx,
542 .break_ctl = linflex_break_ctl,
543 .startup = linflex_startup,
544 .shutdown = linflex_shutdown,
545 .set_termios = linflex_set_termios,
546 .type = linflex_type,
547 .request_port = linflex_request_port,
548 .release_port = linflex_release_port,
549 .config_port = linflex_config_port,
550};
551
552static struct uart_port *linflex_ports[UART_NR];
553
554#ifdef CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE
555static void linflex_console_putchar(struct uart_port *port, unsigned char ch)
556{
557 unsigned long cr;
558
559 cr = readl(port->membase + UARTCR);
560
561 writeb(ch, port->membase + BDRL);
562
563 if (!(cr & LINFLEXD_UARTCR_TFBM))
564 while ((readl(port->membase + UARTSR) &
565 LINFLEXD_UARTSR_DTFTFF)
566 != LINFLEXD_UARTSR_DTFTFF)
567 ;
568 else
569 while (readl(port->membase + UARTSR) &
570 LINFLEXD_UARTSR_DTFTFF)
571 ;
572
573 if (!(cr & LINFLEXD_UARTCR_TFBM)) {
574 writel((readl(port->membase + UARTSR) |
575 LINFLEXD_UARTSR_DTFTFF),
576 port->membase + UARTSR);
577 }
578}
579
580static void linflex_earlycon_putchar(struct uart_port *port, unsigned char ch)
581{
582 unsigned long flags;
583 char *ret;
584
585 if (!linflex_earlycon_same_instance) {
586 linflex_console_putchar(port, ch);
587 return;
588 }
589
590 spin_lock_irqsave(&init_lock, flags);
591 if (!during_init)
592 goto outside_init;
593
594 if (earlycon_buf.len >= 1 << CONFIG_LOG_BUF_SHIFT)
595 goto init_release;
596
597 if (!earlycon_buf.cap) {
598 earlycon_buf.content = kmalloc(EARLYCON_BUFFER_INITIAL_CAP,
599 GFP_ATOMIC);
600 earlycon_buf.cap = earlycon_buf.content ?
601 EARLYCON_BUFFER_INITIAL_CAP : 0;
602 } else if (earlycon_buf.len == earlycon_buf.cap) {
603 ret = krealloc(earlycon_buf.content, earlycon_buf.cap << 1,
604 GFP_ATOMIC);
605 if (ret) {
606 earlycon_buf.content = ret;
607 earlycon_buf.cap <<= 1;
608 }
609 }
610
611 if (earlycon_buf.len < earlycon_buf.cap)
612 earlycon_buf.content[earlycon_buf.len++] = ch;
613
614 goto init_release;
615
616outside_init:
617 linflex_console_putchar(port, ch);
618init_release:
619 spin_unlock_irqrestore(&init_lock, flags);
620}
621
622static void linflex_string_write(struct uart_port *sport, const char *s,
623 unsigned int count)
624{
625 unsigned long cr, ier = 0;
626
627 ier = readl(sport->membase + LINIER);
628 linflex_stop_tx(sport);
629
630 cr = readl(sport->membase + UARTCR);
631 cr |= (LINFLEXD_UARTCR_TXEN);
632 writel(cr, sport->membase + UARTCR);
633
634 uart_console_write(sport, s, count, linflex_console_putchar);
635
636 writel(ier, sport->membase + LINIER);
637}
638
639static void
640linflex_console_write(struct console *co, const char *s, unsigned int count)
641{
642 struct uart_port *sport = linflex_ports[co->index];
643 unsigned long flags;
644 int locked = 1;
645
646 if (sport->sysrq)
647 locked = 0;
648 else if (oops_in_progress)
649 locked = uart_port_trylock_irqsave(sport, &flags);
650 else
651 uart_port_lock_irqsave(sport, &flags);
652
653 linflex_string_write(sport, s, count);
654
655 if (locked)
656 uart_port_unlock_irqrestore(sport, flags);
657}
658
659/*
660 * if the port was already initialised (eg, by a boot loader),
661 * try to determine the current setup.
662 */
663static void __init
664linflex_console_get_options(struct uart_port *sport, int *parity, int *bits)
665{
666 unsigned long cr;
667
668 cr = readl(sport->membase + UARTCR);
669 cr &= LINFLEXD_UARTCR_RXEN | LINFLEXD_UARTCR_TXEN;
670
671 if (!cr)
672 return;
673
674 /* ok, the port was enabled */
675
676 *parity = 'n';
677 if (cr & LINFLEXD_UARTCR_PCE) {
678 if (cr & LINFLEXD_UARTCR_PC0)
679 *parity = 'o';
680 else
681 *parity = 'e';
682 }
683
684 if ((cr & LINFLEXD_UARTCR_WL0) && ((cr & LINFLEXD_UARTCR_WL1) == 0)) {
685 if (cr & LINFLEXD_UARTCR_PCE)
686 *bits = 9;
687 else
688 *bits = 8;
689 }
690}
691
692static int __init linflex_console_setup(struct console *co, char *options)
693{
694 struct uart_port *sport;
695 int baud = 115200;
696 int bits = 8;
697 int parity = 'n';
698 int flow = 'n';
699 int ret;
700 int i;
701 unsigned long flags;
702 /*
703 * check whether an invalid uart number has been specified, and
704 * if so, search for the first available port that does have
705 * console support.
706 */
707 if (co->index == -1 || co->index >= ARRAY_SIZE(linflex_ports))
708 co->index = 0;
709
710 sport = linflex_ports[co->index];
711 if (!sport)
712 return -ENODEV;
713
714 if (options)
715 uart_parse_options(options, &baud, &parity, &bits, &flow);
716 else
717 linflex_console_get_options(sport, &parity, &bits);
718
719 if (earlycon_port && sport->mapbase == earlycon_port->mapbase) {
720 linflex_earlycon_same_instance = true;
721
722 spin_lock_irqsave(&init_lock, flags);
723 during_init = true;
724 spin_unlock_irqrestore(&init_lock, flags);
725
726 /* Workaround for character loss or output of many invalid
727 * characters, when INIT mode is entered shortly after a
728 * character has just been printed.
729 */
730 udelay(PREINIT_DELAY);
731 }
732
733 linflex_setup_watermark(sport);
734
735 ret = uart_set_options(sport, co, baud, parity, bits, flow);
736
737 if (!linflex_earlycon_same_instance)
738 goto done;
739
740 spin_lock_irqsave(&init_lock, flags);
741
742 /* Emptying buffer */
743 if (earlycon_buf.len) {
744 for (i = 0; i < earlycon_buf.len; i++)
745 linflex_console_putchar(earlycon_port,
746 earlycon_buf.content[i]);
747
748 kfree(earlycon_buf.content);
749 earlycon_buf.len = 0;
750 }
751
752 during_init = false;
753 spin_unlock_irqrestore(&init_lock, flags);
754
755done:
756 return ret;
757}
758
759static struct uart_driver linflex_reg;
760static struct console linflex_console = {
761 .name = DEV_NAME,
762 .write = linflex_console_write,
763 .device = uart_console_device,
764 .setup = linflex_console_setup,
765 .flags = CON_PRINTBUFFER,
766 .index = -1,
767 .data = &linflex_reg,
768};
769
770static void linflex_earlycon_write(struct console *con, const char *s,
771 unsigned int n)
772{
773 struct earlycon_device *dev = con->data;
774
775 uart_console_write(&dev->port, s, n, linflex_earlycon_putchar);
776}
777
778static int __init linflex_early_console_setup(struct earlycon_device *device,
779 const char *options)
780{
781 if (!device->port.membase)
782 return -ENODEV;
783
784 device->con->write = linflex_earlycon_write;
785 earlycon_port = &device->port;
786
787 return 0;
788}
789
790OF_EARLYCON_DECLARE(linflex, "fsl,s32v234-linflexuart",
791 linflex_early_console_setup);
792
793#define LINFLEX_CONSOLE (&linflex_console)
794#else
795#define LINFLEX_CONSOLE NULL
796#endif
797
798static struct uart_driver linflex_reg = {
799 .owner = THIS_MODULE,
800 .driver_name = DRIVER_NAME,
801 .dev_name = DEV_NAME,
802 .nr = ARRAY_SIZE(linflex_ports),
803 .cons = LINFLEX_CONSOLE,
804};
805
806static int linflex_probe(struct platform_device *pdev)
807{
808 struct device_node *np = pdev->dev.of_node;
809 struct uart_port *sport;
810 struct resource *res;
811 int ret;
812
813 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
814 if (!sport)
815 return -ENOMEM;
816
817 ret = of_alias_get_id(np, "serial");
818 if (ret < 0) {
819 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
820 return ret;
821 }
822 if (ret >= UART_NR) {
823 dev_err(&pdev->dev, "driver limited to %d serial ports\n",
824 UART_NR);
825 return -ENOMEM;
826 }
827
828 sport->line = ret;
829
830 sport->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
831 if (IS_ERR(sport->membase))
832 return PTR_ERR(sport->membase);
833 sport->mapbase = res->start;
834
835 ret = platform_get_irq(pdev, 0);
836 if (ret < 0)
837 return ret;
838
839 sport->dev = &pdev->dev;
840 sport->iotype = UPIO_MEM;
841 sport->irq = ret;
842 sport->ops = &linflex_pops;
843 sport->flags = UPF_BOOT_AUTOCONF;
844 sport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE);
845
846 linflex_ports[sport->line] = sport;
847
848 platform_set_drvdata(pdev, sport);
849
850 return uart_add_one_port(&linflex_reg, sport);
851}
852
853static void linflex_remove(struct platform_device *pdev)
854{
855 struct uart_port *sport = platform_get_drvdata(pdev);
856
857 uart_remove_one_port(&linflex_reg, sport);
858}
859
860#ifdef CONFIG_PM_SLEEP
861static int linflex_suspend(struct device *dev)
862{
863 struct uart_port *sport = dev_get_drvdata(dev);
864
865 uart_suspend_port(&linflex_reg, sport);
866
867 return 0;
868}
869
870static int linflex_resume(struct device *dev)
871{
872 struct uart_port *sport = dev_get_drvdata(dev);
873
874 uart_resume_port(&linflex_reg, sport);
875
876 return 0;
877}
878#endif
879
880static SIMPLE_DEV_PM_OPS(linflex_pm_ops, linflex_suspend, linflex_resume);
881
882static struct platform_driver linflex_driver = {
883 .probe = linflex_probe,
884 .remove_new = linflex_remove,
885 .driver = {
886 .name = DRIVER_NAME,
887 .of_match_table = linflex_dt_ids,
888 .pm = &linflex_pm_ops,
889 },
890};
891
892static int __init linflex_serial_init(void)
893{
894 int ret;
895
896 ret = uart_register_driver(&linflex_reg);
897 if (ret)
898 return ret;
899
900 ret = platform_driver_register(&linflex_driver);
901 if (ret)
902 uart_unregister_driver(&linflex_reg);
903
904 return ret;
905}
906
907static void __exit linflex_serial_exit(void)
908{
909 platform_driver_unregister(&linflex_driver);
910 uart_unregister_driver(&linflex_reg);
911}
912
913module_init(linflex_serial_init);
914module_exit(linflex_serial_exit);
915
916MODULE_DESCRIPTION("Freescale LINFlexD serial port driver");
917MODULE_LICENSE("GPL v2");