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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef ARCH_X86_CPU_H
3#define ARCH_X86_CPU_H
4
5/* attempt to consolidate cpu attributes */
6struct cpu_dev {
7 const char *c_vendor;
8
9 /* some have two possibilities for cpuid string */
10 const char *c_ident[2];
11
12 void (*c_early_init)(struct cpuinfo_x86 *);
13 void (*c_bsp_init)(struct cpuinfo_x86 *);
14 void (*c_init)(struct cpuinfo_x86 *);
15 void (*c_identify)(struct cpuinfo_x86 *);
16 void (*c_detect_tlb)(struct cpuinfo_x86 *);
17 int c_x86_vendor;
18#ifdef CONFIG_X86_32
19 /* Optional vendor specific routine to obtain the cache size. */
20 unsigned int (*legacy_cache_size)(struct cpuinfo_x86 *,
21 unsigned int);
22
23 /* Family/stepping-based lookup table for model names. */
24 struct legacy_cpu_model_info {
25 int family;
26 const char *model_names[16];
27 } legacy_models[5];
28#endif
29};
30
31struct _tlb_table {
32 unsigned char descriptor;
33 char tlb_type;
34 unsigned int entries;
35 /* unsigned int ways; */
36 char info[128];
37};
38
39#define cpu_dev_register(cpu_devX) \
40 static const struct cpu_dev *const __cpu_dev_##cpu_devX __used \
41 __attribute__((__section__(".x86_cpu_dev.init"))) = \
42 &cpu_devX;
43
44extern const struct cpu_dev *const __x86_cpu_dev_start[],
45 *const __x86_cpu_dev_end[];
46
47#ifdef CONFIG_CPU_SUP_INTEL
48enum tsx_ctrl_states {
49 TSX_CTRL_ENABLE,
50 TSX_CTRL_DISABLE,
51 TSX_CTRL_NOT_SUPPORTED,
52};
53
54extern __ro_after_init enum tsx_ctrl_states tsx_ctrl_state;
55
56extern void __init tsx_init(void);
57extern void tsx_enable(void);
58extern void tsx_disable(void);
59#else
60static inline void tsx_init(void) { }
61#endif /* CONFIG_CPU_SUP_INTEL */
62
63extern void get_cpu_cap(struct cpuinfo_x86 *c);
64extern void get_cpu_address_sizes(struct cpuinfo_x86 *c);
65extern void cpu_detect_cache_sizes(struct cpuinfo_x86 *c);
66extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
67extern void init_intel_cacheinfo(struct cpuinfo_x86 *c);
68extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
69extern void init_hygon_cacheinfo(struct cpuinfo_x86 *c);
70
71extern void detect_num_cpu_cores(struct cpuinfo_x86 *c);
72extern int detect_extended_topology_early(struct cpuinfo_x86 *c);
73extern int detect_extended_topology(struct cpuinfo_x86 *c);
74extern int detect_ht_early(struct cpuinfo_x86 *c);
75extern void detect_ht(struct cpuinfo_x86 *c);
76
77unsigned int aperfmperf_get_khz(int cpu);
78
79extern void x86_spec_ctrl_setup_ap(void);
80
81extern u64 x86_read_arch_cap_msr(void);
82
83#endif /* ARCH_X86_CPU_H */
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef ARCH_X86_CPU_H
3#define ARCH_X86_CPU_H
4
5#include <asm/cpu.h>
6#include <asm/topology.h>
7
8#include "topology.h"
9
10/* attempt to consolidate cpu attributes */
11struct cpu_dev {
12 const char *c_vendor;
13
14 /* some have two possibilities for cpuid string */
15 const char *c_ident[2];
16
17 void (*c_early_init)(struct cpuinfo_x86 *);
18 void (*c_bsp_init)(struct cpuinfo_x86 *);
19 void (*c_init)(struct cpuinfo_x86 *);
20 void (*c_identify)(struct cpuinfo_x86 *);
21 void (*c_detect_tlb)(struct cpuinfo_x86 *);
22 int c_x86_vendor;
23#ifdef CONFIG_X86_32
24 /* Optional vendor specific routine to obtain the cache size. */
25 unsigned int (*legacy_cache_size)(struct cpuinfo_x86 *,
26 unsigned int);
27
28 /* Family/stepping-based lookup table for model names. */
29 struct legacy_cpu_model_info {
30 int family;
31 const char *model_names[16];
32 } legacy_models[5];
33#endif
34};
35
36struct _tlb_table {
37 unsigned char descriptor;
38 char tlb_type;
39 unsigned int entries;
40 /* unsigned int ways; */
41 char info[128];
42};
43
44#define cpu_dev_register(cpu_devX) \
45 static const struct cpu_dev *const __cpu_dev_##cpu_devX __used \
46 __section(".x86_cpu_dev.init") = \
47 &cpu_devX;
48
49extern const struct cpu_dev *const __x86_cpu_dev_start[],
50 *const __x86_cpu_dev_end[];
51
52#ifdef CONFIG_CPU_SUP_INTEL
53enum tsx_ctrl_states {
54 TSX_CTRL_ENABLE,
55 TSX_CTRL_DISABLE,
56 TSX_CTRL_RTM_ALWAYS_ABORT,
57 TSX_CTRL_NOT_SUPPORTED,
58};
59
60extern __ro_after_init enum tsx_ctrl_states tsx_ctrl_state;
61
62extern void __init tsx_init(void);
63void tsx_ap_init(void);
64void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c);
65#else
66static inline void tsx_init(void) { }
67static inline void tsx_ap_init(void) { }
68static inline void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c) { }
69#endif /* CONFIG_CPU_SUP_INTEL */
70
71extern void init_spectral_chicken(struct cpuinfo_x86 *c);
72
73extern void get_cpu_cap(struct cpuinfo_x86 *c);
74extern void get_cpu_address_sizes(struct cpuinfo_x86 *c);
75extern void cpu_detect_cache_sizes(struct cpuinfo_x86 *c);
76extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
77extern void init_intel_cacheinfo(struct cpuinfo_x86 *c);
78extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
79extern void init_hygon_cacheinfo(struct cpuinfo_x86 *c);
80
81extern void check_null_seg_clears_base(struct cpuinfo_x86 *c);
82
83void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u16 die_id);
84void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c);
85
86unsigned int aperfmperf_get_khz(int cpu);
87void cpu_select_mitigations(void);
88
89extern void x86_spec_ctrl_setup_ap(void);
90extern void update_srbds_msr(void);
91extern void update_gds_msr(void);
92
93extern enum spectre_v2_mitigation spectre_v2_enabled;
94
95static inline bool spectre_v2_in_eibrs_mode(enum spectre_v2_mitigation mode)
96{
97 return mode == SPECTRE_V2_EIBRS ||
98 mode == SPECTRE_V2_EIBRS_RETPOLINE ||
99 mode == SPECTRE_V2_EIBRS_LFENCE;
100}
101
102#endif /* ARCH_X86_CPU_H */