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1/*
2 * arch/m68k/q40/config.c
3 *
4 * Copyright (C) 1999 Richard Zidlicky
5 *
6 * originally based on:
7 *
8 * linux/bvme/config.c
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file README.legal in the main directory of this archive
12 * for more details.
13 */
14
15#include <linux/errno.h>
16#include <linux/types.h>
17#include <linux/kernel.h>
18#include <linux/mm.h>
19#include <linux/tty.h>
20#include <linux/console.h>
21#include <linux/linkage.h>
22#include <linux/init.h>
23#include <linux/major.h>
24#include <linux/serial_reg.h>
25#include <linux/rtc.h>
26#include <linux/vt_kern.h>
27#include <linux/bcd.h>
28#include <linux/platform_device.h>
29
30#include <asm/io.h>
31#include <asm/bootinfo.h>
32#include <asm/pgtable.h>
33#include <asm/setup.h>
34#include <asm/irq.h>
35#include <asm/traps.h>
36#include <asm/machdep.h>
37#include <asm/q40_master.h>
38
39extern void q40_init_IRQ(void);
40static void q40_get_model(char *model);
41extern void q40_sched_init(irq_handler_t handler);
42
43static int q40_hwclk(int, struct rtc_time *);
44static unsigned int q40_get_ss(void);
45static int q40_get_rtc_pll(struct rtc_pll_info *pll);
46static int q40_set_rtc_pll(struct rtc_pll_info *pll);
47
48extern void q40_mksound(unsigned int /*freq*/, unsigned int /*ticks*/);
49
50static void q40_mem_console_write(struct console *co, const char *b,
51 unsigned int count);
52
53extern int ql_ticks;
54
55static struct console q40_console_driver = {
56 .name = "debug",
57 .write = q40_mem_console_write,
58 .flags = CON_PRINTBUFFER,
59 .index = -1,
60};
61
62
63/* early debugging function:*/
64extern char *q40_mem_cptr; /*=(char *)0xff020000;*/
65static int _cpleft;
66
67static void q40_mem_console_write(struct console *co, const char *s,
68 unsigned int count)
69{
70 const char *p = s;
71
72 if (count < _cpleft) {
73 while (count-- > 0) {
74 *q40_mem_cptr = *p++;
75 q40_mem_cptr += 4;
76 _cpleft--;
77 }
78 }
79}
80
81static int __init q40_debug_setup(char *arg)
82{
83 /* useful for early debugging stages - writes kernel messages into SRAM */
84 if (MACH_IS_Q40 && !strncmp(arg, "mem", 3)) {
85 /*pr_info("using NVRAM debug, q40_mem_cptr=%p\n",q40_mem_cptr);*/
86 _cpleft = 2000 - ((long)q40_mem_cptr-0xff020000) / 4;
87 register_console(&q40_console_driver);
88 }
89 return 0;
90}
91
92early_param("debug", q40_debug_setup);
93
94#if 0
95void printq40(char *str)
96{
97 int l = strlen(str);
98 char *p = q40_mem_cptr;
99
100 while (l-- > 0 && _cpleft-- > 0) {
101 *p = *str++;
102 p += 4;
103 }
104 q40_mem_cptr = p;
105}
106#endif
107
108static int halted;
109
110#ifdef CONFIG_HEARTBEAT
111static void q40_heartbeat(int on)
112{
113 if (halted)
114 return;
115
116 if (on)
117 Q40_LED_ON();
118 else
119 Q40_LED_OFF();
120}
121#endif
122
123static void q40_reset(void)
124{
125 halted = 1;
126 pr_info("*******************************************\n"
127 "Called q40_reset : press the RESET button!!\n"
128 "*******************************************\n");
129 Q40_LED_ON();
130 while (1)
131 ;
132}
133
134static void q40_halt(void)
135{
136 halted = 1;
137 pr_info("*******************\n"
138 " Called q40_halt\n"
139 "*******************\n");
140 Q40_LED_ON();
141 while (1)
142 ;
143}
144
145static void q40_get_model(char *model)
146{
147 sprintf(model, "Q40");
148}
149
150static unsigned int serports[] =
151{
152 0x3f8,0x2f8,0x3e8,0x2e8,0
153};
154
155static void __init q40_disable_irqs(void)
156{
157 unsigned i, j;
158
159 j = 0;
160 while ((i = serports[j++]))
161 outb(0, i + UART_IER);
162 master_outb(0, EXT_ENABLE_REG);
163 master_outb(0, KEY_IRQ_ENABLE_REG);
164}
165
166void __init config_q40(void)
167{
168 mach_sched_init = q40_sched_init;
169
170 mach_init_IRQ = q40_init_IRQ;
171 mach_hwclk = q40_hwclk;
172 mach_get_ss = q40_get_ss;
173 mach_get_rtc_pll = q40_get_rtc_pll;
174 mach_set_rtc_pll = q40_set_rtc_pll;
175
176 mach_reset = q40_reset;
177 mach_get_model = q40_get_model;
178
179#if IS_ENABLED(CONFIG_INPUT_M68K_BEEP)
180 mach_beep = q40_mksound;
181#endif
182#ifdef CONFIG_HEARTBEAT
183 mach_heartbeat = q40_heartbeat;
184#endif
185 mach_halt = q40_halt;
186
187 /* disable a few things that SMSQ might have left enabled */
188 q40_disable_irqs();
189
190 /* no DMA at all, but ide-scsi requires it.. make sure
191 * all physical RAM fits into the boundary - otherwise
192 * allocator may play costly and useless tricks */
193 mach_max_dma_address = 1024*1024*1024;
194}
195
196
197int __init q40_parse_bootinfo(const struct bi_record *rec)
198{
199 return 1;
200}
201
202/*
203 * Looks like op is non-zero for setting the clock, and zero for
204 * reading the clock.
205 *
206 * struct hwclk_time {
207 * unsigned sec; 0..59
208 * unsigned min; 0..59
209 * unsigned hour; 0..23
210 * unsigned day; 1..31
211 * unsigned mon; 0..11
212 * unsigned year; 00...
213 * int wday; 0..6, 0 is Sunday, -1 means unknown/don't set
214 * };
215 */
216
217static int q40_hwclk(int op, struct rtc_time *t)
218{
219 if (op) {
220 /* Write.... */
221 Q40_RTC_CTRL |= Q40_RTC_WRITE;
222
223 Q40_RTC_SECS = bin2bcd(t->tm_sec);
224 Q40_RTC_MINS = bin2bcd(t->tm_min);
225 Q40_RTC_HOUR = bin2bcd(t->tm_hour);
226 Q40_RTC_DATE = bin2bcd(t->tm_mday);
227 Q40_RTC_MNTH = bin2bcd(t->tm_mon + 1);
228 Q40_RTC_YEAR = bin2bcd(t->tm_year%100);
229 if (t->tm_wday >= 0)
230 Q40_RTC_DOW = bin2bcd(t->tm_wday+1);
231
232 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
233 } else {
234 /* Read.... */
235 Q40_RTC_CTRL |= Q40_RTC_READ;
236
237 t->tm_year = bcd2bin (Q40_RTC_YEAR);
238 t->tm_mon = bcd2bin (Q40_RTC_MNTH)-1;
239 t->tm_mday = bcd2bin (Q40_RTC_DATE);
240 t->tm_hour = bcd2bin (Q40_RTC_HOUR);
241 t->tm_min = bcd2bin (Q40_RTC_MINS);
242 t->tm_sec = bcd2bin (Q40_RTC_SECS);
243
244 Q40_RTC_CTRL &= ~(Q40_RTC_READ);
245
246 if (t->tm_year < 70)
247 t->tm_year += 100;
248 t->tm_wday = bcd2bin(Q40_RTC_DOW)-1;
249 }
250
251 return 0;
252}
253
254static unsigned int q40_get_ss(void)
255{
256 return bcd2bin(Q40_RTC_SECS);
257}
258
259/* get and set PLL calibration of RTC clock */
260#define Q40_RTC_PLL_MASK ((1<<5)-1)
261#define Q40_RTC_PLL_SIGN (1<<5)
262
263static int q40_get_rtc_pll(struct rtc_pll_info *pll)
264{
265 int tmp = Q40_RTC_CTRL;
266
267 pll->pll_value = tmp & Q40_RTC_PLL_MASK;
268 if (tmp & Q40_RTC_PLL_SIGN)
269 pll->pll_value = -pll->pll_value;
270 pll->pll_max = 31;
271 pll->pll_min = -31;
272 pll->pll_posmult = 512;
273 pll->pll_negmult = 256;
274 pll->pll_clock = 125829120;
275
276 return 0;
277}
278
279static int q40_set_rtc_pll(struct rtc_pll_info *pll)
280{
281 if (!pll->pll_ctrl) {
282 /* the docs are a bit unclear so I am doublesetting */
283 /* RTC_WRITE here ... */
284 int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) |
285 Q40_RTC_WRITE;
286 Q40_RTC_CTRL |= Q40_RTC_WRITE;
287 Q40_RTC_CTRL = tmp;
288 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
289 return 0;
290 } else
291 return -EINVAL;
292}
293
294static __init int q40_add_kbd_device(void)
295{
296 struct platform_device *pdev;
297
298 if (!MACH_IS_Q40)
299 return -ENODEV;
300
301 pdev = platform_device_register_simple("q40kbd", -1, NULL, 0);
302 return PTR_ERR_OR_ZERO(pdev);
303}
304arch_initcall(q40_add_kbd_device);
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * arch/m68k/q40/config.c
4 *
5 * Copyright (C) 1999 Richard Zidlicky
6 *
7 * originally based on:
8 *
9 * linux/bvme/config.c
10 */
11
12#include <linux/errno.h>
13#include <linux/types.h>
14#include <linux/kernel.h>
15#include <linux/mm.h>
16#include <linux/tty.h>
17#include <linux/console.h>
18#include <linux/linkage.h>
19#include <linux/init.h>
20#include <linux/major.h>
21#include <linux/serial_reg.h>
22#include <linux/rtc.h>
23#include <linux/vt_kern.h>
24#include <linux/bcd.h>
25#include <linux/platform_device.h>
26
27#include <asm/io.h>
28#include <asm/bootinfo.h>
29#include <asm/setup.h>
30#include <asm/irq.h>
31#include <asm/traps.h>
32#include <asm/machdep.h>
33#include <asm/q40_master.h>
34#include <asm/config.h>
35
36#include "q40.h"
37
38static void q40_get_model(char *model);
39
40static int q40_hwclk(int, struct rtc_time *);
41static int q40_get_rtc_pll(struct rtc_pll_info *pll);
42static int q40_set_rtc_pll(struct rtc_pll_info *pll);
43
44static void q40_mem_console_write(struct console *co, const char *b,
45 unsigned int count);
46
47extern int ql_ticks;
48
49static struct console q40_console_driver = {
50 .name = "debug",
51 .write = q40_mem_console_write,
52 .flags = CON_PRINTBUFFER,
53 .index = -1,
54};
55
56
57/* early debugging function:*/
58extern char *q40_mem_cptr; /*=(char *)0xff020000;*/
59static int _cpleft;
60
61static void q40_mem_console_write(struct console *co, const char *s,
62 unsigned int count)
63{
64 const char *p = s;
65
66 if (count < _cpleft) {
67 while (count-- > 0) {
68 *q40_mem_cptr = *p++;
69 q40_mem_cptr += 4;
70 _cpleft--;
71 }
72 }
73}
74
75static int __init q40_debug_setup(char *arg)
76{
77 /* useful for early debugging stages - writes kernel messages into SRAM */
78 if (MACH_IS_Q40 && !strncmp(arg, "mem", 3)) {
79 /*pr_info("using NVRAM debug, q40_mem_cptr=%p\n",q40_mem_cptr);*/
80 _cpleft = 2000 - ((long)q40_mem_cptr-0xff020000) / 4;
81 register_console(&q40_console_driver);
82 }
83 return 0;
84}
85
86early_param("debug", q40_debug_setup);
87
88#if 0
89void printq40(char *str)
90{
91 int l = strlen(str);
92 char *p = q40_mem_cptr;
93
94 while (l-- > 0 && _cpleft-- > 0) {
95 *p = *str++;
96 p += 4;
97 }
98 q40_mem_cptr = p;
99}
100#endif
101
102static int halted;
103
104#ifdef CONFIG_HEARTBEAT
105static void q40_heartbeat(int on)
106{
107 if (halted)
108 return;
109
110 if (on)
111 Q40_LED_ON();
112 else
113 Q40_LED_OFF();
114}
115#endif
116
117static void q40_reset(void)
118{
119 halted = 1;
120 pr_info("*******************************************\n"
121 "Called q40_reset : press the RESET button!!\n"
122 "*******************************************\n");
123 Q40_LED_ON();
124 while (1)
125 ;
126}
127
128static void q40_halt(void)
129{
130 halted = 1;
131 pr_info("*******************\n"
132 " Called q40_halt\n"
133 "*******************\n");
134 Q40_LED_ON();
135 while (1)
136 ;
137}
138
139static void q40_get_model(char *model)
140{
141 sprintf(model, "Q40");
142}
143
144static unsigned int serports[] =
145{
146 0x3f8,0x2f8,0x3e8,0x2e8,0
147};
148
149static void __init q40_disable_irqs(void)
150{
151 unsigned i, j;
152
153 j = 0;
154 while ((i = serports[j++]))
155 outb(0, i + UART_IER);
156 master_outb(0, EXT_ENABLE_REG);
157 master_outb(0, KEY_IRQ_ENABLE_REG);
158}
159
160void __init config_q40(void)
161{
162 mach_sched_init = q40_sched_init;
163
164 mach_init_IRQ = q40_init_IRQ;
165 mach_hwclk = q40_hwclk;
166 mach_get_rtc_pll = q40_get_rtc_pll;
167 mach_set_rtc_pll = q40_set_rtc_pll;
168
169 mach_reset = q40_reset;
170 mach_get_model = q40_get_model;
171
172#if IS_ENABLED(CONFIG_INPUT_M68K_BEEP)
173 mach_beep = q40_mksound;
174#endif
175#ifdef CONFIG_HEARTBEAT
176 mach_heartbeat = q40_heartbeat;
177#endif
178 mach_halt = q40_halt;
179
180 /* disable a few things that SMSQ might have left enabled */
181 q40_disable_irqs();
182}
183
184
185int __init q40_parse_bootinfo(const struct bi_record *rec)
186{
187 return 1;
188}
189
190/*
191 * Looks like op is non-zero for setting the clock, and zero for
192 * reading the clock.
193 *
194 * struct hwclk_time {
195 * unsigned sec; 0..59
196 * unsigned min; 0..59
197 * unsigned hour; 0..23
198 * unsigned day; 1..31
199 * unsigned mon; 0..11
200 * unsigned year; 00...
201 * int wday; 0..6, 0 is Sunday, -1 means unknown/don't set
202 * };
203 */
204
205static int q40_hwclk(int op, struct rtc_time *t)
206{
207 if (op) {
208 /* Write.... */
209 Q40_RTC_CTRL |= Q40_RTC_WRITE;
210
211 Q40_RTC_SECS = bin2bcd(t->tm_sec);
212 Q40_RTC_MINS = bin2bcd(t->tm_min);
213 Q40_RTC_HOUR = bin2bcd(t->tm_hour);
214 Q40_RTC_DATE = bin2bcd(t->tm_mday);
215 Q40_RTC_MNTH = bin2bcd(t->tm_mon + 1);
216 Q40_RTC_YEAR = bin2bcd(t->tm_year%100);
217 if (t->tm_wday >= 0)
218 Q40_RTC_DOW = bin2bcd(t->tm_wday+1);
219
220 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
221 } else {
222 /* Read.... */
223 Q40_RTC_CTRL |= Q40_RTC_READ;
224
225 t->tm_year = bcd2bin (Q40_RTC_YEAR);
226 t->tm_mon = bcd2bin (Q40_RTC_MNTH)-1;
227 t->tm_mday = bcd2bin (Q40_RTC_DATE);
228 t->tm_hour = bcd2bin (Q40_RTC_HOUR);
229 t->tm_min = bcd2bin (Q40_RTC_MINS);
230 t->tm_sec = bcd2bin (Q40_RTC_SECS);
231
232 Q40_RTC_CTRL &= ~(Q40_RTC_READ);
233
234 if (t->tm_year < 70)
235 t->tm_year += 100;
236 t->tm_wday = bcd2bin(Q40_RTC_DOW)-1;
237 }
238
239 return 0;
240}
241
242/* get and set PLL calibration of RTC clock */
243#define Q40_RTC_PLL_MASK ((1<<5)-1)
244#define Q40_RTC_PLL_SIGN (1<<5)
245
246static int q40_get_rtc_pll(struct rtc_pll_info *pll)
247{
248 int tmp = Q40_RTC_CTRL;
249
250 pll->pll_ctrl = 0;
251 pll->pll_value = tmp & Q40_RTC_PLL_MASK;
252 if (tmp & Q40_RTC_PLL_SIGN)
253 pll->pll_value = -pll->pll_value;
254 pll->pll_max = 31;
255 pll->pll_min = -31;
256 pll->pll_posmult = 512;
257 pll->pll_negmult = 256;
258 pll->pll_clock = 125829120;
259
260 return 0;
261}
262
263static int q40_set_rtc_pll(struct rtc_pll_info *pll)
264{
265 if (!pll->pll_ctrl) {
266 /* the docs are a bit unclear so I am doublesetting */
267 /* RTC_WRITE here ... */
268 int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) |
269 Q40_RTC_WRITE;
270 Q40_RTC_CTRL |= Q40_RTC_WRITE;
271 Q40_RTC_CTRL = tmp;
272 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
273 return 0;
274 } else
275 return -EINVAL;
276}
277
278#define PCIDE_BASE1 0x1f0
279#define PCIDE_BASE2 0x170
280#define PCIDE_CTL 0x206
281
282static const struct resource q40_pata_rsrc_0[] __initconst = {
283 DEFINE_RES_MEM(q40_isa_io_base + PCIDE_BASE1 * 4, 0x38),
284 DEFINE_RES_MEM(q40_isa_io_base + (PCIDE_BASE1 + PCIDE_CTL) * 4, 2),
285 DEFINE_RES_IO(PCIDE_BASE1, 8),
286 DEFINE_RES_IO(PCIDE_BASE1 + PCIDE_CTL, 1),
287 DEFINE_RES_IRQ(14),
288};
289
290static const struct resource q40_pata_rsrc_1[] __initconst = {
291 DEFINE_RES_MEM(q40_isa_io_base + PCIDE_BASE2 * 4, 0x38),
292 DEFINE_RES_MEM(q40_isa_io_base + (PCIDE_BASE2 + PCIDE_CTL) * 4, 2),
293 DEFINE_RES_IO(PCIDE_BASE2, 8),
294 DEFINE_RES_IO(PCIDE_BASE2 + PCIDE_CTL, 1),
295 DEFINE_RES_IRQ(15),
296};
297
298static __init int q40_platform_init(void)
299{
300 if (!MACH_IS_Q40)
301 return -ENODEV;
302
303 platform_device_register_simple("q40kbd", -1, NULL, 0);
304
305 platform_device_register_simple("atari-falcon-ide", 0, q40_pata_rsrc_0,
306 ARRAY_SIZE(q40_pata_rsrc_0));
307
308 platform_device_register_simple("atari-falcon-ide", 1, q40_pata_rsrc_1,
309 ARRAY_SIZE(q40_pata_rsrc_1));
310
311 return 0;
312}
313arch_initcall(q40_platform_init);