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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright(C) 2015 Linaro Limited. All rights reserved.
4 * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
5 */
6
7#ifndef INCLUDE__UTIL_PERF_CS_ETM_H__
8#define INCLUDE__UTIL_PERF_CS_ETM_H__
9
10#include "util/event.h"
11#include <linux/bits.h>
12
13struct perf_session;
14
15/* Versionning header in case things need tro change in the future. That way
16 * decoding of old snapshot is still possible.
17 */
18enum {
19 /* Starting with 0x0 */
20 CS_HEADER_VERSION_0,
21 /* PMU->type (32 bit), total # of CPUs (32 bit) */
22 CS_PMU_TYPE_CPUS,
23 CS_ETM_SNAPSHOT,
24 CS_HEADER_VERSION_0_MAX,
25};
26
27/* Beginning of header common to both ETMv3 and V4 */
28enum {
29 CS_ETM_MAGIC,
30 CS_ETM_CPU,
31};
32
33/* ETMv3/PTM metadata */
34enum {
35 /* Dynamic, configurable parameters */
36 CS_ETM_ETMCR = CS_ETM_CPU + 1,
37 CS_ETM_ETMTRACEIDR,
38 /* RO, taken from sysFS */
39 CS_ETM_ETMCCER,
40 CS_ETM_ETMIDR,
41 CS_ETM_PRIV_MAX,
42};
43
44/* ETMv4 metadata */
45enum {
46 /* Dynamic, configurable parameters */
47 CS_ETMV4_TRCCONFIGR = CS_ETM_CPU + 1,
48 CS_ETMV4_TRCTRACEIDR,
49 /* RO, taken from sysFS */
50 CS_ETMV4_TRCIDR0,
51 CS_ETMV4_TRCIDR1,
52 CS_ETMV4_TRCIDR2,
53 CS_ETMV4_TRCIDR8,
54 CS_ETMV4_TRCAUTHSTATUS,
55 CS_ETMV4_PRIV_MAX,
56};
57
58/*
59 * ETMv3 exception encoding number:
60 * See Embedded Trace Macrocell spcification (ARM IHI 0014Q)
61 * table 7-12 Encoding of Exception[3:0] for non-ARMv7-M processors.
62 */
63enum {
64 CS_ETMV3_EXC_NONE = 0,
65 CS_ETMV3_EXC_DEBUG_HALT = 1,
66 CS_ETMV3_EXC_SMC = 2,
67 CS_ETMV3_EXC_HYP = 3,
68 CS_ETMV3_EXC_ASYNC_DATA_ABORT = 4,
69 CS_ETMV3_EXC_JAZELLE_THUMBEE = 5,
70 CS_ETMV3_EXC_PE_RESET = 8,
71 CS_ETMV3_EXC_UNDEFINED_INSTR = 9,
72 CS_ETMV3_EXC_SVC = 10,
73 CS_ETMV3_EXC_PREFETCH_ABORT = 11,
74 CS_ETMV3_EXC_DATA_FAULT = 12,
75 CS_ETMV3_EXC_GENERIC = 13,
76 CS_ETMV3_EXC_IRQ = 14,
77 CS_ETMV3_EXC_FIQ = 15,
78};
79
80/*
81 * ETMv4 exception encoding number:
82 * See ARM Embedded Trace Macrocell Architecture Specification (ARM IHI 0064D)
83 * table 6-12 Possible values for the TYPE field in an Exception instruction
84 * trace packet, for ARMv7-A/R and ARMv8-A/R PEs.
85 */
86enum {
87 CS_ETMV4_EXC_RESET = 0,
88 CS_ETMV4_EXC_DEBUG_HALT = 1,
89 CS_ETMV4_EXC_CALL = 2,
90 CS_ETMV4_EXC_TRAP = 3,
91 CS_ETMV4_EXC_SYSTEM_ERROR = 4,
92 CS_ETMV4_EXC_INST_DEBUG = 6,
93 CS_ETMV4_EXC_DATA_DEBUG = 7,
94 CS_ETMV4_EXC_ALIGNMENT = 10,
95 CS_ETMV4_EXC_INST_FAULT = 11,
96 CS_ETMV4_EXC_DATA_FAULT = 12,
97 CS_ETMV4_EXC_IRQ = 14,
98 CS_ETMV4_EXC_FIQ = 15,
99 CS_ETMV4_EXC_END = 31,
100};
101
102enum cs_etm_sample_type {
103 CS_ETM_EMPTY,
104 CS_ETM_RANGE,
105 CS_ETM_DISCONTINUITY,
106 CS_ETM_EXCEPTION,
107 CS_ETM_EXCEPTION_RET,
108};
109
110enum cs_etm_isa {
111 CS_ETM_ISA_UNKNOWN,
112 CS_ETM_ISA_A64,
113 CS_ETM_ISA_A32,
114 CS_ETM_ISA_T32,
115};
116
117/* RB tree for quick conversion between traceID and metadata pointers */
118struct intlist *traceid_list;
119
120struct cs_etm_queue;
121
122struct cs_etm_packet {
123 enum cs_etm_sample_type sample_type;
124 enum cs_etm_isa isa;
125 u64 start_addr;
126 u64 end_addr;
127 u32 instr_count;
128 u32 last_instr_type;
129 u32 last_instr_subtype;
130 u32 flags;
131 u32 exception_number;
132 u8 last_instr_cond;
133 u8 last_instr_taken_branch;
134 u8 last_instr_size;
135 u8 trace_chan_id;
136 int cpu;
137};
138
139#define CS_ETM_PACKET_MAX_BUFFER 1024
140
141/*
142 * When working with per-thread scenarios the process under trace can
143 * be scheduled on any CPU and as such, more than one traceID may be
144 * associated with the same process. Since a traceID of '0' is illegal
145 * as per the CoreSight architecture, use that specific value to
146 * identify the queue where all packets (with any traceID) are
147 * aggregated.
148 */
149#define CS_ETM_PER_THREAD_TRACEID 0
150
151struct cs_etm_packet_queue {
152 u32 packet_count;
153 u32 head;
154 u32 tail;
155 u32 instr_count;
156 u64 timestamp;
157 u64 next_timestamp;
158 struct cs_etm_packet packet_buffer[CS_ETM_PACKET_MAX_BUFFER];
159};
160
161#define KiB(x) ((x) * 1024)
162#define MiB(x) ((x) * 1024 * 1024)
163
164#define CS_ETM_INVAL_ADDR 0xdeadbeefdeadbeefUL
165
166#define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
167
168#define CS_ETM_HEADER_SIZE (CS_HEADER_VERSION_0_MAX * sizeof(u64))
169
170#define __perf_cs_etmv3_magic 0x3030303030303030ULL
171#define __perf_cs_etmv4_magic 0x4040404040404040ULL
172#define CS_ETMV3_PRIV_SIZE (CS_ETM_PRIV_MAX * sizeof(u64))
173#define CS_ETMV4_PRIV_SIZE (CS_ETMV4_PRIV_MAX * sizeof(u64))
174
175#ifdef HAVE_CSTRACE_SUPPORT
176int cs_etm__process_auxtrace_info(union perf_event *event,
177 struct perf_session *session);
178int cs_etm__get_cpu(u8 trace_chan_id, int *cpu);
179int cs_etm__etmq_set_tid(struct cs_etm_queue *etmq,
180 pid_t tid, u8 trace_chan_id);
181bool cs_etm__etmq_is_timeless(struct cs_etm_queue *etmq);
182void cs_etm__etmq_set_traceid_queue_timestamp(struct cs_etm_queue *etmq,
183 u8 trace_chan_id);
184struct cs_etm_packet_queue
185*cs_etm__etmq_get_packet_queue(struct cs_etm_queue *etmq, u8 trace_chan_id);
186#else
187static inline int
188cs_etm__process_auxtrace_info(union perf_event *event __maybe_unused,
189 struct perf_session *session __maybe_unused)
190{
191 return -1;
192}
193
194static inline int cs_etm__get_cpu(u8 trace_chan_id __maybe_unused,
195 int *cpu __maybe_unused)
196{
197 return -1;
198}
199
200static inline int cs_etm__etmq_set_tid(
201 struct cs_etm_queue *etmq __maybe_unused,
202 pid_t tid __maybe_unused,
203 u8 trace_chan_id __maybe_unused)
204{
205 return -1;
206}
207
208static inline bool cs_etm__etmq_is_timeless(
209 struct cs_etm_queue *etmq __maybe_unused)
210{
211 /* What else to return? */
212 return true;
213}
214
215static inline void cs_etm__etmq_set_traceid_queue_timestamp(
216 struct cs_etm_queue *etmq __maybe_unused,
217 u8 trace_chan_id __maybe_unused) {}
218
219static inline struct cs_etm_packet_queue *cs_etm__etmq_get_packet_queue(
220 struct cs_etm_queue *etmq __maybe_unused,
221 u8 trace_chan_id __maybe_unused)
222{
223 return NULL;
224}
225#endif
226
227#endif
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright(C) 2015 Linaro Limited. All rights reserved.
4 * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
5 */
6
7#ifndef INCLUDE__UTIL_PERF_CS_ETM_H__
8#define INCLUDE__UTIL_PERF_CS_ETM_H__
9
10#include "debug.h"
11#include "util/event.h"
12#include <linux/bits.h>
13
14struct perf_session;
15struct perf_pmu;
16
17/*
18 * Versioning header in case things need to change in the future. That way
19 * decoding of old snapshot is still possible.
20 */
21enum {
22 /* Starting with 0x0 */
23 CS_HEADER_VERSION,
24 /* PMU->type (32 bit), total # of CPUs (32 bit) */
25 CS_PMU_TYPE_CPUS,
26 CS_ETM_SNAPSHOT,
27 CS_HEADER_VERSION_MAX,
28};
29
30/*
31 * Update the version for new format.
32 *
33 * Version 1: format adds a param count to the per cpu metadata.
34 * This allows easy adding of new metadata parameters.
35 * Requires that new params always added after current ones.
36 * Also allows client reader to handle file versions that are different by
37 * checking the number of params in the file vs the number expected.
38 *
39 * Version 2: Drivers will use PERF_RECORD_AUX_OUTPUT_HW_ID to output
40 * CoreSight Trace ID. ...TRACEIDR metadata will be set to legacy values
41 * but with addition flags.
42 */
43#define CS_HEADER_CURRENT_VERSION 2
44
45/* Beginning of header common to both ETMv3 and V4 */
46enum {
47 CS_ETM_MAGIC,
48 CS_ETM_CPU,
49 /* Number of trace config params in following ETM specific block */
50 CS_ETM_NR_TRC_PARAMS,
51 CS_ETM_COMMON_BLK_MAX_V1,
52};
53
54/* ETMv3/PTM metadata */
55enum {
56 /* Dynamic, configurable parameters */
57 CS_ETM_ETMCR = CS_ETM_COMMON_BLK_MAX_V1,
58 CS_ETM_ETMTRACEIDR,
59 /* RO, taken from sysFS */
60 CS_ETM_ETMCCER,
61 CS_ETM_ETMIDR,
62 CS_ETM_PRIV_MAX,
63};
64
65/* define fixed version 0 length - allow new format reader to read old files. */
66#define CS_ETM_NR_TRC_PARAMS_V0 (CS_ETM_ETMIDR - CS_ETM_ETMCR + 1)
67
68/* ETMv4 metadata */
69enum {
70 /* Dynamic, configurable parameters */
71 CS_ETMV4_TRCCONFIGR = CS_ETM_COMMON_BLK_MAX_V1,
72 CS_ETMV4_TRCTRACEIDR,
73 /* RO, taken from sysFS */
74 CS_ETMV4_TRCIDR0,
75 CS_ETMV4_TRCIDR1,
76 CS_ETMV4_TRCIDR2,
77 CS_ETMV4_TRCIDR8,
78 CS_ETMV4_TRCAUTHSTATUS,
79 CS_ETMV4_TS_SOURCE,
80 CS_ETMV4_PRIV_MAX,
81};
82
83/* define fixed version 0 length - allow new format reader to read old files. */
84#define CS_ETMV4_NR_TRC_PARAMS_V0 (CS_ETMV4_TRCAUTHSTATUS - CS_ETMV4_TRCCONFIGR + 1)
85
86/*
87 * ETE metadata is ETMv4 plus TRCDEVARCH register and doesn't support header V0 since it was
88 * added in header V1
89 */
90enum {
91 /* Dynamic, configurable parameters */
92 CS_ETE_TRCCONFIGR = CS_ETM_COMMON_BLK_MAX_V1,
93 CS_ETE_TRCTRACEIDR,
94 /* RO, taken from sysFS */
95 CS_ETE_TRCIDR0,
96 CS_ETE_TRCIDR1,
97 CS_ETE_TRCIDR2,
98 CS_ETE_TRCIDR8,
99 CS_ETE_TRCAUTHSTATUS,
100 CS_ETE_TRCDEVARCH,
101 CS_ETE_TS_SOURCE,
102 CS_ETE_PRIV_MAX
103};
104
105/*
106 * Check for valid CoreSight trace ID. If an invalid value is present in the metadata,
107 * then IDs are present in the hardware ID packet in the data file.
108 */
109#define CS_IS_VALID_TRACE_ID(id) ((id > 0) && (id < 0x70))
110
111/*
112 * ETMv3 exception encoding number:
113 * See Embedded Trace Macrocell specification (ARM IHI 0014Q)
114 * table 7-12 Encoding of Exception[3:0] for non-ARMv7-M processors.
115 */
116enum {
117 CS_ETMV3_EXC_NONE = 0,
118 CS_ETMV3_EXC_DEBUG_HALT = 1,
119 CS_ETMV3_EXC_SMC = 2,
120 CS_ETMV3_EXC_HYP = 3,
121 CS_ETMV3_EXC_ASYNC_DATA_ABORT = 4,
122 CS_ETMV3_EXC_JAZELLE_THUMBEE = 5,
123 CS_ETMV3_EXC_PE_RESET = 8,
124 CS_ETMV3_EXC_UNDEFINED_INSTR = 9,
125 CS_ETMV3_EXC_SVC = 10,
126 CS_ETMV3_EXC_PREFETCH_ABORT = 11,
127 CS_ETMV3_EXC_DATA_FAULT = 12,
128 CS_ETMV3_EXC_GENERIC = 13,
129 CS_ETMV3_EXC_IRQ = 14,
130 CS_ETMV3_EXC_FIQ = 15,
131};
132
133/*
134 * ETMv4 exception encoding number:
135 * See ARM Embedded Trace Macrocell Architecture Specification (ARM IHI 0064D)
136 * table 6-12 Possible values for the TYPE field in an Exception instruction
137 * trace packet, for ARMv7-A/R and ARMv8-A/R PEs.
138 */
139enum {
140 CS_ETMV4_EXC_RESET = 0,
141 CS_ETMV4_EXC_DEBUG_HALT = 1,
142 CS_ETMV4_EXC_CALL = 2,
143 CS_ETMV4_EXC_TRAP = 3,
144 CS_ETMV4_EXC_SYSTEM_ERROR = 4,
145 CS_ETMV4_EXC_INST_DEBUG = 6,
146 CS_ETMV4_EXC_DATA_DEBUG = 7,
147 CS_ETMV4_EXC_ALIGNMENT = 10,
148 CS_ETMV4_EXC_INST_FAULT = 11,
149 CS_ETMV4_EXC_DATA_FAULT = 12,
150 CS_ETMV4_EXC_IRQ = 14,
151 CS_ETMV4_EXC_FIQ = 15,
152 CS_ETMV4_EXC_END = 31,
153};
154
155enum cs_etm_sample_type {
156 CS_ETM_EMPTY,
157 CS_ETM_RANGE,
158 CS_ETM_DISCONTINUITY,
159 CS_ETM_EXCEPTION,
160 CS_ETM_EXCEPTION_RET,
161};
162
163enum cs_etm_isa {
164 CS_ETM_ISA_UNKNOWN,
165 CS_ETM_ISA_A64,
166 CS_ETM_ISA_A32,
167 CS_ETM_ISA_T32,
168};
169
170struct cs_etm_queue;
171
172struct cs_etm_packet {
173 enum cs_etm_sample_type sample_type;
174 enum cs_etm_isa isa;
175 u64 start_addr;
176 u64 end_addr;
177 u32 instr_count;
178 u32 last_instr_type;
179 u32 last_instr_subtype;
180 u32 flags;
181 u32 exception_number;
182 bool last_instr_cond;
183 bool last_instr_taken_branch;
184 u8 last_instr_size;
185 u8 trace_chan_id;
186 int cpu;
187};
188
189#define CS_ETM_PACKET_MAX_BUFFER 1024
190
191/*
192 * When working with per-thread scenarios the process under trace can
193 * be scheduled on any CPU and as such, more than one traceID may be
194 * associated with the same process. Since a traceID of '0' is illegal
195 * as per the CoreSight architecture, use that specific value to
196 * identify the queue where all packets (with any traceID) are
197 * aggregated.
198 */
199#define CS_ETM_PER_THREAD_TRACEID 0
200
201struct cs_etm_packet_queue {
202 u32 packet_count;
203 u32 head;
204 u32 tail;
205 u32 instr_count;
206 u64 cs_timestamp; /* Timestamp from trace data, converted to ns if possible */
207 u64 next_cs_timestamp;
208 struct cs_etm_packet packet_buffer[CS_ETM_PACKET_MAX_BUFFER];
209};
210
211#define KiB(x) ((x) * 1024)
212#define MiB(x) ((x) * 1024 * 1024)
213
214#define CS_ETM_INVAL_ADDR 0xdeadbeefdeadbeefUL
215
216#define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
217
218#define CS_ETM_HEADER_SIZE (CS_HEADER_VERSION_MAX * sizeof(u64))
219
220#define __perf_cs_etmv3_magic 0x3030303030303030ULL
221#define __perf_cs_etmv4_magic 0x4040404040404040ULL
222#define __perf_cs_ete_magic 0x5050505050505050ULL
223#define CS_ETMV3_PRIV_SIZE (CS_ETM_PRIV_MAX * sizeof(u64))
224#define CS_ETMV4_PRIV_SIZE (CS_ETMV4_PRIV_MAX * sizeof(u64))
225#define CS_ETE_PRIV_SIZE (CS_ETE_PRIV_MAX * sizeof(u64))
226
227#define INFO_HEADER_SIZE (sizeof(((struct perf_record_auxtrace_info *)0)->type) + \
228 sizeof(((struct perf_record_auxtrace_info *)0)->reserved__))
229
230/* CoreSight trace ID is currently the bottom 7 bits of the value */
231#define CORESIGHT_TRACE_ID_VAL_MASK GENMASK(6, 0)
232
233/*
234 * perf record will set the legacy meta data values as unused initially.
235 * This allows perf report to manage the decoders created when dynamic
236 * allocation in operation.
237 */
238#define CORESIGHT_TRACE_ID_UNUSED_FLAG BIT(31)
239
240/* Value to set for unused trace ID values */
241#define CORESIGHT_TRACE_ID_UNUSED_VAL 0x7F
242
243int cs_etm__process_auxtrace_info(union perf_event *event,
244 struct perf_session *session);
245void cs_etm_get_default_config(const struct perf_pmu *pmu, struct perf_event_attr *attr);
246
247enum cs_etm_pid_fmt {
248 CS_ETM_PIDFMT_NONE,
249 CS_ETM_PIDFMT_CTXTID,
250 CS_ETM_PIDFMT_CTXTID2
251};
252
253#ifdef HAVE_CSTRACE_SUPPORT
254#include <opencsd/ocsd_if_types.h>
255int cs_etm__get_cpu(u8 trace_chan_id, int *cpu);
256enum cs_etm_pid_fmt cs_etm__get_pid_fmt(struct cs_etm_queue *etmq);
257int cs_etm__etmq_set_tid_el(struct cs_etm_queue *etmq, pid_t tid,
258 u8 trace_chan_id, ocsd_ex_level el);
259bool cs_etm__etmq_is_timeless(struct cs_etm_queue *etmq);
260void cs_etm__etmq_set_traceid_queue_timestamp(struct cs_etm_queue *etmq,
261 u8 trace_chan_id);
262struct cs_etm_packet_queue
263*cs_etm__etmq_get_packet_queue(struct cs_etm_queue *etmq, u8 trace_chan_id);
264int cs_etm__process_auxtrace_info_full(union perf_event *event __maybe_unused,
265 struct perf_session *session __maybe_unused);
266u64 cs_etm__convert_sample_time(struct cs_etm_queue *etmq, u64 cs_timestamp);
267#else
268static inline int
269cs_etm__process_auxtrace_info_full(union perf_event *event __maybe_unused,
270 struct perf_session *session __maybe_unused)
271{
272 pr_err("\nCS ETM Trace: OpenCSD is not linked in, please recompile with CORESIGHT=1\n");
273 return -1;
274}
275#endif
276
277#endif