1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * VIA Camera register definitions.
 4 */
 5#define VCR_INTCTRL	0x300	/* Capture interrupt control */
 6#define   VCR_IC_EAV	  0x0001   /* End of active video status */
 7#define	  VCR_IC_EVBI	  0x0002   /* End of VBI status */
 8#define   VCR_IC_FBOTFLD  0x0004   /* "flipping" Bottom field is active */
 9#define   VCR_IC_ACTBUF	  0x0018   /* Active video buffer  */
10#define   VCR_IC_VSYNC	  0x0020   /* 0 = VB, 1 = active video */
11#define   VCR_IC_BOTFLD	  0x0040   /* Bottom field is active */
12#define   VCR_IC_FFULL	  0x0080   /* FIFO full */
13#define   VCR_IC_INTEN	  0x0100   /* End of active video int. enable */
14#define   VCR_IC_VBIINT	  0x0200   /* End of VBI int enable */
15#define   VCR_IC_VBIBUF	  0x0400   /* Current VBI buffer */
16
17#define VCR_TSC		0x308	/* Transport stream control */
18#define VCR_TSC_ENABLE    0x000001   /* Transport stream input enable */
19#define VCR_TSC_DROPERR   0x000002   /* Drop error packets */
20#define VCR_TSC_METHOD    0x00000c   /* DMA method (non-functional) */
21#define VCR_TSC_COUNT     0x07fff0   /* KByte or packet count */
22#define VCR_TSC_CBMODE	  0x080000   /* Change buffer by byte count */
23#define VCR_TSC_PSSIG	  0x100000   /* Packet starting signal disable */
24#define VCR_TSC_BE	  0x200000   /* MSB first (serial mode) */
25#define VCR_TSC_SERIAL	  0x400000   /* Serial input (0 = parallel) */
26
27#define VCR_CAPINTC	0x310	/* Capture interface control */
28#define   VCR_CI_ENABLE   0x00000001  /* Capture enable */
29#define   VCR_CI_BSS	  0x00000002  /* WTF "bit stream selection" */
30#define   VCR_CI_3BUFS	  0x00000004  /* 1 = 3 buffers, 0 = 2 buffers */
31#define   VCR_CI_VIPEN	  0x00000008  /* VIP enable */
32#define   VCR_CI_CCIR601_8  0		/* CCIR601 input stream, 8 bit */
33#define   VCR_CI_CCIR656_8  0x00000010  /* ... CCIR656, 8 bit */
34#define   VCR_CI_CCIR601_16 0x00000020  /* ... CCIR601, 16 bit */
35#define   VCR_CI_CCIR656_16 0x00000030  /* ... CCIR656, 16 bit */
36#define   VCR_CI_HDMODE   0x00000040  /* CCIR656-16 hdr decode mode; 1=16b */
37#define   VCR_CI_BSWAP    0x00000080  /* Swap bytes (16-bit) */
38#define   VCR_CI_YUYV	  0	      /* Byte order 0123 */
39#define   VCR_CI_UYVY	  0x00000100  /* Byte order 1032 */
40#define   VCR_CI_YVYU	  0x00000200  /* Byte order 0321 */
41#define   VCR_CI_VYUY	  0x00000300  /* Byte order 3012 */
42#define   VCR_CI_VIPTYPE  0x00000400  /* VIP type */
43#define   VCR_CI_IFSEN    0x00000800  /* Input field signal enable */
44#define   VCR_CI_DIODD	  0	      /* De-interlace odd, 30fps */
45#define   VCR_CI_DIEVEN   0x00001000  /*    ...even field, 30fps */
46#define   VCR_CI_DIBOTH   0x00002000  /*    ...both fields, 60fps */
47#define   VCR_CI_DIBOTH30 0x00003000  /*    ...both fields, 30fps interlace */
48#define   VCR_CI_CONVTYPE 0x00004000  /* 4:2:2 to 4:4:4; 1 = interpolate */
49#define   VCR_CI_CFC	  0x00008000  /* Capture flipping control */
50#define   VCR_CI_FILTER   0x00070000  /* Horiz filter mode select
51					 000 = none
52					 001 = 2 tap
53					 010 = 3 tap
54					 011 = 4 tap
55					 100 = 5 tap */
56#define   VCR_CI_CLKINV   0x00080000  /* Input CLK inverted */
57#define   VCR_CI_VREFINV  0x00100000  /* VREF inverted */
58#define   VCR_CI_HREFINV  0x00200000  /* HREF inverted */
59#define   VCR_CI_FLDINV   0x00400000  /* Field inverted */
60#define   VCR_CI_CLKPIN	  0x00800000  /* Capture clock pin */
61#define   VCR_CI_THRESH   0x0f000000  /* Capture fifo threshold */
62#define   VCR_CI_HRLE     0x10000000  /* Positive edge of HREF */
63#define   VCR_CI_VRLE     0x20000000  /* Positive edge of VREF */
64#define   VCR_CI_OFLDINV  0x40000000  /* Field output inverted */
65#define   VCR_CI_CLKEN    0x80000000  /* Capture clock enable */
66
67#define VCR_HORRANGE	0x314	/* Active video horizontal range */
68#define VCR_VERTRANGE	0x318	/* Active video vertical range */
69#define VCR_AVSCALE	0x31c	/* Active video scaling control */
70#define   VCR_AVS_HEN	  0x00000800   /* Horizontal scale enable */
71#define   VCR_AVS_VEN	  0x04000000   /* Vertical enable */
72#define VCR_VBIHOR	0x320	/* VBI Data horizontal range */
73#define VCR_VBIVERT	0x324	/* VBI data vertical range */
74#define VCR_VBIBUF1	0x328	/* First VBI buffer */
75#define VCR_VBISTRIDE	0x32c	/* VBI stride */
76#define VCR_ANCDATACNT	0x330	/* Ancillary data count setting */
77#define VCR_MAXDATA	0x334	/* Active data count of active video */
78#define VCR_MAXVBI	0x338	/* Maximum data count of VBI */
79#define VCR_CAPDATA	0x33c	/* Capture data count */
80#define VCR_VBUF1	0x340	/* First video buffer */
81#define VCR_VBUF2	0x344	/* Second video buffer */
82#define VCR_VBUF3	0x348	/* Third video buffer */
83#define VCR_VBUF_MASK	0x1ffffff0	/* Bits 28:4 */
84#define VCR_VBIBUF2	0x34c	/* Second VBI buffer */
85#define VCR_VSTRIDE	0x350	/* Stride of video + coring control */
86#define   VCR_VS_STRIDE_SHIFT 4
87#define   VCR_VS_STRIDE   0x00001ff0  /* Stride (8-byte units) */
88#define   VCR_VS_CCD	  0x007f0000  /* Coring compare data */
89#define   VCR_VS_COREEN   0x00800000  /* Coring enable */
90#define VCR_TS0ERR	0x354	/* TS buffer 0 error indicator */
91#define VCR_TS1ERR	0x358	/* TS buffer 0 error indicator */
92#define VCR_TS2ERR	0x35c	/* TS buffer 0 error indicator */
93
94/* Add 0x1000 for the second capture engine registers */