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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 */
6
7#include "msm_gpu.h"
8#include "msm_gem.h"
9#include "msm_mmu.h"
10#include "msm_fence.h"
11#include "msm_gpu_trace.h"
12#include "adreno/adreno_gpu.h"
13
14#include <generated/utsrelease.h>
15#include <linux/string_helpers.h>
16#include <linux/pm_opp.h>
17#include <linux/devfreq.h>
18#include <linux/devcoredump.h>
19
20/*
21 * Power Management:
22 */
23
24static int msm_devfreq_target(struct device *dev, unsigned long *freq,
25 u32 flags)
26{
27 struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
28 struct dev_pm_opp *opp;
29
30 opp = devfreq_recommended_opp(dev, freq, flags);
31
32 if (IS_ERR(opp))
33 return PTR_ERR(opp);
34
35 if (gpu->funcs->gpu_set_freq)
36 gpu->funcs->gpu_set_freq(gpu, (u64)*freq);
37 else
38 clk_set_rate(gpu->core_clk, *freq);
39
40 dev_pm_opp_put(opp);
41
42 return 0;
43}
44
45static int msm_devfreq_get_dev_status(struct device *dev,
46 struct devfreq_dev_status *status)
47{
48 struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
49 ktime_t time;
50
51 if (gpu->funcs->gpu_get_freq)
52 status->current_frequency = gpu->funcs->gpu_get_freq(gpu);
53 else
54 status->current_frequency = clk_get_rate(gpu->core_clk);
55
56 status->busy_time = gpu->funcs->gpu_busy(gpu);
57
58 time = ktime_get();
59 status->total_time = ktime_us_delta(time, gpu->devfreq.time);
60 gpu->devfreq.time = time;
61
62 return 0;
63}
64
65static int msm_devfreq_get_cur_freq(struct device *dev, unsigned long *freq)
66{
67 struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
68
69 if (gpu->funcs->gpu_get_freq)
70 *freq = gpu->funcs->gpu_get_freq(gpu);
71 else
72 *freq = clk_get_rate(gpu->core_clk);
73
74 return 0;
75}
76
77static struct devfreq_dev_profile msm_devfreq_profile = {
78 .polling_ms = 10,
79 .target = msm_devfreq_target,
80 .get_dev_status = msm_devfreq_get_dev_status,
81 .get_cur_freq = msm_devfreq_get_cur_freq,
82};
83
84static void msm_devfreq_init(struct msm_gpu *gpu)
85{
86 /* We need target support to do devfreq */
87 if (!gpu->funcs->gpu_busy)
88 return;
89
90 msm_devfreq_profile.initial_freq = gpu->fast_rate;
91
92 /*
93 * Don't set the freq_table or max_state and let devfreq build the table
94 * from OPP
95 */
96
97 gpu->devfreq.devfreq = devm_devfreq_add_device(&gpu->pdev->dev,
98 &msm_devfreq_profile, DEVFREQ_GOV_SIMPLE_ONDEMAND,
99 NULL);
100
101 if (IS_ERR(gpu->devfreq.devfreq)) {
102 DRM_DEV_ERROR(&gpu->pdev->dev, "Couldn't initialize GPU devfreq\n");
103 gpu->devfreq.devfreq = NULL;
104 }
105
106 devfreq_suspend_device(gpu->devfreq.devfreq);
107}
108
109static int enable_pwrrail(struct msm_gpu *gpu)
110{
111 struct drm_device *dev = gpu->dev;
112 int ret = 0;
113
114 if (gpu->gpu_reg) {
115 ret = regulator_enable(gpu->gpu_reg);
116 if (ret) {
117 DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_reg': %d\n", ret);
118 return ret;
119 }
120 }
121
122 if (gpu->gpu_cx) {
123 ret = regulator_enable(gpu->gpu_cx);
124 if (ret) {
125 DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_cx': %d\n", ret);
126 return ret;
127 }
128 }
129
130 return 0;
131}
132
133static int disable_pwrrail(struct msm_gpu *gpu)
134{
135 if (gpu->gpu_cx)
136 regulator_disable(gpu->gpu_cx);
137 if (gpu->gpu_reg)
138 regulator_disable(gpu->gpu_reg);
139 return 0;
140}
141
142static int enable_clk(struct msm_gpu *gpu)
143{
144 if (gpu->core_clk && gpu->fast_rate)
145 clk_set_rate(gpu->core_clk, gpu->fast_rate);
146
147 /* Set the RBBM timer rate to 19.2Mhz */
148 if (gpu->rbbmtimer_clk)
149 clk_set_rate(gpu->rbbmtimer_clk, 19200000);
150
151 return clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks);
152}
153
154static int disable_clk(struct msm_gpu *gpu)
155{
156 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks);
157
158 /*
159 * Set the clock to a deliberately low rate. On older targets the clock
160 * speed had to be non zero to avoid problems. On newer targets this
161 * will be rounded down to zero anyway so it all works out.
162 */
163 if (gpu->core_clk)
164 clk_set_rate(gpu->core_clk, 27000000);
165
166 if (gpu->rbbmtimer_clk)
167 clk_set_rate(gpu->rbbmtimer_clk, 0);
168
169 return 0;
170}
171
172static int enable_axi(struct msm_gpu *gpu)
173{
174 if (gpu->ebi1_clk)
175 clk_prepare_enable(gpu->ebi1_clk);
176 return 0;
177}
178
179static int disable_axi(struct msm_gpu *gpu)
180{
181 if (gpu->ebi1_clk)
182 clk_disable_unprepare(gpu->ebi1_clk);
183 return 0;
184}
185
186void msm_gpu_resume_devfreq(struct msm_gpu *gpu)
187{
188 gpu->devfreq.busy_cycles = 0;
189 gpu->devfreq.time = ktime_get();
190
191 devfreq_resume_device(gpu->devfreq.devfreq);
192}
193
194int msm_gpu_pm_resume(struct msm_gpu *gpu)
195{
196 int ret;
197
198 DBG("%s", gpu->name);
199
200 ret = enable_pwrrail(gpu);
201 if (ret)
202 return ret;
203
204 ret = enable_clk(gpu);
205 if (ret)
206 return ret;
207
208 ret = enable_axi(gpu);
209 if (ret)
210 return ret;
211
212 msm_gpu_resume_devfreq(gpu);
213
214 gpu->needs_hw_init = true;
215
216 return 0;
217}
218
219int msm_gpu_pm_suspend(struct msm_gpu *gpu)
220{
221 int ret;
222
223 DBG("%s", gpu->name);
224
225 devfreq_suspend_device(gpu->devfreq.devfreq);
226
227 ret = disable_axi(gpu);
228 if (ret)
229 return ret;
230
231 ret = disable_clk(gpu);
232 if (ret)
233 return ret;
234
235 ret = disable_pwrrail(gpu);
236 if (ret)
237 return ret;
238
239 return 0;
240}
241
242int msm_gpu_hw_init(struct msm_gpu *gpu)
243{
244 int ret;
245
246 WARN_ON(!mutex_is_locked(&gpu->dev->struct_mutex));
247
248 if (!gpu->needs_hw_init)
249 return 0;
250
251 disable_irq(gpu->irq);
252 ret = gpu->funcs->hw_init(gpu);
253 if (!ret)
254 gpu->needs_hw_init = false;
255 enable_irq(gpu->irq);
256
257 return ret;
258}
259
260#ifdef CONFIG_DEV_COREDUMP
261static ssize_t msm_gpu_devcoredump_read(char *buffer, loff_t offset,
262 size_t count, void *data, size_t datalen)
263{
264 struct msm_gpu *gpu = data;
265 struct drm_print_iterator iter;
266 struct drm_printer p;
267 struct msm_gpu_state *state;
268
269 state = msm_gpu_crashstate_get(gpu);
270 if (!state)
271 return 0;
272
273 iter.data = buffer;
274 iter.offset = 0;
275 iter.start = offset;
276 iter.remain = count;
277
278 p = drm_coredump_printer(&iter);
279
280 drm_printf(&p, "---\n");
281 drm_printf(&p, "kernel: " UTS_RELEASE "\n");
282 drm_printf(&p, "module: " KBUILD_MODNAME "\n");
283 drm_printf(&p, "time: %lld.%09ld\n",
284 state->time.tv_sec, state->time.tv_nsec);
285 if (state->comm)
286 drm_printf(&p, "comm: %s\n", state->comm);
287 if (state->cmd)
288 drm_printf(&p, "cmdline: %s\n", state->cmd);
289
290 gpu->funcs->show(gpu, state, &p);
291
292 msm_gpu_crashstate_put(gpu);
293
294 return count - iter.remain;
295}
296
297static void msm_gpu_devcoredump_free(void *data)
298{
299 struct msm_gpu *gpu = data;
300
301 msm_gpu_crashstate_put(gpu);
302}
303
304static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state,
305 struct msm_gem_object *obj, u64 iova, u32 flags)
306{
307 struct msm_gpu_state_bo *state_bo = &state->bos[state->nr_bos];
308
309 /* Don't record write only objects */
310 state_bo->size = obj->base.size;
311 state_bo->iova = iova;
312
313 /* Only store data for non imported buffer objects marked for read */
314 if ((flags & MSM_SUBMIT_BO_READ) && !obj->base.import_attach) {
315 void *ptr;
316
317 state_bo->data = kvmalloc(obj->base.size, GFP_KERNEL);
318 if (!state_bo->data)
319 goto out;
320
321 ptr = msm_gem_get_vaddr_active(&obj->base);
322 if (IS_ERR(ptr)) {
323 kvfree(state_bo->data);
324 state_bo->data = NULL;
325 goto out;
326 }
327
328 memcpy(state_bo->data, ptr, obj->base.size);
329 msm_gem_put_vaddr(&obj->base);
330 }
331out:
332 state->nr_bos++;
333}
334
335static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
336 struct msm_gem_submit *submit, char *comm, char *cmd)
337{
338 struct msm_gpu_state *state;
339
340 /* Check if the target supports capturing crash state */
341 if (!gpu->funcs->gpu_state_get)
342 return;
343
344 /* Only save one crash state at a time */
345 if (gpu->crashstate)
346 return;
347
348 state = gpu->funcs->gpu_state_get(gpu);
349 if (IS_ERR_OR_NULL(state))
350 return;
351
352 /* Fill in the additional crash state information */
353 state->comm = kstrdup(comm, GFP_KERNEL);
354 state->cmd = kstrdup(cmd, GFP_KERNEL);
355
356 if (submit) {
357 int i;
358
359 state->bos = kcalloc(submit->nr_cmds,
360 sizeof(struct msm_gpu_state_bo), GFP_KERNEL);
361
362 for (i = 0; state->bos && i < submit->nr_cmds; i++) {
363 int idx = submit->cmd[i].idx;
364
365 msm_gpu_crashstate_get_bo(state, submit->bos[idx].obj,
366 submit->bos[idx].iova, submit->bos[idx].flags);
367 }
368 }
369
370 /* Set the active crash state to be dumped on failure */
371 gpu->crashstate = state;
372
373 /* FIXME: Release the crashstate if this errors out? */
374 dev_coredumpm(gpu->dev->dev, THIS_MODULE, gpu, 0, GFP_KERNEL,
375 msm_gpu_devcoredump_read, msm_gpu_devcoredump_free);
376}
377#else
378static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
379 struct msm_gem_submit *submit, char *comm, char *cmd)
380{
381}
382#endif
383
384/*
385 * Hangcheck detection for locked gpu:
386 */
387
388static void update_fences(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
389 uint32_t fence)
390{
391 struct msm_gem_submit *submit;
392
393 list_for_each_entry(submit, &ring->submits, node) {
394 if (submit->seqno > fence)
395 break;
396
397 msm_update_fence(submit->ring->fctx,
398 submit->fence->seqno);
399 }
400}
401
402static struct msm_gem_submit *
403find_submit(struct msm_ringbuffer *ring, uint32_t fence)
404{
405 struct msm_gem_submit *submit;
406
407 WARN_ON(!mutex_is_locked(&ring->gpu->dev->struct_mutex));
408
409 list_for_each_entry(submit, &ring->submits, node)
410 if (submit->seqno == fence)
411 return submit;
412
413 return NULL;
414}
415
416static void retire_submits(struct msm_gpu *gpu);
417
418static void recover_worker(struct work_struct *work)
419{
420 struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work);
421 struct drm_device *dev = gpu->dev;
422 struct msm_drm_private *priv = dev->dev_private;
423 struct msm_gem_submit *submit;
424 struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
425 char *comm = NULL, *cmd = NULL;
426 int i;
427
428 mutex_lock(&dev->struct_mutex);
429
430 DRM_DEV_ERROR(dev->dev, "%s: hangcheck recover!\n", gpu->name);
431
432 submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1);
433 if (submit) {
434 struct task_struct *task;
435
436 /* Increment the fault counts */
437 gpu->global_faults++;
438 submit->queue->faults++;
439
440 task = get_pid_task(submit->pid, PIDTYPE_PID);
441 if (task) {
442 comm = kstrdup(task->comm, GFP_KERNEL);
443 cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL);
444 put_task_struct(task);
445 }
446
447 if (comm && cmd) {
448 DRM_DEV_ERROR(dev->dev, "%s: offending task: %s (%s)\n",
449 gpu->name, comm, cmd);
450
451 msm_rd_dump_submit(priv->hangrd, submit,
452 "offending task: %s (%s)", comm, cmd);
453 } else
454 msm_rd_dump_submit(priv->hangrd, submit, NULL);
455 }
456
457 /* Record the crash state */
458 pm_runtime_get_sync(&gpu->pdev->dev);
459 msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
460 pm_runtime_put_sync(&gpu->pdev->dev);
461
462 kfree(cmd);
463 kfree(comm);
464
465 /*
466 * Update all the rings with the latest and greatest fence.. this
467 * needs to happen after msm_rd_dump_submit() to ensure that the
468 * bo's referenced by the offending submit are still around.
469 */
470 for (i = 0; i < gpu->nr_rings; i++) {
471 struct msm_ringbuffer *ring = gpu->rb[i];
472
473 uint32_t fence = ring->memptrs->fence;
474
475 /*
476 * For the current (faulting?) ring/submit advance the fence by
477 * one more to clear the faulting submit
478 */
479 if (ring == cur_ring)
480 fence++;
481
482 update_fences(gpu, ring, fence);
483 }
484
485 if (msm_gpu_active(gpu)) {
486 /* retire completed submits, plus the one that hung: */
487 retire_submits(gpu);
488
489 pm_runtime_get_sync(&gpu->pdev->dev);
490 gpu->funcs->recover(gpu);
491 pm_runtime_put_sync(&gpu->pdev->dev);
492
493 /*
494 * Replay all remaining submits starting with highest priority
495 * ring
496 */
497 for (i = 0; i < gpu->nr_rings; i++) {
498 struct msm_ringbuffer *ring = gpu->rb[i];
499
500 list_for_each_entry(submit, &ring->submits, node)
501 gpu->funcs->submit(gpu, submit, NULL);
502 }
503 }
504
505 mutex_unlock(&dev->struct_mutex);
506
507 msm_gpu_retire(gpu);
508}
509
510static void hangcheck_timer_reset(struct msm_gpu *gpu)
511{
512 DBG("%s", gpu->name);
513 mod_timer(&gpu->hangcheck_timer,
514 round_jiffies_up(jiffies + DRM_MSM_HANGCHECK_JIFFIES));
515}
516
517static void hangcheck_handler(struct timer_list *t)
518{
519 struct msm_gpu *gpu = from_timer(gpu, t, hangcheck_timer);
520 struct drm_device *dev = gpu->dev;
521 struct msm_drm_private *priv = dev->dev_private;
522 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
523 uint32_t fence = ring->memptrs->fence;
524
525 if (fence != ring->hangcheck_fence) {
526 /* some progress has been made.. ya! */
527 ring->hangcheck_fence = fence;
528 } else if (fence < ring->seqno) {
529 /* no progress and not done.. hung! */
530 ring->hangcheck_fence = fence;
531 DRM_DEV_ERROR(dev->dev, "%s: hangcheck detected gpu lockup rb %d!\n",
532 gpu->name, ring->id);
533 DRM_DEV_ERROR(dev->dev, "%s: completed fence: %u\n",
534 gpu->name, fence);
535 DRM_DEV_ERROR(dev->dev, "%s: submitted fence: %u\n",
536 gpu->name, ring->seqno);
537
538 queue_work(priv->wq, &gpu->recover_work);
539 }
540
541 /* if still more pending work, reset the hangcheck timer: */
542 if (ring->seqno > ring->hangcheck_fence)
543 hangcheck_timer_reset(gpu);
544
545 /* workaround for missing irq: */
546 queue_work(priv->wq, &gpu->retire_work);
547}
548
549/*
550 * Performance Counters:
551 */
552
553/* called under perf_lock */
554static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs)
555{
556 uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)];
557 int i, n = min(ncntrs, gpu->num_perfcntrs);
558
559 /* read current values: */
560 for (i = 0; i < gpu->num_perfcntrs; i++)
561 current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg);
562
563 /* update cntrs: */
564 for (i = 0; i < n; i++)
565 cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i];
566
567 /* save current values: */
568 for (i = 0; i < gpu->num_perfcntrs; i++)
569 gpu->last_cntrs[i] = current_cntrs[i];
570
571 return n;
572}
573
574static void update_sw_cntrs(struct msm_gpu *gpu)
575{
576 ktime_t time;
577 uint32_t elapsed;
578 unsigned long flags;
579
580 spin_lock_irqsave(&gpu->perf_lock, flags);
581 if (!gpu->perfcntr_active)
582 goto out;
583
584 time = ktime_get();
585 elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time));
586
587 gpu->totaltime += elapsed;
588 if (gpu->last_sample.active)
589 gpu->activetime += elapsed;
590
591 gpu->last_sample.active = msm_gpu_active(gpu);
592 gpu->last_sample.time = time;
593
594out:
595 spin_unlock_irqrestore(&gpu->perf_lock, flags);
596}
597
598void msm_gpu_perfcntr_start(struct msm_gpu *gpu)
599{
600 unsigned long flags;
601
602 pm_runtime_get_sync(&gpu->pdev->dev);
603
604 spin_lock_irqsave(&gpu->perf_lock, flags);
605 /* we could dynamically enable/disable perfcntr registers too.. */
606 gpu->last_sample.active = msm_gpu_active(gpu);
607 gpu->last_sample.time = ktime_get();
608 gpu->activetime = gpu->totaltime = 0;
609 gpu->perfcntr_active = true;
610 update_hw_cntrs(gpu, 0, NULL);
611 spin_unlock_irqrestore(&gpu->perf_lock, flags);
612}
613
614void msm_gpu_perfcntr_stop(struct msm_gpu *gpu)
615{
616 gpu->perfcntr_active = false;
617 pm_runtime_put_sync(&gpu->pdev->dev);
618}
619
620/* returns -errno or # of cntrs sampled */
621int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
622 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs)
623{
624 unsigned long flags;
625 int ret;
626
627 spin_lock_irqsave(&gpu->perf_lock, flags);
628
629 if (!gpu->perfcntr_active) {
630 ret = -EINVAL;
631 goto out;
632 }
633
634 *activetime = gpu->activetime;
635 *totaltime = gpu->totaltime;
636
637 gpu->activetime = gpu->totaltime = 0;
638
639 ret = update_hw_cntrs(gpu, ncntrs, cntrs);
640
641out:
642 spin_unlock_irqrestore(&gpu->perf_lock, flags);
643
644 return ret;
645}
646
647/*
648 * Cmdstream submission/retirement:
649 */
650
651static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
652 struct msm_gem_submit *submit)
653{
654 int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
655 volatile struct msm_gpu_submit_stats *stats;
656 u64 elapsed, clock = 0;
657 int i;
658
659 stats = &ring->memptrs->stats[index];
660 /* Convert 19.2Mhz alwayson ticks to nanoseconds for elapsed time */
661 elapsed = (stats->alwayson_end - stats->alwayson_start) * 10000;
662 do_div(elapsed, 192);
663
664 /* Calculate the clock frequency from the number of CP cycles */
665 if (elapsed) {
666 clock = (stats->cpcycles_end - stats->cpcycles_start) * 1000;
667 do_div(clock, elapsed);
668 }
669
670 trace_msm_gpu_submit_retired(submit, elapsed, clock,
671 stats->alwayson_start, stats->alwayson_end);
672
673 for (i = 0; i < submit->nr_bos; i++) {
674 struct msm_gem_object *msm_obj = submit->bos[i].obj;
675 /* move to inactive: */
676 msm_gem_move_to_inactive(&msm_obj->base);
677 msm_gem_unpin_iova(&msm_obj->base, submit->aspace);
678 drm_gem_object_put(&msm_obj->base);
679 }
680
681 pm_runtime_mark_last_busy(&gpu->pdev->dev);
682 pm_runtime_put_autosuspend(&gpu->pdev->dev);
683 msm_gem_submit_free(submit);
684}
685
686static void retire_submits(struct msm_gpu *gpu)
687{
688 struct drm_device *dev = gpu->dev;
689 struct msm_gem_submit *submit, *tmp;
690 int i;
691
692 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
693
694 /* Retire the commits starting with highest priority */
695 for (i = 0; i < gpu->nr_rings; i++) {
696 struct msm_ringbuffer *ring = gpu->rb[i];
697
698 list_for_each_entry_safe(submit, tmp, &ring->submits, node) {
699 if (dma_fence_is_signaled(submit->fence))
700 retire_submit(gpu, ring, submit);
701 }
702 }
703}
704
705static void retire_worker(struct work_struct *work)
706{
707 struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work);
708 struct drm_device *dev = gpu->dev;
709 int i;
710
711 for (i = 0; i < gpu->nr_rings; i++)
712 update_fences(gpu, gpu->rb[i], gpu->rb[i]->memptrs->fence);
713
714 mutex_lock(&dev->struct_mutex);
715 retire_submits(gpu);
716 mutex_unlock(&dev->struct_mutex);
717}
718
719/* call from irq handler to schedule work to retire bo's */
720void msm_gpu_retire(struct msm_gpu *gpu)
721{
722 struct msm_drm_private *priv = gpu->dev->dev_private;
723 queue_work(priv->wq, &gpu->retire_work);
724 update_sw_cntrs(gpu);
725}
726
727/* add bo's to gpu's ring, and kick gpu: */
728void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
729 struct msm_file_private *ctx)
730{
731 struct drm_device *dev = gpu->dev;
732 struct msm_drm_private *priv = dev->dev_private;
733 struct msm_ringbuffer *ring = submit->ring;
734 int i;
735
736 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
737
738 pm_runtime_get_sync(&gpu->pdev->dev);
739
740 msm_gpu_hw_init(gpu);
741
742 submit->seqno = ++ring->seqno;
743
744 list_add_tail(&submit->node, &ring->submits);
745
746 msm_rd_dump_submit(priv->rd, submit, NULL);
747
748 update_sw_cntrs(gpu);
749
750 for (i = 0; i < submit->nr_bos; i++) {
751 struct msm_gem_object *msm_obj = submit->bos[i].obj;
752 uint64_t iova;
753
754 /* can't happen yet.. but when we add 2d support we'll have
755 * to deal w/ cross-ring synchronization:
756 */
757 WARN_ON(is_active(msm_obj) && (msm_obj->gpu != gpu));
758
759 /* submit takes a reference to the bo and iova until retired: */
760 drm_gem_object_get(&msm_obj->base);
761 msm_gem_get_and_pin_iova(&msm_obj->base, submit->aspace, &iova);
762
763 if (submit->bos[i].flags & MSM_SUBMIT_BO_WRITE)
764 msm_gem_move_to_active(&msm_obj->base, gpu, true, submit->fence);
765 else if (submit->bos[i].flags & MSM_SUBMIT_BO_READ)
766 msm_gem_move_to_active(&msm_obj->base, gpu, false, submit->fence);
767 }
768
769 gpu->funcs->submit(gpu, submit, ctx);
770 priv->lastctx = ctx;
771
772 hangcheck_timer_reset(gpu);
773}
774
775/*
776 * Init/Cleanup:
777 */
778
779static irqreturn_t irq_handler(int irq, void *data)
780{
781 struct msm_gpu *gpu = data;
782 return gpu->funcs->irq(gpu);
783}
784
785static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu)
786{
787 int ret = devm_clk_bulk_get_all(&pdev->dev, &gpu->grp_clks);
788
789 if (ret < 1) {
790 gpu->nr_clocks = 0;
791 return ret;
792 }
793
794 gpu->nr_clocks = ret;
795
796 gpu->core_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
797 gpu->nr_clocks, "core");
798
799 gpu->rbbmtimer_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
800 gpu->nr_clocks, "rbbmtimer");
801
802 return 0;
803}
804
805static struct msm_gem_address_space *
806msm_gpu_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev,
807 uint64_t va_start, uint64_t va_end)
808{
809 struct msm_gem_address_space *aspace;
810 int ret;
811
812 /*
813 * Setup IOMMU.. eventually we will (I think) do this once per context
814 * and have separate page tables per context. For now, to keep things
815 * simple and to get something working, just use a single address space:
816 */
817 if (!adreno_is_a2xx(to_adreno_gpu(gpu))) {
818 struct iommu_domain *iommu = iommu_domain_alloc(&platform_bus_type);
819 if (!iommu)
820 return NULL;
821
822 iommu->geometry.aperture_start = va_start;
823 iommu->geometry.aperture_end = va_end;
824
825 DRM_DEV_INFO(gpu->dev->dev, "%s: using IOMMU\n", gpu->name);
826
827 aspace = msm_gem_address_space_create(&pdev->dev, iommu, "gpu");
828 if (IS_ERR(aspace))
829 iommu_domain_free(iommu);
830 } else {
831 aspace = msm_gem_address_space_create_a2xx(&pdev->dev, gpu, "gpu",
832 va_start, va_end);
833 }
834
835 if (IS_ERR(aspace)) {
836 DRM_DEV_ERROR(gpu->dev->dev, "failed to init mmu: %ld\n",
837 PTR_ERR(aspace));
838 return ERR_CAST(aspace);
839 }
840
841 ret = aspace->mmu->funcs->attach(aspace->mmu, NULL, 0);
842 if (ret) {
843 msm_gem_address_space_put(aspace);
844 return ERR_PTR(ret);
845 }
846
847 return aspace;
848}
849
850int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
851 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
852 const char *name, struct msm_gpu_config *config)
853{
854 int i, ret, nr_rings = config->nr_rings;
855 void *memptrs;
856 uint64_t memptrs_iova;
857
858 if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs)))
859 gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs);
860
861 gpu->dev = drm;
862 gpu->funcs = funcs;
863 gpu->name = name;
864
865 INIT_LIST_HEAD(&gpu->active_list);
866 INIT_WORK(&gpu->retire_work, retire_worker);
867 INIT_WORK(&gpu->recover_work, recover_worker);
868
869
870 timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0);
871
872 spin_lock_init(&gpu->perf_lock);
873
874
875 /* Map registers: */
876 gpu->mmio = msm_ioremap(pdev, config->ioname, name);
877 if (IS_ERR(gpu->mmio)) {
878 ret = PTR_ERR(gpu->mmio);
879 goto fail;
880 }
881
882 /* Get Interrupt: */
883 gpu->irq = platform_get_irq(pdev, 0);
884 if (gpu->irq < 0) {
885 ret = gpu->irq;
886 DRM_DEV_ERROR(drm->dev, "failed to get irq: %d\n", ret);
887 goto fail;
888 }
889
890 ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler,
891 IRQF_TRIGGER_HIGH, gpu->name, gpu);
892 if (ret) {
893 DRM_DEV_ERROR(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret);
894 goto fail;
895 }
896
897 ret = get_clocks(pdev, gpu);
898 if (ret)
899 goto fail;
900
901 gpu->ebi1_clk = msm_clk_get(pdev, "bus");
902 DBG("ebi1_clk: %p", gpu->ebi1_clk);
903 if (IS_ERR(gpu->ebi1_clk))
904 gpu->ebi1_clk = NULL;
905
906 /* Acquire regulators: */
907 gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd");
908 DBG("gpu_reg: %p", gpu->gpu_reg);
909 if (IS_ERR(gpu->gpu_reg))
910 gpu->gpu_reg = NULL;
911
912 gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx");
913 DBG("gpu_cx: %p", gpu->gpu_cx);
914 if (IS_ERR(gpu->gpu_cx))
915 gpu->gpu_cx = NULL;
916
917 gpu->pdev = pdev;
918 platform_set_drvdata(pdev, gpu);
919
920 msm_devfreq_init(gpu);
921
922 gpu->aspace = msm_gpu_create_address_space(gpu, pdev,
923 config->va_start, config->va_end);
924
925 if (gpu->aspace == NULL)
926 DRM_DEV_INFO(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name);
927 else if (IS_ERR(gpu->aspace)) {
928 ret = PTR_ERR(gpu->aspace);
929 goto fail;
930 }
931
932 memptrs = msm_gem_kernel_new(drm,
933 sizeof(struct msm_rbmemptrs) * nr_rings,
934 MSM_BO_UNCACHED, gpu->aspace, &gpu->memptrs_bo,
935 &memptrs_iova);
936
937 if (IS_ERR(memptrs)) {
938 ret = PTR_ERR(memptrs);
939 DRM_DEV_ERROR(drm->dev, "could not allocate memptrs: %d\n", ret);
940 goto fail;
941 }
942
943 msm_gem_object_set_name(gpu->memptrs_bo, "memptrs");
944
945 if (nr_rings > ARRAY_SIZE(gpu->rb)) {
946 DRM_DEV_INFO_ONCE(drm->dev, "Only creating %zu ringbuffers\n",
947 ARRAY_SIZE(gpu->rb));
948 nr_rings = ARRAY_SIZE(gpu->rb);
949 }
950
951 /* Create ringbuffer(s): */
952 for (i = 0; i < nr_rings; i++) {
953 gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova);
954
955 if (IS_ERR(gpu->rb[i])) {
956 ret = PTR_ERR(gpu->rb[i]);
957 DRM_DEV_ERROR(drm->dev,
958 "could not create ringbuffer %d: %d\n", i, ret);
959 goto fail;
960 }
961
962 memptrs += sizeof(struct msm_rbmemptrs);
963 memptrs_iova += sizeof(struct msm_rbmemptrs);
964 }
965
966 gpu->nr_rings = nr_rings;
967
968 return 0;
969
970fail:
971 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
972 msm_ringbuffer_destroy(gpu->rb[i]);
973 gpu->rb[i] = NULL;
974 }
975
976 msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace, false);
977
978 platform_set_drvdata(pdev, NULL);
979 return ret;
980}
981
982void msm_gpu_cleanup(struct msm_gpu *gpu)
983{
984 int i;
985
986 DBG("%s", gpu->name);
987
988 WARN_ON(!list_empty(&gpu->active_list));
989
990 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
991 msm_ringbuffer_destroy(gpu->rb[i]);
992 gpu->rb[i] = NULL;
993 }
994
995 msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace, false);
996
997 if (!IS_ERR_OR_NULL(gpu->aspace)) {
998 gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu,
999 NULL, 0);
1000 msm_gem_address_space_put(gpu->aspace);
1001 }
1002}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 */
6
7#include "drm/drm_drv.h"
8
9#include "msm_gpu.h"
10#include "msm_gem.h"
11#include "msm_mmu.h"
12#include "msm_fence.h"
13#include "msm_gpu_trace.h"
14#include "adreno/adreno_gpu.h"
15
16#include <generated/utsrelease.h>
17#include <linux/string_helpers.h>
18#include <linux/devcoredump.h>
19#include <linux/sched/task.h>
20
21/*
22 * Power Management:
23 */
24
25static int enable_pwrrail(struct msm_gpu *gpu)
26{
27 struct drm_device *dev = gpu->dev;
28 int ret = 0;
29
30 if (gpu->gpu_reg) {
31 ret = regulator_enable(gpu->gpu_reg);
32 if (ret) {
33 DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_reg': %d\n", ret);
34 return ret;
35 }
36 }
37
38 if (gpu->gpu_cx) {
39 ret = regulator_enable(gpu->gpu_cx);
40 if (ret) {
41 DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_cx': %d\n", ret);
42 return ret;
43 }
44 }
45
46 return 0;
47}
48
49static int disable_pwrrail(struct msm_gpu *gpu)
50{
51 if (gpu->gpu_cx)
52 regulator_disable(gpu->gpu_cx);
53 if (gpu->gpu_reg)
54 regulator_disable(gpu->gpu_reg);
55 return 0;
56}
57
58static int enable_clk(struct msm_gpu *gpu)
59{
60 if (gpu->core_clk && gpu->fast_rate)
61 dev_pm_opp_set_rate(&gpu->pdev->dev, gpu->fast_rate);
62
63 /* Set the RBBM timer rate to 19.2Mhz */
64 if (gpu->rbbmtimer_clk)
65 clk_set_rate(gpu->rbbmtimer_clk, 19200000);
66
67 return clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks);
68}
69
70static int disable_clk(struct msm_gpu *gpu)
71{
72 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks);
73
74 /*
75 * Set the clock to a deliberately low rate. On older targets the clock
76 * speed had to be non zero to avoid problems. On newer targets this
77 * will be rounded down to zero anyway so it all works out.
78 */
79 if (gpu->core_clk)
80 dev_pm_opp_set_rate(&gpu->pdev->dev, 27000000);
81
82 if (gpu->rbbmtimer_clk)
83 clk_set_rate(gpu->rbbmtimer_clk, 0);
84
85 return 0;
86}
87
88static int enable_axi(struct msm_gpu *gpu)
89{
90 return clk_prepare_enable(gpu->ebi1_clk);
91}
92
93static int disable_axi(struct msm_gpu *gpu)
94{
95 clk_disable_unprepare(gpu->ebi1_clk);
96 return 0;
97}
98
99int msm_gpu_pm_resume(struct msm_gpu *gpu)
100{
101 int ret;
102
103 DBG("%s", gpu->name);
104 trace_msm_gpu_resume(0);
105
106 ret = enable_pwrrail(gpu);
107 if (ret)
108 return ret;
109
110 ret = enable_clk(gpu);
111 if (ret)
112 return ret;
113
114 ret = enable_axi(gpu);
115 if (ret)
116 return ret;
117
118 msm_devfreq_resume(gpu);
119
120 gpu->needs_hw_init = true;
121
122 return 0;
123}
124
125int msm_gpu_pm_suspend(struct msm_gpu *gpu)
126{
127 int ret;
128
129 DBG("%s", gpu->name);
130 trace_msm_gpu_suspend(0);
131
132 msm_devfreq_suspend(gpu);
133
134 ret = disable_axi(gpu);
135 if (ret)
136 return ret;
137
138 ret = disable_clk(gpu);
139 if (ret)
140 return ret;
141
142 ret = disable_pwrrail(gpu);
143 if (ret)
144 return ret;
145
146 gpu->suspend_count++;
147
148 return 0;
149}
150
151void msm_gpu_show_fdinfo(struct msm_gpu *gpu, struct msm_file_private *ctx,
152 struct drm_printer *p)
153{
154 drm_printf(p, "drm-engine-gpu:\t%llu ns\n", ctx->elapsed_ns);
155 drm_printf(p, "drm-cycles-gpu:\t%llu\n", ctx->cycles);
156 drm_printf(p, "drm-maxfreq-gpu:\t%u Hz\n", gpu->fast_rate);
157}
158
159int msm_gpu_hw_init(struct msm_gpu *gpu)
160{
161 int ret;
162
163 WARN_ON(!mutex_is_locked(&gpu->lock));
164
165 if (!gpu->needs_hw_init)
166 return 0;
167
168 disable_irq(gpu->irq);
169 ret = gpu->funcs->hw_init(gpu);
170 if (!ret)
171 gpu->needs_hw_init = false;
172 enable_irq(gpu->irq);
173
174 return ret;
175}
176
177#ifdef CONFIG_DEV_COREDUMP
178static ssize_t msm_gpu_devcoredump_read(char *buffer, loff_t offset,
179 size_t count, void *data, size_t datalen)
180{
181 struct msm_gpu *gpu = data;
182 struct drm_print_iterator iter;
183 struct drm_printer p;
184 struct msm_gpu_state *state;
185
186 state = msm_gpu_crashstate_get(gpu);
187 if (!state)
188 return 0;
189
190 iter.data = buffer;
191 iter.offset = 0;
192 iter.start = offset;
193 iter.remain = count;
194
195 p = drm_coredump_printer(&iter);
196
197 drm_printf(&p, "---\n");
198 drm_printf(&p, "kernel: " UTS_RELEASE "\n");
199 drm_printf(&p, "module: " KBUILD_MODNAME "\n");
200 drm_printf(&p, "time: %lld.%09ld\n",
201 state->time.tv_sec, state->time.tv_nsec);
202 if (state->comm)
203 drm_printf(&p, "comm: %s\n", state->comm);
204 if (state->cmd)
205 drm_printf(&p, "cmdline: %s\n", state->cmd);
206
207 gpu->funcs->show(gpu, state, &p);
208
209 msm_gpu_crashstate_put(gpu);
210
211 return count - iter.remain;
212}
213
214static void msm_gpu_devcoredump_free(void *data)
215{
216 struct msm_gpu *gpu = data;
217
218 msm_gpu_crashstate_put(gpu);
219}
220
221static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state,
222 struct drm_gem_object *obj, u64 iova, bool full)
223{
224 struct msm_gpu_state_bo *state_bo = &state->bos[state->nr_bos];
225
226 /* Don't record write only objects */
227 state_bo->size = obj->size;
228 state_bo->iova = iova;
229
230 BUILD_BUG_ON(sizeof(state_bo->name) != sizeof(to_msm_bo(obj)->name));
231
232 memcpy(state_bo->name, to_msm_bo(obj)->name, sizeof(state_bo->name));
233
234 if (full) {
235 void *ptr;
236
237 state_bo->data = kvmalloc(obj->size, GFP_KERNEL);
238 if (!state_bo->data)
239 goto out;
240
241 msm_gem_lock(obj);
242 ptr = msm_gem_get_vaddr_active(obj);
243 msm_gem_unlock(obj);
244 if (IS_ERR(ptr)) {
245 kvfree(state_bo->data);
246 state_bo->data = NULL;
247 goto out;
248 }
249
250 memcpy(state_bo->data, ptr, obj->size);
251 msm_gem_put_vaddr(obj);
252 }
253out:
254 state->nr_bos++;
255}
256
257static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
258 struct msm_gem_submit *submit, char *comm, char *cmd)
259{
260 struct msm_gpu_state *state;
261
262 /* Check if the target supports capturing crash state */
263 if (!gpu->funcs->gpu_state_get)
264 return;
265
266 /* Only save one crash state at a time */
267 if (gpu->crashstate)
268 return;
269
270 state = gpu->funcs->gpu_state_get(gpu);
271 if (IS_ERR_OR_NULL(state))
272 return;
273
274 /* Fill in the additional crash state information */
275 state->comm = kstrdup(comm, GFP_KERNEL);
276 state->cmd = kstrdup(cmd, GFP_KERNEL);
277 state->fault_info = gpu->fault_info;
278
279 if (submit) {
280 int i;
281
282 state->bos = kcalloc(submit->nr_bos,
283 sizeof(struct msm_gpu_state_bo), GFP_KERNEL);
284
285 for (i = 0; state->bos && i < submit->nr_bos; i++) {
286 msm_gpu_crashstate_get_bo(state, submit->bos[i].obj,
287 submit->bos[i].iova,
288 should_dump(submit, i));
289 }
290 }
291
292 /* Set the active crash state to be dumped on failure */
293 gpu->crashstate = state;
294
295 dev_coredumpm(&gpu->pdev->dev, THIS_MODULE, gpu, 0, GFP_KERNEL,
296 msm_gpu_devcoredump_read, msm_gpu_devcoredump_free);
297}
298#else
299static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
300 struct msm_gem_submit *submit, char *comm, char *cmd)
301{
302}
303#endif
304
305/*
306 * Hangcheck detection for locked gpu:
307 */
308
309static struct msm_gem_submit *
310find_submit(struct msm_ringbuffer *ring, uint32_t fence)
311{
312 struct msm_gem_submit *submit;
313 unsigned long flags;
314
315 spin_lock_irqsave(&ring->submit_lock, flags);
316 list_for_each_entry(submit, &ring->submits, node) {
317 if (submit->seqno == fence) {
318 spin_unlock_irqrestore(&ring->submit_lock, flags);
319 return submit;
320 }
321 }
322 spin_unlock_irqrestore(&ring->submit_lock, flags);
323
324 return NULL;
325}
326
327static void retire_submits(struct msm_gpu *gpu);
328
329static void get_comm_cmdline(struct msm_gem_submit *submit, char **comm, char **cmd)
330{
331 struct msm_file_private *ctx = submit->queue->ctx;
332 struct task_struct *task;
333
334 WARN_ON(!mutex_is_locked(&submit->gpu->lock));
335
336 /* Note that kstrdup will return NULL if argument is NULL: */
337 *comm = kstrdup(ctx->comm, GFP_KERNEL);
338 *cmd = kstrdup(ctx->cmdline, GFP_KERNEL);
339
340 task = get_pid_task(submit->pid, PIDTYPE_PID);
341 if (!task)
342 return;
343
344 if (!*comm)
345 *comm = kstrdup(task->comm, GFP_KERNEL);
346
347 if (!*cmd)
348 *cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL);
349
350 put_task_struct(task);
351}
352
353static void recover_worker(struct kthread_work *work)
354{
355 struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work);
356 struct drm_device *dev = gpu->dev;
357 struct msm_drm_private *priv = dev->dev_private;
358 struct msm_gem_submit *submit;
359 struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
360 char *comm = NULL, *cmd = NULL;
361 int i;
362
363 mutex_lock(&gpu->lock);
364
365 DRM_DEV_ERROR(dev->dev, "%s: hangcheck recover!\n", gpu->name);
366
367 submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1);
368
369 /*
370 * If the submit retired while we were waiting for the worker to run,
371 * or waiting to acquire the gpu lock, then nothing more to do.
372 */
373 if (!submit)
374 goto out_unlock;
375
376 /* Increment the fault counts */
377 submit->queue->faults++;
378 if (submit->aspace)
379 submit->aspace->faults++;
380
381 get_comm_cmdline(submit, &comm, &cmd);
382
383 if (comm && cmd) {
384 DRM_DEV_ERROR(dev->dev, "%s: offending task: %s (%s)\n",
385 gpu->name, comm, cmd);
386
387 msm_rd_dump_submit(priv->hangrd, submit,
388 "offending task: %s (%s)", comm, cmd);
389 } else {
390 DRM_DEV_ERROR(dev->dev, "%s: offending task: unknown\n", gpu->name);
391
392 msm_rd_dump_submit(priv->hangrd, submit, NULL);
393 }
394
395 /* Record the crash state */
396 pm_runtime_get_sync(&gpu->pdev->dev);
397 msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
398
399 kfree(cmd);
400 kfree(comm);
401
402 /*
403 * Update all the rings with the latest and greatest fence.. this
404 * needs to happen after msm_rd_dump_submit() to ensure that the
405 * bo's referenced by the offending submit are still around.
406 */
407 for (i = 0; i < gpu->nr_rings; i++) {
408 struct msm_ringbuffer *ring = gpu->rb[i];
409
410 uint32_t fence = ring->memptrs->fence;
411
412 /*
413 * For the current (faulting?) ring/submit advance the fence by
414 * one more to clear the faulting submit
415 */
416 if (ring == cur_ring)
417 ring->memptrs->fence = ++fence;
418
419 msm_update_fence(ring->fctx, fence);
420 }
421
422 if (msm_gpu_active(gpu)) {
423 /* retire completed submits, plus the one that hung: */
424 retire_submits(gpu);
425
426 gpu->funcs->recover(gpu);
427
428 /*
429 * Replay all remaining submits starting with highest priority
430 * ring
431 */
432 for (i = 0; i < gpu->nr_rings; i++) {
433 struct msm_ringbuffer *ring = gpu->rb[i];
434 unsigned long flags;
435
436 spin_lock_irqsave(&ring->submit_lock, flags);
437 list_for_each_entry(submit, &ring->submits, node)
438 gpu->funcs->submit(gpu, submit);
439 spin_unlock_irqrestore(&ring->submit_lock, flags);
440 }
441 }
442
443 pm_runtime_put(&gpu->pdev->dev);
444
445out_unlock:
446 mutex_unlock(&gpu->lock);
447
448 msm_gpu_retire(gpu);
449}
450
451static void fault_worker(struct kthread_work *work)
452{
453 struct msm_gpu *gpu = container_of(work, struct msm_gpu, fault_work);
454 struct msm_gem_submit *submit;
455 struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
456 char *comm = NULL, *cmd = NULL;
457
458 mutex_lock(&gpu->lock);
459
460 submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1);
461 if (submit && submit->fault_dumped)
462 goto resume_smmu;
463
464 if (submit) {
465 get_comm_cmdline(submit, &comm, &cmd);
466
467 /*
468 * When we get GPU iova faults, we can get 1000s of them,
469 * but we really only want to log the first one.
470 */
471 submit->fault_dumped = true;
472 }
473
474 /* Record the crash state */
475 pm_runtime_get_sync(&gpu->pdev->dev);
476 msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
477 pm_runtime_put_sync(&gpu->pdev->dev);
478
479 kfree(cmd);
480 kfree(comm);
481
482resume_smmu:
483 memset(&gpu->fault_info, 0, sizeof(gpu->fault_info));
484 gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu);
485
486 mutex_unlock(&gpu->lock);
487}
488
489static void hangcheck_timer_reset(struct msm_gpu *gpu)
490{
491 struct msm_drm_private *priv = gpu->dev->dev_private;
492 mod_timer(&gpu->hangcheck_timer,
493 round_jiffies_up(jiffies + msecs_to_jiffies(priv->hangcheck_period)));
494}
495
496static bool made_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
497{
498 if (ring->hangcheck_progress_retries >= DRM_MSM_HANGCHECK_PROGRESS_RETRIES)
499 return false;
500
501 if (!gpu->funcs->progress)
502 return false;
503
504 if (!gpu->funcs->progress(gpu, ring))
505 return false;
506
507 ring->hangcheck_progress_retries++;
508 return true;
509}
510
511static void hangcheck_handler(struct timer_list *t)
512{
513 struct msm_gpu *gpu = from_timer(gpu, t, hangcheck_timer);
514 struct drm_device *dev = gpu->dev;
515 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
516 uint32_t fence = ring->memptrs->fence;
517
518 if (fence != ring->hangcheck_fence) {
519 /* some progress has been made.. ya! */
520 ring->hangcheck_fence = fence;
521 ring->hangcheck_progress_retries = 0;
522 } else if (fence_before(fence, ring->fctx->last_fence) &&
523 !made_progress(gpu, ring)) {
524 /* no progress and not done.. hung! */
525 ring->hangcheck_fence = fence;
526 ring->hangcheck_progress_retries = 0;
527 DRM_DEV_ERROR(dev->dev, "%s: hangcheck detected gpu lockup rb %d!\n",
528 gpu->name, ring->id);
529 DRM_DEV_ERROR(dev->dev, "%s: completed fence: %u\n",
530 gpu->name, fence);
531 DRM_DEV_ERROR(dev->dev, "%s: submitted fence: %u\n",
532 gpu->name, ring->fctx->last_fence);
533
534 kthread_queue_work(gpu->worker, &gpu->recover_work);
535 }
536
537 /* if still more pending work, reset the hangcheck timer: */
538 if (fence_after(ring->fctx->last_fence, ring->hangcheck_fence))
539 hangcheck_timer_reset(gpu);
540
541 /* workaround for missing irq: */
542 msm_gpu_retire(gpu);
543}
544
545/*
546 * Performance Counters:
547 */
548
549/* called under perf_lock */
550static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs)
551{
552 uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)];
553 int i, n = min(ncntrs, gpu->num_perfcntrs);
554
555 /* read current values: */
556 for (i = 0; i < gpu->num_perfcntrs; i++)
557 current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg);
558
559 /* update cntrs: */
560 for (i = 0; i < n; i++)
561 cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i];
562
563 /* save current values: */
564 for (i = 0; i < gpu->num_perfcntrs; i++)
565 gpu->last_cntrs[i] = current_cntrs[i];
566
567 return n;
568}
569
570static void update_sw_cntrs(struct msm_gpu *gpu)
571{
572 ktime_t time;
573 uint32_t elapsed;
574 unsigned long flags;
575
576 spin_lock_irqsave(&gpu->perf_lock, flags);
577 if (!gpu->perfcntr_active)
578 goto out;
579
580 time = ktime_get();
581 elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time));
582
583 gpu->totaltime += elapsed;
584 if (gpu->last_sample.active)
585 gpu->activetime += elapsed;
586
587 gpu->last_sample.active = msm_gpu_active(gpu);
588 gpu->last_sample.time = time;
589
590out:
591 spin_unlock_irqrestore(&gpu->perf_lock, flags);
592}
593
594void msm_gpu_perfcntr_start(struct msm_gpu *gpu)
595{
596 unsigned long flags;
597
598 pm_runtime_get_sync(&gpu->pdev->dev);
599
600 spin_lock_irqsave(&gpu->perf_lock, flags);
601 /* we could dynamically enable/disable perfcntr registers too.. */
602 gpu->last_sample.active = msm_gpu_active(gpu);
603 gpu->last_sample.time = ktime_get();
604 gpu->activetime = gpu->totaltime = 0;
605 gpu->perfcntr_active = true;
606 update_hw_cntrs(gpu, 0, NULL);
607 spin_unlock_irqrestore(&gpu->perf_lock, flags);
608}
609
610void msm_gpu_perfcntr_stop(struct msm_gpu *gpu)
611{
612 gpu->perfcntr_active = false;
613 pm_runtime_put_sync(&gpu->pdev->dev);
614}
615
616/* returns -errno or # of cntrs sampled */
617int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
618 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs)
619{
620 unsigned long flags;
621 int ret;
622
623 spin_lock_irqsave(&gpu->perf_lock, flags);
624
625 if (!gpu->perfcntr_active) {
626 ret = -EINVAL;
627 goto out;
628 }
629
630 *activetime = gpu->activetime;
631 *totaltime = gpu->totaltime;
632
633 gpu->activetime = gpu->totaltime = 0;
634
635 ret = update_hw_cntrs(gpu, ncntrs, cntrs);
636
637out:
638 spin_unlock_irqrestore(&gpu->perf_lock, flags);
639
640 return ret;
641}
642
643/*
644 * Cmdstream submission/retirement:
645 */
646
647static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
648 struct msm_gem_submit *submit)
649{
650 int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
651 volatile struct msm_gpu_submit_stats *stats;
652 u64 elapsed, clock = 0, cycles;
653 unsigned long flags;
654
655 stats = &ring->memptrs->stats[index];
656 /* Convert 19.2Mhz alwayson ticks to nanoseconds for elapsed time */
657 elapsed = (stats->alwayson_end - stats->alwayson_start) * 10000;
658 do_div(elapsed, 192);
659
660 cycles = stats->cpcycles_end - stats->cpcycles_start;
661
662 /* Calculate the clock frequency from the number of CP cycles */
663 if (elapsed) {
664 clock = cycles * 1000;
665 do_div(clock, elapsed);
666 }
667
668 submit->queue->ctx->elapsed_ns += elapsed;
669 submit->queue->ctx->cycles += cycles;
670
671 trace_msm_gpu_submit_retired(submit, elapsed, clock,
672 stats->alwayson_start, stats->alwayson_end);
673
674 msm_submit_retire(submit);
675
676 pm_runtime_mark_last_busy(&gpu->pdev->dev);
677
678 spin_lock_irqsave(&ring->submit_lock, flags);
679 list_del(&submit->node);
680 spin_unlock_irqrestore(&ring->submit_lock, flags);
681
682 /* Update devfreq on transition from active->idle: */
683 mutex_lock(&gpu->active_lock);
684 gpu->active_submits--;
685 WARN_ON(gpu->active_submits < 0);
686 if (!gpu->active_submits) {
687 msm_devfreq_idle(gpu);
688 pm_runtime_put_autosuspend(&gpu->pdev->dev);
689 }
690
691 mutex_unlock(&gpu->active_lock);
692
693 msm_gem_submit_put(submit);
694}
695
696static void retire_submits(struct msm_gpu *gpu)
697{
698 int i;
699
700 /* Retire the commits starting with highest priority */
701 for (i = 0; i < gpu->nr_rings; i++) {
702 struct msm_ringbuffer *ring = gpu->rb[i];
703
704 while (true) {
705 struct msm_gem_submit *submit = NULL;
706 unsigned long flags;
707
708 spin_lock_irqsave(&ring->submit_lock, flags);
709 submit = list_first_entry_or_null(&ring->submits,
710 struct msm_gem_submit, node);
711 spin_unlock_irqrestore(&ring->submit_lock, flags);
712
713 /*
714 * If no submit, we are done. If submit->fence hasn't
715 * been signalled, then later submits are not signalled
716 * either, so we are also done.
717 */
718 if (submit && dma_fence_is_signaled(submit->hw_fence)) {
719 retire_submit(gpu, ring, submit);
720 } else {
721 break;
722 }
723 }
724 }
725
726 wake_up_all(&gpu->retire_event);
727}
728
729static void retire_worker(struct kthread_work *work)
730{
731 struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work);
732
733 retire_submits(gpu);
734}
735
736/* call from irq handler to schedule work to retire bo's */
737void msm_gpu_retire(struct msm_gpu *gpu)
738{
739 int i;
740
741 for (i = 0; i < gpu->nr_rings; i++)
742 msm_update_fence(gpu->rb[i]->fctx, gpu->rb[i]->memptrs->fence);
743
744 kthread_queue_work(gpu->worker, &gpu->retire_work);
745 update_sw_cntrs(gpu);
746}
747
748/* add bo's to gpu's ring, and kick gpu: */
749void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
750{
751 struct msm_ringbuffer *ring = submit->ring;
752 unsigned long flags;
753
754 WARN_ON(!mutex_is_locked(&gpu->lock));
755
756 pm_runtime_get_sync(&gpu->pdev->dev);
757
758 msm_gpu_hw_init(gpu);
759
760 submit->seqno = submit->hw_fence->seqno;
761
762 update_sw_cntrs(gpu);
763
764 /*
765 * ring->submits holds a ref to the submit, to deal with the case
766 * that a submit completes before msm_ioctl_gem_submit() returns.
767 */
768 msm_gem_submit_get(submit);
769
770 spin_lock_irqsave(&ring->submit_lock, flags);
771 list_add_tail(&submit->node, &ring->submits);
772 spin_unlock_irqrestore(&ring->submit_lock, flags);
773
774 /* Update devfreq on transition from idle->active: */
775 mutex_lock(&gpu->active_lock);
776 if (!gpu->active_submits) {
777 pm_runtime_get(&gpu->pdev->dev);
778 msm_devfreq_active(gpu);
779 }
780 gpu->active_submits++;
781 mutex_unlock(&gpu->active_lock);
782
783 gpu->funcs->submit(gpu, submit);
784 gpu->cur_ctx_seqno = submit->queue->ctx->seqno;
785
786 pm_runtime_put(&gpu->pdev->dev);
787 hangcheck_timer_reset(gpu);
788}
789
790/*
791 * Init/Cleanup:
792 */
793
794static irqreturn_t irq_handler(int irq, void *data)
795{
796 struct msm_gpu *gpu = data;
797 return gpu->funcs->irq(gpu);
798}
799
800static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu)
801{
802 int ret = devm_clk_bulk_get_all(&pdev->dev, &gpu->grp_clks);
803
804 if (ret < 1) {
805 gpu->nr_clocks = 0;
806 return ret;
807 }
808
809 gpu->nr_clocks = ret;
810
811 gpu->core_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
812 gpu->nr_clocks, "core");
813
814 gpu->rbbmtimer_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
815 gpu->nr_clocks, "rbbmtimer");
816
817 return 0;
818}
819
820/* Return a new address space for a msm_drm_private instance */
821struct msm_gem_address_space *
822msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task)
823{
824 struct msm_gem_address_space *aspace = NULL;
825 if (!gpu)
826 return NULL;
827
828 /*
829 * If the target doesn't support private address spaces then return
830 * the global one
831 */
832 if (gpu->funcs->create_private_address_space) {
833 aspace = gpu->funcs->create_private_address_space(gpu);
834 if (!IS_ERR(aspace))
835 aspace->pid = get_pid(task_pid(task));
836 }
837
838 if (IS_ERR_OR_NULL(aspace))
839 aspace = msm_gem_address_space_get(gpu->aspace);
840
841 return aspace;
842}
843
844int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
845 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
846 const char *name, struct msm_gpu_config *config)
847{
848 struct msm_drm_private *priv = drm->dev_private;
849 int i, ret, nr_rings = config->nr_rings;
850 void *memptrs;
851 uint64_t memptrs_iova;
852
853 if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs)))
854 gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs);
855
856 gpu->dev = drm;
857 gpu->funcs = funcs;
858 gpu->name = name;
859
860 gpu->worker = kthread_create_worker(0, "gpu-worker");
861 if (IS_ERR(gpu->worker)) {
862 ret = PTR_ERR(gpu->worker);
863 gpu->worker = NULL;
864 goto fail;
865 }
866
867 sched_set_fifo_low(gpu->worker->task);
868
869 mutex_init(&gpu->active_lock);
870 mutex_init(&gpu->lock);
871 init_waitqueue_head(&gpu->retire_event);
872 kthread_init_work(&gpu->retire_work, retire_worker);
873 kthread_init_work(&gpu->recover_work, recover_worker);
874 kthread_init_work(&gpu->fault_work, fault_worker);
875
876 priv->hangcheck_period = DRM_MSM_HANGCHECK_DEFAULT_PERIOD;
877
878 /*
879 * If progress detection is supported, halve the hangcheck timer
880 * duration, as it takes two iterations of the hangcheck handler
881 * to detect a hang.
882 */
883 if (funcs->progress)
884 priv->hangcheck_period /= 2;
885
886 timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0);
887
888 spin_lock_init(&gpu->perf_lock);
889
890
891 /* Map registers: */
892 gpu->mmio = msm_ioremap(pdev, config->ioname);
893 if (IS_ERR(gpu->mmio)) {
894 ret = PTR_ERR(gpu->mmio);
895 goto fail;
896 }
897
898 /* Get Interrupt: */
899 gpu->irq = platform_get_irq(pdev, 0);
900 if (gpu->irq < 0) {
901 ret = gpu->irq;
902 goto fail;
903 }
904
905 ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler,
906 IRQF_TRIGGER_HIGH, "gpu-irq", gpu);
907 if (ret) {
908 DRM_DEV_ERROR(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret);
909 goto fail;
910 }
911
912 ret = get_clocks(pdev, gpu);
913 if (ret)
914 goto fail;
915
916 gpu->ebi1_clk = msm_clk_get(pdev, "bus");
917 DBG("ebi1_clk: %p", gpu->ebi1_clk);
918 if (IS_ERR(gpu->ebi1_clk))
919 gpu->ebi1_clk = NULL;
920
921 /* Acquire regulators: */
922 gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd");
923 DBG("gpu_reg: %p", gpu->gpu_reg);
924 if (IS_ERR(gpu->gpu_reg))
925 gpu->gpu_reg = NULL;
926
927 gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx");
928 DBG("gpu_cx: %p", gpu->gpu_cx);
929 if (IS_ERR(gpu->gpu_cx))
930 gpu->gpu_cx = NULL;
931
932 gpu->pdev = pdev;
933 platform_set_drvdata(pdev, &gpu->adreno_smmu);
934
935 msm_devfreq_init(gpu);
936
937
938 gpu->aspace = gpu->funcs->create_address_space(gpu, pdev);
939
940 if (gpu->aspace == NULL)
941 DRM_DEV_INFO(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name);
942 else if (IS_ERR(gpu->aspace)) {
943 ret = PTR_ERR(gpu->aspace);
944 goto fail;
945 }
946
947 memptrs = msm_gem_kernel_new(drm,
948 sizeof(struct msm_rbmemptrs) * nr_rings,
949 check_apriv(gpu, MSM_BO_WC), gpu->aspace, &gpu->memptrs_bo,
950 &memptrs_iova);
951
952 if (IS_ERR(memptrs)) {
953 ret = PTR_ERR(memptrs);
954 DRM_DEV_ERROR(drm->dev, "could not allocate memptrs: %d\n", ret);
955 goto fail;
956 }
957
958 msm_gem_object_set_name(gpu->memptrs_bo, "memptrs");
959
960 if (nr_rings > ARRAY_SIZE(gpu->rb)) {
961 DRM_DEV_INFO_ONCE(drm->dev, "Only creating %zu ringbuffers\n",
962 ARRAY_SIZE(gpu->rb));
963 nr_rings = ARRAY_SIZE(gpu->rb);
964 }
965
966 /* Create ringbuffer(s): */
967 for (i = 0; i < nr_rings; i++) {
968 gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova);
969
970 if (IS_ERR(gpu->rb[i])) {
971 ret = PTR_ERR(gpu->rb[i]);
972 DRM_DEV_ERROR(drm->dev,
973 "could not create ringbuffer %d: %d\n", i, ret);
974 goto fail;
975 }
976
977 memptrs += sizeof(struct msm_rbmemptrs);
978 memptrs_iova += sizeof(struct msm_rbmemptrs);
979 }
980
981 gpu->nr_rings = nr_rings;
982
983 refcount_set(&gpu->sysprof_active, 1);
984
985 return 0;
986
987fail:
988 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
989 msm_ringbuffer_destroy(gpu->rb[i]);
990 gpu->rb[i] = NULL;
991 }
992
993 msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace);
994
995 platform_set_drvdata(pdev, NULL);
996 return ret;
997}
998
999void msm_gpu_cleanup(struct msm_gpu *gpu)
1000{
1001 int i;
1002
1003 DBG("%s", gpu->name);
1004
1005 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
1006 msm_ringbuffer_destroy(gpu->rb[i]);
1007 gpu->rb[i] = NULL;
1008 }
1009
1010 msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace);
1011
1012 if (!IS_ERR_OR_NULL(gpu->aspace)) {
1013 gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu);
1014 msm_gem_address_space_put(gpu->aspace);
1015 }
1016
1017 if (gpu->worker) {
1018 kthread_destroy_worker(gpu->worker);
1019 }
1020
1021 msm_devfreq_cleanup(gpu);
1022
1023 platform_set_drvdata(gpu->pdev, NULL);
1024}