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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 */
6
7#ifndef __HDMI_CONNECTOR_H__
8#define __HDMI_CONNECTOR_H__
9
10#include <linux/i2c.h>
11#include <linux/clk.h>
12#include <linux/platform_device.h>
13#include <linux/regulator/consumer.h>
14#include <linux/gpio/consumer.h>
15#include <linux/hdmi.h>
16
17#include "msm_drv.h"
18#include "hdmi.xml.h"
19
20#define HDMI_MAX_NUM_GPIO 6
21
22struct hdmi_phy;
23struct hdmi_platform_config;
24
25struct hdmi_gpio_data {
26 struct gpio_desc *gpiod;
27 bool output;
28 int value;
29};
30
31struct hdmi_audio {
32 bool enabled;
33 struct hdmi_audio_infoframe infoframe;
34 int rate;
35};
36
37struct hdmi_hdcp_ctrl;
38
39struct hdmi {
40 struct drm_device *dev;
41 struct platform_device *pdev;
42 struct platform_device *audio_pdev;
43
44 const struct hdmi_platform_config *config;
45
46 /* audio state: */
47 struct hdmi_audio audio;
48
49 /* video state: */
50 bool power_on;
51 unsigned long int pixclock;
52
53 void __iomem *mmio;
54 void __iomem *qfprom_mmio;
55 phys_addr_t mmio_phy_addr;
56
57 struct regulator **hpd_regs;
58 struct regulator **pwr_regs;
59 struct clk **hpd_clks;
60 struct clk **pwr_clks;
61
62 struct hdmi_phy *phy;
63 struct device *phy_dev;
64
65 struct i2c_adapter *i2c;
66 struct drm_connector *connector;
67 struct drm_bridge *bridge;
68
69 /* the encoder we are hooked to (outside of hdmi block) */
70 struct drm_encoder *encoder;
71
72 bool hdmi_mode; /* are we in hdmi mode? */
73
74 int irq;
75 struct workqueue_struct *workq;
76
77 struct hdmi_hdcp_ctrl *hdcp_ctrl;
78
79 /*
80 * spinlock to protect registers shared by different execution
81 * REG_HDMI_CTRL
82 * REG_HDMI_DDC_ARBITRATION
83 * REG_HDMI_HDCP_INT_CTRL
84 * REG_HDMI_HPD_CTRL
85 */
86 spinlock_t reg_lock;
87};
88
89/* platform config data (ie. from DT, or pdata) */
90struct hdmi_platform_config {
91 const char *mmio_name;
92 const char *qfprom_mmio_name;
93
94 /* regulators that need to be on for hpd: */
95 const char **hpd_reg_names;
96 int hpd_reg_cnt;
97
98 /* regulators that need to be on for screen pwr: */
99 const char **pwr_reg_names;
100 int pwr_reg_cnt;
101
102 /* clks that need to be on for hpd: */
103 const char **hpd_clk_names;
104 const long unsigned *hpd_freq;
105 int hpd_clk_cnt;
106
107 /* clks that need to be on for screen pwr (ie pixel clk): */
108 const char **pwr_clk_names;
109 int pwr_clk_cnt;
110
111 /* gpio's: */
112 struct hdmi_gpio_data gpios[HDMI_MAX_NUM_GPIO];
113};
114
115void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on);
116
117static inline void hdmi_write(struct hdmi *hdmi, u32 reg, u32 data)
118{
119 msm_writel(data, hdmi->mmio + reg);
120}
121
122static inline u32 hdmi_read(struct hdmi *hdmi, u32 reg)
123{
124 return msm_readl(hdmi->mmio + reg);
125}
126
127static inline u32 hdmi_qfprom_read(struct hdmi *hdmi, u32 reg)
128{
129 return msm_readl(hdmi->qfprom_mmio + reg);
130}
131
132/*
133 * hdmi phy:
134 */
135
136enum hdmi_phy_type {
137 MSM_HDMI_PHY_8x60,
138 MSM_HDMI_PHY_8960,
139 MSM_HDMI_PHY_8x74,
140 MSM_HDMI_PHY_8996,
141 MSM_HDMI_PHY_MAX,
142};
143
144struct hdmi_phy_cfg {
145 enum hdmi_phy_type type;
146 void (*powerup)(struct hdmi_phy *phy, unsigned long int pixclock);
147 void (*powerdown)(struct hdmi_phy *phy);
148 const char * const *reg_names;
149 int num_regs;
150 const char * const *clk_names;
151 int num_clks;
152};
153
154extern const struct hdmi_phy_cfg msm_hdmi_phy_8x60_cfg;
155extern const struct hdmi_phy_cfg msm_hdmi_phy_8960_cfg;
156extern const struct hdmi_phy_cfg msm_hdmi_phy_8x74_cfg;
157extern const struct hdmi_phy_cfg msm_hdmi_phy_8996_cfg;
158
159struct hdmi_phy {
160 struct platform_device *pdev;
161 void __iomem *mmio;
162 struct hdmi_phy_cfg *cfg;
163 const struct hdmi_phy_funcs *funcs;
164 struct regulator **regs;
165 struct clk **clks;
166};
167
168static inline void hdmi_phy_write(struct hdmi_phy *phy, u32 reg, u32 data)
169{
170 msm_writel(data, phy->mmio + reg);
171}
172
173static inline u32 hdmi_phy_read(struct hdmi_phy *phy, u32 reg)
174{
175 return msm_readl(phy->mmio + reg);
176}
177
178int msm_hdmi_phy_resource_enable(struct hdmi_phy *phy);
179void msm_hdmi_phy_resource_disable(struct hdmi_phy *phy);
180void msm_hdmi_phy_powerup(struct hdmi_phy *phy, unsigned long int pixclock);
181void msm_hdmi_phy_powerdown(struct hdmi_phy *phy);
182void __init msm_hdmi_phy_driver_register(void);
183void __exit msm_hdmi_phy_driver_unregister(void);
184
185#ifdef CONFIG_COMMON_CLK
186int msm_hdmi_pll_8960_init(struct platform_device *pdev);
187int msm_hdmi_pll_8996_init(struct platform_device *pdev);
188#else
189static inline int msm_hdmi_pll_8960_init(struct platform_device *pdev)
190{
191 return -ENODEV;
192}
193
194static inline int msm_hdmi_pll_8996_init(struct platform_device *pdev)
195{
196 return -ENODEV;
197}
198#endif
199
200/*
201 * audio:
202 */
203/* Supported HDMI Audio channels and rates */
204#define MSM_HDMI_AUDIO_CHANNEL_2 0
205#define MSM_HDMI_AUDIO_CHANNEL_4 1
206#define MSM_HDMI_AUDIO_CHANNEL_6 2
207#define MSM_HDMI_AUDIO_CHANNEL_8 3
208
209#define HDMI_SAMPLE_RATE_32KHZ 0
210#define HDMI_SAMPLE_RATE_44_1KHZ 1
211#define HDMI_SAMPLE_RATE_48KHZ 2
212#define HDMI_SAMPLE_RATE_88_2KHZ 3
213#define HDMI_SAMPLE_RATE_96KHZ 4
214#define HDMI_SAMPLE_RATE_176_4KHZ 5
215#define HDMI_SAMPLE_RATE_192KHZ 6
216
217int msm_hdmi_audio_update(struct hdmi *hdmi);
218int msm_hdmi_audio_info_setup(struct hdmi *hdmi, bool enabled,
219 uint32_t num_of_channels, uint32_t channel_allocation,
220 uint32_t level_shift, bool down_mix);
221void msm_hdmi_audio_set_sample_rate(struct hdmi *hdmi, int rate);
222
223
224/*
225 * hdmi bridge:
226 */
227
228struct drm_bridge *msm_hdmi_bridge_init(struct hdmi *hdmi);
229void msm_hdmi_bridge_destroy(struct drm_bridge *bridge);
230
231/*
232 * hdmi connector:
233 */
234
235void msm_hdmi_connector_irq(struct drm_connector *connector);
236struct drm_connector *msm_hdmi_connector_init(struct hdmi *hdmi);
237int msm_hdmi_hpd_enable(struct drm_connector *connector);
238
239/*
240 * i2c adapter for ddc:
241 */
242
243void msm_hdmi_i2c_irq(struct i2c_adapter *i2c);
244void msm_hdmi_i2c_destroy(struct i2c_adapter *i2c);
245struct i2c_adapter *msm_hdmi_i2c_init(struct hdmi *hdmi);
246
247/*
248 * hdcp
249 */
250#ifdef CONFIG_DRM_MSM_HDMI_HDCP
251struct hdmi_hdcp_ctrl *msm_hdmi_hdcp_init(struct hdmi *hdmi);
252void msm_hdmi_hdcp_destroy(struct hdmi *hdmi);
253void msm_hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl);
254void msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl);
255void msm_hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl);
256#else
257static inline struct hdmi_hdcp_ctrl *msm_hdmi_hdcp_init(struct hdmi *hdmi)
258{
259 return ERR_PTR(-ENXIO);
260}
261static inline void msm_hdmi_hdcp_destroy(struct hdmi *hdmi) {}
262static inline void msm_hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl) {}
263static inline void msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl) {}
264static inline void msm_hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl) {}
265#endif
266
267#endif /* __HDMI_CONNECTOR_H__ */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 */
6
7#ifndef __HDMI_CONNECTOR_H__
8#define __HDMI_CONNECTOR_H__
9
10#include <linux/i2c.h>
11#include <linux/clk.h>
12#include <linux/platform_device.h>
13#include <linux/regulator/consumer.h>
14#include <linux/gpio/consumer.h>
15#include <linux/hdmi.h>
16
17#include <drm/drm_bridge.h>
18
19#include "msm_drv.h"
20#include "hdmi.xml.h"
21
22struct hdmi_phy;
23struct hdmi_platform_config;
24
25struct hdmi_audio {
26 bool enabled;
27 struct hdmi_audio_infoframe infoframe;
28 int rate;
29};
30
31struct hdmi_hdcp_ctrl;
32
33struct hdmi {
34 struct drm_device *dev;
35 struct platform_device *pdev;
36 struct platform_device *audio_pdev;
37
38 const struct hdmi_platform_config *config;
39
40 /* audio state: */
41 struct hdmi_audio audio;
42
43 /* video state: */
44 bool power_on;
45 unsigned long int pixclock;
46
47 void __iomem *mmio;
48 void __iomem *qfprom_mmio;
49 phys_addr_t mmio_phy_addr;
50
51 struct regulator_bulk_data *hpd_regs;
52 struct regulator_bulk_data *pwr_regs;
53 struct clk **hpd_clks;
54 struct clk **pwr_clks;
55
56 struct gpio_desc *hpd_gpiod;
57
58 struct hdmi_phy *phy;
59 struct device *phy_dev;
60
61 struct i2c_adapter *i2c;
62 struct drm_connector *connector;
63 struct drm_bridge *bridge;
64
65 struct drm_bridge *next_bridge;
66
67 /* the encoder we are hooked to (outside of hdmi block) */
68 struct drm_encoder *encoder;
69
70 bool hdmi_mode; /* are we in hdmi mode? */
71
72 int irq;
73 struct workqueue_struct *workq;
74
75 struct hdmi_hdcp_ctrl *hdcp_ctrl;
76
77 /*
78 * spinlock to protect registers shared by different execution
79 * REG_HDMI_CTRL
80 * REG_HDMI_DDC_ARBITRATION
81 * REG_HDMI_HDCP_INT_CTRL
82 * REG_HDMI_HPD_CTRL
83 */
84 spinlock_t reg_lock;
85};
86
87/* platform config data (ie. from DT, or pdata) */
88struct hdmi_platform_config {
89 /* regulators that need to be on for hpd: */
90 const char **hpd_reg_names;
91 int hpd_reg_cnt;
92
93 /* regulators that need to be on for screen pwr: */
94 const char **pwr_reg_names;
95 int pwr_reg_cnt;
96
97 /* clks that need to be on for hpd: */
98 const char **hpd_clk_names;
99 const long unsigned *hpd_freq;
100 int hpd_clk_cnt;
101
102 /* clks that need to be on for screen pwr (ie pixel clk): */
103 const char **pwr_clk_names;
104 int pwr_clk_cnt;
105};
106
107struct hdmi_bridge {
108 struct drm_bridge base;
109 struct hdmi *hdmi;
110 struct work_struct hpd_work;
111};
112#define to_hdmi_bridge(x) container_of(x, struct hdmi_bridge, base)
113
114void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on);
115
116static inline void hdmi_write(struct hdmi *hdmi, u32 reg, u32 data)
117{
118 msm_writel(data, hdmi->mmio + reg);
119}
120
121static inline u32 hdmi_read(struct hdmi *hdmi, u32 reg)
122{
123 return msm_readl(hdmi->mmio + reg);
124}
125
126static inline u32 hdmi_qfprom_read(struct hdmi *hdmi, u32 reg)
127{
128 return msm_readl(hdmi->qfprom_mmio + reg);
129}
130
131/*
132 * hdmi phy:
133 */
134
135enum hdmi_phy_type {
136 MSM_HDMI_PHY_8x60,
137 MSM_HDMI_PHY_8960,
138 MSM_HDMI_PHY_8x74,
139 MSM_HDMI_PHY_8996,
140 MSM_HDMI_PHY_MAX,
141};
142
143struct hdmi_phy_cfg {
144 enum hdmi_phy_type type;
145 void (*powerup)(struct hdmi_phy *phy, unsigned long int pixclock);
146 void (*powerdown)(struct hdmi_phy *phy);
147 const char * const *reg_names;
148 int num_regs;
149 const char * const *clk_names;
150 int num_clks;
151};
152
153extern const struct hdmi_phy_cfg msm_hdmi_phy_8x60_cfg;
154extern const struct hdmi_phy_cfg msm_hdmi_phy_8960_cfg;
155extern const struct hdmi_phy_cfg msm_hdmi_phy_8x74_cfg;
156extern const struct hdmi_phy_cfg msm_hdmi_phy_8996_cfg;
157
158struct hdmi_phy {
159 struct platform_device *pdev;
160 void __iomem *mmio;
161 struct hdmi_phy_cfg *cfg;
162 const struct hdmi_phy_funcs *funcs;
163 struct regulator_bulk_data *regs;
164 struct clk **clks;
165};
166
167static inline void hdmi_phy_write(struct hdmi_phy *phy, u32 reg, u32 data)
168{
169 msm_writel(data, phy->mmio + reg);
170}
171
172static inline u32 hdmi_phy_read(struct hdmi_phy *phy, u32 reg)
173{
174 return msm_readl(phy->mmio + reg);
175}
176
177int msm_hdmi_phy_resource_enable(struct hdmi_phy *phy);
178void msm_hdmi_phy_resource_disable(struct hdmi_phy *phy);
179void msm_hdmi_phy_powerup(struct hdmi_phy *phy, unsigned long int pixclock);
180void msm_hdmi_phy_powerdown(struct hdmi_phy *phy);
181void __init msm_hdmi_phy_driver_register(void);
182void __exit msm_hdmi_phy_driver_unregister(void);
183
184#ifdef CONFIG_COMMON_CLK
185int msm_hdmi_pll_8960_init(struct platform_device *pdev);
186int msm_hdmi_pll_8996_init(struct platform_device *pdev);
187#else
188static inline int msm_hdmi_pll_8960_init(struct platform_device *pdev)
189{
190 return -ENODEV;
191}
192
193static inline int msm_hdmi_pll_8996_init(struct platform_device *pdev)
194{
195 return -ENODEV;
196}
197#endif
198
199/*
200 * audio:
201 */
202/* Supported HDMI Audio channels and rates */
203#define MSM_HDMI_AUDIO_CHANNEL_2 0
204#define MSM_HDMI_AUDIO_CHANNEL_4 1
205#define MSM_HDMI_AUDIO_CHANNEL_6 2
206#define MSM_HDMI_AUDIO_CHANNEL_8 3
207
208#define HDMI_SAMPLE_RATE_32KHZ 0
209#define HDMI_SAMPLE_RATE_44_1KHZ 1
210#define HDMI_SAMPLE_RATE_48KHZ 2
211#define HDMI_SAMPLE_RATE_88_2KHZ 3
212#define HDMI_SAMPLE_RATE_96KHZ 4
213#define HDMI_SAMPLE_RATE_176_4KHZ 5
214#define HDMI_SAMPLE_RATE_192KHZ 6
215
216int msm_hdmi_audio_update(struct hdmi *hdmi);
217int msm_hdmi_audio_info_setup(struct hdmi *hdmi, bool enabled,
218 uint32_t num_of_channels, uint32_t channel_allocation,
219 uint32_t level_shift, bool down_mix);
220void msm_hdmi_audio_set_sample_rate(struct hdmi *hdmi, int rate);
221
222
223/*
224 * hdmi bridge:
225 */
226
227int msm_hdmi_bridge_init(struct hdmi *hdmi);
228
229void msm_hdmi_hpd_irq(struct drm_bridge *bridge);
230enum drm_connector_status msm_hdmi_bridge_detect(
231 struct drm_bridge *bridge);
232int msm_hdmi_hpd_enable(struct drm_bridge *bridge);
233void msm_hdmi_hpd_disable(struct hdmi *hdmi);
234
235/*
236 * i2c adapter for ddc:
237 */
238
239void msm_hdmi_i2c_irq(struct i2c_adapter *i2c);
240void msm_hdmi_i2c_destroy(struct i2c_adapter *i2c);
241struct i2c_adapter *msm_hdmi_i2c_init(struct hdmi *hdmi);
242
243/*
244 * hdcp
245 */
246#ifdef CONFIG_DRM_MSM_HDMI_HDCP
247struct hdmi_hdcp_ctrl *msm_hdmi_hdcp_init(struct hdmi *hdmi);
248void msm_hdmi_hdcp_destroy(struct hdmi *hdmi);
249void msm_hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl);
250void msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl);
251void msm_hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl);
252#else
253static inline struct hdmi_hdcp_ctrl *msm_hdmi_hdcp_init(struct hdmi *hdmi)
254{
255 return ERR_PTR(-ENXIO);
256}
257static inline void msm_hdmi_hdcp_destroy(struct hdmi *hdmi) {}
258static inline void msm_hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl) {}
259static inline void msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl) {}
260static inline void msm_hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl) {}
261#endif
262
263#endif /* __HDMI_CONNECTOR_H__ */