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1/*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#include <drm/drm_print.h>
26
27#include "gem/i915_gem_context.h"
28
29#include "i915_drv.h"
30
31#include "gt/intel_gt.h"
32
33#include "intel_engine.h"
34#include "intel_engine_pm.h"
35#include "intel_engine_pool.h"
36#include "intel_engine_user.h"
37#include "intel_context.h"
38#include "intel_lrc.h"
39#include "intel_reset.h"
40
41/* Haswell does have the CXT_SIZE register however it does not appear to be
42 * valid. Now, docs explain in dwords what is in the context object. The full
43 * size is 70720 bytes, however, the power context and execlist context will
44 * never be saved (power context is stored elsewhere, and execlists don't work
45 * on HSW) - so the final size, including the extra state required for the
46 * Resource Streamer, is 66944 bytes, which rounds to 17 pages.
47 */
48#define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
49
50#define DEFAULT_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
51#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
52#define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
53#define GEN10_LR_CONTEXT_RENDER_SIZE (18 * PAGE_SIZE)
54#define GEN11_LR_CONTEXT_RENDER_SIZE (14 * PAGE_SIZE)
55
56#define GEN8_LR_CONTEXT_OTHER_SIZE ( 2 * PAGE_SIZE)
57
58#define MAX_MMIO_BASES 3
59struct engine_info {
60 unsigned int hw_id;
61 u8 class;
62 u8 instance;
63 /* mmio bases table *must* be sorted in reverse gen order */
64 struct engine_mmio_base {
65 u32 gen : 8;
66 u32 base : 24;
67 } mmio_bases[MAX_MMIO_BASES];
68};
69
70static const struct engine_info intel_engines[] = {
71 [RCS0] = {
72 .hw_id = RCS0_HW,
73 .class = RENDER_CLASS,
74 .instance = 0,
75 .mmio_bases = {
76 { .gen = 1, .base = RENDER_RING_BASE }
77 },
78 },
79 [BCS0] = {
80 .hw_id = BCS0_HW,
81 .class = COPY_ENGINE_CLASS,
82 .instance = 0,
83 .mmio_bases = {
84 { .gen = 6, .base = BLT_RING_BASE }
85 },
86 },
87 [VCS0] = {
88 .hw_id = VCS0_HW,
89 .class = VIDEO_DECODE_CLASS,
90 .instance = 0,
91 .mmio_bases = {
92 { .gen = 11, .base = GEN11_BSD_RING_BASE },
93 { .gen = 6, .base = GEN6_BSD_RING_BASE },
94 { .gen = 4, .base = BSD_RING_BASE }
95 },
96 },
97 [VCS1] = {
98 .hw_id = VCS1_HW,
99 .class = VIDEO_DECODE_CLASS,
100 .instance = 1,
101 .mmio_bases = {
102 { .gen = 11, .base = GEN11_BSD2_RING_BASE },
103 { .gen = 8, .base = GEN8_BSD2_RING_BASE }
104 },
105 },
106 [VCS2] = {
107 .hw_id = VCS2_HW,
108 .class = VIDEO_DECODE_CLASS,
109 .instance = 2,
110 .mmio_bases = {
111 { .gen = 11, .base = GEN11_BSD3_RING_BASE }
112 },
113 },
114 [VCS3] = {
115 .hw_id = VCS3_HW,
116 .class = VIDEO_DECODE_CLASS,
117 .instance = 3,
118 .mmio_bases = {
119 { .gen = 11, .base = GEN11_BSD4_RING_BASE }
120 },
121 },
122 [VECS0] = {
123 .hw_id = VECS0_HW,
124 .class = VIDEO_ENHANCEMENT_CLASS,
125 .instance = 0,
126 .mmio_bases = {
127 { .gen = 11, .base = GEN11_VEBOX_RING_BASE },
128 { .gen = 7, .base = VEBOX_RING_BASE }
129 },
130 },
131 [VECS1] = {
132 .hw_id = VECS1_HW,
133 .class = VIDEO_ENHANCEMENT_CLASS,
134 .instance = 1,
135 .mmio_bases = {
136 { .gen = 11, .base = GEN11_VEBOX2_RING_BASE }
137 },
138 },
139};
140
141/**
142 * intel_engine_context_size() - return the size of the context for an engine
143 * @dev_priv: i915 device private
144 * @class: engine class
145 *
146 * Each engine class may require a different amount of space for a context
147 * image.
148 *
149 * Return: size (in bytes) of an engine class specific context image
150 *
151 * Note: this size includes the HWSP, which is part of the context image
152 * in LRC mode, but does not include the "shared data page" used with
153 * GuC submission. The caller should account for this if using the GuC.
154 */
155u32 intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
156{
157 u32 cxt_size;
158
159 BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE);
160
161 switch (class) {
162 case RENDER_CLASS:
163 switch (INTEL_GEN(dev_priv)) {
164 default:
165 MISSING_CASE(INTEL_GEN(dev_priv));
166 return DEFAULT_LR_CONTEXT_RENDER_SIZE;
167 case 12:
168 case 11:
169 return GEN11_LR_CONTEXT_RENDER_SIZE;
170 case 10:
171 return GEN10_LR_CONTEXT_RENDER_SIZE;
172 case 9:
173 return GEN9_LR_CONTEXT_RENDER_SIZE;
174 case 8:
175 return GEN8_LR_CONTEXT_RENDER_SIZE;
176 case 7:
177 if (IS_HASWELL(dev_priv))
178 return HSW_CXT_TOTAL_SIZE;
179
180 cxt_size = I915_READ(GEN7_CXT_SIZE);
181 return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64,
182 PAGE_SIZE);
183 case 6:
184 cxt_size = I915_READ(CXT_SIZE);
185 return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
186 PAGE_SIZE);
187 case 5:
188 case 4:
189 /*
190 * There is a discrepancy here between the size reported
191 * by the register and the size of the context layout
192 * in the docs. Both are described as authorative!
193 *
194 * The discrepancy is on the order of a few cachelines,
195 * but the total is under one page (4k), which is our
196 * minimum allocation anyway so it should all come
197 * out in the wash.
198 */
199 cxt_size = I915_READ(CXT_SIZE) + 1;
200 DRM_DEBUG_DRIVER("gen%d CXT_SIZE = %d bytes [0x%08x]\n",
201 INTEL_GEN(dev_priv),
202 cxt_size * 64,
203 cxt_size - 1);
204 return round_up(cxt_size * 64, PAGE_SIZE);
205 case 3:
206 case 2:
207 /* For the special day when i810 gets merged. */
208 case 1:
209 return 0;
210 }
211 break;
212 default:
213 MISSING_CASE(class);
214 /* fall through */
215 case VIDEO_DECODE_CLASS:
216 case VIDEO_ENHANCEMENT_CLASS:
217 case COPY_ENGINE_CLASS:
218 if (INTEL_GEN(dev_priv) < 8)
219 return 0;
220 return GEN8_LR_CONTEXT_OTHER_SIZE;
221 }
222}
223
224static u32 __engine_mmio_base(struct drm_i915_private *i915,
225 const struct engine_mmio_base *bases)
226{
227 int i;
228
229 for (i = 0; i < MAX_MMIO_BASES; i++)
230 if (INTEL_GEN(i915) >= bases[i].gen)
231 break;
232
233 GEM_BUG_ON(i == MAX_MMIO_BASES);
234 GEM_BUG_ON(!bases[i].base);
235
236 return bases[i].base;
237}
238
239static void __sprint_engine_name(struct intel_engine_cs *engine)
240{
241 /*
242 * Before we know what the uABI name for this engine will be,
243 * we still would like to keep track of this engine in the debug logs.
244 * We throw in a ' here as a reminder that this isn't its final name.
245 */
246 GEM_WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s'%u",
247 intel_engine_class_repr(engine->class),
248 engine->instance) >= sizeof(engine->name));
249}
250
251void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)
252{
253 /*
254 * Though they added more rings on g4x/ilk, they did not add
255 * per-engine HWSTAM until gen6.
256 */
257 if (INTEL_GEN(engine->i915) < 6 && engine->class != RENDER_CLASS)
258 return;
259
260 if (INTEL_GEN(engine->i915) >= 3)
261 ENGINE_WRITE(engine, RING_HWSTAM, mask);
262 else
263 ENGINE_WRITE16(engine, RING_HWSTAM, mask);
264}
265
266static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine)
267{
268 /* Mask off all writes into the unknown HWSP */
269 intel_engine_set_hwsp_writemask(engine, ~0u);
270}
271
272static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
273{
274 const struct engine_info *info = &intel_engines[id];
275 struct intel_engine_cs *engine;
276
277 BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));
278 BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));
279
280 if (GEM_DEBUG_WARN_ON(info->class > MAX_ENGINE_CLASS))
281 return -EINVAL;
282
283 if (GEM_DEBUG_WARN_ON(info->instance > MAX_ENGINE_INSTANCE))
284 return -EINVAL;
285
286 if (GEM_DEBUG_WARN_ON(gt->engine_class[info->class][info->instance]))
287 return -EINVAL;
288
289 engine = kzalloc(sizeof(*engine), GFP_KERNEL);
290 if (!engine)
291 return -ENOMEM;
292
293 BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES);
294
295 engine->id = id;
296 engine->mask = BIT(id);
297 engine->i915 = gt->i915;
298 engine->gt = gt;
299 engine->uncore = gt->uncore;
300 engine->hw_id = engine->guc_id = info->hw_id;
301 engine->mmio_base = __engine_mmio_base(gt->i915, info->mmio_bases);
302
303 engine->class = info->class;
304 engine->instance = info->instance;
305 __sprint_engine_name(engine);
306
307 /*
308 * To be overridden by the backend on setup. However to facilitate
309 * cleanup on error during setup, we always provide the destroy vfunc.
310 */
311 engine->destroy = (typeof(engine->destroy))kfree;
312
313 engine->context_size = intel_engine_context_size(gt->i915,
314 engine->class);
315 if (WARN_ON(engine->context_size > BIT(20)))
316 engine->context_size = 0;
317 if (engine->context_size)
318 DRIVER_CAPS(gt->i915)->has_logical_contexts = true;
319
320 /* Nothing to do here, execute in order of dependencies */
321 engine->schedule = NULL;
322
323 seqlock_init(&engine->stats.lock);
324
325 ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);
326
327 /* Scrub mmio state on takeover */
328 intel_engine_sanitize_mmio(engine);
329
330 gt->engine_class[info->class][info->instance] = engine;
331
332 intel_engine_add_user(engine);
333 gt->i915->engine[id] = engine;
334
335 return 0;
336}
337
338static void __setup_engine_capabilities(struct intel_engine_cs *engine)
339{
340 struct drm_i915_private *i915 = engine->i915;
341
342 if (engine->class == VIDEO_DECODE_CLASS) {
343 /*
344 * HEVC support is present on first engine instance
345 * before Gen11 and on all instances afterwards.
346 */
347 if (INTEL_GEN(i915) >= 11 ||
348 (INTEL_GEN(i915) >= 9 && engine->instance == 0))
349 engine->uabi_capabilities |=
350 I915_VIDEO_CLASS_CAPABILITY_HEVC;
351
352 /*
353 * SFC block is present only on even logical engine
354 * instances.
355 */
356 if ((INTEL_GEN(i915) >= 11 &&
357 RUNTIME_INFO(i915)->vdbox_sfc_access & engine->mask) ||
358 (INTEL_GEN(i915) >= 9 && engine->instance == 0))
359 engine->uabi_capabilities |=
360 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
361 } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
362 if (INTEL_GEN(i915) >= 9)
363 engine->uabi_capabilities |=
364 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
365 }
366}
367
368static void intel_setup_engine_capabilities(struct drm_i915_private *i915)
369{
370 struct intel_engine_cs *engine;
371 enum intel_engine_id id;
372
373 for_each_engine(engine, i915, id)
374 __setup_engine_capabilities(engine);
375}
376
377/**
378 * intel_engines_cleanup() - free the resources allocated for Command Streamers
379 * @i915: the i915 devic
380 */
381void intel_engines_cleanup(struct drm_i915_private *i915)
382{
383 struct intel_engine_cs *engine;
384 enum intel_engine_id id;
385
386 for_each_engine(engine, i915, id) {
387 engine->destroy(engine);
388 i915->engine[id] = NULL;
389 }
390}
391
392/**
393 * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers
394 * @i915: the i915 device
395 *
396 * Return: non-zero if the initialization failed.
397 */
398int intel_engines_init_mmio(struct drm_i915_private *i915)
399{
400 struct intel_device_info *device_info = mkwrite_device_info(i915);
401 const unsigned int engine_mask = INTEL_INFO(i915)->engine_mask;
402 unsigned int mask = 0;
403 unsigned int i;
404 int err;
405
406 WARN_ON(engine_mask == 0);
407 WARN_ON(engine_mask &
408 GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
409
410 if (i915_inject_probe_failure(i915))
411 return -ENODEV;
412
413 for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
414 if (!HAS_ENGINE(i915, i))
415 continue;
416
417 err = intel_engine_setup(&i915->gt, i);
418 if (err)
419 goto cleanup;
420
421 mask |= BIT(i);
422 }
423
424 /*
425 * Catch failures to update intel_engines table when the new engines
426 * are added to the driver by a warning and disabling the forgotten
427 * engines.
428 */
429 if (WARN_ON(mask != engine_mask))
430 device_info->engine_mask = mask;
431
432 RUNTIME_INFO(i915)->num_engines = hweight32(mask);
433
434 intel_gt_check_and_clear_faults(&i915->gt);
435
436 intel_setup_engine_capabilities(i915);
437
438 return 0;
439
440cleanup:
441 intel_engines_cleanup(i915);
442 return err;
443}
444
445/**
446 * intel_engines_init() - init the Engine Command Streamers
447 * @i915: i915 device private
448 *
449 * Return: non-zero if the initialization failed.
450 */
451int intel_engines_init(struct drm_i915_private *i915)
452{
453 int (*init)(struct intel_engine_cs *engine);
454 struct intel_engine_cs *engine;
455 enum intel_engine_id id;
456 int err;
457
458 if (HAS_EXECLISTS(i915))
459 init = intel_execlists_submission_init;
460 else
461 init = intel_ring_submission_init;
462
463 for_each_engine(engine, i915, id) {
464 err = init(engine);
465 if (err)
466 goto cleanup;
467 }
468
469 return 0;
470
471cleanup:
472 intel_engines_cleanup(i915);
473 return err;
474}
475
476void intel_engine_init_execlists(struct intel_engine_cs *engine)
477{
478 struct intel_engine_execlists * const execlists = &engine->execlists;
479
480 execlists->port_mask = 1;
481 GEM_BUG_ON(!is_power_of_2(execlists_num_ports(execlists)));
482 GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS);
483
484 memset(execlists->pending, 0, sizeof(execlists->pending));
485 execlists->active =
486 memset(execlists->inflight, 0, sizeof(execlists->inflight));
487
488 execlists->queue_priority_hint = INT_MIN;
489 execlists->queue = RB_ROOT_CACHED;
490}
491
492static void cleanup_status_page(struct intel_engine_cs *engine)
493{
494 struct i915_vma *vma;
495
496 /* Prevent writes into HWSP after returning the page to the system */
497 intel_engine_set_hwsp_writemask(engine, ~0u);
498
499 vma = fetch_and_zero(&engine->status_page.vma);
500 if (!vma)
501 return;
502
503 if (!HWS_NEEDS_PHYSICAL(engine->i915))
504 i915_vma_unpin(vma);
505
506 i915_gem_object_unpin_map(vma->obj);
507 i915_gem_object_put(vma->obj);
508}
509
510static int pin_ggtt_status_page(struct intel_engine_cs *engine,
511 struct i915_vma *vma)
512{
513 unsigned int flags;
514
515 flags = PIN_GLOBAL;
516 if (!HAS_LLC(engine->i915))
517 /*
518 * On g33, we cannot place HWS above 256MiB, so
519 * restrict its pinning to the low mappable arena.
520 * Though this restriction is not documented for
521 * gen4, gen5, or byt, they also behave similarly
522 * and hang if the HWS is placed at the top of the
523 * GTT. To generalise, it appears that all !llc
524 * platforms have issues with us placing the HWS
525 * above the mappable region (even though we never
526 * actually map it).
527 */
528 flags |= PIN_MAPPABLE;
529 else
530 flags |= PIN_HIGH;
531
532 return i915_vma_pin(vma, 0, 0, flags);
533}
534
535static int init_status_page(struct intel_engine_cs *engine)
536{
537 struct drm_i915_gem_object *obj;
538 struct i915_vma *vma;
539 void *vaddr;
540 int ret;
541
542 /*
543 * Though the HWS register does support 36bit addresses, historically
544 * we have had hangs and corruption reported due to wild writes if
545 * the HWS is placed above 4G. We only allow objects to be allocated
546 * in GFP_DMA32 for i965, and no earlier physical address users had
547 * access to more than 4G.
548 */
549 obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
550 if (IS_ERR(obj)) {
551 DRM_ERROR("Failed to allocate status page\n");
552 return PTR_ERR(obj);
553 }
554
555 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
556
557 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
558 if (IS_ERR(vma)) {
559 ret = PTR_ERR(vma);
560 goto err;
561 }
562
563 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
564 if (IS_ERR(vaddr)) {
565 ret = PTR_ERR(vaddr);
566 goto err;
567 }
568
569 engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE);
570 engine->status_page.vma = vma;
571
572 if (!HWS_NEEDS_PHYSICAL(engine->i915)) {
573 ret = pin_ggtt_status_page(engine, vma);
574 if (ret)
575 goto err_unpin;
576 }
577
578 return 0;
579
580err_unpin:
581 i915_gem_object_unpin_map(obj);
582err:
583 i915_gem_object_put(obj);
584 return ret;
585}
586
587static int intel_engine_setup_common(struct intel_engine_cs *engine)
588{
589 int err;
590
591 init_llist_head(&engine->barrier_tasks);
592
593 err = init_status_page(engine);
594 if (err)
595 return err;
596
597 intel_engine_init_active(engine, ENGINE_PHYSICAL);
598 intel_engine_init_breadcrumbs(engine);
599 intel_engine_init_execlists(engine);
600 intel_engine_init_hangcheck(engine);
601 intel_engine_init_cmd_parser(engine);
602 intel_engine_init__pm(engine);
603
604 intel_engine_pool_init(&engine->pool);
605
606 /* Use the whole device by default */
607 engine->sseu =
608 intel_sseu_from_device_info(&RUNTIME_INFO(engine->i915)->sseu);
609
610 intel_engine_init_workarounds(engine);
611 intel_engine_init_whitelist(engine);
612 intel_engine_init_ctx_wa(engine);
613
614 return 0;
615}
616
617/**
618 * intel_engines_setup- setup engine state not requiring hw access
619 * @i915: Device to setup.
620 *
621 * Initializes engine structure members shared between legacy and execlists
622 * submission modes which do not require hardware access.
623 *
624 * Typically done early in the submission mode specific engine setup stage.
625 */
626int intel_engines_setup(struct drm_i915_private *i915)
627{
628 int (*setup)(struct intel_engine_cs *engine);
629 struct intel_engine_cs *engine;
630 enum intel_engine_id id;
631 int err;
632
633 if (HAS_EXECLISTS(i915))
634 setup = intel_execlists_submission_setup;
635 else
636 setup = intel_ring_submission_setup;
637
638 for_each_engine(engine, i915, id) {
639 err = intel_engine_setup_common(engine);
640 if (err)
641 goto cleanup;
642
643 err = setup(engine);
644 if (err)
645 goto cleanup;
646
647 /* We expect the backend to take control over its state */
648 GEM_BUG_ON(engine->destroy == (typeof(engine->destroy))kfree);
649
650 GEM_BUG_ON(!engine->cops);
651 }
652
653 return 0;
654
655cleanup:
656 intel_engines_cleanup(i915);
657 return err;
658}
659
660struct measure_breadcrumb {
661 struct i915_request rq;
662 struct intel_timeline timeline;
663 struct intel_ring ring;
664 u32 cs[1024];
665};
666
667static int measure_breadcrumb_dw(struct intel_engine_cs *engine)
668{
669 struct measure_breadcrumb *frame;
670 int dw = -ENOMEM;
671
672 GEM_BUG_ON(!engine->gt->scratch);
673
674 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
675 if (!frame)
676 return -ENOMEM;
677
678 if (intel_timeline_init(&frame->timeline,
679 engine->gt,
680 engine->status_page.vma))
681 goto out_frame;
682
683 frame->ring.vaddr = frame->cs;
684 frame->ring.size = sizeof(frame->cs);
685 frame->ring.effective_size = frame->ring.size;
686 intel_ring_update_space(&frame->ring);
687
688 frame->rq.i915 = engine->i915;
689 frame->rq.engine = engine;
690 frame->rq.ring = &frame->ring;
691 frame->rq.timeline = &frame->timeline;
692
693 dw = intel_timeline_pin(&frame->timeline);
694 if (dw < 0)
695 goto out_timeline;
696
697 dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs;
698 GEM_BUG_ON(dw & 1); /* RING_TAIL must be qword aligned */
699
700 intel_timeline_unpin(&frame->timeline);
701
702out_timeline:
703 intel_timeline_fini(&frame->timeline);
704out_frame:
705 kfree(frame);
706 return dw;
707}
708
709void
710intel_engine_init_active(struct intel_engine_cs *engine, unsigned int subclass)
711{
712 INIT_LIST_HEAD(&engine->active.requests);
713
714 spin_lock_init(&engine->active.lock);
715 lockdep_set_subclass(&engine->active.lock, subclass);
716
717 /*
718 * Due to an interesting quirk in lockdep's internal debug tracking,
719 * after setting a subclass we must ensure the lock is used. Otherwise,
720 * nr_unused_locks is incremented once too often.
721 */
722#ifdef CONFIG_DEBUG_LOCK_ALLOC
723 local_irq_disable();
724 lock_map_acquire(&engine->active.lock.dep_map);
725 lock_map_release(&engine->active.lock.dep_map);
726 local_irq_enable();
727#endif
728}
729
730static struct intel_context *
731create_kernel_context(struct intel_engine_cs *engine)
732{
733 struct intel_context *ce;
734 int err;
735
736 ce = intel_context_create(engine->i915->kernel_context, engine);
737 if (IS_ERR(ce))
738 return ce;
739
740 ce->ring = __intel_context_ring_size(SZ_4K);
741
742 err = intel_context_pin(ce);
743 if (err) {
744 intel_context_put(ce);
745 return ERR_PTR(err);
746 }
747
748 return ce;
749}
750
751/**
752 * intel_engines_init_common - initialize cengine state which might require hw access
753 * @engine: Engine to initialize.
754 *
755 * Initializes @engine@ structure members shared between legacy and execlists
756 * submission modes which do require hardware access.
757 *
758 * Typcally done at later stages of submission mode specific engine setup.
759 *
760 * Returns zero on success or an error code on failure.
761 */
762int intel_engine_init_common(struct intel_engine_cs *engine)
763{
764 struct intel_context *ce;
765 int ret;
766
767 engine->set_default_submission(engine);
768
769 /*
770 * We may need to do things with the shrinker which
771 * require us to immediately switch back to the default
772 * context. This can cause a problem as pinning the
773 * default context also requires GTT space which may not
774 * be available. To avoid this we always pin the default
775 * context.
776 */
777 ce = create_kernel_context(engine);
778 if (IS_ERR(ce))
779 return PTR_ERR(ce);
780
781 engine->kernel_context = ce;
782
783 ret = measure_breadcrumb_dw(engine);
784 if (ret < 0)
785 goto err_unpin;
786
787 engine->emit_fini_breadcrumb_dw = ret;
788
789 return 0;
790
791err_unpin:
792 intel_context_unpin(ce);
793 intel_context_put(ce);
794 return ret;
795}
796
797/**
798 * intel_engines_cleanup_common - cleans up the engine state created by
799 * the common initiailizers.
800 * @engine: Engine to cleanup.
801 *
802 * This cleans up everything created by the common helpers.
803 */
804void intel_engine_cleanup_common(struct intel_engine_cs *engine)
805{
806 GEM_BUG_ON(!list_empty(&engine->active.requests));
807
808 cleanup_status_page(engine);
809
810 intel_engine_pool_fini(&engine->pool);
811 intel_engine_fini_breadcrumbs(engine);
812 intel_engine_cleanup_cmd_parser(engine);
813
814 if (engine->default_state)
815 i915_gem_object_put(engine->default_state);
816
817 intel_context_unpin(engine->kernel_context);
818 intel_context_put(engine->kernel_context);
819 GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
820
821 intel_wa_list_free(&engine->ctx_wa_list);
822 intel_wa_list_free(&engine->wa_list);
823 intel_wa_list_free(&engine->whitelist);
824}
825
826u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
827{
828 struct drm_i915_private *i915 = engine->i915;
829
830 u64 acthd;
831
832 if (INTEL_GEN(i915) >= 8)
833 acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW);
834 else if (INTEL_GEN(i915) >= 4)
835 acthd = ENGINE_READ(engine, RING_ACTHD);
836 else
837 acthd = ENGINE_READ(engine, ACTHD);
838
839 return acthd;
840}
841
842u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)
843{
844 u64 bbaddr;
845
846 if (INTEL_GEN(engine->i915) >= 8)
847 bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW);
848 else
849 bbaddr = ENGINE_READ(engine, RING_BBADDR);
850
851 return bbaddr;
852}
853
854int intel_engine_stop_cs(struct intel_engine_cs *engine)
855{
856 struct intel_uncore *uncore = engine->uncore;
857 const u32 base = engine->mmio_base;
858 const i915_reg_t mode = RING_MI_MODE(base);
859 int err;
860
861 if (INTEL_GEN(engine->i915) < 3)
862 return -ENODEV;
863
864 GEM_TRACE("%s\n", engine->name);
865
866 intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
867
868 err = 0;
869 if (__intel_wait_for_register_fw(uncore,
870 mode, MODE_IDLE, MODE_IDLE,
871 1000, 0,
872 NULL)) {
873 GEM_TRACE("%s: timed out on STOP_RING -> IDLE\n", engine->name);
874 err = -ETIMEDOUT;
875 }
876
877 /* A final mmio read to let GPU writes be hopefully flushed to memory */
878 intel_uncore_posting_read_fw(uncore, mode);
879
880 return err;
881}
882
883void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine)
884{
885 GEM_TRACE("%s\n", engine->name);
886
887 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
888}
889
890const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
891{
892 switch (type) {
893 case I915_CACHE_NONE: return " uncached";
894 case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
895 case I915_CACHE_L3_LLC: return " L3+LLC";
896 case I915_CACHE_WT: return " WT";
897 default: return "";
898 }
899}
900
901static u32
902read_subslice_reg(struct intel_engine_cs *engine, int slice, int subslice,
903 i915_reg_t reg)
904{
905 struct drm_i915_private *i915 = engine->i915;
906 struct intel_uncore *uncore = engine->uncore;
907 u32 mcr_mask, mcr_ss, mcr, old_mcr, val;
908 enum forcewake_domains fw_domains;
909
910 if (INTEL_GEN(i915) >= 11) {
911 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
912 mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
913 } else {
914 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
915 mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
916 }
917
918 fw_domains = intel_uncore_forcewake_for_reg(uncore, reg,
919 FW_REG_READ);
920 fw_domains |= intel_uncore_forcewake_for_reg(uncore,
921 GEN8_MCR_SELECTOR,
922 FW_REG_READ | FW_REG_WRITE);
923
924 spin_lock_irq(&uncore->lock);
925 intel_uncore_forcewake_get__locked(uncore, fw_domains);
926
927 old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
928
929 mcr &= ~mcr_mask;
930 mcr |= mcr_ss;
931 intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
932
933 val = intel_uncore_read_fw(uncore, reg);
934
935 mcr &= ~mcr_mask;
936 mcr |= old_mcr & mcr_mask;
937
938 intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
939
940 intel_uncore_forcewake_put__locked(uncore, fw_domains);
941 spin_unlock_irq(&uncore->lock);
942
943 return val;
944}
945
946/* NB: please notice the memset */
947void intel_engine_get_instdone(struct intel_engine_cs *engine,
948 struct intel_instdone *instdone)
949{
950 struct drm_i915_private *i915 = engine->i915;
951 struct intel_uncore *uncore = engine->uncore;
952 u32 mmio_base = engine->mmio_base;
953 int slice;
954 int subslice;
955
956 memset(instdone, 0, sizeof(*instdone));
957
958 switch (INTEL_GEN(i915)) {
959 default:
960 instdone->instdone =
961 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
962
963 if (engine->id != RCS0)
964 break;
965
966 instdone->slice_common =
967 intel_uncore_read(uncore, GEN7_SC_INSTDONE);
968 for_each_instdone_slice_subslice(i915, slice, subslice) {
969 instdone->sampler[slice][subslice] =
970 read_subslice_reg(engine, slice, subslice,
971 GEN7_SAMPLER_INSTDONE);
972 instdone->row[slice][subslice] =
973 read_subslice_reg(engine, slice, subslice,
974 GEN7_ROW_INSTDONE);
975 }
976 break;
977 case 7:
978 instdone->instdone =
979 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
980
981 if (engine->id != RCS0)
982 break;
983
984 instdone->slice_common =
985 intel_uncore_read(uncore, GEN7_SC_INSTDONE);
986 instdone->sampler[0][0] =
987 intel_uncore_read(uncore, GEN7_SAMPLER_INSTDONE);
988 instdone->row[0][0] =
989 intel_uncore_read(uncore, GEN7_ROW_INSTDONE);
990
991 break;
992 case 6:
993 case 5:
994 case 4:
995 instdone->instdone =
996 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
997 if (engine->id == RCS0)
998 /* HACK: Using the wrong struct member */
999 instdone->slice_common =
1000 intel_uncore_read(uncore, GEN4_INSTDONE1);
1001 break;
1002 case 3:
1003 case 2:
1004 instdone->instdone = intel_uncore_read(uncore, GEN2_INSTDONE);
1005 break;
1006 }
1007}
1008
1009static bool ring_is_idle(struct intel_engine_cs *engine)
1010{
1011 bool idle = true;
1012
1013 if (I915_SELFTEST_ONLY(!engine->mmio_base))
1014 return true;
1015
1016 if (!intel_engine_pm_get_if_awake(engine))
1017 return true;
1018
1019 /* First check that no commands are left in the ring */
1020 if ((ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) !=
1021 (ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR))
1022 idle = false;
1023
1024 /* No bit for gen2, so assume the CS parser is idle */
1025 if (INTEL_GEN(engine->i915) > 2 &&
1026 !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE))
1027 idle = false;
1028
1029 intel_engine_pm_put(engine);
1030
1031 return idle;
1032}
1033
1034/**
1035 * intel_engine_is_idle() - Report if the engine has finished process all work
1036 * @engine: the intel_engine_cs
1037 *
1038 * Return true if there are no requests pending, nothing left to be submitted
1039 * to hardware, and that the engine is idle.
1040 */
1041bool intel_engine_is_idle(struct intel_engine_cs *engine)
1042{
1043 /* More white lies, if wedged, hw state is inconsistent */
1044 if (intel_gt_is_wedged(engine->gt))
1045 return true;
1046
1047 if (!intel_engine_pm_is_awake(engine))
1048 return true;
1049
1050 /* Waiting to drain ELSP? */
1051 if (execlists_active(&engine->execlists)) {
1052 struct tasklet_struct *t = &engine->execlists.tasklet;
1053
1054 synchronize_hardirq(engine->i915->drm.pdev->irq);
1055
1056 local_bh_disable();
1057 if (tasklet_trylock(t)) {
1058 /* Must wait for any GPU reset in progress. */
1059 if (__tasklet_is_enabled(t))
1060 t->func(t->data);
1061 tasklet_unlock(t);
1062 }
1063 local_bh_enable();
1064
1065 /* Otherwise flush the tasklet if it was on another cpu */
1066 tasklet_unlock_wait(t);
1067
1068 if (execlists_active(&engine->execlists))
1069 return false;
1070 }
1071
1072 /* ELSP is empty, but there are ready requests? E.g. after reset */
1073 if (!RB_EMPTY_ROOT(&engine->execlists.queue.rb_root))
1074 return false;
1075
1076 /* Ring stopped? */
1077 return ring_is_idle(engine);
1078}
1079
1080bool intel_engines_are_idle(struct intel_gt *gt)
1081{
1082 struct intel_engine_cs *engine;
1083 enum intel_engine_id id;
1084
1085 /*
1086 * If the driver is wedged, HW state may be very inconsistent and
1087 * report that it is still busy, even though we have stopped using it.
1088 */
1089 if (intel_gt_is_wedged(gt))
1090 return true;
1091
1092 /* Already parked (and passed an idleness test); must still be idle */
1093 if (!READ_ONCE(gt->awake))
1094 return true;
1095
1096 for_each_engine(engine, gt->i915, id) {
1097 if (!intel_engine_is_idle(engine))
1098 return false;
1099 }
1100
1101 return true;
1102}
1103
1104void intel_engines_reset_default_submission(struct intel_gt *gt)
1105{
1106 struct intel_engine_cs *engine;
1107 enum intel_engine_id id;
1108
1109 for_each_engine(engine, gt->i915, id)
1110 engine->set_default_submission(engine);
1111}
1112
1113bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
1114{
1115 switch (INTEL_GEN(engine->i915)) {
1116 case 2:
1117 return false; /* uses physical not virtual addresses */
1118 case 3:
1119 /* maybe only uses physical not virtual addresses */
1120 return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915));
1121 case 6:
1122 return engine->class != VIDEO_DECODE_CLASS; /* b0rked */
1123 default:
1124 return true;
1125 }
1126}
1127
1128static int print_sched_attr(struct drm_i915_private *i915,
1129 const struct i915_sched_attr *attr,
1130 char *buf, int x, int len)
1131{
1132 if (attr->priority == I915_PRIORITY_INVALID)
1133 return x;
1134
1135 x += snprintf(buf + x, len - x,
1136 " prio=%d", attr->priority);
1137
1138 return x;
1139}
1140
1141static void print_request(struct drm_printer *m,
1142 struct i915_request *rq,
1143 const char *prefix)
1144{
1145 const char *name = rq->fence.ops->get_timeline_name(&rq->fence);
1146 char buf[80] = "";
1147 int x = 0;
1148
1149 x = print_sched_attr(rq->i915, &rq->sched.attr, buf, x, sizeof(buf));
1150
1151 drm_printf(m, "%s %llx:%llx%s%s %s @ %dms: %s\n",
1152 prefix,
1153 rq->fence.context, rq->fence.seqno,
1154 i915_request_completed(rq) ? "!" :
1155 i915_request_started(rq) ? "*" :
1156 "",
1157 test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
1158 &rq->fence.flags) ? "+" :
1159 test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
1160 &rq->fence.flags) ? "-" :
1161 "",
1162 buf,
1163 jiffies_to_msecs(jiffies - rq->emitted_jiffies),
1164 name);
1165}
1166
1167static void hexdump(struct drm_printer *m, const void *buf, size_t len)
1168{
1169 const size_t rowsize = 8 * sizeof(u32);
1170 const void *prev = NULL;
1171 bool skip = false;
1172 size_t pos;
1173
1174 for (pos = 0; pos < len; pos += rowsize) {
1175 char line[128];
1176
1177 if (prev && !memcmp(prev, buf + pos, rowsize)) {
1178 if (!skip) {
1179 drm_printf(m, "*\n");
1180 skip = true;
1181 }
1182 continue;
1183 }
1184
1185 WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos,
1186 rowsize, sizeof(u32),
1187 line, sizeof(line),
1188 false) >= sizeof(line));
1189 drm_printf(m, "[%04zx] %s\n", pos, line);
1190
1191 prev = buf + pos;
1192 skip = false;
1193 }
1194}
1195
1196static void intel_engine_print_registers(struct intel_engine_cs *engine,
1197 struct drm_printer *m)
1198{
1199 struct drm_i915_private *dev_priv = engine->i915;
1200 struct intel_engine_execlists * const execlists = &engine->execlists;
1201 u64 addr;
1202
1203 if (engine->id == RENDER_CLASS && IS_GEN_RANGE(dev_priv, 4, 7))
1204 drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
1205 drm_printf(m, "\tRING_START: 0x%08x\n",
1206 ENGINE_READ(engine, RING_START));
1207 drm_printf(m, "\tRING_HEAD: 0x%08x\n",
1208 ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR);
1209 drm_printf(m, "\tRING_TAIL: 0x%08x\n",
1210 ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR);
1211 drm_printf(m, "\tRING_CTL: 0x%08x%s\n",
1212 ENGINE_READ(engine, RING_CTL),
1213 ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
1214 if (INTEL_GEN(engine->i915) > 2) {
1215 drm_printf(m, "\tRING_MODE: 0x%08x%s\n",
1216 ENGINE_READ(engine, RING_MI_MODE),
1217 ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : "");
1218 }
1219
1220 if (INTEL_GEN(dev_priv) >= 6) {
1221 drm_printf(m, "\tRING_IMR: %08x\n",
1222 ENGINE_READ(engine, RING_IMR));
1223 }
1224
1225 addr = intel_engine_get_active_head(engine);
1226 drm_printf(m, "\tACTHD: 0x%08x_%08x\n",
1227 upper_32_bits(addr), lower_32_bits(addr));
1228 addr = intel_engine_get_last_batch_head(engine);
1229 drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
1230 upper_32_bits(addr), lower_32_bits(addr));
1231 if (INTEL_GEN(dev_priv) >= 8)
1232 addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW);
1233 else if (INTEL_GEN(dev_priv) >= 4)
1234 addr = ENGINE_READ(engine, RING_DMA_FADD);
1235 else
1236 addr = ENGINE_READ(engine, DMA_FADD_I8XX);
1237 drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
1238 upper_32_bits(addr), lower_32_bits(addr));
1239 if (INTEL_GEN(dev_priv) >= 4) {
1240 drm_printf(m, "\tIPEIR: 0x%08x\n",
1241 ENGINE_READ(engine, RING_IPEIR));
1242 drm_printf(m, "\tIPEHR: 0x%08x\n",
1243 ENGINE_READ(engine, RING_IPEHR));
1244 } else {
1245 drm_printf(m, "\tIPEIR: 0x%08x\n", ENGINE_READ(engine, IPEIR));
1246 drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR));
1247 }
1248
1249 if (HAS_EXECLISTS(dev_priv)) {
1250 struct i915_request * const *port, *rq;
1251 const u32 *hws =
1252 &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
1253 const u8 num_entries = execlists->csb_size;
1254 unsigned int idx;
1255 u8 read, write;
1256
1257 drm_printf(m, "\tExeclist status: 0x%08x %08x, entries %u\n",
1258 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO),
1259 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI),
1260 num_entries);
1261
1262 read = execlists->csb_head;
1263 write = READ_ONCE(*execlists->csb_write);
1264
1265 drm_printf(m, "\tExeclist CSB read %d, write %d, tasklet queued? %s (%s)\n",
1266 read, write,
1267 yesno(test_bit(TASKLET_STATE_SCHED,
1268 &engine->execlists.tasklet.state)),
1269 enableddisabled(!atomic_read(&engine->execlists.tasklet.count)));
1270 if (read >= num_entries)
1271 read = 0;
1272 if (write >= num_entries)
1273 write = 0;
1274 if (read > write)
1275 write += num_entries;
1276 while (read < write) {
1277 idx = ++read % num_entries;
1278 drm_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
1279 idx, hws[idx * 2], hws[idx * 2 + 1]);
1280 }
1281
1282 execlists_active_lock_bh(execlists);
1283 for (port = execlists->active; (rq = *port); port++) {
1284 char hdr[80];
1285 int len;
1286
1287 len = snprintf(hdr, sizeof(hdr),
1288 "\t\tActive[%d: ",
1289 (int)(port - execlists->active));
1290 if (!i915_request_signaled(rq))
1291 len += snprintf(hdr + len, sizeof(hdr) - len,
1292 "ring:{start:%08x, hwsp:%08x, seqno:%08x}, ",
1293 i915_ggtt_offset(rq->ring->vma),
1294 rq->timeline->hwsp_offset,
1295 hwsp_seqno(rq));
1296 snprintf(hdr + len, sizeof(hdr) - len, "rq: ");
1297 print_request(m, rq, hdr);
1298 }
1299 for (port = execlists->pending; (rq = *port); port++) {
1300 char hdr[80];
1301
1302 snprintf(hdr, sizeof(hdr),
1303 "\t\tPending[%d] ring:{start:%08x, hwsp:%08x, seqno:%08x}, rq: ",
1304 (int)(port - execlists->pending),
1305 i915_ggtt_offset(rq->ring->vma),
1306 rq->timeline->hwsp_offset,
1307 hwsp_seqno(rq));
1308 print_request(m, rq, hdr);
1309 }
1310 execlists_active_unlock_bh(execlists);
1311 } else if (INTEL_GEN(dev_priv) > 6) {
1312 drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
1313 ENGINE_READ(engine, RING_PP_DIR_BASE));
1314 drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
1315 ENGINE_READ(engine, RING_PP_DIR_BASE_READ));
1316 drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
1317 ENGINE_READ(engine, RING_PP_DIR_DCLV));
1318 }
1319}
1320
1321static void print_request_ring(struct drm_printer *m, struct i915_request *rq)
1322{
1323 void *ring;
1324 int size;
1325
1326 drm_printf(m,
1327 "[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]:\n",
1328 rq->head, rq->postfix, rq->tail,
1329 rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
1330 rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
1331
1332 size = rq->tail - rq->head;
1333 if (rq->tail < rq->head)
1334 size += rq->ring->size;
1335
1336 ring = kmalloc(size, GFP_ATOMIC);
1337 if (ring) {
1338 const void *vaddr = rq->ring->vaddr;
1339 unsigned int head = rq->head;
1340 unsigned int len = 0;
1341
1342 if (rq->tail < head) {
1343 len = rq->ring->size - head;
1344 memcpy(ring, vaddr + head, len);
1345 head = 0;
1346 }
1347 memcpy(ring + len, vaddr + head, size - len);
1348
1349 hexdump(m, ring, size);
1350 kfree(ring);
1351 }
1352}
1353
1354void intel_engine_dump(struct intel_engine_cs *engine,
1355 struct drm_printer *m,
1356 const char *header, ...)
1357{
1358 struct i915_gpu_error * const error = &engine->i915->gpu_error;
1359 struct i915_request *rq;
1360 intel_wakeref_t wakeref;
1361 unsigned long flags;
1362
1363 if (header) {
1364 va_list ap;
1365
1366 va_start(ap, header);
1367 drm_vprintf(m, header, &ap);
1368 va_end(ap);
1369 }
1370
1371 if (intel_gt_is_wedged(engine->gt))
1372 drm_printf(m, "*** WEDGED ***\n");
1373
1374 drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count));
1375 drm_printf(m, "\tHangcheck: %d ms ago\n",
1376 jiffies_to_msecs(jiffies - engine->hangcheck.action_timestamp));
1377 drm_printf(m, "\tReset count: %d (global %d)\n",
1378 i915_reset_engine_count(error, engine),
1379 i915_reset_count(error));
1380
1381 drm_printf(m, "\tRequests:\n");
1382
1383 spin_lock_irqsave(&engine->active.lock, flags);
1384 rq = intel_engine_find_active_request(engine);
1385 if (rq) {
1386 print_request(m, rq, "\t\tactive ");
1387
1388 drm_printf(m, "\t\tring->start: 0x%08x\n",
1389 i915_ggtt_offset(rq->ring->vma));
1390 drm_printf(m, "\t\tring->head: 0x%08x\n",
1391 rq->ring->head);
1392 drm_printf(m, "\t\tring->tail: 0x%08x\n",
1393 rq->ring->tail);
1394 drm_printf(m, "\t\tring->emit: 0x%08x\n",
1395 rq->ring->emit);
1396 drm_printf(m, "\t\tring->space: 0x%08x\n",
1397 rq->ring->space);
1398 drm_printf(m, "\t\tring->hwsp: 0x%08x\n",
1399 rq->timeline->hwsp_offset);
1400
1401 print_request_ring(m, rq);
1402 }
1403 spin_unlock_irqrestore(&engine->active.lock, flags);
1404
1405 drm_printf(m, "\tMMIO base: 0x%08x\n", engine->mmio_base);
1406 wakeref = intel_runtime_pm_get_if_in_use(&engine->i915->runtime_pm);
1407 if (wakeref) {
1408 intel_engine_print_registers(engine, m);
1409 intel_runtime_pm_put(&engine->i915->runtime_pm, wakeref);
1410 } else {
1411 drm_printf(m, "\tDevice is asleep; skipping register dump\n");
1412 }
1413
1414 intel_execlists_show_requests(engine, m, print_request, 8);
1415
1416 drm_printf(m, "HWSP:\n");
1417 hexdump(m, engine->status_page.addr, PAGE_SIZE);
1418
1419 drm_printf(m, "Idle? %s\n", yesno(intel_engine_is_idle(engine)));
1420
1421 intel_engine_print_breadcrumbs(engine, m);
1422}
1423
1424/**
1425 * intel_enable_engine_stats() - Enable engine busy tracking on engine
1426 * @engine: engine to enable stats collection
1427 *
1428 * Start collecting the engine busyness data for @engine.
1429 *
1430 * Returns 0 on success or a negative error code.
1431 */
1432int intel_enable_engine_stats(struct intel_engine_cs *engine)
1433{
1434 struct intel_engine_execlists *execlists = &engine->execlists;
1435 unsigned long flags;
1436 int err = 0;
1437
1438 if (!intel_engine_supports_stats(engine))
1439 return -ENODEV;
1440
1441 execlists_active_lock_bh(execlists);
1442 write_seqlock_irqsave(&engine->stats.lock, flags);
1443
1444 if (unlikely(engine->stats.enabled == ~0)) {
1445 err = -EBUSY;
1446 goto unlock;
1447 }
1448
1449 if (engine->stats.enabled++ == 0) {
1450 struct i915_request * const *port;
1451 struct i915_request *rq;
1452
1453 engine->stats.enabled_at = ktime_get();
1454
1455 /* XXX submission method oblivious? */
1456 for (port = execlists->active; (rq = *port); port++)
1457 engine->stats.active++;
1458
1459 for (port = execlists->pending; (rq = *port); port++) {
1460 /* Exclude any contexts already counted in active */
1461 if (!intel_context_inflight_count(rq->hw_context))
1462 engine->stats.active++;
1463 }
1464
1465 if (engine->stats.active)
1466 engine->stats.start = engine->stats.enabled_at;
1467 }
1468
1469unlock:
1470 write_sequnlock_irqrestore(&engine->stats.lock, flags);
1471 execlists_active_unlock_bh(execlists);
1472
1473 return err;
1474}
1475
1476static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine)
1477{
1478 ktime_t total = engine->stats.total;
1479
1480 /*
1481 * If the engine is executing something at the moment
1482 * add it to the total.
1483 */
1484 if (engine->stats.active)
1485 total = ktime_add(total,
1486 ktime_sub(ktime_get(), engine->stats.start));
1487
1488 return total;
1489}
1490
1491/**
1492 * intel_engine_get_busy_time() - Return current accumulated engine busyness
1493 * @engine: engine to report on
1494 *
1495 * Returns accumulated time @engine was busy since engine stats were enabled.
1496 */
1497ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine)
1498{
1499 unsigned int seq;
1500 ktime_t total;
1501
1502 do {
1503 seq = read_seqbegin(&engine->stats.lock);
1504 total = __intel_engine_get_busy_time(engine);
1505 } while (read_seqretry(&engine->stats.lock, seq));
1506
1507 return total;
1508}
1509
1510/**
1511 * intel_disable_engine_stats() - Disable engine busy tracking on engine
1512 * @engine: engine to disable stats collection
1513 *
1514 * Stops collecting the engine busyness data for @engine.
1515 */
1516void intel_disable_engine_stats(struct intel_engine_cs *engine)
1517{
1518 unsigned long flags;
1519
1520 if (!intel_engine_supports_stats(engine))
1521 return;
1522
1523 write_seqlock_irqsave(&engine->stats.lock, flags);
1524 WARN_ON_ONCE(engine->stats.enabled == 0);
1525 if (--engine->stats.enabled == 0) {
1526 engine->stats.total = __intel_engine_get_busy_time(engine);
1527 engine->stats.active = 0;
1528 }
1529 write_sequnlock_irqrestore(&engine->stats.lock, flags);
1530}
1531
1532static bool match_ring(struct i915_request *rq)
1533{
1534 u32 ring = ENGINE_READ(rq->engine, RING_START);
1535
1536 return ring == i915_ggtt_offset(rq->ring->vma);
1537}
1538
1539struct i915_request *
1540intel_engine_find_active_request(struct intel_engine_cs *engine)
1541{
1542 struct i915_request *request, *active = NULL;
1543
1544 /*
1545 * We are called by the error capture, reset and to dump engine
1546 * state at random points in time. In particular, note that neither is
1547 * crucially ordered with an interrupt. After a hang, the GPU is dead
1548 * and we assume that no more writes can happen (we waited long enough
1549 * for all writes that were in transaction to be flushed) - adding an
1550 * extra delay for a recent interrupt is pointless. Hence, we do
1551 * not need an engine->irq_seqno_barrier() before the seqno reads.
1552 * At all other times, we must assume the GPU is still running, but
1553 * we only care about the snapshot of this moment.
1554 */
1555 lockdep_assert_held(&engine->active.lock);
1556 list_for_each_entry(request, &engine->active.requests, sched.link) {
1557 if (i915_request_completed(request))
1558 continue;
1559
1560 if (!i915_request_started(request))
1561 continue;
1562
1563 /* More than one preemptible request may match! */
1564 if (!match_ring(request))
1565 continue;
1566
1567 active = request;
1568 break;
1569 }
1570
1571 return active;
1572}
1573
1574#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1575#include "mock_engine.c"
1576#include "selftest_engine.c"
1577#include "selftest_engine_cs.c"
1578#endif
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2016 Intel Corporation
4 */
5
6#include <linux/string_helpers.h>
7
8#include <drm/drm_print.h>
9
10#include "gem/i915_gem_context.h"
11#include "gem/i915_gem_internal.h"
12#include "gt/intel_gt_print.h"
13#include "gt/intel_gt_regs.h"
14
15#include "i915_cmd_parser.h"
16#include "i915_drv.h"
17#include "i915_irq.h"
18#include "i915_reg.h"
19#include "intel_breadcrumbs.h"
20#include "intel_context.h"
21#include "intel_engine.h"
22#include "intel_engine_pm.h"
23#include "intel_engine_regs.h"
24#include "intel_engine_user.h"
25#include "intel_execlists_submission.h"
26#include "intel_gt.h"
27#include "intel_gt_mcr.h"
28#include "intel_gt_pm.h"
29#include "intel_gt_requests.h"
30#include "intel_lrc.h"
31#include "intel_lrc_reg.h"
32#include "intel_reset.h"
33#include "intel_ring.h"
34#include "uc/intel_guc_submission.h"
35
36/* Haswell does have the CXT_SIZE register however it does not appear to be
37 * valid. Now, docs explain in dwords what is in the context object. The full
38 * size is 70720 bytes, however, the power context and execlist context will
39 * never be saved (power context is stored elsewhere, and execlists don't work
40 * on HSW) - so the final size, including the extra state required for the
41 * Resource Streamer, is 66944 bytes, which rounds to 17 pages.
42 */
43#define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
44
45#define DEFAULT_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
46#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
47#define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
48#define GEN11_LR_CONTEXT_RENDER_SIZE (14 * PAGE_SIZE)
49
50#define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
51
52#define MAX_MMIO_BASES 3
53struct engine_info {
54 u8 class;
55 u8 instance;
56 /* mmio bases table *must* be sorted in reverse graphics_ver order */
57 struct engine_mmio_base {
58 u32 graphics_ver : 8;
59 u32 base : 24;
60 } mmio_bases[MAX_MMIO_BASES];
61};
62
63static const struct engine_info intel_engines[] = {
64 [RCS0] = {
65 .class = RENDER_CLASS,
66 .instance = 0,
67 .mmio_bases = {
68 { .graphics_ver = 1, .base = RENDER_RING_BASE }
69 },
70 },
71 [BCS0] = {
72 .class = COPY_ENGINE_CLASS,
73 .instance = 0,
74 .mmio_bases = {
75 { .graphics_ver = 6, .base = BLT_RING_BASE }
76 },
77 },
78 [BCS1] = {
79 .class = COPY_ENGINE_CLASS,
80 .instance = 1,
81 .mmio_bases = {
82 { .graphics_ver = 12, .base = XEHPC_BCS1_RING_BASE }
83 },
84 },
85 [BCS2] = {
86 .class = COPY_ENGINE_CLASS,
87 .instance = 2,
88 .mmio_bases = {
89 { .graphics_ver = 12, .base = XEHPC_BCS2_RING_BASE }
90 },
91 },
92 [BCS3] = {
93 .class = COPY_ENGINE_CLASS,
94 .instance = 3,
95 .mmio_bases = {
96 { .graphics_ver = 12, .base = XEHPC_BCS3_RING_BASE }
97 },
98 },
99 [BCS4] = {
100 .class = COPY_ENGINE_CLASS,
101 .instance = 4,
102 .mmio_bases = {
103 { .graphics_ver = 12, .base = XEHPC_BCS4_RING_BASE }
104 },
105 },
106 [BCS5] = {
107 .class = COPY_ENGINE_CLASS,
108 .instance = 5,
109 .mmio_bases = {
110 { .graphics_ver = 12, .base = XEHPC_BCS5_RING_BASE }
111 },
112 },
113 [BCS6] = {
114 .class = COPY_ENGINE_CLASS,
115 .instance = 6,
116 .mmio_bases = {
117 { .graphics_ver = 12, .base = XEHPC_BCS6_RING_BASE }
118 },
119 },
120 [BCS7] = {
121 .class = COPY_ENGINE_CLASS,
122 .instance = 7,
123 .mmio_bases = {
124 { .graphics_ver = 12, .base = XEHPC_BCS7_RING_BASE }
125 },
126 },
127 [BCS8] = {
128 .class = COPY_ENGINE_CLASS,
129 .instance = 8,
130 .mmio_bases = {
131 { .graphics_ver = 12, .base = XEHPC_BCS8_RING_BASE }
132 },
133 },
134 [VCS0] = {
135 .class = VIDEO_DECODE_CLASS,
136 .instance = 0,
137 .mmio_bases = {
138 { .graphics_ver = 11, .base = GEN11_BSD_RING_BASE },
139 { .graphics_ver = 6, .base = GEN6_BSD_RING_BASE },
140 { .graphics_ver = 4, .base = BSD_RING_BASE }
141 },
142 },
143 [VCS1] = {
144 .class = VIDEO_DECODE_CLASS,
145 .instance = 1,
146 .mmio_bases = {
147 { .graphics_ver = 11, .base = GEN11_BSD2_RING_BASE },
148 { .graphics_ver = 8, .base = GEN8_BSD2_RING_BASE }
149 },
150 },
151 [VCS2] = {
152 .class = VIDEO_DECODE_CLASS,
153 .instance = 2,
154 .mmio_bases = {
155 { .graphics_ver = 11, .base = GEN11_BSD3_RING_BASE }
156 },
157 },
158 [VCS3] = {
159 .class = VIDEO_DECODE_CLASS,
160 .instance = 3,
161 .mmio_bases = {
162 { .graphics_ver = 11, .base = GEN11_BSD4_RING_BASE }
163 },
164 },
165 [VCS4] = {
166 .class = VIDEO_DECODE_CLASS,
167 .instance = 4,
168 .mmio_bases = {
169 { .graphics_ver = 12, .base = XEHP_BSD5_RING_BASE }
170 },
171 },
172 [VCS5] = {
173 .class = VIDEO_DECODE_CLASS,
174 .instance = 5,
175 .mmio_bases = {
176 { .graphics_ver = 12, .base = XEHP_BSD6_RING_BASE }
177 },
178 },
179 [VCS6] = {
180 .class = VIDEO_DECODE_CLASS,
181 .instance = 6,
182 .mmio_bases = {
183 { .graphics_ver = 12, .base = XEHP_BSD7_RING_BASE }
184 },
185 },
186 [VCS7] = {
187 .class = VIDEO_DECODE_CLASS,
188 .instance = 7,
189 .mmio_bases = {
190 { .graphics_ver = 12, .base = XEHP_BSD8_RING_BASE }
191 },
192 },
193 [VECS0] = {
194 .class = VIDEO_ENHANCEMENT_CLASS,
195 .instance = 0,
196 .mmio_bases = {
197 { .graphics_ver = 11, .base = GEN11_VEBOX_RING_BASE },
198 { .graphics_ver = 7, .base = VEBOX_RING_BASE }
199 },
200 },
201 [VECS1] = {
202 .class = VIDEO_ENHANCEMENT_CLASS,
203 .instance = 1,
204 .mmio_bases = {
205 { .graphics_ver = 11, .base = GEN11_VEBOX2_RING_BASE }
206 },
207 },
208 [VECS2] = {
209 .class = VIDEO_ENHANCEMENT_CLASS,
210 .instance = 2,
211 .mmio_bases = {
212 { .graphics_ver = 12, .base = XEHP_VEBOX3_RING_BASE }
213 },
214 },
215 [VECS3] = {
216 .class = VIDEO_ENHANCEMENT_CLASS,
217 .instance = 3,
218 .mmio_bases = {
219 { .graphics_ver = 12, .base = XEHP_VEBOX4_RING_BASE }
220 },
221 },
222 [CCS0] = {
223 .class = COMPUTE_CLASS,
224 .instance = 0,
225 .mmio_bases = {
226 { .graphics_ver = 12, .base = GEN12_COMPUTE0_RING_BASE }
227 }
228 },
229 [CCS1] = {
230 .class = COMPUTE_CLASS,
231 .instance = 1,
232 .mmio_bases = {
233 { .graphics_ver = 12, .base = GEN12_COMPUTE1_RING_BASE }
234 }
235 },
236 [CCS2] = {
237 .class = COMPUTE_CLASS,
238 .instance = 2,
239 .mmio_bases = {
240 { .graphics_ver = 12, .base = GEN12_COMPUTE2_RING_BASE }
241 }
242 },
243 [CCS3] = {
244 .class = COMPUTE_CLASS,
245 .instance = 3,
246 .mmio_bases = {
247 { .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
248 }
249 },
250 [GSC0] = {
251 .class = OTHER_CLASS,
252 .instance = OTHER_GSC_INSTANCE,
253 .mmio_bases = {
254 { .graphics_ver = 12, .base = MTL_GSC_RING_BASE }
255 }
256 },
257};
258
259/**
260 * intel_engine_context_size() - return the size of the context for an engine
261 * @gt: the gt
262 * @class: engine class
263 *
264 * Each engine class may require a different amount of space for a context
265 * image.
266 *
267 * Return: size (in bytes) of an engine class specific context image
268 *
269 * Note: this size includes the HWSP, which is part of the context image
270 * in LRC mode, but does not include the "shared data page" used with
271 * GuC submission. The caller should account for this if using the GuC.
272 */
273u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
274{
275 struct intel_uncore *uncore = gt->uncore;
276 u32 cxt_size;
277
278 BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE);
279
280 switch (class) {
281 case COMPUTE_CLASS:
282 fallthrough;
283 case RENDER_CLASS:
284 switch (GRAPHICS_VER(gt->i915)) {
285 default:
286 MISSING_CASE(GRAPHICS_VER(gt->i915));
287 return DEFAULT_LR_CONTEXT_RENDER_SIZE;
288 case 12:
289 case 11:
290 return GEN11_LR_CONTEXT_RENDER_SIZE;
291 case 9:
292 return GEN9_LR_CONTEXT_RENDER_SIZE;
293 case 8:
294 return GEN8_LR_CONTEXT_RENDER_SIZE;
295 case 7:
296 if (IS_HASWELL(gt->i915))
297 return HSW_CXT_TOTAL_SIZE;
298
299 cxt_size = intel_uncore_read(uncore, GEN7_CXT_SIZE);
300 return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64,
301 PAGE_SIZE);
302 case 6:
303 cxt_size = intel_uncore_read(uncore, CXT_SIZE);
304 return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
305 PAGE_SIZE);
306 case 5:
307 case 4:
308 /*
309 * There is a discrepancy here between the size reported
310 * by the register and the size of the context layout
311 * in the docs. Both are described as authorative!
312 *
313 * The discrepancy is on the order of a few cachelines,
314 * but the total is under one page (4k), which is our
315 * minimum allocation anyway so it should all come
316 * out in the wash.
317 */
318 cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1;
319 gt_dbg(gt, "graphics_ver = %d CXT_SIZE = %d bytes [0x%08x]\n",
320 GRAPHICS_VER(gt->i915), cxt_size * 64,
321 cxt_size - 1);
322 return round_up(cxt_size * 64, PAGE_SIZE);
323 case 3:
324 case 2:
325 /* For the special day when i810 gets merged. */
326 case 1:
327 return 0;
328 }
329 break;
330 default:
331 MISSING_CASE(class);
332 fallthrough;
333 case VIDEO_DECODE_CLASS:
334 case VIDEO_ENHANCEMENT_CLASS:
335 case COPY_ENGINE_CLASS:
336 case OTHER_CLASS:
337 if (GRAPHICS_VER(gt->i915) < 8)
338 return 0;
339 return GEN8_LR_CONTEXT_OTHER_SIZE;
340 }
341}
342
343static u32 __engine_mmio_base(struct drm_i915_private *i915,
344 const struct engine_mmio_base *bases)
345{
346 int i;
347
348 for (i = 0; i < MAX_MMIO_BASES; i++)
349 if (GRAPHICS_VER(i915) >= bases[i].graphics_ver)
350 break;
351
352 GEM_BUG_ON(i == MAX_MMIO_BASES);
353 GEM_BUG_ON(!bases[i].base);
354
355 return bases[i].base;
356}
357
358static void __sprint_engine_name(struct intel_engine_cs *engine)
359{
360 /*
361 * Before we know what the uABI name for this engine will be,
362 * we still would like to keep track of this engine in the debug logs.
363 * We throw in a ' here as a reminder that this isn't its final name.
364 */
365 GEM_WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s'%u",
366 intel_engine_class_repr(engine->class),
367 engine->instance) >= sizeof(engine->name));
368}
369
370void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)
371{
372 /*
373 * Though they added more rings on g4x/ilk, they did not add
374 * per-engine HWSTAM until gen6.
375 */
376 if (GRAPHICS_VER(engine->i915) < 6 && engine->class != RENDER_CLASS)
377 return;
378
379 if (GRAPHICS_VER(engine->i915) >= 3)
380 ENGINE_WRITE(engine, RING_HWSTAM, mask);
381 else
382 ENGINE_WRITE16(engine, RING_HWSTAM, mask);
383}
384
385static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine)
386{
387 /* Mask off all writes into the unknown HWSP */
388 intel_engine_set_hwsp_writemask(engine, ~0u);
389}
390
391static void nop_irq_handler(struct intel_engine_cs *engine, u16 iir)
392{
393 GEM_DEBUG_WARN_ON(iir);
394}
395
396static u32 get_reset_domain(u8 ver, enum intel_engine_id id)
397{
398 u32 reset_domain;
399
400 if (ver >= 11) {
401 static const u32 engine_reset_domains[] = {
402 [RCS0] = GEN11_GRDOM_RENDER,
403 [BCS0] = GEN11_GRDOM_BLT,
404 [BCS1] = XEHPC_GRDOM_BLT1,
405 [BCS2] = XEHPC_GRDOM_BLT2,
406 [BCS3] = XEHPC_GRDOM_BLT3,
407 [BCS4] = XEHPC_GRDOM_BLT4,
408 [BCS5] = XEHPC_GRDOM_BLT5,
409 [BCS6] = XEHPC_GRDOM_BLT6,
410 [BCS7] = XEHPC_GRDOM_BLT7,
411 [BCS8] = XEHPC_GRDOM_BLT8,
412 [VCS0] = GEN11_GRDOM_MEDIA,
413 [VCS1] = GEN11_GRDOM_MEDIA2,
414 [VCS2] = GEN11_GRDOM_MEDIA3,
415 [VCS3] = GEN11_GRDOM_MEDIA4,
416 [VCS4] = GEN11_GRDOM_MEDIA5,
417 [VCS5] = GEN11_GRDOM_MEDIA6,
418 [VCS6] = GEN11_GRDOM_MEDIA7,
419 [VCS7] = GEN11_GRDOM_MEDIA8,
420 [VECS0] = GEN11_GRDOM_VECS,
421 [VECS1] = GEN11_GRDOM_VECS2,
422 [VECS2] = GEN11_GRDOM_VECS3,
423 [VECS3] = GEN11_GRDOM_VECS4,
424 [CCS0] = GEN11_GRDOM_RENDER,
425 [CCS1] = GEN11_GRDOM_RENDER,
426 [CCS2] = GEN11_GRDOM_RENDER,
427 [CCS3] = GEN11_GRDOM_RENDER,
428 [GSC0] = GEN12_GRDOM_GSC,
429 };
430 GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||
431 !engine_reset_domains[id]);
432 reset_domain = engine_reset_domains[id];
433 } else {
434 static const u32 engine_reset_domains[] = {
435 [RCS0] = GEN6_GRDOM_RENDER,
436 [BCS0] = GEN6_GRDOM_BLT,
437 [VCS0] = GEN6_GRDOM_MEDIA,
438 [VCS1] = GEN8_GRDOM_MEDIA2,
439 [VECS0] = GEN6_GRDOM_VECS,
440 };
441 GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||
442 !engine_reset_domains[id]);
443 reset_domain = engine_reset_domains[id];
444 }
445
446 return reset_domain;
447}
448
449static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id,
450 u8 logical_instance)
451{
452 const struct engine_info *info = &intel_engines[id];
453 struct drm_i915_private *i915 = gt->i915;
454 struct intel_engine_cs *engine;
455 u8 guc_class;
456
457 BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));
458 BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));
459 BUILD_BUG_ON(I915_MAX_VCS > (MAX_ENGINE_INSTANCE + 1));
460 BUILD_BUG_ON(I915_MAX_VECS > (MAX_ENGINE_INSTANCE + 1));
461
462 if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine)))
463 return -EINVAL;
464
465 if (GEM_DEBUG_WARN_ON(info->class > MAX_ENGINE_CLASS))
466 return -EINVAL;
467
468 if (GEM_DEBUG_WARN_ON(info->instance > MAX_ENGINE_INSTANCE))
469 return -EINVAL;
470
471 if (GEM_DEBUG_WARN_ON(gt->engine_class[info->class][info->instance]))
472 return -EINVAL;
473
474 engine = kzalloc(sizeof(*engine), GFP_KERNEL);
475 if (!engine)
476 return -ENOMEM;
477
478 BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES);
479
480 INIT_LIST_HEAD(&engine->pinned_contexts_list);
481 engine->id = id;
482 engine->legacy_idx = INVALID_ENGINE;
483 engine->mask = BIT(id);
484 engine->reset_domain = get_reset_domain(GRAPHICS_VER(gt->i915),
485 id);
486 engine->i915 = i915;
487 engine->gt = gt;
488 engine->uncore = gt->uncore;
489 guc_class = engine_class_to_guc_class(info->class);
490 engine->guc_id = MAKE_GUC_ID(guc_class, info->instance);
491 engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases);
492
493 engine->irq_handler = nop_irq_handler;
494
495 engine->class = info->class;
496 engine->instance = info->instance;
497 engine->logical_mask = BIT(logical_instance);
498 __sprint_engine_name(engine);
499
500 if ((engine->class == COMPUTE_CLASS && !RCS_MASK(engine->gt) &&
501 __ffs(CCS_MASK(engine->gt)) == engine->instance) ||
502 engine->class == RENDER_CLASS)
503 engine->flags |= I915_ENGINE_FIRST_RENDER_COMPUTE;
504
505 /* features common between engines sharing EUs */
506 if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) {
507 engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
508 engine->flags |= I915_ENGINE_HAS_EU_PRIORITY;
509 }
510
511 engine->props.heartbeat_interval_ms =
512 CONFIG_DRM_I915_HEARTBEAT_INTERVAL;
513 engine->props.max_busywait_duration_ns =
514 CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT;
515 engine->props.preempt_timeout_ms =
516 CONFIG_DRM_I915_PREEMPT_TIMEOUT;
517 engine->props.stop_timeout_ms =
518 CONFIG_DRM_I915_STOP_TIMEOUT;
519 engine->props.timeslice_duration_ms =
520 CONFIG_DRM_I915_TIMESLICE_DURATION;
521
522 /*
523 * Mid-thread pre-emption is not available in Gen12. Unfortunately,
524 * some compute workloads run quite long threads. That means they get
525 * reset due to not pre-empting in a timely manner. So, bump the
526 * pre-emption timeout value to be much higher for compute engines.
527 */
528 if (GRAPHICS_VER(i915) == 12 && (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE))
529 engine->props.preempt_timeout_ms = CONFIG_DRM_I915_PREEMPT_TIMEOUT_COMPUTE;
530
531 /* Cap properties according to any system limits */
532#define CLAMP_PROP(field) \
533 do { \
534 u64 clamp = intel_clamp_##field(engine, engine->props.field); \
535 if (clamp != engine->props.field) { \
536 drm_notice(&engine->i915->drm, \
537 "Warning, clamping %s to %lld to prevent overflow\n", \
538 #field, clamp); \
539 engine->props.field = clamp; \
540 } \
541 } while (0)
542
543 CLAMP_PROP(heartbeat_interval_ms);
544 CLAMP_PROP(max_busywait_duration_ns);
545 CLAMP_PROP(preempt_timeout_ms);
546 CLAMP_PROP(stop_timeout_ms);
547 CLAMP_PROP(timeslice_duration_ms);
548
549#undef CLAMP_PROP
550
551 engine->defaults = engine->props; /* never to change again */
552
553 engine->context_size = intel_engine_context_size(gt, engine->class);
554 if (WARN_ON(engine->context_size > BIT(20)))
555 engine->context_size = 0;
556 if (engine->context_size)
557 DRIVER_CAPS(i915)->has_logical_contexts = true;
558
559 ewma__engine_latency_init(&engine->latency);
560
561 ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);
562
563 /* Scrub mmio state on takeover */
564 intel_engine_sanitize_mmio(engine);
565
566 gt->engine_class[info->class][info->instance] = engine;
567 gt->engine[id] = engine;
568
569 return 0;
570}
571
572u64 intel_clamp_heartbeat_interval_ms(struct intel_engine_cs *engine, u64 value)
573{
574 value = min_t(u64, value, jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT));
575
576 return value;
577}
578
579u64 intel_clamp_max_busywait_duration_ns(struct intel_engine_cs *engine, u64 value)
580{
581 value = min(value, jiffies_to_nsecs(2));
582
583 return value;
584}
585
586u64 intel_clamp_preempt_timeout_ms(struct intel_engine_cs *engine, u64 value)
587{
588 /*
589 * NB: The GuC API only supports 32bit values. However, the limit is further
590 * reduced due to internal calculations which would otherwise overflow.
591 */
592 if (intel_guc_submission_is_wanted(&engine->gt->uc.guc))
593 value = min_t(u64, value, guc_policy_max_preempt_timeout_ms());
594
595 value = min_t(u64, value, jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT));
596
597 return value;
598}
599
600u64 intel_clamp_stop_timeout_ms(struct intel_engine_cs *engine, u64 value)
601{
602 value = min_t(u64, value, jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT));
603
604 return value;
605}
606
607u64 intel_clamp_timeslice_duration_ms(struct intel_engine_cs *engine, u64 value)
608{
609 /*
610 * NB: The GuC API only supports 32bit values. However, the limit is further
611 * reduced due to internal calculations which would otherwise overflow.
612 */
613 if (intel_guc_submission_is_wanted(&engine->gt->uc.guc))
614 value = min_t(u64, value, guc_policy_max_exec_quantum_ms());
615
616 value = min_t(u64, value, jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT));
617
618 return value;
619}
620
621static void __setup_engine_capabilities(struct intel_engine_cs *engine)
622{
623 struct drm_i915_private *i915 = engine->i915;
624
625 if (engine->class == VIDEO_DECODE_CLASS) {
626 /*
627 * HEVC support is present on first engine instance
628 * before Gen11 and on all instances afterwards.
629 */
630 if (GRAPHICS_VER(i915) >= 11 ||
631 (GRAPHICS_VER(i915) >= 9 && engine->instance == 0))
632 engine->uabi_capabilities |=
633 I915_VIDEO_CLASS_CAPABILITY_HEVC;
634
635 /*
636 * SFC block is present only on even logical engine
637 * instances.
638 */
639 if ((GRAPHICS_VER(i915) >= 11 &&
640 (engine->gt->info.vdbox_sfc_access &
641 BIT(engine->instance))) ||
642 (GRAPHICS_VER(i915) >= 9 && engine->instance == 0))
643 engine->uabi_capabilities |=
644 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
645 } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
646 if (GRAPHICS_VER(i915) >= 9 &&
647 engine->gt->info.sfc_mask & BIT(engine->instance))
648 engine->uabi_capabilities |=
649 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
650 }
651}
652
653static void intel_setup_engine_capabilities(struct intel_gt *gt)
654{
655 struct intel_engine_cs *engine;
656 enum intel_engine_id id;
657
658 for_each_engine(engine, gt, id)
659 __setup_engine_capabilities(engine);
660}
661
662/**
663 * intel_engines_release() - free the resources allocated for Command Streamers
664 * @gt: pointer to struct intel_gt
665 */
666void intel_engines_release(struct intel_gt *gt)
667{
668 struct intel_engine_cs *engine;
669 enum intel_engine_id id;
670
671 /*
672 * Before we release the resources held by engine, we must be certain
673 * that the HW is no longer accessing them -- having the GPU scribble
674 * to or read from a page being used for something else causes no end
675 * of fun.
676 *
677 * The GPU should be reset by this point, but assume the worst just
678 * in case we aborted before completely initialising the engines.
679 */
680 GEM_BUG_ON(intel_gt_pm_is_awake(gt));
681 if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
682 __intel_gt_reset(gt, ALL_ENGINES);
683
684 /* Decouple the backend; but keep the layout for late GPU resets */
685 for_each_engine(engine, gt, id) {
686 if (!engine->release)
687 continue;
688
689 intel_wakeref_wait_for_idle(&engine->wakeref);
690 GEM_BUG_ON(intel_engine_pm_is_awake(engine));
691
692 engine->release(engine);
693 engine->release = NULL;
694
695 memset(&engine->reset, 0, sizeof(engine->reset));
696 }
697}
698
699void intel_engine_free_request_pool(struct intel_engine_cs *engine)
700{
701 if (!engine->request_pool)
702 return;
703
704 kmem_cache_free(i915_request_slab_cache(), engine->request_pool);
705}
706
707void intel_engines_free(struct intel_gt *gt)
708{
709 struct intel_engine_cs *engine;
710 enum intel_engine_id id;
711
712 /* Free the requests! dma-resv keeps fences around for an eternity */
713 rcu_barrier();
714
715 for_each_engine(engine, gt, id) {
716 intel_engine_free_request_pool(engine);
717 kfree(engine);
718 gt->engine[id] = NULL;
719 }
720}
721
722static
723bool gen11_vdbox_has_sfc(struct intel_gt *gt,
724 unsigned int physical_vdbox,
725 unsigned int logical_vdbox, u16 vdbox_mask)
726{
727 struct drm_i915_private *i915 = gt->i915;
728
729 /*
730 * In Gen11, only even numbered logical VDBOXes are hooked
731 * up to an SFC (Scaler & Format Converter) unit.
732 * In Gen12, Even numbered physical instance always are connected
733 * to an SFC. Odd numbered physical instances have SFC only if
734 * previous even instance is fused off.
735 *
736 * Starting with Xe_HP, there's also a dedicated SFC_ENABLE field
737 * in the fuse register that tells us whether a specific SFC is present.
738 */
739 if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0)
740 return false;
741 else if (MEDIA_VER(i915) >= 12)
742 return (physical_vdbox % 2 == 0) ||
743 !(BIT(physical_vdbox - 1) & vdbox_mask);
744 else if (MEDIA_VER(i915) == 11)
745 return logical_vdbox % 2 == 0;
746
747 return false;
748}
749
750static void engine_mask_apply_media_fuses(struct intel_gt *gt)
751{
752 struct drm_i915_private *i915 = gt->i915;
753 unsigned int logical_vdbox = 0;
754 unsigned int i;
755 u32 media_fuse, fuse1;
756 u16 vdbox_mask;
757 u16 vebox_mask;
758
759 if (MEDIA_VER(gt->i915) < 11)
760 return;
761
762 /*
763 * On newer platforms the fusing register is called 'enable' and has
764 * enable semantics, while on older platforms it is called 'disable'
765 * and bits have disable semantices.
766 */
767 media_fuse = intel_uncore_read(gt->uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
768 if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
769 media_fuse = ~media_fuse;
770
771 vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
772 vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
773 GEN11_GT_VEBOX_DISABLE_SHIFT;
774
775 if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
776 fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
777 gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
778 } else {
779 gt->info.sfc_mask = ~0;
780 }
781
782 for (i = 0; i < I915_MAX_VCS; i++) {
783 if (!HAS_ENGINE(gt, _VCS(i))) {
784 vdbox_mask &= ~BIT(i);
785 continue;
786 }
787
788 if (!(BIT(i) & vdbox_mask)) {
789 gt->info.engine_mask &= ~BIT(_VCS(i));
790 gt_dbg(gt, "vcs%u fused off\n", i);
791 continue;
792 }
793
794 if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
795 gt->info.vdbox_sfc_access |= BIT(i);
796 logical_vdbox++;
797 }
798 gt_dbg(gt, "vdbox enable: %04x, instances: %04lx\n", vdbox_mask, VDBOX_MASK(gt));
799 GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
800
801 for (i = 0; i < I915_MAX_VECS; i++) {
802 if (!HAS_ENGINE(gt, _VECS(i))) {
803 vebox_mask &= ~BIT(i);
804 continue;
805 }
806
807 if (!(BIT(i) & vebox_mask)) {
808 gt->info.engine_mask &= ~BIT(_VECS(i));
809 gt_dbg(gt, "vecs%u fused off\n", i);
810 }
811 }
812 gt_dbg(gt, "vebox enable: %04x, instances: %04lx\n", vebox_mask, VEBOX_MASK(gt));
813 GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
814}
815
816static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
817{
818 struct drm_i915_private *i915 = gt->i915;
819 struct intel_gt_info *info = >->info;
820 int ss_per_ccs = info->sseu.max_subslices / I915_MAX_CCS;
821 unsigned long ccs_mask;
822 unsigned int i;
823
824 if (GRAPHICS_VER(i915) < 11)
825 return;
826
827 if (hweight32(CCS_MASK(gt)) <= 1)
828 return;
829
830 ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask,
831 ss_per_ccs);
832 /*
833 * If all DSS in a quadrant are fused off, the corresponding CCS
834 * engine is not available for use.
835 */
836 for_each_clear_bit(i, &ccs_mask, I915_MAX_CCS) {
837 info->engine_mask &= ~BIT(_CCS(i));
838 gt_dbg(gt, "ccs%u fused off\n", i);
839 }
840}
841
842static void engine_mask_apply_copy_fuses(struct intel_gt *gt)
843{
844 struct drm_i915_private *i915 = gt->i915;
845 struct intel_gt_info *info = >->info;
846 unsigned long meml3_mask;
847 unsigned long quad;
848
849 if (!(GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60) &&
850 GRAPHICS_VER_FULL(i915) < IP_VER(12, 70)))
851 return;
852
853 meml3_mask = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
854 meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask);
855
856 /*
857 * Link Copy engines may be fused off according to meml3_mask. Each
858 * bit is a quad that houses 2 Link Copy and two Sub Copy engines.
859 */
860 for_each_clear_bit(quad, &meml3_mask, GEN12_MAX_MSLICES) {
861 unsigned int instance = quad * 2 + 1;
862 intel_engine_mask_t mask = GENMASK(_BCS(instance + 1),
863 _BCS(instance));
864
865 if (mask & info->engine_mask) {
866 gt_dbg(gt, "bcs%u fused off\n", instance);
867 gt_dbg(gt, "bcs%u fused off\n", instance + 1);
868
869 info->engine_mask &= ~mask;
870 }
871 }
872}
873
874/*
875 * Determine which engines are fused off in our particular hardware.
876 * Note that we have a catch-22 situation where we need to be able to access
877 * the blitter forcewake domain to read the engine fuses, but at the same time
878 * we need to know which engines are available on the system to know which
879 * forcewake domains are present. We solve this by intializing the forcewake
880 * domains based on the full engine mask in the platform capabilities before
881 * calling this function and pruning the domains for fused-off engines
882 * afterwards.
883 */
884static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
885{
886 struct intel_gt_info *info = >->info;
887
888 GEM_BUG_ON(!info->engine_mask);
889
890 engine_mask_apply_media_fuses(gt);
891 engine_mask_apply_compute_fuses(gt);
892 engine_mask_apply_copy_fuses(gt);
893
894 /*
895 * The only use of the GSC CS is to load and communicate with the GSC
896 * FW, so we have no use for it if we don't have the FW.
897 *
898 * IMPORTANT: in cases where we don't have the GSC FW, we have a
899 * catch-22 situation that breaks media C6 due to 2 requirements:
900 * 1) once turned on, the GSC power well will not go to sleep unless the
901 * GSC FW is loaded.
902 * 2) to enable idling (which is required for media C6) we need to
903 * initialize the IDLE_MSG register for the GSC CS and do at least 1
904 * submission, which will wake up the GSC power well.
905 */
906 if (__HAS_ENGINE(info->engine_mask, GSC0) && !intel_uc_wants_gsc_uc(>->uc)) {
907 gt_notice(gt, "No GSC FW selected, disabling GSC CS and media C6\n");
908 info->engine_mask &= ~BIT(GSC0);
909 }
910
911 return info->engine_mask;
912}
913
914static void populate_logical_ids(struct intel_gt *gt, u8 *logical_ids,
915 u8 class, const u8 *map, u8 num_instances)
916{
917 int i, j;
918 u8 current_logical_id = 0;
919
920 for (j = 0; j < num_instances; ++j) {
921 for (i = 0; i < ARRAY_SIZE(intel_engines); ++i) {
922 if (!HAS_ENGINE(gt, i) ||
923 intel_engines[i].class != class)
924 continue;
925
926 if (intel_engines[i].instance == map[j]) {
927 logical_ids[intel_engines[i].instance] =
928 current_logical_id++;
929 break;
930 }
931 }
932 }
933}
934
935static void setup_logical_ids(struct intel_gt *gt, u8 *logical_ids, u8 class)
936{
937 /*
938 * Logical to physical mapping is needed for proper support
939 * to split-frame feature.
940 */
941 if (MEDIA_VER(gt->i915) >= 11 && class == VIDEO_DECODE_CLASS) {
942 const u8 map[] = { 0, 2, 4, 6, 1, 3, 5, 7 };
943
944 populate_logical_ids(gt, logical_ids, class,
945 map, ARRAY_SIZE(map));
946 } else {
947 int i;
948 u8 map[MAX_ENGINE_INSTANCE + 1];
949
950 for (i = 0; i < MAX_ENGINE_INSTANCE + 1; ++i)
951 map[i] = i;
952 populate_logical_ids(gt, logical_ids, class,
953 map, ARRAY_SIZE(map));
954 }
955}
956
957/**
958 * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers
959 * @gt: pointer to struct intel_gt
960 *
961 * Return: non-zero if the initialization failed.
962 */
963int intel_engines_init_mmio(struct intel_gt *gt)
964{
965 struct drm_i915_private *i915 = gt->i915;
966 const unsigned int engine_mask = init_engine_mask(gt);
967 unsigned int mask = 0;
968 unsigned int i, class;
969 u8 logical_ids[MAX_ENGINE_INSTANCE + 1];
970 int err;
971
972 drm_WARN_ON(&i915->drm, engine_mask == 0);
973 drm_WARN_ON(&i915->drm, engine_mask &
974 GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
975
976 if (i915_inject_probe_failure(i915))
977 return -ENODEV;
978
979 for (class = 0; class < MAX_ENGINE_CLASS + 1; ++class) {
980 setup_logical_ids(gt, logical_ids, class);
981
982 for (i = 0; i < ARRAY_SIZE(intel_engines); ++i) {
983 u8 instance = intel_engines[i].instance;
984
985 if (intel_engines[i].class != class ||
986 !HAS_ENGINE(gt, i))
987 continue;
988
989 err = intel_engine_setup(gt, i,
990 logical_ids[instance]);
991 if (err)
992 goto cleanup;
993
994 mask |= BIT(i);
995 }
996 }
997
998 /*
999 * Catch failures to update intel_engines table when the new engines
1000 * are added to the driver by a warning and disabling the forgotten
1001 * engines.
1002 */
1003 if (drm_WARN_ON(&i915->drm, mask != engine_mask))
1004 gt->info.engine_mask = mask;
1005
1006 gt->info.num_engines = hweight32(mask);
1007
1008 intel_gt_check_and_clear_faults(gt);
1009
1010 intel_setup_engine_capabilities(gt);
1011
1012 intel_uncore_prune_engine_fw_domains(gt->uncore, gt);
1013
1014 return 0;
1015
1016cleanup:
1017 intel_engines_free(gt);
1018 return err;
1019}
1020
1021void intel_engine_init_execlists(struct intel_engine_cs *engine)
1022{
1023 struct intel_engine_execlists * const execlists = &engine->execlists;
1024
1025 execlists->port_mask = 1;
1026 GEM_BUG_ON(!is_power_of_2(execlists_num_ports(execlists)));
1027 GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS);
1028
1029 memset(execlists->pending, 0, sizeof(execlists->pending));
1030 execlists->active =
1031 memset(execlists->inflight, 0, sizeof(execlists->inflight));
1032}
1033
1034static void cleanup_status_page(struct intel_engine_cs *engine)
1035{
1036 struct i915_vma *vma;
1037
1038 /* Prevent writes into HWSP after returning the page to the system */
1039 intel_engine_set_hwsp_writemask(engine, ~0u);
1040
1041 vma = fetch_and_zero(&engine->status_page.vma);
1042 if (!vma)
1043 return;
1044
1045 if (!HWS_NEEDS_PHYSICAL(engine->i915))
1046 i915_vma_unpin(vma);
1047
1048 i915_gem_object_unpin_map(vma->obj);
1049 i915_gem_object_put(vma->obj);
1050}
1051
1052static int pin_ggtt_status_page(struct intel_engine_cs *engine,
1053 struct i915_gem_ww_ctx *ww,
1054 struct i915_vma *vma)
1055{
1056 unsigned int flags;
1057
1058 if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt))
1059 /*
1060 * On g33, we cannot place HWS above 256MiB, so
1061 * restrict its pinning to the low mappable arena.
1062 * Though this restriction is not documented for
1063 * gen4, gen5, or byt, they also behave similarly
1064 * and hang if the HWS is placed at the top of the
1065 * GTT. To generalise, it appears that all !llc
1066 * platforms have issues with us placing the HWS
1067 * above the mappable region (even though we never
1068 * actually map it).
1069 */
1070 flags = PIN_MAPPABLE;
1071 else
1072 flags = PIN_HIGH;
1073
1074 return i915_ggtt_pin(vma, ww, 0, flags);
1075}
1076
1077static int init_status_page(struct intel_engine_cs *engine)
1078{
1079 struct drm_i915_gem_object *obj;
1080 struct i915_gem_ww_ctx ww;
1081 struct i915_vma *vma;
1082 void *vaddr;
1083 int ret;
1084
1085 INIT_LIST_HEAD(&engine->status_page.timelines);
1086
1087 /*
1088 * Though the HWS register does support 36bit addresses, historically
1089 * we have had hangs and corruption reported due to wild writes if
1090 * the HWS is placed above 4G. We only allow objects to be allocated
1091 * in GFP_DMA32 for i965, and no earlier physical address users had
1092 * access to more than 4G.
1093 */
1094 obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
1095 if (IS_ERR(obj)) {
1096 gt_err(engine->gt, "Failed to allocate status page\n");
1097 return PTR_ERR(obj);
1098 }
1099
1100 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
1101
1102 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
1103 if (IS_ERR(vma)) {
1104 ret = PTR_ERR(vma);
1105 goto err_put;
1106 }
1107
1108 i915_gem_ww_ctx_init(&ww, true);
1109retry:
1110 ret = i915_gem_object_lock(obj, &ww);
1111 if (!ret && !HWS_NEEDS_PHYSICAL(engine->i915))
1112 ret = pin_ggtt_status_page(engine, &ww, vma);
1113 if (ret)
1114 goto err;
1115
1116 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
1117 if (IS_ERR(vaddr)) {
1118 ret = PTR_ERR(vaddr);
1119 goto err_unpin;
1120 }
1121
1122 engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE);
1123 engine->status_page.vma = vma;
1124
1125err_unpin:
1126 if (ret)
1127 i915_vma_unpin(vma);
1128err:
1129 if (ret == -EDEADLK) {
1130 ret = i915_gem_ww_ctx_backoff(&ww);
1131 if (!ret)
1132 goto retry;
1133 }
1134 i915_gem_ww_ctx_fini(&ww);
1135err_put:
1136 if (ret)
1137 i915_gem_object_put(obj);
1138 return ret;
1139}
1140
1141static int intel_engine_init_tlb_invalidation(struct intel_engine_cs *engine)
1142{
1143 static const union intel_engine_tlb_inv_reg gen8_regs[] = {
1144 [RENDER_CLASS].reg = GEN8_RTCR,
1145 [VIDEO_DECODE_CLASS].reg = GEN8_M1TCR, /* , GEN8_M2TCR */
1146 [VIDEO_ENHANCEMENT_CLASS].reg = GEN8_VTCR,
1147 [COPY_ENGINE_CLASS].reg = GEN8_BTCR,
1148 };
1149 static const union intel_engine_tlb_inv_reg gen12_regs[] = {
1150 [RENDER_CLASS].reg = GEN12_GFX_TLB_INV_CR,
1151 [VIDEO_DECODE_CLASS].reg = GEN12_VD_TLB_INV_CR,
1152 [VIDEO_ENHANCEMENT_CLASS].reg = GEN12_VE_TLB_INV_CR,
1153 [COPY_ENGINE_CLASS].reg = GEN12_BLT_TLB_INV_CR,
1154 [COMPUTE_CLASS].reg = GEN12_COMPCTX_TLB_INV_CR,
1155 };
1156 static const union intel_engine_tlb_inv_reg xehp_regs[] = {
1157 [RENDER_CLASS].mcr_reg = XEHP_GFX_TLB_INV_CR,
1158 [VIDEO_DECODE_CLASS].mcr_reg = XEHP_VD_TLB_INV_CR,
1159 [VIDEO_ENHANCEMENT_CLASS].mcr_reg = XEHP_VE_TLB_INV_CR,
1160 [COPY_ENGINE_CLASS].mcr_reg = XEHP_BLT_TLB_INV_CR,
1161 [COMPUTE_CLASS].mcr_reg = XEHP_COMPCTX_TLB_INV_CR,
1162 };
1163 static const union intel_engine_tlb_inv_reg xelpmp_regs[] = {
1164 [VIDEO_DECODE_CLASS].reg = GEN12_VD_TLB_INV_CR,
1165 [VIDEO_ENHANCEMENT_CLASS].reg = GEN12_VE_TLB_INV_CR,
1166 [OTHER_CLASS].reg = XELPMP_GSC_TLB_INV_CR,
1167 };
1168 struct drm_i915_private *i915 = engine->i915;
1169 const unsigned int instance = engine->instance;
1170 const unsigned int class = engine->class;
1171 const union intel_engine_tlb_inv_reg *regs;
1172 union intel_engine_tlb_inv_reg reg;
1173 unsigned int num = 0;
1174 u32 val;
1175
1176 /*
1177 * New platforms should not be added with catch-all-newer (>=)
1178 * condition so that any later platform added triggers the below warning
1179 * and in turn mandates a human cross-check of whether the invalidation
1180 * flows have compatible semantics.
1181 *
1182 * For instance with the 11.00 -> 12.00 transition three out of five
1183 * respective engine registers were moved to masked type. Then after the
1184 * 12.00 -> 12.50 transition multi cast handling is required too.
1185 */
1186
1187 if (engine->gt->type == GT_MEDIA) {
1188 if (MEDIA_VER_FULL(i915) == IP_VER(13, 0)) {
1189 regs = xelpmp_regs;
1190 num = ARRAY_SIZE(xelpmp_regs);
1191 }
1192 } else {
1193 if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 71) ||
1194 GRAPHICS_VER_FULL(i915) == IP_VER(12, 70) ||
1195 GRAPHICS_VER_FULL(i915) == IP_VER(12, 50) ||
1196 GRAPHICS_VER_FULL(i915) == IP_VER(12, 55)) {
1197 regs = xehp_regs;
1198 num = ARRAY_SIZE(xehp_regs);
1199 } else if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 0) ||
1200 GRAPHICS_VER_FULL(i915) == IP_VER(12, 10)) {
1201 regs = gen12_regs;
1202 num = ARRAY_SIZE(gen12_regs);
1203 } else if (GRAPHICS_VER(i915) >= 8 && GRAPHICS_VER(i915) <= 11) {
1204 regs = gen8_regs;
1205 num = ARRAY_SIZE(gen8_regs);
1206 } else if (GRAPHICS_VER(i915) < 8) {
1207 return 0;
1208 }
1209 }
1210
1211 if (gt_WARN_ONCE(engine->gt, !num,
1212 "Platform does not implement TLB invalidation!"))
1213 return -ENODEV;
1214
1215 if (gt_WARN_ON_ONCE(engine->gt,
1216 class >= num ||
1217 (!regs[class].reg.reg &&
1218 !regs[class].mcr_reg.reg)))
1219 return -ERANGE;
1220
1221 reg = regs[class];
1222
1223 if (regs == xelpmp_regs && class == OTHER_CLASS) {
1224 /*
1225 * There's only a single GSC instance, but it uses register bit
1226 * 1 instead of either 0 or OTHER_GSC_INSTANCE.
1227 */
1228 GEM_WARN_ON(instance != OTHER_GSC_INSTANCE);
1229 val = 1;
1230 } else if (regs == gen8_regs && class == VIDEO_DECODE_CLASS && instance == 1) {
1231 reg.reg = GEN8_M2TCR;
1232 val = 0;
1233 } else {
1234 val = instance;
1235 }
1236
1237 val = BIT(val);
1238
1239 engine->tlb_inv.mcr = regs == xehp_regs;
1240 engine->tlb_inv.reg = reg;
1241 engine->tlb_inv.done = val;
1242
1243 if (GRAPHICS_VER(i915) >= 12 &&
1244 (engine->class == VIDEO_DECODE_CLASS ||
1245 engine->class == VIDEO_ENHANCEMENT_CLASS ||
1246 engine->class == COMPUTE_CLASS ||
1247 engine->class == OTHER_CLASS))
1248 engine->tlb_inv.request = _MASKED_BIT_ENABLE(val);
1249 else
1250 engine->tlb_inv.request = val;
1251
1252 return 0;
1253}
1254
1255static int engine_setup_common(struct intel_engine_cs *engine)
1256{
1257 int err;
1258
1259 init_llist_head(&engine->barrier_tasks);
1260
1261 err = intel_engine_init_tlb_invalidation(engine);
1262 if (err)
1263 return err;
1264
1265 err = init_status_page(engine);
1266 if (err)
1267 return err;
1268
1269 engine->breadcrumbs = intel_breadcrumbs_create(engine);
1270 if (!engine->breadcrumbs) {
1271 err = -ENOMEM;
1272 goto err_status;
1273 }
1274
1275 engine->sched_engine = i915_sched_engine_create(ENGINE_PHYSICAL);
1276 if (!engine->sched_engine) {
1277 err = -ENOMEM;
1278 goto err_sched_engine;
1279 }
1280 engine->sched_engine->private_data = engine;
1281
1282 err = intel_engine_init_cmd_parser(engine);
1283 if (err)
1284 goto err_cmd_parser;
1285
1286 intel_engine_init_execlists(engine);
1287 intel_engine_init__pm(engine);
1288 intel_engine_init_retire(engine);
1289
1290 /* Use the whole device by default */
1291 engine->sseu =
1292 intel_sseu_from_device_info(&engine->gt->info.sseu);
1293
1294 intel_engine_init_workarounds(engine);
1295 intel_engine_init_whitelist(engine);
1296 intel_engine_init_ctx_wa(engine);
1297
1298 if (GRAPHICS_VER(engine->i915) >= 12)
1299 engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO;
1300
1301 return 0;
1302
1303err_cmd_parser:
1304 i915_sched_engine_put(engine->sched_engine);
1305err_sched_engine:
1306 intel_breadcrumbs_put(engine->breadcrumbs);
1307err_status:
1308 cleanup_status_page(engine);
1309 return err;
1310}
1311
1312struct measure_breadcrumb {
1313 struct i915_request rq;
1314 struct intel_ring ring;
1315 u32 cs[2048];
1316};
1317
1318static int measure_breadcrumb_dw(struct intel_context *ce)
1319{
1320 struct intel_engine_cs *engine = ce->engine;
1321 struct measure_breadcrumb *frame;
1322 int dw;
1323
1324 GEM_BUG_ON(!engine->gt->scratch);
1325
1326 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1327 if (!frame)
1328 return -ENOMEM;
1329
1330 frame->rq.i915 = engine->i915;
1331 frame->rq.engine = engine;
1332 frame->rq.context = ce;
1333 rcu_assign_pointer(frame->rq.timeline, ce->timeline);
1334 frame->rq.hwsp_seqno = ce->timeline->hwsp_seqno;
1335
1336 frame->ring.vaddr = frame->cs;
1337 frame->ring.size = sizeof(frame->cs);
1338 frame->ring.wrap =
1339 BITS_PER_TYPE(frame->ring.size) - ilog2(frame->ring.size);
1340 frame->ring.effective_size = frame->ring.size;
1341 intel_ring_update_space(&frame->ring);
1342 frame->rq.ring = &frame->ring;
1343
1344 mutex_lock(&ce->timeline->mutex);
1345 spin_lock_irq(&engine->sched_engine->lock);
1346
1347 dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs;
1348
1349 spin_unlock_irq(&engine->sched_engine->lock);
1350 mutex_unlock(&ce->timeline->mutex);
1351
1352 GEM_BUG_ON(dw & 1); /* RING_TAIL must be qword aligned */
1353
1354 kfree(frame);
1355 return dw;
1356}
1357
1358struct intel_context *
1359intel_engine_create_pinned_context(struct intel_engine_cs *engine,
1360 struct i915_address_space *vm,
1361 unsigned int ring_size,
1362 unsigned int hwsp,
1363 struct lock_class_key *key,
1364 const char *name)
1365{
1366 struct intel_context *ce;
1367 int err;
1368
1369 ce = intel_context_create(engine);
1370 if (IS_ERR(ce))
1371 return ce;
1372
1373 __set_bit(CONTEXT_BARRIER_BIT, &ce->flags);
1374 ce->timeline = page_pack_bits(NULL, hwsp);
1375 ce->ring = NULL;
1376 ce->ring_size = ring_size;
1377
1378 i915_vm_put(ce->vm);
1379 ce->vm = i915_vm_get(vm);
1380
1381 err = intel_context_pin(ce); /* perma-pin so it is always available */
1382 if (err) {
1383 intel_context_put(ce);
1384 return ERR_PTR(err);
1385 }
1386
1387 list_add_tail(&ce->pinned_contexts_link, &engine->pinned_contexts_list);
1388
1389 /*
1390 * Give our perma-pinned kernel timelines a separate lockdep class,
1391 * so that we can use them from within the normal user timelines
1392 * should we need to inject GPU operations during their request
1393 * construction.
1394 */
1395 lockdep_set_class_and_name(&ce->timeline->mutex, key, name);
1396
1397 return ce;
1398}
1399
1400void intel_engine_destroy_pinned_context(struct intel_context *ce)
1401{
1402 struct intel_engine_cs *engine = ce->engine;
1403 struct i915_vma *hwsp = engine->status_page.vma;
1404
1405 GEM_BUG_ON(ce->timeline->hwsp_ggtt != hwsp);
1406
1407 mutex_lock(&hwsp->vm->mutex);
1408 list_del(&ce->timeline->engine_link);
1409 mutex_unlock(&hwsp->vm->mutex);
1410
1411 list_del(&ce->pinned_contexts_link);
1412 intel_context_unpin(ce);
1413 intel_context_put(ce);
1414}
1415
1416static struct intel_context *
1417create_ggtt_bind_context(struct intel_engine_cs *engine)
1418{
1419 static struct lock_class_key kernel;
1420
1421 /*
1422 * MI_UPDATE_GTT can insert up to 511 PTE entries and there could be multiple
1423 * bind requets at a time so get a bigger ring.
1424 */
1425 return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_512K,
1426 I915_GEM_HWS_GGTT_BIND_ADDR,
1427 &kernel, "ggtt_bind_context");
1428}
1429
1430static struct intel_context *
1431create_kernel_context(struct intel_engine_cs *engine)
1432{
1433 static struct lock_class_key kernel;
1434
1435 return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K,
1436 I915_GEM_HWS_SEQNO_ADDR,
1437 &kernel, "kernel_context");
1438}
1439
1440/*
1441 * engine_init_common - initialize engine state which might require hw access
1442 * @engine: Engine to initialize.
1443 *
1444 * Initializes @engine@ structure members shared between legacy and execlists
1445 * submission modes which do require hardware access.
1446 *
1447 * Typcally done at later stages of submission mode specific engine setup.
1448 *
1449 * Returns zero on success or an error code on failure.
1450 */
1451static int engine_init_common(struct intel_engine_cs *engine)
1452{
1453 struct intel_context *ce, *bce = NULL;
1454 int ret;
1455
1456 engine->set_default_submission(engine);
1457
1458 /*
1459 * We may need to do things with the shrinker which
1460 * require us to immediately switch back to the default
1461 * context. This can cause a problem as pinning the
1462 * default context also requires GTT space which may not
1463 * be available. To avoid this we always pin the default
1464 * context.
1465 */
1466 ce = create_kernel_context(engine);
1467 if (IS_ERR(ce))
1468 return PTR_ERR(ce);
1469 /*
1470 * Create a separate pinned context for GGTT update with blitter engine
1471 * if a platform require such service. MI_UPDATE_GTT works on other
1472 * engines as well but BCS should be less busy engine so pick that for
1473 * GGTT updates.
1474 */
1475 if (i915_ggtt_require_binder(engine->i915) && engine->id == BCS0) {
1476 bce = create_ggtt_bind_context(engine);
1477 if (IS_ERR(bce)) {
1478 ret = PTR_ERR(bce);
1479 goto err_ce_context;
1480 }
1481 }
1482
1483 ret = measure_breadcrumb_dw(ce);
1484 if (ret < 0)
1485 goto err_bce_context;
1486
1487 engine->emit_fini_breadcrumb_dw = ret;
1488 engine->kernel_context = ce;
1489 engine->bind_context = bce;
1490
1491 return 0;
1492
1493err_bce_context:
1494 if (bce)
1495 intel_engine_destroy_pinned_context(bce);
1496err_ce_context:
1497 intel_engine_destroy_pinned_context(ce);
1498 return ret;
1499}
1500
1501int intel_engines_init(struct intel_gt *gt)
1502{
1503 int (*setup)(struct intel_engine_cs *engine);
1504 struct intel_engine_cs *engine;
1505 enum intel_engine_id id;
1506 int err;
1507
1508 if (intel_uc_uses_guc_submission(>->uc)) {
1509 gt->submission_method = INTEL_SUBMISSION_GUC;
1510 setup = intel_guc_submission_setup;
1511 } else if (HAS_EXECLISTS(gt->i915)) {
1512 gt->submission_method = INTEL_SUBMISSION_ELSP;
1513 setup = intel_execlists_submission_setup;
1514 } else {
1515 gt->submission_method = INTEL_SUBMISSION_RING;
1516 setup = intel_ring_submission_setup;
1517 }
1518
1519 for_each_engine(engine, gt, id) {
1520 err = engine_setup_common(engine);
1521 if (err)
1522 return err;
1523
1524 err = setup(engine);
1525 if (err) {
1526 intel_engine_cleanup_common(engine);
1527 return err;
1528 }
1529
1530 /* The backend should now be responsible for cleanup */
1531 GEM_BUG_ON(engine->release == NULL);
1532
1533 err = engine_init_common(engine);
1534 if (err)
1535 return err;
1536
1537 intel_engine_add_user(engine);
1538 }
1539
1540 return 0;
1541}
1542
1543/**
1544 * intel_engine_cleanup_common - cleans up the engine state created by
1545 * the common initiailizers.
1546 * @engine: Engine to cleanup.
1547 *
1548 * This cleans up everything created by the common helpers.
1549 */
1550void intel_engine_cleanup_common(struct intel_engine_cs *engine)
1551{
1552 GEM_BUG_ON(!list_empty(&engine->sched_engine->requests));
1553
1554 i915_sched_engine_put(engine->sched_engine);
1555 intel_breadcrumbs_put(engine->breadcrumbs);
1556
1557 intel_engine_fini_retire(engine);
1558 intel_engine_cleanup_cmd_parser(engine);
1559
1560 if (engine->default_state)
1561 fput(engine->default_state);
1562
1563 if (engine->kernel_context)
1564 intel_engine_destroy_pinned_context(engine->kernel_context);
1565
1566 if (engine->bind_context)
1567 intel_engine_destroy_pinned_context(engine->bind_context);
1568
1569
1570 GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
1571 cleanup_status_page(engine);
1572
1573 intel_wa_list_free(&engine->ctx_wa_list);
1574 intel_wa_list_free(&engine->wa_list);
1575 intel_wa_list_free(&engine->whitelist);
1576}
1577
1578/**
1579 * intel_engine_resume - re-initializes the HW state of the engine
1580 * @engine: Engine to resume.
1581 *
1582 * Returns zero on success or an error code on failure.
1583 */
1584int intel_engine_resume(struct intel_engine_cs *engine)
1585{
1586 intel_engine_apply_workarounds(engine);
1587 intel_engine_apply_whitelist(engine);
1588
1589 return engine->resume(engine);
1590}
1591
1592u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
1593{
1594 struct drm_i915_private *i915 = engine->i915;
1595
1596 u64 acthd;
1597
1598 if (GRAPHICS_VER(i915) >= 8)
1599 acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW);
1600 else if (GRAPHICS_VER(i915) >= 4)
1601 acthd = ENGINE_READ(engine, RING_ACTHD);
1602 else
1603 acthd = ENGINE_READ(engine, ACTHD);
1604
1605 return acthd;
1606}
1607
1608u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)
1609{
1610 u64 bbaddr;
1611
1612 if (GRAPHICS_VER(engine->i915) >= 8)
1613 bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW);
1614 else
1615 bbaddr = ENGINE_READ(engine, RING_BBADDR);
1616
1617 return bbaddr;
1618}
1619
1620static unsigned long stop_timeout(const struct intel_engine_cs *engine)
1621{
1622 if (in_atomic() || irqs_disabled()) /* inside atomic preempt-reset? */
1623 return 0;
1624
1625 /*
1626 * If we are doing a normal GPU reset, we can take our time and allow
1627 * the engine to quiesce. We've stopped submission to the engine, and
1628 * if we wait long enough an innocent context should complete and
1629 * leave the engine idle. So they should not be caught unaware by
1630 * the forthcoming GPU reset (which usually follows the stop_cs)!
1631 */
1632 return READ_ONCE(engine->props.stop_timeout_ms);
1633}
1634
1635static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
1636 int fast_timeout_us,
1637 int slow_timeout_ms)
1638{
1639 struct intel_uncore *uncore = engine->uncore;
1640 const i915_reg_t mode = RING_MI_MODE(engine->mmio_base);
1641 int err;
1642
1643 intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
1644
1645 /*
1646 * Wa_22011802037: Prior to doing a reset, ensure CS is
1647 * stopped, set ring stop bit and prefetch disable bit to halt CS
1648 */
1649 if (intel_engine_reset_needs_wa_22011802037(engine->gt))
1650 intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
1651 _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
1652
1653 err = __intel_wait_for_register_fw(engine->uncore, mode,
1654 MODE_IDLE, MODE_IDLE,
1655 fast_timeout_us,
1656 slow_timeout_ms,
1657 NULL);
1658
1659 /* A final mmio read to let GPU writes be hopefully flushed to memory */
1660 intel_uncore_posting_read_fw(uncore, mode);
1661 return err;
1662}
1663
1664int intel_engine_stop_cs(struct intel_engine_cs *engine)
1665{
1666 int err = 0;
1667
1668 if (GRAPHICS_VER(engine->i915) < 3)
1669 return -ENODEV;
1670
1671 ENGINE_TRACE(engine, "\n");
1672 /*
1673 * TODO: Find out why occasionally stopping the CS times out. Seen
1674 * especially with gem_eio tests.
1675 *
1676 * Occasionally trying to stop the cs times out, but does not adversely
1677 * affect functionality. The timeout is set as a config parameter that
1678 * defaults to 100ms. In most cases the follow up operation is to wait
1679 * for pending MI_FORCE_WAKES. The assumption is that this timeout is
1680 * sufficient for any pending MI_FORCEWAKEs to complete. Once root
1681 * caused, the caller must check and handle the return from this
1682 * function.
1683 */
1684 if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) {
1685 ENGINE_TRACE(engine,
1686 "timed out on STOP_RING -> IDLE; HEAD:%04x, TAIL:%04x\n",
1687 ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR,
1688 ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR);
1689
1690 /*
1691 * Sometimes we observe that the idle flag is not
1692 * set even though the ring is empty. So double
1693 * check before giving up.
1694 */
1695 if ((ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) !=
1696 (ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR))
1697 err = -ETIMEDOUT;
1698 }
1699
1700 return err;
1701}
1702
1703void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine)
1704{
1705 ENGINE_TRACE(engine, "\n");
1706
1707 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
1708}
1709
1710static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine)
1711{
1712 static const i915_reg_t _reg[I915_NUM_ENGINES] = {
1713 [RCS0] = MSG_IDLE_CS,
1714 [BCS0] = MSG_IDLE_BCS,
1715 [VCS0] = MSG_IDLE_VCS0,
1716 [VCS1] = MSG_IDLE_VCS1,
1717 [VCS2] = MSG_IDLE_VCS2,
1718 [VCS3] = MSG_IDLE_VCS3,
1719 [VCS4] = MSG_IDLE_VCS4,
1720 [VCS5] = MSG_IDLE_VCS5,
1721 [VCS6] = MSG_IDLE_VCS6,
1722 [VCS7] = MSG_IDLE_VCS7,
1723 [VECS0] = MSG_IDLE_VECS0,
1724 [VECS1] = MSG_IDLE_VECS1,
1725 [VECS2] = MSG_IDLE_VECS2,
1726 [VECS3] = MSG_IDLE_VECS3,
1727 [CCS0] = MSG_IDLE_CS,
1728 [CCS1] = MSG_IDLE_CS,
1729 [CCS2] = MSG_IDLE_CS,
1730 [CCS3] = MSG_IDLE_CS,
1731 };
1732 u32 val;
1733
1734 if (!_reg[engine->id].reg)
1735 return 0;
1736
1737 val = intel_uncore_read(engine->uncore, _reg[engine->id]);
1738
1739 /* bits[29:25] & bits[13:9] >> shift */
1740 return (val & (val >> 16) & MSG_IDLE_FW_MASK) >> MSG_IDLE_FW_SHIFT;
1741}
1742
1743static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask)
1744{
1745 int ret;
1746
1747 /* Ensure GPM receives fw up/down after CS is stopped */
1748 udelay(1);
1749
1750 /* Wait for forcewake request to complete in GPM */
1751 ret = __intel_wait_for_register_fw(gt->uncore,
1752 GEN9_PWRGT_DOMAIN_STATUS,
1753 fw_mask, fw_mask, 5000, 0, NULL);
1754
1755 /* Ensure CS receives fw ack from GPM */
1756 udelay(1);
1757
1758 if (ret)
1759 GT_TRACE(gt, "Failed to complete pending forcewake %d\n", ret);
1760}
1761
1762/*
1763 * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any
1764 * pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The
1765 * pending status is indicated by bits[13:9] (masked by bits[29:25]) in the
1766 * MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we
1767 * are concerned only with the gt reset here, we use a logical OR of pending
1768 * forcewakeups from all reset domains and then wait for them to complete by
1769 * querying PWRGT_DOMAIN_STATUS.
1770 */
1771void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine)
1772{
1773 u32 fw_pending = __cs_pending_mi_force_wakes(engine);
1774
1775 if (fw_pending)
1776 __gpm_wait_for_fw_complete(engine->gt, fw_pending);
1777}
1778
1779/* NB: please notice the memset */
1780void intel_engine_get_instdone(const struct intel_engine_cs *engine,
1781 struct intel_instdone *instdone)
1782{
1783 struct drm_i915_private *i915 = engine->i915;
1784 struct intel_uncore *uncore = engine->uncore;
1785 u32 mmio_base = engine->mmio_base;
1786 int slice;
1787 int subslice;
1788 int iter;
1789
1790 memset(instdone, 0, sizeof(*instdone));
1791
1792 if (GRAPHICS_VER(i915) >= 8) {
1793 instdone->instdone =
1794 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1795
1796 if (engine->id != RCS0)
1797 return;
1798
1799 instdone->slice_common =
1800 intel_uncore_read(uncore, GEN7_SC_INSTDONE);
1801 if (GRAPHICS_VER(i915) >= 12) {
1802 instdone->slice_common_extra[0] =
1803 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA);
1804 instdone->slice_common_extra[1] =
1805 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA2);
1806 }
1807
1808 for_each_ss_steering(iter, engine->gt, slice, subslice) {
1809 instdone->sampler[slice][subslice] =
1810 intel_gt_mcr_read(engine->gt,
1811 GEN8_SAMPLER_INSTDONE,
1812 slice, subslice);
1813 instdone->row[slice][subslice] =
1814 intel_gt_mcr_read(engine->gt,
1815 GEN8_ROW_INSTDONE,
1816 slice, subslice);
1817 }
1818
1819 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
1820 for_each_ss_steering(iter, engine->gt, slice, subslice)
1821 instdone->geom_svg[slice][subslice] =
1822 intel_gt_mcr_read(engine->gt,
1823 XEHPG_INSTDONE_GEOM_SVG,
1824 slice, subslice);
1825 }
1826 } else if (GRAPHICS_VER(i915) >= 7) {
1827 instdone->instdone =
1828 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1829
1830 if (engine->id != RCS0)
1831 return;
1832
1833 instdone->slice_common =
1834 intel_uncore_read(uncore, GEN7_SC_INSTDONE);
1835 instdone->sampler[0][0] =
1836 intel_uncore_read(uncore, GEN7_SAMPLER_INSTDONE);
1837 instdone->row[0][0] =
1838 intel_uncore_read(uncore, GEN7_ROW_INSTDONE);
1839 } else if (GRAPHICS_VER(i915) >= 4) {
1840 instdone->instdone =
1841 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1842 if (engine->id == RCS0)
1843 /* HACK: Using the wrong struct member */
1844 instdone->slice_common =
1845 intel_uncore_read(uncore, GEN4_INSTDONE1);
1846 } else {
1847 instdone->instdone = intel_uncore_read(uncore, GEN2_INSTDONE);
1848 }
1849}
1850
1851static bool ring_is_idle(struct intel_engine_cs *engine)
1852{
1853 bool idle = true;
1854
1855 if (I915_SELFTEST_ONLY(!engine->mmio_base))
1856 return true;
1857
1858 if (!intel_engine_pm_get_if_awake(engine))
1859 return true;
1860
1861 /* First check that no commands are left in the ring */
1862 if ((ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) !=
1863 (ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR))
1864 idle = false;
1865
1866 /* No bit for gen2, so assume the CS parser is idle */
1867 if (GRAPHICS_VER(engine->i915) > 2 &&
1868 !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE))
1869 idle = false;
1870
1871 intel_engine_pm_put(engine);
1872
1873 return idle;
1874}
1875
1876void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync)
1877{
1878 struct tasklet_struct *t = &engine->sched_engine->tasklet;
1879
1880 if (!t->callback)
1881 return;
1882
1883 local_bh_disable();
1884 if (tasklet_trylock(t)) {
1885 /* Must wait for any GPU reset in progress. */
1886 if (__tasklet_is_enabled(t))
1887 t->callback(t);
1888 tasklet_unlock(t);
1889 }
1890 local_bh_enable();
1891
1892 /* Synchronise and wait for the tasklet on another CPU */
1893 if (sync)
1894 tasklet_unlock_wait(t);
1895}
1896
1897/**
1898 * intel_engine_is_idle() - Report if the engine has finished process all work
1899 * @engine: the intel_engine_cs
1900 *
1901 * Return true if there are no requests pending, nothing left to be submitted
1902 * to hardware, and that the engine is idle.
1903 */
1904bool intel_engine_is_idle(struct intel_engine_cs *engine)
1905{
1906 /* More white lies, if wedged, hw state is inconsistent */
1907 if (intel_gt_is_wedged(engine->gt))
1908 return true;
1909
1910 if (!intel_engine_pm_is_awake(engine))
1911 return true;
1912
1913 /* Waiting to drain ELSP? */
1914 intel_synchronize_hardirq(engine->i915);
1915 intel_engine_flush_submission(engine);
1916
1917 /* ELSP is empty, but there are ready requests? E.g. after reset */
1918 if (!i915_sched_engine_is_empty(engine->sched_engine))
1919 return false;
1920
1921 /* Ring stopped? */
1922 return ring_is_idle(engine);
1923}
1924
1925bool intel_engines_are_idle(struct intel_gt *gt)
1926{
1927 struct intel_engine_cs *engine;
1928 enum intel_engine_id id;
1929
1930 /*
1931 * If the driver is wedged, HW state may be very inconsistent and
1932 * report that it is still busy, even though we have stopped using it.
1933 */
1934 if (intel_gt_is_wedged(gt))
1935 return true;
1936
1937 /* Already parked (and passed an idleness test); must still be idle */
1938 if (!READ_ONCE(gt->awake))
1939 return true;
1940
1941 for_each_engine(engine, gt, id) {
1942 if (!intel_engine_is_idle(engine))
1943 return false;
1944 }
1945
1946 return true;
1947}
1948
1949bool intel_engine_irq_enable(struct intel_engine_cs *engine)
1950{
1951 if (!engine->irq_enable)
1952 return false;
1953
1954 /* Caller disables interrupts */
1955 spin_lock(engine->gt->irq_lock);
1956 engine->irq_enable(engine);
1957 spin_unlock(engine->gt->irq_lock);
1958
1959 return true;
1960}
1961
1962void intel_engine_irq_disable(struct intel_engine_cs *engine)
1963{
1964 if (!engine->irq_disable)
1965 return;
1966
1967 /* Caller disables interrupts */
1968 spin_lock(engine->gt->irq_lock);
1969 engine->irq_disable(engine);
1970 spin_unlock(engine->gt->irq_lock);
1971}
1972
1973void intel_engines_reset_default_submission(struct intel_gt *gt)
1974{
1975 struct intel_engine_cs *engine;
1976 enum intel_engine_id id;
1977
1978 for_each_engine(engine, gt, id) {
1979 if (engine->sanitize)
1980 engine->sanitize(engine);
1981
1982 engine->set_default_submission(engine);
1983 }
1984}
1985
1986bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
1987{
1988 switch (GRAPHICS_VER(engine->i915)) {
1989 case 2:
1990 return false; /* uses physical not virtual addresses */
1991 case 3:
1992 /* maybe only uses physical not virtual addresses */
1993 return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915));
1994 case 4:
1995 return !IS_I965G(engine->i915); /* who knows! */
1996 case 6:
1997 return engine->class != VIDEO_DECODE_CLASS; /* b0rked */
1998 default:
1999 return true;
2000 }
2001}
2002
2003static struct intel_timeline *get_timeline(struct i915_request *rq)
2004{
2005 struct intel_timeline *tl;
2006
2007 /*
2008 * Even though we are holding the engine->sched_engine->lock here, there
2009 * is no control over the submission queue per-se and we are
2010 * inspecting the active state at a random point in time, with an
2011 * unknown queue. Play safe and make sure the timeline remains valid.
2012 * (Only being used for pretty printing, one extra kref shouldn't
2013 * cause a camel stampede!)
2014 */
2015 rcu_read_lock();
2016 tl = rcu_dereference(rq->timeline);
2017 if (!kref_get_unless_zero(&tl->kref))
2018 tl = NULL;
2019 rcu_read_unlock();
2020
2021 return tl;
2022}
2023
2024static int print_ring(char *buf, int sz, struct i915_request *rq)
2025{
2026 int len = 0;
2027
2028 if (!i915_request_signaled(rq)) {
2029 struct intel_timeline *tl = get_timeline(rq);
2030
2031 len = scnprintf(buf, sz,
2032 "ring:{start:%08x, hwsp:%08x, seqno:%08x, runtime:%llums}, ",
2033 i915_ggtt_offset(rq->ring->vma),
2034 tl ? tl->hwsp_offset : 0,
2035 hwsp_seqno(rq),
2036 DIV_ROUND_CLOSEST_ULL(intel_context_get_total_runtime_ns(rq->context),
2037 1000 * 1000));
2038
2039 if (tl)
2040 intel_timeline_put(tl);
2041 }
2042
2043 return len;
2044}
2045
2046static void hexdump(struct drm_printer *m, const void *buf, size_t len)
2047{
2048 const size_t rowsize = 8 * sizeof(u32);
2049 const void *prev = NULL;
2050 bool skip = false;
2051 size_t pos;
2052
2053 for (pos = 0; pos < len; pos += rowsize) {
2054 char line[128];
2055
2056 if (prev && !memcmp(prev, buf + pos, rowsize)) {
2057 if (!skip) {
2058 drm_printf(m, "*\n");
2059 skip = true;
2060 }
2061 continue;
2062 }
2063
2064 WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos,
2065 rowsize, sizeof(u32),
2066 line, sizeof(line),
2067 false) >= sizeof(line));
2068 drm_printf(m, "[%04zx] %s\n", pos, line);
2069
2070 prev = buf + pos;
2071 skip = false;
2072 }
2073}
2074
2075static const char *repr_timer(const struct timer_list *t)
2076{
2077 if (!READ_ONCE(t->expires))
2078 return "inactive";
2079
2080 if (timer_pending(t))
2081 return "active";
2082
2083 return "expired";
2084}
2085
2086static void intel_engine_print_registers(struct intel_engine_cs *engine,
2087 struct drm_printer *m)
2088{
2089 struct drm_i915_private *i915 = engine->i915;
2090 struct intel_engine_execlists * const execlists = &engine->execlists;
2091 u64 addr;
2092
2093 if (engine->id == RENDER_CLASS && IS_GRAPHICS_VER(i915, 4, 7))
2094 drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
2095 if (HAS_EXECLISTS(i915)) {
2096 drm_printf(m, "\tEL_STAT_HI: 0x%08x\n",
2097 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI));
2098 drm_printf(m, "\tEL_STAT_LO: 0x%08x\n",
2099 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO));
2100 }
2101 drm_printf(m, "\tRING_START: 0x%08x\n",
2102 ENGINE_READ(engine, RING_START));
2103 drm_printf(m, "\tRING_HEAD: 0x%08x\n",
2104 ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR);
2105 drm_printf(m, "\tRING_TAIL: 0x%08x\n",
2106 ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR);
2107 drm_printf(m, "\tRING_CTL: 0x%08x%s\n",
2108 ENGINE_READ(engine, RING_CTL),
2109 ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
2110 if (GRAPHICS_VER(engine->i915) > 2) {
2111 drm_printf(m, "\tRING_MODE: 0x%08x%s\n",
2112 ENGINE_READ(engine, RING_MI_MODE),
2113 ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : "");
2114 }
2115
2116 if (GRAPHICS_VER(i915) >= 6) {
2117 drm_printf(m, "\tRING_IMR: 0x%08x\n",
2118 ENGINE_READ(engine, RING_IMR));
2119 drm_printf(m, "\tRING_ESR: 0x%08x\n",
2120 ENGINE_READ(engine, RING_ESR));
2121 drm_printf(m, "\tRING_EMR: 0x%08x\n",
2122 ENGINE_READ(engine, RING_EMR));
2123 drm_printf(m, "\tRING_EIR: 0x%08x\n",
2124 ENGINE_READ(engine, RING_EIR));
2125 }
2126
2127 addr = intel_engine_get_active_head(engine);
2128 drm_printf(m, "\tACTHD: 0x%08x_%08x\n",
2129 upper_32_bits(addr), lower_32_bits(addr));
2130 addr = intel_engine_get_last_batch_head(engine);
2131 drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
2132 upper_32_bits(addr), lower_32_bits(addr));
2133 if (GRAPHICS_VER(i915) >= 8)
2134 addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW);
2135 else if (GRAPHICS_VER(i915) >= 4)
2136 addr = ENGINE_READ(engine, RING_DMA_FADD);
2137 else
2138 addr = ENGINE_READ(engine, DMA_FADD_I8XX);
2139 drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
2140 upper_32_bits(addr), lower_32_bits(addr));
2141 if (GRAPHICS_VER(i915) >= 4) {
2142 drm_printf(m, "\tIPEIR: 0x%08x\n",
2143 ENGINE_READ(engine, RING_IPEIR));
2144 drm_printf(m, "\tIPEHR: 0x%08x\n",
2145 ENGINE_READ(engine, RING_IPEHR));
2146 } else {
2147 drm_printf(m, "\tIPEIR: 0x%08x\n", ENGINE_READ(engine, IPEIR));
2148 drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR));
2149 }
2150
2151 if (HAS_EXECLISTS(i915) && !intel_engine_uses_guc(engine)) {
2152 struct i915_request * const *port, *rq;
2153 const u32 *hws =
2154 &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
2155 const u8 num_entries = execlists->csb_size;
2156 unsigned int idx;
2157 u8 read, write;
2158
2159 drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? %s, timeslice? %s\n",
2160 str_yes_no(test_bit(TASKLET_STATE_SCHED, &engine->sched_engine->tasklet.state)),
2161 str_enabled_disabled(!atomic_read(&engine->sched_engine->tasklet.count)),
2162 repr_timer(&engine->execlists.preempt),
2163 repr_timer(&engine->execlists.timer));
2164
2165 read = execlists->csb_head;
2166 write = READ_ONCE(*execlists->csb_write);
2167
2168 drm_printf(m, "\tExeclist status: 0x%08x %08x; CSB read:%d, write:%d, entries:%d\n",
2169 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO),
2170 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI),
2171 read, write, num_entries);
2172
2173 if (read >= num_entries)
2174 read = 0;
2175 if (write >= num_entries)
2176 write = 0;
2177 if (read > write)
2178 write += num_entries;
2179 while (read < write) {
2180 idx = ++read % num_entries;
2181 drm_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
2182 idx, hws[idx * 2], hws[idx * 2 + 1]);
2183 }
2184
2185 i915_sched_engine_active_lock_bh(engine->sched_engine);
2186 rcu_read_lock();
2187 for (port = execlists->active; (rq = *port); port++) {
2188 char hdr[160];
2189 int len;
2190
2191 len = scnprintf(hdr, sizeof(hdr),
2192 "\t\tActive[%d]: ccid:%08x%s%s, ",
2193 (int)(port - execlists->active),
2194 rq->context->lrc.ccid,
2195 intel_context_is_closed(rq->context) ? "!" : "",
2196 intel_context_is_banned(rq->context) ? "*" : "");
2197 len += print_ring(hdr + len, sizeof(hdr) - len, rq);
2198 scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
2199 i915_request_show(m, rq, hdr, 0);
2200 }
2201 for (port = execlists->pending; (rq = *port); port++) {
2202 char hdr[160];
2203 int len;
2204
2205 len = scnprintf(hdr, sizeof(hdr),
2206 "\t\tPending[%d]: ccid:%08x%s%s, ",
2207 (int)(port - execlists->pending),
2208 rq->context->lrc.ccid,
2209 intel_context_is_closed(rq->context) ? "!" : "",
2210 intel_context_is_banned(rq->context) ? "*" : "");
2211 len += print_ring(hdr + len, sizeof(hdr) - len, rq);
2212 scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
2213 i915_request_show(m, rq, hdr, 0);
2214 }
2215 rcu_read_unlock();
2216 i915_sched_engine_active_unlock_bh(engine->sched_engine);
2217 } else if (GRAPHICS_VER(i915) > 6) {
2218 drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
2219 ENGINE_READ(engine, RING_PP_DIR_BASE));
2220 drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
2221 ENGINE_READ(engine, RING_PP_DIR_BASE_READ));
2222 drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
2223 ENGINE_READ(engine, RING_PP_DIR_DCLV));
2224 }
2225}
2226
2227static void print_request_ring(struct drm_printer *m, struct i915_request *rq)
2228{
2229 struct i915_vma_resource *vma_res = rq->batch_res;
2230 void *ring;
2231 int size;
2232
2233 drm_printf(m,
2234 "[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]:\n",
2235 rq->head, rq->postfix, rq->tail,
2236 vma_res ? upper_32_bits(vma_res->start) : ~0u,
2237 vma_res ? lower_32_bits(vma_res->start) : ~0u);
2238
2239 size = rq->tail - rq->head;
2240 if (rq->tail < rq->head)
2241 size += rq->ring->size;
2242
2243 ring = kmalloc(size, GFP_ATOMIC);
2244 if (ring) {
2245 const void *vaddr = rq->ring->vaddr;
2246 unsigned int head = rq->head;
2247 unsigned int len = 0;
2248
2249 if (rq->tail < head) {
2250 len = rq->ring->size - head;
2251 memcpy(ring, vaddr + head, len);
2252 head = 0;
2253 }
2254 memcpy(ring + len, vaddr + head, size - len);
2255
2256 hexdump(m, ring, size);
2257 kfree(ring);
2258 }
2259}
2260
2261static unsigned long read_ul(void *p, size_t x)
2262{
2263 return *(unsigned long *)(p + x);
2264}
2265
2266static void print_properties(struct intel_engine_cs *engine,
2267 struct drm_printer *m)
2268{
2269 static const struct pmap {
2270 size_t offset;
2271 const char *name;
2272 } props[] = {
2273#define P(x) { \
2274 .offset = offsetof(typeof(engine->props), x), \
2275 .name = #x \
2276}
2277 P(heartbeat_interval_ms),
2278 P(max_busywait_duration_ns),
2279 P(preempt_timeout_ms),
2280 P(stop_timeout_ms),
2281 P(timeslice_duration_ms),
2282
2283 {},
2284#undef P
2285 };
2286 const struct pmap *p;
2287
2288 drm_printf(m, "\tProperties:\n");
2289 for (p = props; p->name; p++)
2290 drm_printf(m, "\t\t%s: %lu [default %lu]\n",
2291 p->name,
2292 read_ul(&engine->props, p->offset),
2293 read_ul(&engine->defaults, p->offset));
2294}
2295
2296static void engine_dump_request(struct i915_request *rq, struct drm_printer *m, const char *msg)
2297{
2298 struct intel_timeline *tl = get_timeline(rq);
2299
2300 i915_request_show(m, rq, msg, 0);
2301
2302 drm_printf(m, "\t\tring->start: 0x%08x\n",
2303 i915_ggtt_offset(rq->ring->vma));
2304 drm_printf(m, "\t\tring->head: 0x%08x\n",
2305 rq->ring->head);
2306 drm_printf(m, "\t\tring->tail: 0x%08x\n",
2307 rq->ring->tail);
2308 drm_printf(m, "\t\tring->emit: 0x%08x\n",
2309 rq->ring->emit);
2310 drm_printf(m, "\t\tring->space: 0x%08x\n",
2311 rq->ring->space);
2312
2313 if (tl) {
2314 drm_printf(m, "\t\tring->hwsp: 0x%08x\n",
2315 tl->hwsp_offset);
2316 intel_timeline_put(tl);
2317 }
2318
2319 print_request_ring(m, rq);
2320
2321 if (rq->context->lrc_reg_state) {
2322 drm_printf(m, "Logical Ring Context:\n");
2323 hexdump(m, rq->context->lrc_reg_state, PAGE_SIZE);
2324 }
2325}
2326
2327void intel_engine_dump_active_requests(struct list_head *requests,
2328 struct i915_request *hung_rq,
2329 struct drm_printer *m)
2330{
2331 struct i915_request *rq;
2332 const char *msg;
2333 enum i915_request_state state;
2334
2335 list_for_each_entry(rq, requests, sched.link) {
2336 if (rq == hung_rq)
2337 continue;
2338
2339 state = i915_test_request_state(rq);
2340 if (state < I915_REQUEST_QUEUED)
2341 continue;
2342
2343 if (state == I915_REQUEST_ACTIVE)
2344 msg = "\t\tactive on engine";
2345 else
2346 msg = "\t\tactive in queue";
2347
2348 engine_dump_request(rq, m, msg);
2349 }
2350}
2351
2352static void engine_dump_active_requests(struct intel_engine_cs *engine,
2353 struct drm_printer *m)
2354{
2355 struct intel_context *hung_ce = NULL;
2356 struct i915_request *hung_rq = NULL;
2357
2358 /*
2359 * No need for an engine->irq_seqno_barrier() before the seqno reads.
2360 * The GPU is still running so requests are still executing and any
2361 * hardware reads will be out of date by the time they are reported.
2362 * But the intention here is just to report an instantaneous snapshot
2363 * so that's fine.
2364 */
2365 intel_engine_get_hung_entity(engine, &hung_ce, &hung_rq);
2366
2367 drm_printf(m, "\tRequests:\n");
2368
2369 if (hung_rq)
2370 engine_dump_request(hung_rq, m, "\t\thung");
2371 else if (hung_ce)
2372 drm_printf(m, "\t\tGot hung ce but no hung rq!\n");
2373
2374 if (intel_uc_uses_guc_submission(&engine->gt->uc))
2375 intel_guc_dump_active_requests(engine, hung_rq, m);
2376 else
2377 intel_execlists_dump_active_requests(engine, hung_rq, m);
2378
2379 if (hung_rq)
2380 i915_request_put(hung_rq);
2381}
2382
2383void intel_engine_dump(struct intel_engine_cs *engine,
2384 struct drm_printer *m,
2385 const char *header, ...)
2386{
2387 struct i915_gpu_error * const error = &engine->i915->gpu_error;
2388 struct i915_request *rq;
2389 intel_wakeref_t wakeref;
2390 ktime_t dummy;
2391
2392 if (header) {
2393 va_list ap;
2394
2395 va_start(ap, header);
2396 drm_vprintf(m, header, &ap);
2397 va_end(ap);
2398 }
2399
2400 if (intel_gt_is_wedged(engine->gt))
2401 drm_printf(m, "*** WEDGED ***\n");
2402
2403 drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count));
2404 drm_printf(m, "\tBarriers?: %s\n",
2405 str_yes_no(!llist_empty(&engine->barrier_tasks)));
2406 drm_printf(m, "\tLatency: %luus\n",
2407 ewma__engine_latency_read(&engine->latency));
2408 if (intel_engine_supports_stats(engine))
2409 drm_printf(m, "\tRuntime: %llums\n",
2410 ktime_to_ms(intel_engine_get_busy_time(engine,
2411 &dummy)));
2412 drm_printf(m, "\tForcewake: %x domains, %d active\n",
2413 engine->fw_domain, READ_ONCE(engine->fw_active));
2414
2415 rcu_read_lock();
2416 rq = READ_ONCE(engine->heartbeat.systole);
2417 if (rq)
2418 drm_printf(m, "\tHeartbeat: %d ms ago\n",
2419 jiffies_to_msecs(jiffies - rq->emitted_jiffies));
2420 rcu_read_unlock();
2421 drm_printf(m, "\tReset count: %d (global %d)\n",
2422 i915_reset_engine_count(error, engine),
2423 i915_reset_count(error));
2424 print_properties(engine, m);
2425
2426 engine_dump_active_requests(engine, m);
2427
2428 drm_printf(m, "\tMMIO base: 0x%08x\n", engine->mmio_base);
2429 wakeref = intel_runtime_pm_get_if_in_use(engine->uncore->rpm);
2430 if (wakeref) {
2431 intel_engine_print_registers(engine, m);
2432 intel_runtime_pm_put(engine->uncore->rpm, wakeref);
2433 } else {
2434 drm_printf(m, "\tDevice is asleep; skipping register dump\n");
2435 }
2436
2437 intel_execlists_show_requests(engine, m, i915_request_show, 8);
2438
2439 drm_printf(m, "HWSP:\n");
2440 hexdump(m, engine->status_page.addr, PAGE_SIZE);
2441
2442 drm_printf(m, "Idle? %s\n", str_yes_no(intel_engine_is_idle(engine)));
2443
2444 intel_engine_print_breadcrumbs(engine, m);
2445}
2446
2447/**
2448 * intel_engine_get_busy_time() - Return current accumulated engine busyness
2449 * @engine: engine to report on
2450 * @now: monotonic timestamp of sampling
2451 *
2452 * Returns accumulated time @engine was busy since engine stats were enabled.
2453 */
2454ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now)
2455{
2456 return engine->busyness(engine, now);
2457}
2458
2459struct intel_context *
2460intel_engine_create_virtual(struct intel_engine_cs **siblings,
2461 unsigned int count, unsigned long flags)
2462{
2463 if (count == 0)
2464 return ERR_PTR(-EINVAL);
2465
2466 if (count == 1 && !(flags & FORCE_VIRTUAL))
2467 return intel_context_create(siblings[0]);
2468
2469 GEM_BUG_ON(!siblings[0]->cops->create_virtual);
2470 return siblings[0]->cops->create_virtual(siblings, count, flags);
2471}
2472
2473static struct i915_request *engine_execlist_find_hung_request(struct intel_engine_cs *engine)
2474{
2475 struct i915_request *request, *active = NULL;
2476
2477 /*
2478 * This search does not work in GuC submission mode. However, the GuC
2479 * will report the hanging context directly to the driver itself. So
2480 * the driver should never get here when in GuC mode.
2481 */
2482 GEM_BUG_ON(intel_uc_uses_guc_submission(&engine->gt->uc));
2483
2484 /*
2485 * We are called by the error capture, reset and to dump engine
2486 * state at random points in time. In particular, note that neither is
2487 * crucially ordered with an interrupt. After a hang, the GPU is dead
2488 * and we assume that no more writes can happen (we waited long enough
2489 * for all writes that were in transaction to be flushed) - adding an
2490 * extra delay for a recent interrupt is pointless. Hence, we do
2491 * not need an engine->irq_seqno_barrier() before the seqno reads.
2492 * At all other times, we must assume the GPU is still running, but
2493 * we only care about the snapshot of this moment.
2494 */
2495 lockdep_assert_held(&engine->sched_engine->lock);
2496
2497 rcu_read_lock();
2498 request = execlists_active(&engine->execlists);
2499 if (request) {
2500 struct intel_timeline *tl = request->context->timeline;
2501
2502 list_for_each_entry_from_reverse(request, &tl->requests, link) {
2503 if (__i915_request_is_complete(request))
2504 break;
2505
2506 active = request;
2507 }
2508 }
2509 rcu_read_unlock();
2510 if (active)
2511 return active;
2512
2513 list_for_each_entry(request, &engine->sched_engine->requests,
2514 sched.link) {
2515 if (i915_test_request_state(request) != I915_REQUEST_ACTIVE)
2516 continue;
2517
2518 active = request;
2519 break;
2520 }
2521
2522 return active;
2523}
2524
2525void intel_engine_get_hung_entity(struct intel_engine_cs *engine,
2526 struct intel_context **ce, struct i915_request **rq)
2527{
2528 unsigned long flags;
2529
2530 *ce = intel_engine_get_hung_context(engine);
2531 if (*ce) {
2532 intel_engine_clear_hung_context(engine);
2533
2534 *rq = intel_context_get_active_request(*ce);
2535 return;
2536 }
2537
2538 /*
2539 * Getting here with GuC enabled means it is a forced error capture
2540 * with no actual hang. So, no need to attempt the execlist search.
2541 */
2542 if (intel_uc_uses_guc_submission(&engine->gt->uc))
2543 return;
2544
2545 spin_lock_irqsave(&engine->sched_engine->lock, flags);
2546 *rq = engine_execlist_find_hung_request(engine);
2547 if (*rq)
2548 *rq = i915_request_get_rcu(*rq);
2549 spin_unlock_irqrestore(&engine->sched_engine->lock, flags);
2550}
2551
2552void xehp_enable_ccs_engines(struct intel_engine_cs *engine)
2553{
2554 /*
2555 * If there are any non-fused-off CCS engines, we need to enable CCS
2556 * support in the RCU_MODE register. This only needs to be done once,
2557 * so for simplicity we'll take care of this in the RCS engine's
2558 * resume handler; since the RCS and all CCS engines belong to the
2559 * same reset domain and are reset together, this will also take care
2560 * of re-applying the setting after i915-triggered resets.
2561 */
2562 if (!CCS_MASK(engine->gt))
2563 return;
2564
2565 intel_uncore_write(engine->uncore, GEN12_RCU_MODE,
2566 _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));
2567}
2568
2569#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2570#include "mock_engine.c"
2571#include "selftest_engine.c"
2572#include "selftest_engine_cs.c"
2573#endif