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1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2019 Intel Corporation
4 */
5
6#ifndef __INTEL_DP_H__
7#define __INTEL_DP_H__
8
9#include <linux/types.h>
10
11#include <drm/i915_drm.h>
12
13#include "i915_reg.h"
14
15enum pipe;
16struct drm_connector_state;
17struct drm_encoder;
18struct drm_i915_private;
19struct drm_modeset_acquire_ctx;
20struct intel_connector;
21struct intel_crtc_state;
22struct intel_digital_port;
23struct intel_dp;
24struct intel_encoder;
25
26struct link_config_limits {
27 int min_clock, max_clock;
28 int min_lane_count, max_lane_count;
29 int min_bpp, max_bpp;
30};
31
32void intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
33 struct intel_crtc_state *pipe_config,
34 struct link_config_limits *limits);
35bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
36 const struct drm_connector_state *conn_state);
37int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state);
38bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
39 i915_reg_t dp_reg, enum port port,
40 enum pipe *pipe);
41bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
42 enum port port);
43bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
44 struct intel_connector *intel_connector);
45void intel_dp_set_link_params(struct intel_dp *intel_dp,
46 int link_rate, u8 lane_count,
47 bool link_mst);
48int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
49 int link_rate, u8 lane_count);
50int intel_dp_retrain_link(struct intel_encoder *encoder,
51 struct drm_modeset_acquire_ctx *ctx);
52void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
53void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
54 const struct intel_crtc_state *crtc_state,
55 bool enable);
56void intel_dp_encoder_reset(struct drm_encoder *encoder);
57void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
58void intel_dp_encoder_flush_work(struct drm_encoder *encoder);
59int intel_dp_compute_config(struct intel_encoder *encoder,
60 struct intel_crtc_state *pipe_config,
61 struct drm_connector_state *conn_state);
62bool intel_dp_is_edp(struct intel_dp *intel_dp);
63bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
64enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
65 bool long_hpd);
66void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
67 const struct drm_connector_state *conn_state);
68void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
69void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
70void intel_edp_panel_on(struct intel_dp *intel_dp);
71void intel_edp_panel_off(struct intel_dp *intel_dp);
72void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
73void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
74int intel_dp_max_link_rate(struct intel_dp *intel_dp);
75int intel_dp_max_lane_count(struct intel_dp *intel_dp);
76int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
77void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
78u32 intel_dp_pack_aux(const u8 *src, int src_bytes);
79
80void intel_edp_drrs_enable(struct intel_dp *intel_dp,
81 const struct intel_crtc_state *crtc_state);
82void intel_edp_drrs_disable(struct intel_dp *intel_dp,
83 const struct intel_crtc_state *crtc_state);
84void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
85 unsigned int frontbuffer_bits);
86void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
87 unsigned int frontbuffer_bits);
88
89void
90intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
91 u8 dp_train_pat);
92void
93intel_dp_set_signal_levels(struct intel_dp *intel_dp);
94void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
95u8
96intel_dp_voltage_max(struct intel_dp *intel_dp);
97u8
98intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing);
99void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
100 u8 *link_bw, u8 *rate_select);
101bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
102bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
103bool
104intel_dp_get_link_status(struct intel_dp *intel_dp, u8 *link_status);
105
106bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
107bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp);
108int intel_dp_link_required(int pixel_clock, int bpp);
109int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
110bool intel_digital_port_connected(struct intel_encoder *encoder);
111
112static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
113{
114 return ~((1 << lane_count) - 1) & 0xf;
115}
116
117u32 intel_dp_mode_to_fec_clock(u32 mode_clock);
118
119#endif /* __INTEL_DP_H__ */
1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2019 Intel Corporation
4 */
5
6#ifndef __INTEL_DP_H__
7#define __INTEL_DP_H__
8
9#include <linux/types.h>
10
11enum intel_output_format;
12enum pipe;
13enum port;
14struct drm_connector_state;
15struct drm_encoder;
16struct drm_i915_private;
17struct drm_modeset_acquire_ctx;
18struct drm_dp_vsc_sdp;
19struct intel_atomic_state;
20struct intel_connector;
21struct intel_crtc_state;
22struct intel_digital_port;
23struct intel_dp;
24struct intel_encoder;
25
26struct link_config_limits {
27 int min_rate, max_rate;
28 int min_lane_count, max_lane_count;
29 struct {
30 /* Uncompressed DSC input or link output bpp in 1 bpp units */
31 int min_bpp, max_bpp;
32 } pipe;
33 struct {
34 /* Compressed or uncompressed link output bpp in 1/16 bpp units */
35 int min_bpp_x16, max_bpp_x16;
36 } link;
37};
38
39void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
40void intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
41 struct intel_crtc_state *pipe_config,
42 struct link_config_limits *limits);
43bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
44 const struct drm_connector_state *conn_state);
45int intel_dp_min_bpp(enum intel_output_format output_format);
46bool intel_dp_init_connector(struct intel_digital_port *dig_port,
47 struct intel_connector *intel_connector);
48void intel_dp_connector_sync_state(struct intel_connector *connector,
49 const struct intel_crtc_state *crtc_state);
50void intel_dp_set_link_params(struct intel_dp *intel_dp,
51 int link_rate, int lane_count);
52int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
53 int link_rate, u8 lane_count);
54int intel_dp_get_active_pipes(struct intel_dp *intel_dp,
55 struct drm_modeset_acquire_ctx *ctx,
56 u8 *pipe_mask);
57int intel_dp_retrain_link(struct intel_encoder *encoder,
58 struct drm_modeset_acquire_ctx *ctx);
59void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode);
60void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
61 const struct intel_crtc_state *crtc_state);
62void intel_dp_sink_enable_decompression(struct intel_atomic_state *state,
63 struct intel_connector *connector,
64 const struct intel_crtc_state *new_crtc_state);
65void intel_dp_sink_disable_decompression(struct intel_atomic_state *state,
66 struct intel_connector *connector,
67 const struct intel_crtc_state *old_crtc_state);
68void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
69void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder);
70void intel_dp_encoder_flush_work(struct drm_encoder *encoder);
71int intel_dp_compute_config(struct intel_encoder *encoder,
72 struct intel_crtc_state *pipe_config,
73 struct drm_connector_state *conn_state);
74int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
75 struct intel_crtc_state *pipe_config,
76 struct drm_connector_state *conn_state,
77 struct link_config_limits *limits,
78 int timeslots,
79 bool recompute_pipe_bpp);
80void intel_dp_audio_compute_config(struct intel_encoder *encoder,
81 struct intel_crtc_state *pipe_config,
82 struct drm_connector_state *conn_state);
83bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp);
84bool intel_dp_is_edp(struct intel_dp *intel_dp);
85bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);
86int intel_dp_link_symbol_size(int rate);
87int intel_dp_link_symbol_clock(int rate);
88bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
89enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port,
90 bool long_hpd);
91void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
92 const struct drm_connector_state *conn_state);
93void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
94void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
95void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
96void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
97int intel_dp_max_link_rate(struct intel_dp *intel_dp);
98int intel_dp_max_lane_count(struct intel_dp *intel_dp);
99int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
100
101void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
102 u8 *link_bw, u8 *rate_select);
103bool intel_dp_source_supports_tps3(struct drm_i915_private *i915);
104bool intel_dp_source_supports_tps4(struct drm_i915_private *i915);
105
106bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp);
107int intel_dp_link_required(int pixel_clock, int bpp);
108int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16,
109 int bw_overhead);
110int intel_dp_max_data_rate(int max_link_rate, int max_lanes);
111bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp);
112bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
113 const struct drm_connector_state *conn_state);
114void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
115 const struct intel_crtc_state *crtc_state,
116 const struct drm_connector_state *conn_state,
117 struct drm_dp_vsc_sdp *vsc);
118void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
119 const struct intel_crtc_state *crtc_state,
120 const struct drm_dp_vsc_sdp *vsc);
121void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
122 const struct intel_crtc_state *crtc_state,
123 const struct drm_connector_state *conn_state);
124void intel_read_dp_sdp(struct intel_encoder *encoder,
125 struct intel_crtc_state *crtc_state,
126 unsigned int type);
127bool intel_digital_port_connected(struct intel_encoder *encoder);
128int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
129 u8 dsc_max_bpc);
130u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
131 u32 link_clock, u32 lane_count,
132 u32 mode_clock, u32 mode_hdisplay,
133 bool bigjoiner,
134 enum intel_output_format output_format,
135 u32 pipe_bpp,
136 u32 timeslots);
137int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config);
138int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,
139 struct intel_crtc_state *pipe_config,
140 int bpc);
141u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
142 int mode_clock, int mode_hdisplay,
143 bool bigjoiner);
144bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
145 int hdisplay, int clock);
146
147static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
148{
149 return ~((1 << lane_count) - 1) & 0xf;
150}
151
152bool intel_dp_supports_fec(struct intel_dp *intel_dp,
153 const struct intel_connector *connector,
154 const struct intel_crtc_state *pipe_config);
155u32 intel_dp_mode_to_fec_clock(u32 mode_clock);
156int intel_dp_bw_fec_overhead(bool fec_enabled);
157
158bool intel_dp_supports_fec(struct intel_dp *intel_dp,
159 const struct intel_connector *connector,
160 const struct intel_crtc_state *pipe_config);
161
162u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp);
163
164void intel_ddi_update_pipe(struct intel_atomic_state *state,
165 struct intel_encoder *encoder,
166 const struct intel_crtc_state *crtc_state,
167 const struct drm_connector_state *conn_state);
168
169bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
170 struct intel_crtc_state *crtc_state);
171void intel_dp_sync_state(struct intel_encoder *encoder,
172 const struct intel_crtc_state *crtc_state);
173
174void intel_dp_check_frl_training(struct intel_dp *intel_dp);
175void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
176 const struct intel_crtc_state *crtc_state);
177void intel_dp_phy_test(struct intel_encoder *encoder);
178
179void intel_dp_wait_source_oui(struct intel_dp *intel_dp);
180int intel_dp_output_bpp(enum intel_output_format output_format, int bpp);
181
182bool
183intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
184 const struct intel_crtc_state *crtc_state,
185 bool dsc,
186 struct link_config_limits *limits);
187
188void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector);
189
190#endif /* __INTEL_DP_H__ */