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1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2019 Intel Corporation
4 */
5
6#ifndef __INTEL_DISPLAY_POWER_H__
7#define __INTEL_DISPLAY_POWER_H__
8
9#include "intel_display.h"
10#include "intel_runtime_pm.h"
11#include "i915_reg.h"
12
13struct drm_i915_private;
14struct intel_encoder;
15
16enum intel_display_power_domain {
17 POWER_DOMAIN_DISPLAY_CORE,
18 POWER_DOMAIN_PIPE_A,
19 POWER_DOMAIN_PIPE_B,
20 POWER_DOMAIN_PIPE_C,
21 POWER_DOMAIN_PIPE_D,
22 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
23 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
24 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
25 POWER_DOMAIN_PIPE_D_PANEL_FITTER,
26 POWER_DOMAIN_TRANSCODER_A,
27 POWER_DOMAIN_TRANSCODER_B,
28 POWER_DOMAIN_TRANSCODER_C,
29 POWER_DOMAIN_TRANSCODER_D,
30 POWER_DOMAIN_TRANSCODER_EDP,
31 /* VDSC/joining for TRANSCODER_EDP (ICL) or TRANSCODER_A (TGL) */
32 POWER_DOMAIN_TRANSCODER_VDSC_PW2,
33 POWER_DOMAIN_TRANSCODER_DSI_A,
34 POWER_DOMAIN_TRANSCODER_DSI_C,
35 POWER_DOMAIN_PORT_DDI_A_LANES,
36 POWER_DOMAIN_PORT_DDI_B_LANES,
37 POWER_DOMAIN_PORT_DDI_C_LANES,
38 POWER_DOMAIN_PORT_DDI_D_LANES,
39 POWER_DOMAIN_PORT_DDI_TC1_LANES = POWER_DOMAIN_PORT_DDI_D_LANES,
40 POWER_DOMAIN_PORT_DDI_E_LANES,
41 POWER_DOMAIN_PORT_DDI_TC2_LANES = POWER_DOMAIN_PORT_DDI_E_LANES,
42 POWER_DOMAIN_PORT_DDI_F_LANES,
43 POWER_DOMAIN_PORT_DDI_TC3_LANES = POWER_DOMAIN_PORT_DDI_F_LANES,
44 POWER_DOMAIN_PORT_DDI_TC4_LANES,
45 POWER_DOMAIN_PORT_DDI_TC5_LANES,
46 POWER_DOMAIN_PORT_DDI_TC6_LANES,
47 POWER_DOMAIN_PORT_DDI_A_IO,
48 POWER_DOMAIN_PORT_DDI_B_IO,
49 POWER_DOMAIN_PORT_DDI_C_IO,
50 POWER_DOMAIN_PORT_DDI_D_IO,
51 POWER_DOMAIN_PORT_DDI_TC1_IO = POWER_DOMAIN_PORT_DDI_D_IO,
52 POWER_DOMAIN_PORT_DDI_E_IO,
53 POWER_DOMAIN_PORT_DDI_TC2_IO = POWER_DOMAIN_PORT_DDI_E_IO,
54 POWER_DOMAIN_PORT_DDI_F_IO,
55 POWER_DOMAIN_PORT_DDI_TC3_IO = POWER_DOMAIN_PORT_DDI_F_IO,
56 POWER_DOMAIN_PORT_DDI_G_IO,
57 POWER_DOMAIN_PORT_DDI_TC4_IO = POWER_DOMAIN_PORT_DDI_G_IO,
58 POWER_DOMAIN_PORT_DDI_H_IO,
59 POWER_DOMAIN_PORT_DDI_TC5_IO = POWER_DOMAIN_PORT_DDI_H_IO,
60 POWER_DOMAIN_PORT_DDI_I_IO,
61 POWER_DOMAIN_PORT_DDI_TC6_IO = POWER_DOMAIN_PORT_DDI_I_IO,
62 POWER_DOMAIN_PORT_DSI,
63 POWER_DOMAIN_PORT_CRT,
64 POWER_DOMAIN_PORT_OTHER,
65 POWER_DOMAIN_VGA,
66 POWER_DOMAIN_AUDIO,
67 POWER_DOMAIN_AUX_A,
68 POWER_DOMAIN_AUX_B,
69 POWER_DOMAIN_AUX_C,
70 POWER_DOMAIN_AUX_D,
71 POWER_DOMAIN_AUX_TC1 = POWER_DOMAIN_AUX_D,
72 POWER_DOMAIN_AUX_E,
73 POWER_DOMAIN_AUX_TC2 = POWER_DOMAIN_AUX_E,
74 POWER_DOMAIN_AUX_F,
75 POWER_DOMAIN_AUX_TC3 = POWER_DOMAIN_AUX_F,
76 POWER_DOMAIN_AUX_TC4,
77 POWER_DOMAIN_AUX_TC5,
78 POWER_DOMAIN_AUX_TC6,
79 POWER_DOMAIN_AUX_IO_A,
80 POWER_DOMAIN_AUX_TBT1,
81 POWER_DOMAIN_AUX_TBT2,
82 POWER_DOMAIN_AUX_TBT3,
83 POWER_DOMAIN_AUX_TBT4,
84 POWER_DOMAIN_AUX_TBT5,
85 POWER_DOMAIN_AUX_TBT6,
86 POWER_DOMAIN_GMBUS,
87 POWER_DOMAIN_MODESET,
88 POWER_DOMAIN_GT_IRQ,
89 POWER_DOMAIN_DPLL_DC_OFF,
90 POWER_DOMAIN_INIT,
91
92 POWER_DOMAIN_NUM,
93};
94
95/*
96 * i915_power_well_id:
97 *
98 * IDs used to look up power wells. Power wells accessed directly bypassing
99 * the power domains framework must be assigned a unique ID. The rest of power
100 * wells must be assigned DISP_PW_ID_NONE.
101 */
102enum i915_power_well_id {
103 DISP_PW_ID_NONE,
104
105 VLV_DISP_PW_DISP2D,
106 BXT_DISP_PW_DPIO_CMN_A,
107 VLV_DISP_PW_DPIO_CMN_BC,
108 GLK_DISP_PW_DPIO_CMN_C,
109 CHV_DISP_PW_DPIO_CMN_D,
110 HSW_DISP_PW_GLOBAL,
111 SKL_DISP_PW_MISC_IO,
112 SKL_DISP_PW_1,
113 SKL_DISP_PW_2,
114};
115
116#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
117#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
118 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
119#define POWER_DOMAIN_TRANSCODER(tran) \
120 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
121 (tran) + POWER_DOMAIN_TRANSCODER_A)
122
123struct i915_power_well;
124
125struct i915_power_well_ops {
126 /*
127 * Synchronize the well's hw state to match the current sw state, for
128 * example enable/disable it based on the current refcount. Called
129 * during driver init and resume time, possibly after first calling
130 * the enable/disable handlers.
131 */
132 void (*sync_hw)(struct drm_i915_private *dev_priv,
133 struct i915_power_well *power_well);
134 /*
135 * Enable the well and resources that depend on it (for example
136 * interrupts located on the well). Called after the 0->1 refcount
137 * transition.
138 */
139 void (*enable)(struct drm_i915_private *dev_priv,
140 struct i915_power_well *power_well);
141 /*
142 * Disable the well and resources that depend on it. Called after
143 * the 1->0 refcount transition.
144 */
145 void (*disable)(struct drm_i915_private *dev_priv,
146 struct i915_power_well *power_well);
147 /* Returns the hw enabled state. */
148 bool (*is_enabled)(struct drm_i915_private *dev_priv,
149 struct i915_power_well *power_well);
150};
151
152struct i915_power_well_regs {
153 i915_reg_t bios;
154 i915_reg_t driver;
155 i915_reg_t kvmr;
156 i915_reg_t debug;
157};
158
159/* Power well structure for haswell */
160struct i915_power_well_desc {
161 const char *name;
162 bool always_on;
163 u64 domains;
164 /* unique identifier for this power well */
165 enum i915_power_well_id id;
166 /*
167 * Arbitraty data associated with this power well. Platform and power
168 * well specific.
169 */
170 union {
171 struct {
172 /*
173 * request/status flag index in the PUNIT power well
174 * control/status registers.
175 */
176 u8 idx;
177 } vlv;
178 struct {
179 enum dpio_phy phy;
180 } bxt;
181 struct {
182 const struct i915_power_well_regs *regs;
183 /*
184 * request/status flag index in the power well
185 * constrol/status registers.
186 */
187 u8 idx;
188 /* Mask of pipes whose IRQ logic is backed by the pw */
189 u8 irq_pipe_mask;
190 /* The pw is backing the VGA functionality */
191 bool has_vga:1;
192 bool has_fuses:1;
193 /*
194 * The pw is for an ICL+ TypeC PHY port in
195 * Thunderbolt mode.
196 */
197 bool is_tc_tbt:1;
198 } hsw;
199 };
200 const struct i915_power_well_ops *ops;
201};
202
203struct i915_power_well {
204 const struct i915_power_well_desc *desc;
205 /* power well enable/disable usage count */
206 int count;
207 /* cached hw enabled state */
208 bool hw_enabled;
209};
210
211struct i915_power_domains {
212 /*
213 * Power wells needed for initialization at driver init and suspend
214 * time are on. They are kept on until after the first modeset.
215 */
216 bool initializing;
217 bool display_core_suspended;
218 int power_well_count;
219
220 intel_wakeref_t wakeref;
221
222 struct mutex lock;
223 int domain_use_count[POWER_DOMAIN_NUM];
224
225 struct delayed_work async_put_work;
226 intel_wakeref_t async_put_wakeref;
227 u64 async_put_domains[2];
228
229 struct i915_power_well *power_wells;
230};
231
232#define for_each_power_domain(domain, mask) \
233 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
234 for_each_if(BIT_ULL(domain) & (mask))
235
236#define for_each_power_well(__dev_priv, __power_well) \
237 for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
238 (__power_well) - (__dev_priv)->power_domains.power_wells < \
239 (__dev_priv)->power_domains.power_well_count; \
240 (__power_well)++)
241
242#define for_each_power_well_reverse(__dev_priv, __power_well) \
243 for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
244 (__dev_priv)->power_domains.power_well_count - 1; \
245 (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
246 (__power_well)--)
247
248#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
249 for_each_power_well(__dev_priv, __power_well) \
250 for_each_if((__power_well)->desc->domains & (__domain_mask))
251
252#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \
253 for_each_power_well_reverse(__dev_priv, __power_well) \
254 for_each_if((__power_well)->desc->domains & (__domain_mask))
255
256int intel_power_domains_init(struct drm_i915_private *dev_priv);
257void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
258void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
259void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv);
260void intel_power_domains_enable(struct drm_i915_private *dev_priv);
261void intel_power_domains_disable(struct drm_i915_private *dev_priv);
262void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
263 enum i915_drm_suspend_mode);
264void intel_power_domains_resume(struct drm_i915_private *dev_priv);
265
266void intel_display_power_suspend_late(struct drm_i915_private *i915);
267void intel_display_power_resume_early(struct drm_i915_private *i915);
268void intel_display_power_suspend(struct drm_i915_private *i915);
269void intel_display_power_resume(struct drm_i915_private *i915);
270
271const char *
272intel_display_power_domain_str(struct drm_i915_private *i915,
273 enum intel_display_power_domain domain);
274
275bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
276 enum intel_display_power_domain domain);
277bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
278 enum intel_display_power_domain domain);
279intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
280 enum intel_display_power_domain domain);
281intel_wakeref_t
282intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
283 enum intel_display_power_domain domain);
284void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
285 enum intel_display_power_domain domain);
286void __intel_display_power_put_async(struct drm_i915_private *i915,
287 enum intel_display_power_domain domain,
288 intel_wakeref_t wakeref);
289void intel_display_power_flush_work(struct drm_i915_private *i915);
290#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
291void intel_display_power_put(struct drm_i915_private *dev_priv,
292 enum intel_display_power_domain domain,
293 intel_wakeref_t wakeref);
294static inline void
295intel_display_power_put_async(struct drm_i915_private *i915,
296 enum intel_display_power_domain domain,
297 intel_wakeref_t wakeref)
298{
299 __intel_display_power_put_async(i915, domain, wakeref);
300}
301#else
302static inline void
303intel_display_power_put(struct drm_i915_private *i915,
304 enum intel_display_power_domain domain,
305 intel_wakeref_t wakeref)
306{
307 intel_display_power_put_unchecked(i915, domain);
308}
309
310static inline void
311intel_display_power_put_async(struct drm_i915_private *i915,
312 enum intel_display_power_domain domain,
313 intel_wakeref_t wakeref)
314{
315 __intel_display_power_put_async(i915, domain, -1);
316}
317#endif
318
319#define with_intel_display_power(i915, domain, wf) \
320 for ((wf) = intel_display_power_get((i915), (domain)); (wf); \
321 intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)
322
323void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
324 u8 req_slices);
325
326void chv_phy_powergate_lanes(struct intel_encoder *encoder,
327 bool override, unsigned int mask);
328bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
329 enum dpio_channel ch, bool override);
330
331#endif /* __INTEL_DISPLAY_POWER_H__ */
1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2019 Intel Corporation
4 */
5
6#ifndef __INTEL_DISPLAY_POWER_H__
7#define __INTEL_DISPLAY_POWER_H__
8
9#include <linux/mutex.h>
10#include <linux/workqueue.h>
11
12#include "intel_wakeref.h"
13
14enum aux_ch;
15enum port;
16struct drm_i915_private;
17struct i915_power_well;
18struct intel_encoder;
19struct seq_file;
20
21/*
22 * Keep the pipe, transcoder, port (DDI_LANES,DDI_IO,AUX) domain instances
23 * consecutive, so that the pipe,transcoder,port -> power domain macros
24 * work correctly.
25 */
26enum intel_display_power_domain {
27 POWER_DOMAIN_DISPLAY_CORE,
28 POWER_DOMAIN_PIPE_A,
29 POWER_DOMAIN_PIPE_B,
30 POWER_DOMAIN_PIPE_C,
31 POWER_DOMAIN_PIPE_D,
32 POWER_DOMAIN_PIPE_PANEL_FITTER_A,
33 POWER_DOMAIN_PIPE_PANEL_FITTER_B,
34 POWER_DOMAIN_PIPE_PANEL_FITTER_C,
35 POWER_DOMAIN_PIPE_PANEL_FITTER_D,
36 POWER_DOMAIN_TRANSCODER_A,
37 POWER_DOMAIN_TRANSCODER_B,
38 POWER_DOMAIN_TRANSCODER_C,
39 POWER_DOMAIN_TRANSCODER_D,
40 POWER_DOMAIN_TRANSCODER_EDP,
41 POWER_DOMAIN_TRANSCODER_DSI_A,
42 POWER_DOMAIN_TRANSCODER_DSI_C,
43
44 /* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */
45 POWER_DOMAIN_TRANSCODER_VDSC_PW2,
46
47 POWER_DOMAIN_PORT_DDI_LANES_A,
48 POWER_DOMAIN_PORT_DDI_LANES_B,
49 POWER_DOMAIN_PORT_DDI_LANES_C,
50 POWER_DOMAIN_PORT_DDI_LANES_D,
51 POWER_DOMAIN_PORT_DDI_LANES_E,
52 POWER_DOMAIN_PORT_DDI_LANES_F,
53
54 POWER_DOMAIN_PORT_DDI_LANES_TC1,
55 POWER_DOMAIN_PORT_DDI_LANES_TC2,
56 POWER_DOMAIN_PORT_DDI_LANES_TC3,
57 POWER_DOMAIN_PORT_DDI_LANES_TC4,
58 POWER_DOMAIN_PORT_DDI_LANES_TC5,
59 POWER_DOMAIN_PORT_DDI_LANES_TC6,
60
61 POWER_DOMAIN_PORT_DDI_IO_A,
62 POWER_DOMAIN_PORT_DDI_IO_B,
63 POWER_DOMAIN_PORT_DDI_IO_C,
64 POWER_DOMAIN_PORT_DDI_IO_D,
65 POWER_DOMAIN_PORT_DDI_IO_E,
66 POWER_DOMAIN_PORT_DDI_IO_F,
67
68 POWER_DOMAIN_PORT_DDI_IO_TC1,
69 POWER_DOMAIN_PORT_DDI_IO_TC2,
70 POWER_DOMAIN_PORT_DDI_IO_TC3,
71 POWER_DOMAIN_PORT_DDI_IO_TC4,
72 POWER_DOMAIN_PORT_DDI_IO_TC5,
73 POWER_DOMAIN_PORT_DDI_IO_TC6,
74
75 POWER_DOMAIN_PORT_DSI,
76 POWER_DOMAIN_PORT_CRT,
77 POWER_DOMAIN_PORT_OTHER,
78 POWER_DOMAIN_VGA,
79 POWER_DOMAIN_AUDIO_MMIO,
80 POWER_DOMAIN_AUDIO_PLAYBACK,
81
82 POWER_DOMAIN_AUX_IO_A,
83 POWER_DOMAIN_AUX_IO_B,
84 POWER_DOMAIN_AUX_IO_C,
85 POWER_DOMAIN_AUX_IO_D,
86 POWER_DOMAIN_AUX_IO_E,
87 POWER_DOMAIN_AUX_IO_F,
88
89 POWER_DOMAIN_AUX_A,
90 POWER_DOMAIN_AUX_B,
91 POWER_DOMAIN_AUX_C,
92 POWER_DOMAIN_AUX_D,
93 POWER_DOMAIN_AUX_E,
94 POWER_DOMAIN_AUX_F,
95
96 POWER_DOMAIN_AUX_USBC1,
97 POWER_DOMAIN_AUX_USBC2,
98 POWER_DOMAIN_AUX_USBC3,
99 POWER_DOMAIN_AUX_USBC4,
100 POWER_DOMAIN_AUX_USBC5,
101 POWER_DOMAIN_AUX_USBC6,
102
103 POWER_DOMAIN_AUX_TBT1,
104 POWER_DOMAIN_AUX_TBT2,
105 POWER_DOMAIN_AUX_TBT3,
106 POWER_DOMAIN_AUX_TBT4,
107 POWER_DOMAIN_AUX_TBT5,
108 POWER_DOMAIN_AUX_TBT6,
109
110 POWER_DOMAIN_GMBUS,
111 POWER_DOMAIN_GT_IRQ,
112 POWER_DOMAIN_DC_OFF,
113 POWER_DOMAIN_TC_COLD_OFF,
114 POWER_DOMAIN_INIT,
115
116 POWER_DOMAIN_NUM,
117 POWER_DOMAIN_INVALID = POWER_DOMAIN_NUM,
118};
119
120#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
121#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
122 ((pipe) + POWER_DOMAIN_PIPE_PANEL_FITTER_A)
123#define POWER_DOMAIN_TRANSCODER(tran) \
124 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
125 (tran) + POWER_DOMAIN_TRANSCODER_A)
126
127struct intel_power_domain_mask {
128 DECLARE_BITMAP(bits, POWER_DOMAIN_NUM);
129};
130
131struct i915_power_domains {
132 /*
133 * Power wells needed for initialization at driver init and suspend
134 * time are on. They are kept on until after the first modeset.
135 */
136 bool initializing;
137 bool display_core_suspended;
138 int power_well_count;
139
140 u32 dc_state;
141 u32 target_dc_state;
142 u32 allowed_dc_mask;
143
144 intel_wakeref_t init_wakeref;
145 intel_wakeref_t disable_wakeref;
146
147 struct mutex lock;
148 int domain_use_count[POWER_DOMAIN_NUM];
149
150 struct delayed_work async_put_work;
151 intel_wakeref_t async_put_wakeref;
152 struct intel_power_domain_mask async_put_domains[2];
153 int async_put_next_delay;
154
155 struct i915_power_well *power_wells;
156};
157
158struct intel_display_power_domain_set {
159 struct intel_power_domain_mask mask;
160#ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM
161 intel_wakeref_t wakerefs[POWER_DOMAIN_NUM];
162#endif
163};
164
165#define for_each_power_domain(__domain, __mask) \
166 for ((__domain) = 0; (__domain) < POWER_DOMAIN_NUM; (__domain)++) \
167 for_each_if(test_bit((__domain), (__mask)->bits))
168
169int intel_power_domains_init(struct drm_i915_private *dev_priv);
170void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
171void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
172void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv);
173void intel_power_domains_enable(struct drm_i915_private *dev_priv);
174void intel_power_domains_disable(struct drm_i915_private *dev_priv);
175void intel_power_domains_suspend(struct drm_i915_private *dev_priv, bool s2idle);
176void intel_power_domains_resume(struct drm_i915_private *dev_priv);
177void intel_power_domains_sanitize_state(struct drm_i915_private *dev_priv);
178
179void intel_display_power_suspend_late(struct drm_i915_private *i915);
180void intel_display_power_resume_early(struct drm_i915_private *i915);
181void intel_display_power_suspend(struct drm_i915_private *i915);
182void intel_display_power_resume(struct drm_i915_private *i915);
183void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
184 u32 state);
185
186const char *
187intel_display_power_domain_str(enum intel_display_power_domain domain);
188
189bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
190 enum intel_display_power_domain domain);
191bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
192 enum intel_display_power_domain domain);
193intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
194 enum intel_display_power_domain domain);
195intel_wakeref_t
196intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
197 enum intel_display_power_domain domain);
198void __intel_display_power_put_async(struct drm_i915_private *i915,
199 enum intel_display_power_domain domain,
200 intel_wakeref_t wakeref,
201 int delay_ms);
202void intel_display_power_flush_work(struct drm_i915_private *i915);
203#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
204void intel_display_power_put(struct drm_i915_private *dev_priv,
205 enum intel_display_power_domain domain,
206 intel_wakeref_t wakeref);
207static inline void
208intel_display_power_put_async(struct drm_i915_private *i915,
209 enum intel_display_power_domain domain,
210 intel_wakeref_t wakeref)
211{
212 __intel_display_power_put_async(i915, domain, wakeref, -1);
213}
214
215static inline void
216intel_display_power_put_async_delay(struct drm_i915_private *i915,
217 enum intel_display_power_domain domain,
218 intel_wakeref_t wakeref,
219 int delay_ms)
220{
221 __intel_display_power_put_async(i915, domain, wakeref, delay_ms);
222}
223#else
224void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
225 enum intel_display_power_domain domain);
226
227static inline void
228intel_display_power_put(struct drm_i915_private *i915,
229 enum intel_display_power_domain domain,
230 intel_wakeref_t wakeref)
231{
232 intel_display_power_put_unchecked(i915, domain);
233}
234
235static inline void
236intel_display_power_put_async(struct drm_i915_private *i915,
237 enum intel_display_power_domain domain,
238 intel_wakeref_t wakeref)
239{
240 __intel_display_power_put_async(i915, domain, -1, -1);
241}
242
243static inline void
244intel_display_power_put_async_delay(struct drm_i915_private *i915,
245 enum intel_display_power_domain domain,
246 intel_wakeref_t wakeref,
247 int delay_ms)
248{
249 __intel_display_power_put_async(i915, domain, -1, delay_ms);
250}
251#endif
252
253void
254intel_display_power_get_in_set(struct drm_i915_private *i915,
255 struct intel_display_power_domain_set *power_domain_set,
256 enum intel_display_power_domain domain);
257
258bool
259intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
260 struct intel_display_power_domain_set *power_domain_set,
261 enum intel_display_power_domain domain);
262
263void
264intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
265 struct intel_display_power_domain_set *power_domain_set,
266 struct intel_power_domain_mask *mask);
267
268static inline void
269intel_display_power_put_all_in_set(struct drm_i915_private *i915,
270 struct intel_display_power_domain_set *power_domain_set)
271{
272 intel_display_power_put_mask_in_set(i915, power_domain_set, &power_domain_set->mask);
273}
274
275void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m);
276
277enum intel_display_power_domain
278intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port port);
279enum intel_display_power_domain
280intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port);
281enum intel_display_power_domain
282intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
283enum intel_display_power_domain
284intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
285enum intel_display_power_domain
286intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
287
288/*
289 * FIXME: We should probably switch this to a 0-based scheme to be consistent
290 * with how we now name/number DBUF_CTL instances.
291 */
292enum dbuf_slice {
293 DBUF_S1,
294 DBUF_S2,
295 DBUF_S3,
296 DBUF_S4,
297 I915_MAX_DBUF_SLICES
298};
299
300void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
301 u8 req_slices);
302
303#define with_intel_display_power(i915, domain, wf) \
304 for ((wf) = intel_display_power_get((i915), (domain)); (wf); \
305 intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)
306
307#define with_intel_display_power_if_enabled(i915, domain, wf) \
308 for ((wf) = intel_display_power_get_if_enabled((i915), (domain)); (wf); \
309 intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)
310
311#endif /* __INTEL_DISPLAY_POWER_H__ */