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v5.4
 1// SPDX-License-Identifier: GPL-2.0-only
 2/**************************************************************************
 3 * Copyright (c) 2011, Intel Corporation.
 4 * All Rights Reserved.
 5 *
 6 **************************************************************************/
 7
 8#include "psb_drv.h"
 
 9
10void gma_get_core_freq(struct drm_device *dev)
11{
12	uint32_t clock;
 
13	struct pci_dev *pci_root =
14		pci_get_domain_bus_and_slot(pci_domain_nr(dev->pdev->bus),
15					    0, 0);
16	struct drm_psb_private *dev_priv = dev->dev_private;
17
18	/*pci_write_config_dword(pci_root, 0xD4, 0x00C32004);*/
19	/*pci_write_config_dword(pci_root, 0xD0, 0xE0033000);*/
20
21	pci_write_config_dword(pci_root, 0xD0, 0xD0050300);
22	pci_read_config_dword(pci_root, 0xD4, &clock);
23	pci_dev_put(pci_root);
24
25	switch (clock & 0x07) {
26	case 0:
27		dev_priv->core_freq = 100;
28		break;
29	case 1:
30		dev_priv->core_freq = 133;
31		break;
32	case 2:
33		dev_priv->core_freq = 150;
34		break;
35	case 3:
36		dev_priv->core_freq = 178;
37		break;
38	case 4:
39		dev_priv->core_freq = 200;
40		break;
41	case 5:
42	case 6:
43	case 7:
44		dev_priv->core_freq = 266;
45		break;
46	default:
47		dev_priv->core_freq = 0;
48	}
49}
v6.8
 1// SPDX-License-Identifier: GPL-2.0-only
 2/**************************************************************************
 3 * Copyright (c) 2011, Intel Corporation.
 4 * All Rights Reserved.
 5 *
 6 **************************************************************************/
 7
 8#include "psb_drv.h"
 9#include "gma_device.h"
10
11void gma_get_core_freq(struct drm_device *dev)
12{
13	uint32_t clock;
14	struct pci_dev *pdev = to_pci_dev(dev->dev);
15	struct pci_dev *pci_root =
16		pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
17					    0, 0);
18	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
19
20	/*pci_write_config_dword(pci_root, 0xD4, 0x00C32004);*/
21	/*pci_write_config_dword(pci_root, 0xD0, 0xE0033000);*/
22
23	pci_write_config_dword(pci_root, 0xD0, 0xD0050300);
24	pci_read_config_dword(pci_root, 0xD4, &clock);
25	pci_dev_put(pci_root);
26
27	switch (clock & 0x07) {
28	case 0:
29		dev_priv->core_freq = 100;
30		break;
31	case 1:
32		dev_priv->core_freq = 133;
33		break;
34	case 2:
35		dev_priv->core_freq = 150;
36		break;
37	case 3:
38		dev_priv->core_freq = 178;
39		break;
40	case 4:
41		dev_priv->core_freq = 200;
42		break;
43	case 5:
44	case 6:
45	case 7:
46		dev_priv->core_freq = 266;
47		break;
48	default:
49		dev_priv->core_freq = 0;
50	}
51}