1/* SPDX-License-Identifier: GPL-2.0 */
 2#ifndef __ASM_MACH_LOONGSON64_IRQ_H_
 3#define __ASM_MACH_LOONGSON64_IRQ_H_
 4
 5#include <boot_param.h>
 6
 7#ifdef CONFIG_CPU_LOONGSON3
 8
 9/* cpu core interrupt numbers */
10#define MIPS_CPU_IRQ_BASE 56
11
12#define LOONGSON_UART_IRQ   (MIPS_CPU_IRQ_BASE + 2) /* UART */
13#define LOONGSON_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 3) /* CASCADE */
14#define LOONGSON_TIMER_IRQ  (MIPS_CPU_IRQ_BASE + 7) /* CPU Timer */
15
16#define LOONGSON_HT1_CFG_BASE		loongson_sysconf.ht_control_base
17#define LOONGSON_HT1_INT_VECTOR_BASE	(LOONGSON_HT1_CFG_BASE + 0x80)
18#define LOONGSON_HT1_INT_EN_BASE	(LOONGSON_HT1_CFG_BASE + 0xa0)
19#define LOONGSON_HT1_INT_VECTOR(n)	\
20		LOONGSON3_REG32(LOONGSON_HT1_INT_VECTOR_BASE, 4 * (n))
21#define LOONGSON_HT1_INTN_EN(n)		\
22		LOONGSON3_REG32(LOONGSON_HT1_INT_EN_BASE, 4 * (n))
23
24#define LOONGSON_INT_ROUTER_OFFSET	0x1400
25#define LOONGSON_INT_ROUTER_INTEN	\
26	  LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x24)
27#define LOONGSON_INT_ROUTER_INTENSET	\
28	  LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x28)
29#define LOONGSON_INT_ROUTER_INTENCLR	\
30	  LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x2c)
31#define LOONGSON_INT_ROUTER_ENTRY(n)	\
32	  LOONGSON3_REG8(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + n)
33#define LOONGSON_INT_ROUTER_LPC		LOONGSON_INT_ROUTER_ENTRY(0x0a)
34#define LOONGSON_INT_ROUTER_HT1(n)	LOONGSON_INT_ROUTER_ENTRY(n + 0x18)
35
36#define LOONGSON_INT_COREx_INTy(x, y)	(1<<(x) | 1<<(y+4))	/* route to int y of core x */
37
38#endif
39
40extern void fixup_irqs(void);
41extern void loongson3_ipi_interrupt(struct pt_regs *regs);
42
43#include_next <irq.h>
44#endif /* __ASM_MACH_LOONGSON64_IRQ_H_ */

 1/* SPDX-License-Identifier: GPL-2.0 */
 2#ifndef __ASM_MACH_LOONGSON64_IRQ_H_
 3#define __ASM_MACH_LOONGSON64_IRQ_H_
 4
 
 
 
 
 5/* cpu core interrupt numbers */
 6#define NR_IRQS_LEGACY		16
 7#define NR_MIPS_CPU_IRQS	8
 8#define NR_MAX_CHAINED_IRQS	40 /* Chained IRQs means those not directly used by devices */
 9#define NR_IRQS			(NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_CHAINED_IRQS + 256)
10#define MAX_IO_PICS		1
11#define MIPS_CPU_IRQ_BASE 	NR_IRQS_LEGACY
12#define GSI_MIN_CPU_IRQ		0
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
13
14#include <asm/mach-generic/irq.h>
 
15
 
16#endif /* __ASM_MACH_LOONGSON64_IRQ_H_ */