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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * linux/arch/arm/vfp/vfpinstr.h
4 *
5 * Copyright (C) 2004 ARM Limited.
6 * Written by Deep Blue Solutions Limited.
7 *
8 * VFP instruction masks.
9 */
10#define INST_CPRTDO(inst) (((inst) & 0x0f000000) == 0x0e000000)
11#define INST_CPRT(inst) ((inst) & (1 << 4))
12#define INST_CPRT_L(inst) ((inst) & (1 << 20))
13#define INST_CPRT_Rd(inst) (((inst) & (15 << 12)) >> 12)
14#define INST_CPRT_OP(inst) (((inst) >> 21) & 7)
15#define INST_CPNUM(inst) ((inst) & 0xf00)
16#define CPNUM(cp) ((cp) << 8)
17
18#define FOP_MASK (0x00b00040)
19#define FOP_FMAC (0x00000000)
20#define FOP_FNMAC (0x00000040)
21#define FOP_FMSC (0x00100000)
22#define FOP_FNMSC (0x00100040)
23#define FOP_FMUL (0x00200000)
24#define FOP_FNMUL (0x00200040)
25#define FOP_FADD (0x00300000)
26#define FOP_FSUB (0x00300040)
27#define FOP_FDIV (0x00800000)
28#define FOP_EXT (0x00b00040)
29
30#define FOP_TO_IDX(inst) ((inst & 0x00b00000) >> 20 | (inst & (1 << 6)) >> 4)
31
32#define FEXT_MASK (0x000f0080)
33#define FEXT_FCPY (0x00000000)
34#define FEXT_FABS (0x00000080)
35#define FEXT_FNEG (0x00010000)
36#define FEXT_FSQRT (0x00010080)
37#define FEXT_FCMP (0x00040000)
38#define FEXT_FCMPE (0x00040080)
39#define FEXT_FCMPZ (0x00050000)
40#define FEXT_FCMPEZ (0x00050080)
41#define FEXT_FCVT (0x00070080)
42#define FEXT_FUITO (0x00080000)
43#define FEXT_FSITO (0x00080080)
44#define FEXT_FTOUI (0x000c0000)
45#define FEXT_FTOUIZ (0x000c0080)
46#define FEXT_FTOSI (0x000d0000)
47#define FEXT_FTOSIZ (0x000d0080)
48
49#define FEXT_TO_IDX(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7)
50
51#define vfp_get_sd(inst) ((inst & 0x0000f000) >> 11 | (inst & (1 << 22)) >> 22)
52#define vfp_get_dd(inst) ((inst & 0x0000f000) >> 12 | (inst & (1 << 22)) >> 18)
53#define vfp_get_sm(inst) ((inst & 0x0000000f) << 1 | (inst & (1 << 5)) >> 5)
54#define vfp_get_dm(inst) ((inst & 0x0000000f) | (inst & (1 << 5)) >> 1)
55#define vfp_get_sn(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7)
56#define vfp_get_dn(inst) ((inst & 0x000f0000) >> 16 | (inst & (1 << 7)) >> 3)
57
58#define vfp_single(inst) (((inst) & 0x0000f00) == 0xa00)
59
60#define FPSCR_N (1 << 31)
61#define FPSCR_Z (1 << 30)
62#define FPSCR_C (1 << 29)
63#define FPSCR_V (1 << 28)
64
65/*
66 * Since we aren't building with -mfpu=vfp, we need to code
67 * these instructions using their MRC/MCR equivalents.
68 */
69#define vfpreg(_vfp_) #_vfp_
70
71#define fmrx(_vfp_) ({ \
72 u32 __v; \
73 asm("mrc p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmrx %0, " #_vfp_ \
74 : "=r" (__v) : : "cc"); \
75 __v; \
76 })
77
78#define fmxr(_vfp_,_var_) \
79 asm("mcr p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr " #_vfp_ ", %0" \
80 : : "r" (_var_) : "cc")
81
82u32 vfp_single_cpdo(u32 inst, u32 fpscr);
83u32 vfp_single_cprt(u32 inst, u32 fpscr, struct pt_regs *regs);
84
85u32 vfp_double_cpdo(u32 inst, u32 fpscr);
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * linux/arch/arm/vfp/vfpinstr.h
4 *
5 * Copyright (C) 2004 ARM Limited.
6 * Written by Deep Blue Solutions Limited.
7 *
8 * VFP instruction masks.
9 */
10#define INST_CPRTDO(inst) (((inst) & 0x0f000000) == 0x0e000000)
11#define INST_CPRT(inst) ((inst) & (1 << 4))
12#define INST_CPRT_L(inst) ((inst) & (1 << 20))
13#define INST_CPRT_Rd(inst) (((inst) & (15 << 12)) >> 12)
14#define INST_CPRT_OP(inst) (((inst) >> 21) & 7)
15#define INST_CPNUM(inst) ((inst) & 0xf00)
16#define CPNUM(cp) ((cp) << 8)
17
18#define FOP_MASK (0x00b00040)
19#define FOP_FMAC (0x00000000)
20#define FOP_FNMAC (0x00000040)
21#define FOP_FMSC (0x00100000)
22#define FOP_FNMSC (0x00100040)
23#define FOP_FMUL (0x00200000)
24#define FOP_FNMUL (0x00200040)
25#define FOP_FADD (0x00300000)
26#define FOP_FSUB (0x00300040)
27#define FOP_FDIV (0x00800000)
28#define FOP_EXT (0x00b00040)
29
30#define FOP_TO_IDX(inst) ((inst & 0x00b00000) >> 20 | (inst & (1 << 6)) >> 4)
31
32#define FEXT_MASK (0x000f0080)
33#define FEXT_FCPY (0x00000000)
34#define FEXT_FABS (0x00000080)
35#define FEXT_FNEG (0x00010000)
36#define FEXT_FSQRT (0x00010080)
37#define FEXT_FCMP (0x00040000)
38#define FEXT_FCMPE (0x00040080)
39#define FEXT_FCMPZ (0x00050000)
40#define FEXT_FCMPEZ (0x00050080)
41#define FEXT_FCVT (0x00070080)
42#define FEXT_FUITO (0x00080000)
43#define FEXT_FSITO (0x00080080)
44#define FEXT_FTOUI (0x000c0000)
45#define FEXT_FTOUIZ (0x000c0080)
46#define FEXT_FTOSI (0x000d0000)
47#define FEXT_FTOSIZ (0x000d0080)
48
49#define FEXT_TO_IDX(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7)
50
51#define vfp_get_sd(inst) ((inst & 0x0000f000) >> 11 | (inst & (1 << 22)) >> 22)
52#define vfp_get_dd(inst) ((inst & 0x0000f000) >> 12 | (inst & (1 << 22)) >> 18)
53#define vfp_get_sm(inst) ((inst & 0x0000000f) << 1 | (inst & (1 << 5)) >> 5)
54#define vfp_get_dm(inst) ((inst & 0x0000000f) | (inst & (1 << 5)) >> 1)
55#define vfp_get_sn(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7)
56#define vfp_get_dn(inst) ((inst & 0x000f0000) >> 16 | (inst & (1 << 7)) >> 3)
57
58#define vfp_single(inst) (((inst) & 0x0000f00) == 0xa00)
59
60#define FPSCR_N (1 << 31)
61#define FPSCR_Z (1 << 30)
62#define FPSCR_C (1 << 29)
63#define FPSCR_V (1 << 28)
64
65#ifdef CONFIG_AS_VFP_VMRS_FPINST
66
67#define fmrx(_vfp_) ({ \
68 u32 __v; \
69 asm(".fpu vfpv2\n" \
70 "vmrs %0, " #_vfp_ \
71 : "=r" (__v) : : "cc"); \
72 __v; \
73 })
74
75#define fmxr(_vfp_,_var_) \
76 asm(".fpu vfpv2\n" \
77 "vmsr " #_vfp_ ", %0" \
78 : : "r" (_var_) : "cc")
79
80#else
81
82#define vfpreg(_vfp_) #_vfp_
83
84#define fmrx(_vfp_) ({ \
85 u32 __v; \
86 asm("mrc p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmrx %0, " #_vfp_ \
87 : "=r" (__v) : : "cc"); \
88 __v; \
89 })
90
91#define fmxr(_vfp_,_var_) \
92 asm("mcr p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr " #_vfp_ ", %0" \
93 : : "r" (_var_) : "cc")
94
95#endif
96
97u32 vfp_single_cpdo(u32 inst, u32 fpscr);
98u32 vfp_single_cprt(u32 inst, u32 fpscr, struct pt_regs *regs);
99
100u32 vfp_double_cpdo(u32 inst, u32 fpscr);