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  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Device Tree Source for OMAP3430 ES1 clock data
  4 *
  5 * Copyright (C) 2013 Texas Instruments, Inc.
  6 */
  7&cm_clocks {
  8	gfx_l3_ck: gfx_l3_ck@b10 {
  9		#clock-cells = <0>;
 10		compatible = "ti,wait-gate-clock";
 11		clocks = <&l3_ick>;
 12		reg = <0x0b10>;
 13		ti,bit-shift = <0>;
 14	};
 15
 16	gfx_l3_fck: gfx_l3_fck@b40 {
 17		#clock-cells = <0>;
 18		compatible = "ti,divider-clock";
 19		clocks = <&l3_ick>;
 20		ti,max-div = <7>;
 21		reg = <0x0b40>;
 22		ti,index-starts-at-one;
 23	};
 24
 25	gfx_l3_ick: gfx_l3_ick {
 26		#clock-cells = <0>;
 27		compatible = "fixed-factor-clock";
 28		clocks = <&gfx_l3_ck>;
 29		clock-mult = <1>;
 30		clock-div = <1>;
 31	};
 32
 33	gfx_cg1_ck: gfx_cg1_ck@b00 {
 34		#clock-cells = <0>;
 35		compatible = "ti,wait-gate-clock";
 36		clocks = <&gfx_l3_fck>;
 37		reg = <0x0b00>;
 38		ti,bit-shift = <1>;
 39	};
 40
 41	gfx_cg2_ck: gfx_cg2_ck@b00 {
 42		#clock-cells = <0>;
 43		compatible = "ti,wait-gate-clock";
 44		clocks = <&gfx_l3_fck>;
 45		reg = <0x0b00>;
 46		ti,bit-shift = <2>;
 47	};
 48
 49	d2d_26m_fck: d2d_26m_fck@a00 {
 50		#clock-cells = <0>;
 51		compatible = "ti,wait-gate-clock";
 52		clocks = <&sys_ck>;
 53		reg = <0x0a00>;
 54		ti,bit-shift = <3>;
 55	};
 56
 57	fshostusb_fck: fshostusb_fck@a00 {
 58		#clock-cells = <0>;
 59		compatible = "ti,wait-gate-clock";
 60		clocks = <&core_48m_fck>;
 61		reg = <0x0a00>;
 62		ti,bit-shift = <5>;
 63	};
 64
 65	ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1@a00 {
 66		#clock-cells = <0>;
 67		compatible = "ti,composite-no-wait-gate-clock";
 68		clocks = <&corex2_fck>;
 69		ti,bit-shift = <0>;
 70		reg = <0x0a00>;
 71	};
 72
 73	ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1@a40 {
 74		#clock-cells = <0>;
 75		compatible = "ti,composite-divider-clock";
 76		clocks = <&corex2_fck>;
 77		ti,bit-shift = <8>;
 78		reg = <0x0a40>;
 79		ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
 80	};
 81
 82	ssi_ssr_fck: ssi_ssr_fck_3430es1 {
 83		#clock-cells = <0>;
 84		compatible = "ti,composite-clock";
 85		clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>;
 86	};
 87
 88	ssi_sst_fck: ssi_sst_fck_3430es1 {
 89		#clock-cells = <0>;
 90		compatible = "fixed-factor-clock";
 91		clocks = <&ssi_ssr_fck>;
 92		clock-mult = <1>;
 93		clock-div = <2>;
 94	};
 95
 96	hsotgusb_ick_3430es1: hsotgusb_ick_3430es1@a10 {
 97		#clock-cells = <0>;
 98		compatible = "ti,omap3-no-wait-interface-clock";
 99		clocks = <&core_l3_ick>;
100		reg = <0x0a10>;
101		ti,bit-shift = <4>;
102	};
103
104	fac_ick: fac_ick@a10 {
105		#clock-cells = <0>;
106		compatible = "ti,omap3-interface-clock";
107		clocks = <&core_l4_ick>;
108		reg = <0x0a10>;
109		ti,bit-shift = <8>;
110	};
111
112	ssi_l4_ick: ssi_l4_ick {
113		#clock-cells = <0>;
114		compatible = "fixed-factor-clock";
115		clocks = <&l4_ick>;
116		clock-mult = <1>;
117		clock-div = <1>;
118	};
119
120	ssi_ick: ssi_ick_3430es1@a10 {
121		#clock-cells = <0>;
122		compatible = "ti,omap3-no-wait-interface-clock";
123		clocks = <&ssi_l4_ick>;
124		reg = <0x0a10>;
125		ti,bit-shift = <0>;
126	};
127
128	usb_l4_gate_ick: usb_l4_gate_ick@a10 {
129		#clock-cells = <0>;
130		compatible = "ti,composite-interface-clock";
131		clocks = <&l4_ick>;
132		ti,bit-shift = <5>;
133		reg = <0x0a10>;
134	};
135
136	usb_l4_div_ick: usb_l4_div_ick@a40 {
137		#clock-cells = <0>;
138		compatible = "ti,composite-divider-clock";
139		clocks = <&l4_ick>;
140		ti,bit-shift = <4>;
141		ti,max-div = <1>;
142		reg = <0x0a40>;
143		ti,index-starts-at-one;
144	};
145
146	usb_l4_ick: usb_l4_ick {
147		#clock-cells = <0>;
148		compatible = "ti,composite-clock";
149		clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
150	};
151
152	dss1_alwon_fck: dss1_alwon_fck_3430es1@e00 {
153		#clock-cells = <0>;
154		compatible = "ti,gate-clock";
155		clocks = <&dpll4_m4x2_ck>;
156		ti,bit-shift = <0>;
157		reg = <0x0e00>;
158		ti,set-rate-parent;
159	};
160
161	dss_ick: dss_ick_3430es1@e10 {
162		#clock-cells = <0>;
163		compatible = "ti,omap3-no-wait-interface-clock";
164		clocks = <&l4_ick>;
165		reg = <0x0e10>;
166		ti,bit-shift = <0>;
167	};
168};
169
170&cm_clockdomains {
171	core_l3_clkdm: core_l3_clkdm {
172		compatible = "ti,clockdomain";
173		clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es1>;
174	};
175
176	gfx_3430es1_clkdm: gfx_3430es1_clkdm {
177		compatible = "ti,clockdomain";
178		clocks = <&gfx_l3_ck>, <&gfx_cg1_ck>, <&gfx_cg2_ck>;
179	};
180
181	dss_clkdm: dss_clkdm {
182		compatible = "ti,clockdomain";
183		clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
184			 <&dss1_alwon_fck>, <&dss_ick>;
185	};
186
187	d2d_clkdm: d2d_clkdm {
188		compatible = "ti,clockdomain";
189		clocks = <&d2d_26m_fck>;
190	};
191
192	core_l4_clkdm: core_l4_clkdm {
193		compatible = "ti,clockdomain";
194		clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
195			 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
196			 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
197			 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
198			 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
199			 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
200			 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
201			 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
202			 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
203			 <&fshostusb_fck>, <&fac_ick>, <&ssi_ick>;
204	};
205};