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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * This file contains work-arounds for many known PCI hardware bugs.
4 * Devices present only on certain architectures (host bridges et cetera)
5 * should be handled in arch-specific code.
6 *
7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 *
9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 *
11 * Init/reset quirks for USB host controllers should be in the USB quirks
12 * file, where their drivers can use them.
13 */
14
15#include <linux/types.h>
16#include <linux/kernel.h>
17#include <linux/export.h>
18#include <linux/pci.h>
19#include <linux/init.h>
20#include <linux/delay.h>
21#include <linux/acpi.h>
22#include <linux/dmi.h>
23#include <linux/ioport.h>
24#include <linux/sched.h>
25#include <linux/ktime.h>
26#include <linux/mm.h>
27#include <linux/nvme.h>
28#include <linux/platform_data/x86/apple.h>
29#include <linux/pm_runtime.h>
30#include <linux/switchtec.h>
31#include <asm/dma.h> /* isa_dma_bridge_buggy */
32#include "pci.h"
33
34static ktime_t fixup_debug_start(struct pci_dev *dev,
35 void (*fn)(struct pci_dev *dev))
36{
37 if (initcall_debug)
38 pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current));
39
40 return ktime_get();
41}
42
43static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
44 void (*fn)(struct pci_dev *dev))
45{
46 ktime_t delta, rettime;
47 unsigned long long duration;
48
49 rettime = ktime_get();
50 delta = ktime_sub(rettime, calltime);
51 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
52 if (initcall_debug || duration > 10000)
53 pci_info(dev, "%pS took %lld usecs\n", fn, duration);
54}
55
56static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
57 struct pci_fixup *end)
58{
59 ktime_t calltime;
60
61 for (; f < end; f++)
62 if ((f->class == (u32) (dev->class >> f->class_shift) ||
63 f->class == (u32) PCI_ANY_ID) &&
64 (f->vendor == dev->vendor ||
65 f->vendor == (u16) PCI_ANY_ID) &&
66 (f->device == dev->device ||
67 f->device == (u16) PCI_ANY_ID)) {
68 void (*hook)(struct pci_dev *dev);
69#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
70 hook = offset_to_ptr(&f->hook_offset);
71#else
72 hook = f->hook;
73#endif
74 calltime = fixup_debug_start(dev, hook);
75 hook(dev);
76 fixup_debug_report(dev, calltime, hook);
77 }
78}
79
80extern struct pci_fixup __start_pci_fixups_early[];
81extern struct pci_fixup __end_pci_fixups_early[];
82extern struct pci_fixup __start_pci_fixups_header[];
83extern struct pci_fixup __end_pci_fixups_header[];
84extern struct pci_fixup __start_pci_fixups_final[];
85extern struct pci_fixup __end_pci_fixups_final[];
86extern struct pci_fixup __start_pci_fixups_enable[];
87extern struct pci_fixup __end_pci_fixups_enable[];
88extern struct pci_fixup __start_pci_fixups_resume[];
89extern struct pci_fixup __end_pci_fixups_resume[];
90extern struct pci_fixup __start_pci_fixups_resume_early[];
91extern struct pci_fixup __end_pci_fixups_resume_early[];
92extern struct pci_fixup __start_pci_fixups_suspend[];
93extern struct pci_fixup __end_pci_fixups_suspend[];
94extern struct pci_fixup __start_pci_fixups_suspend_late[];
95extern struct pci_fixup __end_pci_fixups_suspend_late[];
96
97static bool pci_apply_fixup_final_quirks;
98
99void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
100{
101 struct pci_fixup *start, *end;
102
103 switch (pass) {
104 case pci_fixup_early:
105 start = __start_pci_fixups_early;
106 end = __end_pci_fixups_early;
107 break;
108
109 case pci_fixup_header:
110 start = __start_pci_fixups_header;
111 end = __end_pci_fixups_header;
112 break;
113
114 case pci_fixup_final:
115 if (!pci_apply_fixup_final_quirks)
116 return;
117 start = __start_pci_fixups_final;
118 end = __end_pci_fixups_final;
119 break;
120
121 case pci_fixup_enable:
122 start = __start_pci_fixups_enable;
123 end = __end_pci_fixups_enable;
124 break;
125
126 case pci_fixup_resume:
127 start = __start_pci_fixups_resume;
128 end = __end_pci_fixups_resume;
129 break;
130
131 case pci_fixup_resume_early:
132 start = __start_pci_fixups_resume_early;
133 end = __end_pci_fixups_resume_early;
134 break;
135
136 case pci_fixup_suspend:
137 start = __start_pci_fixups_suspend;
138 end = __end_pci_fixups_suspend;
139 break;
140
141 case pci_fixup_suspend_late:
142 start = __start_pci_fixups_suspend_late;
143 end = __end_pci_fixups_suspend_late;
144 break;
145
146 default:
147 /* stupid compiler warning, you would think with an enum... */
148 return;
149 }
150 pci_do_fixups(dev, start, end);
151}
152EXPORT_SYMBOL(pci_fixup_device);
153
154static int __init pci_apply_final_quirks(void)
155{
156 struct pci_dev *dev = NULL;
157 u8 cls = 0;
158 u8 tmp;
159
160 if (pci_cache_line_size)
161 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2);
162
163 pci_apply_fixup_final_quirks = true;
164 for_each_pci_dev(dev) {
165 pci_fixup_device(pci_fixup_final, dev);
166 /*
167 * If arch hasn't set it explicitly yet, use the CLS
168 * value shared by all PCI devices. If there's a
169 * mismatch, fall back to the default value.
170 */
171 if (!pci_cache_line_size) {
172 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
173 if (!cls)
174 cls = tmp;
175 if (!tmp || cls == tmp)
176 continue;
177
178 pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n",
179 cls << 2, tmp << 2,
180 pci_dfl_cache_line_size << 2);
181 pci_cache_line_size = pci_dfl_cache_line_size;
182 }
183 }
184
185 if (!pci_cache_line_size) {
186 pr_info("PCI: CLS %u bytes, default %u\n", cls << 2,
187 pci_dfl_cache_line_size << 2);
188 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
189 }
190
191 return 0;
192}
193fs_initcall_sync(pci_apply_final_quirks);
194
195/*
196 * Decoding should be disabled for a PCI device during BAR sizing to avoid
197 * conflict. But doing so may cause problems on host bridge and perhaps other
198 * key system devices. For devices that need to have mmio decoding always-on,
199 * we need to set the dev->mmio_always_on bit.
200 */
201static void quirk_mmio_always_on(struct pci_dev *dev)
202{
203 dev->mmio_always_on = 1;
204}
205DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
206 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
207
208/*
209 * The Mellanox Tavor device gives false positive parity errors. Mark this
210 * device with a broken_parity_status to allow PCI scanning code to "skip"
211 * this now blacklisted device.
212 */
213static void quirk_mellanox_tavor(struct pci_dev *dev)
214{
215 dev->broken_parity_status = 1; /* This device gives false positives */
216}
217DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
218DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
219
220/*
221 * Deal with broken BIOSes that neglect to enable passive release,
222 * which can cause problems in combination with the 82441FX/PPro MTRRs
223 */
224static void quirk_passive_release(struct pci_dev *dev)
225{
226 struct pci_dev *d = NULL;
227 unsigned char dlc;
228
229 /*
230 * We have to make sure a particular bit is set in the PIIX3
231 * ISA bridge, so we have to go out and find it.
232 */
233 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
234 pci_read_config_byte(d, 0x82, &dlc);
235 if (!(dlc & 1<<1)) {
236 pci_info(d, "PIIX3: Enabling Passive Release\n");
237 dlc |= 1<<1;
238 pci_write_config_byte(d, 0x82, dlc);
239 }
240 }
241}
242DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
243DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
244
245/*
246 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a
247 * workaround but VIA don't answer queries. If you happen to have good
248 * contacts at VIA ask them for me please -- Alan
249 *
250 * This appears to be BIOS not version dependent. So presumably there is a
251 * chipset level fix.
252 */
253static void quirk_isa_dma_hangs(struct pci_dev *dev)
254{
255 if (!isa_dma_bridge_buggy) {
256 isa_dma_bridge_buggy = 1;
257 pci_info(dev, "Activating ISA DMA hang workarounds\n");
258 }
259}
260/*
261 * It's not totally clear which chipsets are the problematic ones. We know
262 * 82C586 and 82C596 variants are affected.
263 */
264DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
265DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
266DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
267DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
268DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
269DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
270DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
271
272/*
273 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
274 * for some HT machines to use C4 w/o hanging.
275 */
276static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
277{
278 u32 pmbase;
279 u16 pm1a;
280
281 pci_read_config_dword(dev, 0x40, &pmbase);
282 pmbase = pmbase & 0xff80;
283 pm1a = inw(pmbase);
284
285 if (pm1a & 0x10) {
286 pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
287 outw(0x10, pmbase);
288 }
289}
290DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
291
292/* Chipsets where PCI->PCI transfers vanish or hang */
293static void quirk_nopcipci(struct pci_dev *dev)
294{
295 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
296 pci_info(dev, "Disabling direct PCI/PCI transfers\n");
297 pci_pci_problems |= PCIPCI_FAIL;
298 }
299}
300DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
301DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
302
303static void quirk_nopciamd(struct pci_dev *dev)
304{
305 u8 rev;
306 pci_read_config_byte(dev, 0x08, &rev);
307 if (rev == 0x13) {
308 /* Erratum 24 */
309 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
310 pci_pci_problems |= PCIAGP_FAIL;
311 }
312}
313DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
314
315/* Triton requires workarounds to be used by the drivers */
316static void quirk_triton(struct pci_dev *dev)
317{
318 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
319 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
320 pci_pci_problems |= PCIPCI_TRITON;
321 }
322}
323DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
324DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
325DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
326DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
327
328/*
329 * VIA Apollo KT133 needs PCI latency patch
330 * Made according to a Windows driver-based patch by George E. Breese;
331 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
332 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
333 * which Mr Breese based his work.
334 *
335 * Updated based on further information from the site and also on
336 * information provided by VIA
337 */
338static void quirk_vialatency(struct pci_dev *dev)
339{
340 struct pci_dev *p;
341 u8 busarb;
342
343 /*
344 * Ok, we have a potential problem chipset here. Now see if we have
345 * a buggy southbridge.
346 */
347 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
348 if (p != NULL) {
349
350 /*
351 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A;
352 * thanks Dan Hollis.
353 * Check for buggy part revisions
354 */
355 if (p->revision < 0x40 || p->revision > 0x42)
356 goto exit;
357 } else {
358 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
359 if (p == NULL) /* No problem parts */
360 goto exit;
361
362 /* Check for buggy part revisions */
363 if (p->revision < 0x10 || p->revision > 0x12)
364 goto exit;
365 }
366
367 /*
368 * Ok we have the problem. Now set the PCI master grant to occur
369 * every master grant. The apparent bug is that under high PCI load
370 * (quite common in Linux of course) you can get data loss when the
371 * CPU is held off the bus for 3 bus master requests. This happens
372 * to include the IDE controllers....
373 *
374 * VIA only apply this fix when an SB Live! is present but under
375 * both Linux and Windows this isn't enough, and we have seen
376 * corruption without SB Live! but with things like 3 UDMA IDE
377 * controllers. So we ignore that bit of the VIA recommendation..
378 */
379 pci_read_config_byte(dev, 0x76, &busarb);
380
381 /*
382 * Set bit 4 and bit 5 of byte 76 to 0x01
383 * "Master priority rotation on every PCI master grant"
384 */
385 busarb &= ~(1<<5);
386 busarb |= (1<<4);
387 pci_write_config_byte(dev, 0x76, busarb);
388 pci_info(dev, "Applying VIA southbridge workaround\n");
389exit:
390 pci_dev_put(p);
391}
392DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
393DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
394DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
395/* Must restore this on a resume from RAM */
396DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
397DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
398DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
399
400/* VIA Apollo VP3 needs ETBF on BT848/878 */
401static void quirk_viaetbf(struct pci_dev *dev)
402{
403 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
404 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
405 pci_pci_problems |= PCIPCI_VIAETBF;
406 }
407}
408DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
409
410static void quirk_vsfx(struct pci_dev *dev)
411{
412 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
413 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
414 pci_pci_problems |= PCIPCI_VSFX;
415 }
416}
417DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
418
419/*
420 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP
421 * space. Latency must be set to 0xA and Triton workaround applied too.
422 * [Info kindly provided by ALi]
423 */
424static void quirk_alimagik(struct pci_dev *dev)
425{
426 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
427 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
428 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
429 }
430}
431DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
432DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
433
434/* Natoma has some interesting boundary conditions with Zoran stuff at least */
435static void quirk_natoma(struct pci_dev *dev)
436{
437 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
438 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
439 pci_pci_problems |= PCIPCI_NATOMA;
440 }
441}
442DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
443DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
444DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
445DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
446DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
447DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
448
449/*
450 * This chip can cause PCI parity errors if config register 0xA0 is read
451 * while DMAs are occurring.
452 */
453static void quirk_citrine(struct pci_dev *dev)
454{
455 dev->cfg_size = 0xA0;
456}
457DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
458
459/*
460 * This chip can cause bus lockups if config addresses above 0x600
461 * are read or written.
462 */
463static void quirk_nfp6000(struct pci_dev *dev)
464{
465 dev->cfg_size = 0x600;
466}
467DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
468DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
469DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000);
470DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
471
472/* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
473static void quirk_extend_bar_to_page(struct pci_dev *dev)
474{
475 int i;
476
477 for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {
478 struct resource *r = &dev->resource[i];
479
480 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
481 r->end = PAGE_SIZE - 1;
482 r->start = 0;
483 r->flags |= IORESOURCE_UNSET;
484 pci_info(dev, "expanded BAR %d to page size: %pR\n",
485 i, r);
486 }
487 }
488}
489DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
490
491/*
492 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
493 * If it's needed, re-allocate the region.
494 */
495static void quirk_s3_64M(struct pci_dev *dev)
496{
497 struct resource *r = &dev->resource[0];
498
499 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
500 r->flags |= IORESOURCE_UNSET;
501 r->start = 0;
502 r->end = 0x3ffffff;
503 }
504}
505DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
506DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
507
508static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
509 const char *name)
510{
511 u32 region;
512 struct pci_bus_region bus_region;
513 struct resource *res = dev->resource + pos;
514
515 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion);
516
517 if (!region)
518 return;
519
520 res->name = pci_name(dev);
521 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
522 res->flags |=
523 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
524 region &= ~(size - 1);
525
526 /* Convert from PCI bus to resource space */
527 bus_region.start = region;
528 bus_region.end = region + size - 1;
529 pcibios_bus_to_resource(dev->bus, res, &bus_region);
530
531 pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
532 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
533}
534
535/*
536 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
537 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
538 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
539 * (which conflicts w/ BAR1's memory range).
540 *
541 * CS553x's ISA PCI BARs may also be read-only (ref:
542 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
543 */
544static void quirk_cs5536_vsa(struct pci_dev *dev)
545{
546 static char *name = "CS5536 ISA bridge";
547
548 if (pci_resource_len(dev, 0) != 8) {
549 quirk_io(dev, 0, 8, name); /* SMB */
550 quirk_io(dev, 1, 256, name); /* GPIO */
551 quirk_io(dev, 2, 64, name); /* MFGPT */
552 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n",
553 name);
554 }
555}
556DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
557
558static void quirk_io_region(struct pci_dev *dev, int port,
559 unsigned size, int nr, const char *name)
560{
561 u16 region;
562 struct pci_bus_region bus_region;
563 struct resource *res = dev->resource + nr;
564
565 pci_read_config_word(dev, port, ®ion);
566 region &= ~(size - 1);
567
568 if (!region)
569 return;
570
571 res->name = pci_name(dev);
572 res->flags = IORESOURCE_IO;
573
574 /* Convert from PCI bus to resource space */
575 bus_region.start = region;
576 bus_region.end = region + size - 1;
577 pcibios_bus_to_resource(dev->bus, res, &bus_region);
578
579 if (!pci_claim_resource(dev, nr))
580 pci_info(dev, "quirk: %pR claimed by %s\n", res, name);
581}
582
583/*
584 * ATI Northbridge setups MCE the processor if you even read somewhere
585 * between 0x3b0->0x3bb or read 0x3d3
586 */
587static void quirk_ati_exploding_mce(struct pci_dev *dev)
588{
589 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
590 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
591 request_region(0x3b0, 0x0C, "RadeonIGP");
592 request_region(0x3d3, 0x01, "RadeonIGP");
593}
594DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
595
596/*
597 * In the AMD NL platform, this device ([1022:7912]) has a class code of
598 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
599 * claim it.
600 *
601 * But the dwc3 driver is a more specific driver for this device, and we'd
602 * prefer to use it instead of xhci. To prevent xhci from claiming the
603 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
604 * defines as "USB device (not host controller)". The dwc3 driver can then
605 * claim it based on its Vendor and Device ID.
606 */
607static void quirk_amd_nl_class(struct pci_dev *pdev)
608{
609 u32 class = pdev->class;
610
611 /* Use "USB Device (not host controller)" class */
612 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
613 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
614 class, pdev->class);
615}
616DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
617 quirk_amd_nl_class);
618
619/*
620 * Synopsys USB 3.x host HAPS platform has a class code of
621 * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these
622 * devices should use dwc3-haps driver. Change these devices' class code to
623 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
624 * them.
625 */
626static void quirk_synopsys_haps(struct pci_dev *pdev)
627{
628 u32 class = pdev->class;
629
630 switch (pdev->device) {
631 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3:
632 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI:
633 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31:
634 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
635 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
636 class, pdev->class);
637 break;
638 }
639}
640DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID,
641 PCI_CLASS_SERIAL_USB_XHCI, 0,
642 quirk_synopsys_haps);
643
644/*
645 * Let's make the southbridge information explicit instead of having to
646 * worry about people probing the ACPI areas, for example.. (Yes, it
647 * happens, and if you read the wrong ACPI register it will put the machine
648 * to sleep with no way of waking it up again. Bummer).
649 *
650 * ALI M7101: Two IO regions pointed to by words at
651 * 0xE0 (64 bytes of ACPI registers)
652 * 0xE2 (32 bytes of SMB registers)
653 */
654static void quirk_ali7101_acpi(struct pci_dev *dev)
655{
656 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
657 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
658}
659DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
660
661static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
662{
663 u32 devres;
664 u32 mask, size, base;
665
666 pci_read_config_dword(dev, port, &devres);
667 if ((devres & enable) != enable)
668 return;
669 mask = (devres >> 16) & 15;
670 base = devres & 0xffff;
671 size = 16;
672 for (;;) {
673 unsigned bit = size >> 1;
674 if ((bit & mask) == bit)
675 break;
676 size = bit;
677 }
678 /*
679 * For now we only print it out. Eventually we'll want to
680 * reserve it (at least if it's in the 0x1000+ range), but
681 * let's get enough confirmation reports first.
682 */
683 base &= -size;
684 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
685}
686
687static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
688{
689 u32 devres;
690 u32 mask, size, base;
691
692 pci_read_config_dword(dev, port, &devres);
693 if ((devres & enable) != enable)
694 return;
695 base = devres & 0xffff0000;
696 mask = (devres & 0x3f) << 16;
697 size = 128 << 16;
698 for (;;) {
699 unsigned bit = size >> 1;
700 if ((bit & mask) == bit)
701 break;
702 size = bit;
703 }
704
705 /*
706 * For now we only print it out. Eventually we'll want to
707 * reserve it, but let's get enough confirmation reports first.
708 */
709 base &= -size;
710 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
711}
712
713/*
714 * PIIX4 ACPI: Two IO regions pointed to by longwords at
715 * 0x40 (64 bytes of ACPI registers)
716 * 0x90 (16 bytes of SMB registers)
717 * and a few strange programmable PIIX4 device resources.
718 */
719static void quirk_piix4_acpi(struct pci_dev *dev)
720{
721 u32 res_a;
722
723 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
724 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
725
726 /* Device resource A has enables for some of the other ones */
727 pci_read_config_dword(dev, 0x5c, &res_a);
728
729 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
730 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
731
732 /* Device resource D is just bitfields for static resources */
733
734 /* Device 12 enabled? */
735 if (res_a & (1 << 29)) {
736 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
737 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
738 }
739 /* Device 13 enabled? */
740 if (res_a & (1 << 30)) {
741 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
742 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
743 }
744 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
745 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
746}
747DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
748DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
749
750#define ICH_PMBASE 0x40
751#define ICH_ACPI_CNTL 0x44
752#define ICH4_ACPI_EN 0x10
753#define ICH6_ACPI_EN 0x80
754#define ICH4_GPIOBASE 0x58
755#define ICH4_GPIO_CNTL 0x5c
756#define ICH4_GPIO_EN 0x10
757#define ICH6_GPIOBASE 0x48
758#define ICH6_GPIO_CNTL 0x4c
759#define ICH6_GPIO_EN 0x10
760
761/*
762 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
763 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
764 * 0x58 (64 bytes of GPIO I/O space)
765 */
766static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
767{
768 u8 enable;
769
770 /*
771 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
772 * with low legacy (and fixed) ports. We don't know the decoding
773 * priority and can't tell whether the legacy device or the one created
774 * here is really at that address. This happens on boards with broken
775 * BIOSes.
776 */
777 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
778 if (enable & ICH4_ACPI_EN)
779 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
780 "ICH4 ACPI/GPIO/TCO");
781
782 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
783 if (enable & ICH4_GPIO_EN)
784 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
785 "ICH4 GPIO");
786}
787DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
788DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
789DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
790DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
791DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
792DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
793DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
794DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
795DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
796DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
797
798static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
799{
800 u8 enable;
801
802 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
803 if (enable & ICH6_ACPI_EN)
804 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
805 "ICH6 ACPI/GPIO/TCO");
806
807 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
808 if (enable & ICH6_GPIO_EN)
809 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
810 "ICH6 GPIO");
811}
812
813static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
814 const char *name, int dynsize)
815{
816 u32 val;
817 u32 size, base;
818
819 pci_read_config_dword(dev, reg, &val);
820
821 /* Enabled? */
822 if (!(val & 1))
823 return;
824 base = val & 0xfffc;
825 if (dynsize) {
826 /*
827 * This is not correct. It is 16, 32 or 64 bytes depending on
828 * register D31:F0:ADh bits 5:4.
829 *
830 * But this gets us at least _part_ of it.
831 */
832 size = 16;
833 } else {
834 size = 128;
835 }
836 base &= ~(size-1);
837
838 /*
839 * Just print it out for now. We should reserve it after more
840 * debugging.
841 */
842 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
843}
844
845static void quirk_ich6_lpc(struct pci_dev *dev)
846{
847 /* Shared ACPI/GPIO decode with all ICH6+ */
848 ich6_lpc_acpi_gpio(dev);
849
850 /* ICH6-specific generic IO decode */
851 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
852 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
853}
854DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
855DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
856
857static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
858 const char *name)
859{
860 u32 val;
861 u32 mask, base;
862
863 pci_read_config_dword(dev, reg, &val);
864
865 /* Enabled? */
866 if (!(val & 1))
867 return;
868
869 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */
870 base = val & 0xfffc;
871 mask = (val >> 16) & 0xfc;
872 mask |= 3;
873
874 /*
875 * Just print it out for now. We should reserve it after more
876 * debugging.
877 */
878 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
879}
880
881/* ICH7-10 has the same common LPC generic IO decode registers */
882static void quirk_ich7_lpc(struct pci_dev *dev)
883{
884 /* We share the common ACPI/GPIO decode with ICH6 */
885 ich6_lpc_acpi_gpio(dev);
886
887 /* And have 4 ICH7+ generic decodes */
888 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
889 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
890 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
891 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
892}
893DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
894DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
895DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
896DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
897DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
898DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
899DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
900DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
901DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
902DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
903DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
904DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
905DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
906
907/*
908 * VIA ACPI: One IO region pointed to by longword at
909 * 0x48 or 0x20 (256 bytes of ACPI registers)
910 */
911static void quirk_vt82c586_acpi(struct pci_dev *dev)
912{
913 if (dev->revision & 0x10)
914 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
915 "vt82c586 ACPI");
916}
917DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
918
919/*
920 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
921 * 0x48 (256 bytes of ACPI registers)
922 * 0x70 (128 bytes of hardware monitoring register)
923 * 0x90 (16 bytes of SMB registers)
924 */
925static void quirk_vt82c686_acpi(struct pci_dev *dev)
926{
927 quirk_vt82c586_acpi(dev);
928
929 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
930 "vt82c686 HW-mon");
931
932 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
933}
934DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
935
936/*
937 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
938 * 0x88 (128 bytes of power management registers)
939 * 0xd0 (16 bytes of SMB registers)
940 */
941static void quirk_vt8235_acpi(struct pci_dev *dev)
942{
943 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
944 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
945}
946DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
947
948/*
949 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
950 * back-to-back: Disable fast back-to-back on the secondary bus segment
951 */
952static void quirk_xio2000a(struct pci_dev *dev)
953{
954 struct pci_dev *pdev;
955 u16 command;
956
957 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
958 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
959 pci_read_config_word(pdev, PCI_COMMAND, &command);
960 if (command & PCI_COMMAND_FAST_BACK)
961 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
962 }
963}
964DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
965 quirk_xio2000a);
966
967#ifdef CONFIG_X86_IO_APIC
968
969#include <asm/io_apic.h>
970
971/*
972 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
973 * devices to the external APIC.
974 *
975 * TODO: When we have device-specific interrupt routers, this code will go
976 * away from quirks.
977 */
978static void quirk_via_ioapic(struct pci_dev *dev)
979{
980 u8 tmp;
981
982 if (nr_ioapics < 1)
983 tmp = 0; /* nothing routed to external APIC */
984 else
985 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
986
987 pci_info(dev, "%sbling VIA external APIC routing\n",
988 tmp == 0 ? "Disa" : "Ena");
989
990 /* Offset 0x58: External APIC IRQ output control */
991 pci_write_config_byte(dev, 0x58, tmp);
992}
993DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
994DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
995
996/*
997 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
998 * This leads to doubled level interrupt rates.
999 * Set this bit to get rid of cycle wastage.
1000 * Otherwise uncritical.
1001 */
1002static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
1003{
1004 u8 misc_control2;
1005#define BYPASS_APIC_DEASSERT 8
1006
1007 pci_read_config_byte(dev, 0x5B, &misc_control2);
1008 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
1009 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
1010 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
1011 }
1012}
1013DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
1014DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
1015
1016/*
1017 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
1018 * We check all revs >= B0 (yet not in the pre production!) as the bug
1019 * is currently marked NoFix
1020 *
1021 * We have multiple reports of hangs with this chipset that went away with
1022 * noapic specified. For the moment we assume it's the erratum. We may be wrong
1023 * of course. However the advice is demonstrably good even if so.
1024 */
1025static void quirk_amd_ioapic(struct pci_dev *dev)
1026{
1027 if (dev->revision >= 0x02) {
1028 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
1029 pci_warn(dev, " : booting with the \"noapic\" option\n");
1030 }
1031}
1032DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
1033#endif /* CONFIG_X86_IO_APIC */
1034
1035#if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
1036
1037static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
1038{
1039 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */
1040 if (dev->subsystem_device == 0xa118)
1041 dev->sriov->link = dev->devfn;
1042}
1043DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
1044#endif
1045
1046/*
1047 * Some settings of MMRBC can lead to data corruption so block changes.
1048 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1049 */
1050static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
1051{
1052 if (dev->subordinate && dev->revision <= 0x12) {
1053 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
1054 dev->revision);
1055 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
1056 }
1057}
1058DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
1059
1060/*
1061 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up
1062 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register
1063 * at all. Therefore it seems like setting the pci_dev's IRQ to the value
1064 * of the ACPI SCI interrupt is only done for convenience.
1065 * -jgarzik
1066 */
1067static void quirk_via_acpi(struct pci_dev *d)
1068{
1069 u8 irq;
1070
1071 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */
1072 pci_read_config_byte(d, 0x42, &irq);
1073 irq &= 0xf;
1074 if (irq && (irq != 2))
1075 d->irq = irq;
1076}
1077DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
1078DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
1079
1080/* VIA bridges which have VLink */
1081static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
1082
1083static void quirk_via_bridge(struct pci_dev *dev)
1084{
1085 /* See what bridge we have and find the device ranges */
1086 switch (dev->device) {
1087 case PCI_DEVICE_ID_VIA_82C686:
1088 /*
1089 * The VT82C686 is special; it attaches to PCI and can have
1090 * any device number. All its subdevices are functions of
1091 * that single device.
1092 */
1093 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
1094 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
1095 break;
1096 case PCI_DEVICE_ID_VIA_8237:
1097 case PCI_DEVICE_ID_VIA_8237A:
1098 via_vlink_dev_lo = 15;
1099 break;
1100 case PCI_DEVICE_ID_VIA_8235:
1101 via_vlink_dev_lo = 16;
1102 break;
1103 case PCI_DEVICE_ID_VIA_8231:
1104 case PCI_DEVICE_ID_VIA_8233_0:
1105 case PCI_DEVICE_ID_VIA_8233A:
1106 case PCI_DEVICE_ID_VIA_8233C_0:
1107 via_vlink_dev_lo = 17;
1108 break;
1109 }
1110}
1111DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
1112DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
1113DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
1114DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
1115DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
1116DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
1117DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
1118DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
1119
1120/*
1121 * quirk_via_vlink - VIA VLink IRQ number update
1122 * @dev: PCI device
1123 *
1124 * If the device we are dealing with is on a PIC IRQ we need to ensure that
1125 * the IRQ line register which usually is not relevant for PCI cards, is
1126 * actually written so that interrupts get sent to the right place.
1127 *
1128 * We only do this on systems where a VIA south bridge was detected, and
1129 * only for VIA devices on the motherboard (see quirk_via_bridge above).
1130 */
1131static void quirk_via_vlink(struct pci_dev *dev)
1132{
1133 u8 irq, new_irq;
1134
1135 /* Check if we have VLink at all */
1136 if (via_vlink_dev_lo == -1)
1137 return;
1138
1139 new_irq = dev->irq;
1140
1141 /* Don't quirk interrupts outside the legacy IRQ range */
1142 if (!new_irq || new_irq > 15)
1143 return;
1144
1145 /* Internal device ? */
1146 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
1147 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1148 return;
1149
1150 /*
1151 * This is an internal VLink device on a PIC interrupt. The BIOS
1152 * ought to have set this but may not have, so we redo it.
1153 */
1154 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1155 if (new_irq != irq) {
1156 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n",
1157 irq, new_irq);
1158 udelay(15); /* unknown if delay really needed */
1159 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
1160 }
1161}
1162DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
1163
1164/*
1165 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID
1166 * of VT82C597 for backward compatibility. We need to switch it off to be
1167 * able to recognize the real type of the chip.
1168 */
1169static void quirk_vt82c598_id(struct pci_dev *dev)
1170{
1171 pci_write_config_byte(dev, 0xfc, 0);
1172 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
1173}
1174DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
1175
1176/*
1177 * CardBus controllers have a legacy base address that enables them to
1178 * respond as i82365 pcmcia controllers. We don't want them to do this
1179 * even if the Linux CardBus driver is not loaded, because the Linux i82365
1180 * driver does not (and should not) handle CardBus.
1181 */
1182static void quirk_cardbus_legacy(struct pci_dev *dev)
1183{
1184 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
1185}
1186DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1187 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1188DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
1189 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1190
1191/*
1192 * Following the PCI ordering rules is optional on the AMD762. I'm not sure
1193 * what the designers were smoking but let's not inhale...
1194 *
1195 * To be fair to AMD, it follows the spec by default, it's BIOS people who
1196 * turn it off!
1197 */
1198static void quirk_amd_ordering(struct pci_dev *dev)
1199{
1200 u32 pcic;
1201 pci_read_config_dword(dev, 0x4C, &pcic);
1202 if ((pcic & 6) != 6) {
1203 pcic |= 6;
1204 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1205 pci_write_config_dword(dev, 0x4C, pcic);
1206 pci_read_config_dword(dev, 0x84, &pcic);
1207 pcic |= (1 << 23); /* Required in this mode */
1208 pci_write_config_dword(dev, 0x84, pcic);
1209 }
1210}
1211DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1212DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1213
1214/*
1215 * DreamWorks-provided workaround for Dunord I-3000 problem
1216 *
1217 * This card decodes and responds to addresses not apparently assigned to
1218 * it. We force a larger allocation to ensure that nothing gets put too
1219 * close to it.
1220 */
1221static void quirk_dunord(struct pci_dev *dev)
1222{
1223 struct resource *r = &dev->resource[1];
1224
1225 r->flags |= IORESOURCE_UNSET;
1226 r->start = 0;
1227 r->end = 0xffffff;
1228}
1229DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1230
1231/*
1232 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1233 * decoding (transparent), and does indicate this in the ProgIf.
1234 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1235 */
1236static void quirk_transparent_bridge(struct pci_dev *dev)
1237{
1238 dev->transparent = 1;
1239}
1240DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1241DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1242
1243/*
1244 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
1245 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets
1246 * found at http://www.national.com/analog for info on what these bits do.
1247 * <christer@weinigel.se>
1248 */
1249static void quirk_mediagx_master(struct pci_dev *dev)
1250{
1251 u8 reg;
1252
1253 pci_read_config_byte(dev, 0x41, ®);
1254 if (reg & 2) {
1255 reg &= ~2;
1256 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1257 reg);
1258 pci_write_config_byte(dev, 0x41, reg);
1259 }
1260}
1261DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1262DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1263
1264/*
1265 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but
1266 * in the odd case it is not the results are corruption hence the presence
1267 * of a Linux check.
1268 */
1269static void quirk_disable_pxb(struct pci_dev *pdev)
1270{
1271 u16 config;
1272
1273 if (pdev->revision != 0x04) /* Only C0 requires this */
1274 return;
1275 pci_read_config_word(pdev, 0x40, &config);
1276 if (config & (1<<6)) {
1277 config &= ~(1<<6);
1278 pci_write_config_word(pdev, 0x40, config);
1279 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n");
1280 }
1281}
1282DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1283DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1284
1285static void quirk_amd_ide_mode(struct pci_dev *pdev)
1286{
1287 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1288 u8 tmp;
1289
1290 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1291 if (tmp == 0x01) {
1292 pci_read_config_byte(pdev, 0x40, &tmp);
1293 pci_write_config_byte(pdev, 0x40, tmp|1);
1294 pci_write_config_byte(pdev, 0x9, 1);
1295 pci_write_config_byte(pdev, 0xa, 6);
1296 pci_write_config_byte(pdev, 0x40, tmp);
1297
1298 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1299 pci_info(pdev, "set SATA to AHCI mode\n");
1300 }
1301}
1302DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1303DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1304DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1305DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1306DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1307DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1308DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1309DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1310
1311/* Serverworks CSB5 IDE does not fully support native mode */
1312static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1313{
1314 u8 prog;
1315 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1316 if (prog & 5) {
1317 prog &= ~5;
1318 pdev->class &= ~5;
1319 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1320 /* PCI layer will sort out resources */
1321 }
1322}
1323DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1324
1325/* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
1326static void quirk_ide_samemode(struct pci_dev *pdev)
1327{
1328 u8 prog;
1329
1330 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1331
1332 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1333 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n");
1334 prog &= ~5;
1335 pdev->class &= ~5;
1336 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1337 }
1338}
1339DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1340
1341/* Some ATA devices break if put into D3 */
1342static void quirk_no_ata_d3(struct pci_dev *pdev)
1343{
1344 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1345}
1346/* Quirk the legacy ATA devices only. The AHCI ones are ok */
1347DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1348 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1349DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1350 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1351/* ALi loses some register settings that we cannot then restore */
1352DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1353 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1354/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1355 occur when mode detecting */
1356DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1357 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1358
1359/*
1360 * This was originally an Alpha-specific thing, but it really fits here.
1361 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1362 */
1363static void quirk_eisa_bridge(struct pci_dev *dev)
1364{
1365 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1366}
1367DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1368
1369/*
1370 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1371 * is not activated. The myth is that Asus said that they do not want the
1372 * users to be irritated by just another PCI Device in the Win98 device
1373 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1374 * package 2.7.0 for details)
1375 *
1376 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1377 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1378 * becomes necessary to do this tweak in two steps -- the chosen trigger
1379 * is either the Host bridge (preferred) or on-board VGA controller.
1380 *
1381 * Note that we used to unhide the SMBus that way on Toshiba laptops
1382 * (Satellite A40 and Tecra M2) but then found that the thermal management
1383 * was done by SMM code, which could cause unsynchronized concurrent
1384 * accesses to the SMBus registers, with potentially bad effects. Thus you
1385 * should be very careful when adding new entries: if SMM is accessing the
1386 * Intel SMBus, this is a very good reason to leave it hidden.
1387 *
1388 * Likewise, many recent laptops use ACPI for thermal management. If the
1389 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1390 * natively, and keeping the SMBus hidden is the right thing to do. If you
1391 * are about to add an entry in the table below, please first disassemble
1392 * the DSDT and double-check that there is no code accessing the SMBus.
1393 */
1394static int asus_hides_smbus;
1395
1396static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1397{
1398 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1399 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1400 switch (dev->subsystem_device) {
1401 case 0x8025: /* P4B-LX */
1402 case 0x8070: /* P4B */
1403 case 0x8088: /* P4B533 */
1404 case 0x1626: /* L3C notebook */
1405 asus_hides_smbus = 1;
1406 }
1407 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1408 switch (dev->subsystem_device) {
1409 case 0x80b1: /* P4GE-V */
1410 case 0x80b2: /* P4PE */
1411 case 0x8093: /* P4B533-V */
1412 asus_hides_smbus = 1;
1413 }
1414 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1415 switch (dev->subsystem_device) {
1416 case 0x8030: /* P4T533 */
1417 asus_hides_smbus = 1;
1418 }
1419 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1420 switch (dev->subsystem_device) {
1421 case 0x8070: /* P4G8X Deluxe */
1422 asus_hides_smbus = 1;
1423 }
1424 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1425 switch (dev->subsystem_device) {
1426 case 0x80c9: /* PU-DLS */
1427 asus_hides_smbus = 1;
1428 }
1429 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1430 switch (dev->subsystem_device) {
1431 case 0x1751: /* M2N notebook */
1432 case 0x1821: /* M5N notebook */
1433 case 0x1897: /* A6L notebook */
1434 asus_hides_smbus = 1;
1435 }
1436 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1437 switch (dev->subsystem_device) {
1438 case 0x184b: /* W1N notebook */
1439 case 0x186a: /* M6Ne notebook */
1440 asus_hides_smbus = 1;
1441 }
1442 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1443 switch (dev->subsystem_device) {
1444 case 0x80f2: /* P4P800-X */
1445 asus_hides_smbus = 1;
1446 }
1447 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1448 switch (dev->subsystem_device) {
1449 case 0x1882: /* M6V notebook */
1450 case 0x1977: /* A6VA notebook */
1451 asus_hides_smbus = 1;
1452 }
1453 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1454 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1455 switch (dev->subsystem_device) {
1456 case 0x088C: /* HP Compaq nc8000 */
1457 case 0x0890: /* HP Compaq nc6000 */
1458 asus_hides_smbus = 1;
1459 }
1460 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1461 switch (dev->subsystem_device) {
1462 case 0x12bc: /* HP D330L */
1463 case 0x12bd: /* HP D530 */
1464 case 0x006a: /* HP Compaq nx9500 */
1465 asus_hides_smbus = 1;
1466 }
1467 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1468 switch (dev->subsystem_device) {
1469 case 0x12bf: /* HP xw4100 */
1470 asus_hides_smbus = 1;
1471 }
1472 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1473 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1474 switch (dev->subsystem_device) {
1475 case 0xC00C: /* Samsung P35 notebook */
1476 asus_hides_smbus = 1;
1477 }
1478 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1479 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1480 switch (dev->subsystem_device) {
1481 case 0x0058: /* Compaq Evo N620c */
1482 asus_hides_smbus = 1;
1483 }
1484 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1485 switch (dev->subsystem_device) {
1486 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1487 /* Motherboard doesn't have Host bridge
1488 * subvendor/subdevice IDs, therefore checking
1489 * its on-board VGA controller */
1490 asus_hides_smbus = 1;
1491 }
1492 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1493 switch (dev->subsystem_device) {
1494 case 0x00b8: /* Compaq Evo D510 CMT */
1495 case 0x00b9: /* Compaq Evo D510 SFF */
1496 case 0x00ba: /* Compaq Evo D510 USDT */
1497 /* Motherboard doesn't have Host bridge
1498 * subvendor/subdevice IDs and on-board VGA
1499 * controller is disabled if an AGP card is
1500 * inserted, therefore checking USB UHCI
1501 * Controller #1 */
1502 asus_hides_smbus = 1;
1503 }
1504 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1505 switch (dev->subsystem_device) {
1506 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1507 /* Motherboard doesn't have host bridge
1508 * subvendor/subdevice IDs, therefore checking
1509 * its on-board VGA controller */
1510 asus_hides_smbus = 1;
1511 }
1512 }
1513}
1514DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1515DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1516DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1517DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1518DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1519DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1520DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1521DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1522DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1523DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1524
1525DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1526DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1527DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1528
1529static void asus_hides_smbus_lpc(struct pci_dev *dev)
1530{
1531 u16 val;
1532
1533 if (likely(!asus_hides_smbus))
1534 return;
1535
1536 pci_read_config_word(dev, 0xF2, &val);
1537 if (val & 0x8) {
1538 pci_write_config_word(dev, 0xF2, val & (~0x8));
1539 pci_read_config_word(dev, 0xF2, &val);
1540 if (val & 0x8)
1541 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1542 val);
1543 else
1544 pci_info(dev, "Enabled i801 SMBus device\n");
1545 }
1546}
1547DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1548DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1549DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1550DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1551DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1552DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1553DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1554DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1555DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1556DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1557DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1558DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1559DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1560DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1561
1562/* It appears we just have one such device. If not, we have a warning */
1563static void __iomem *asus_rcba_base;
1564static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1565{
1566 u32 rcba;
1567
1568 if (likely(!asus_hides_smbus))
1569 return;
1570 WARN_ON(asus_rcba_base);
1571
1572 pci_read_config_dword(dev, 0xF0, &rcba);
1573 /* use bits 31:14, 16 kB aligned */
1574 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1575 if (asus_rcba_base == NULL)
1576 return;
1577}
1578
1579static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1580{
1581 u32 val;
1582
1583 if (likely(!asus_hides_smbus || !asus_rcba_base))
1584 return;
1585
1586 /* read the Function Disable register, dword mode only */
1587 val = readl(asus_rcba_base + 0x3418);
1588
1589 /* enable the SMBus device */
1590 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
1591}
1592
1593static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1594{
1595 if (likely(!asus_hides_smbus || !asus_rcba_base))
1596 return;
1597
1598 iounmap(asus_rcba_base);
1599 asus_rcba_base = NULL;
1600 pci_info(dev, "Enabled ICH6/i801 SMBus device\n");
1601}
1602
1603static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1604{
1605 asus_hides_smbus_lpc_ich6_suspend(dev);
1606 asus_hides_smbus_lpc_ich6_resume_early(dev);
1607 asus_hides_smbus_lpc_ich6_resume(dev);
1608}
1609DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1610DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1611DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1612DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1613
1614/* SiS 96x south bridge: BIOS typically hides SMBus device... */
1615static void quirk_sis_96x_smbus(struct pci_dev *dev)
1616{
1617 u8 val = 0;
1618 pci_read_config_byte(dev, 0x77, &val);
1619 if (val & 0x10) {
1620 pci_info(dev, "Enabling SiS 96x SMBus\n");
1621 pci_write_config_byte(dev, 0x77, val & ~0x10);
1622 }
1623}
1624DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1625DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1626DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1627DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1628DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1629DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1630DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1631DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1632
1633/*
1634 * ... This is further complicated by the fact that some SiS96x south
1635 * bridges pretend to be 85C503/5513 instead. In that case see if we
1636 * spotted a compatible north bridge to make sure.
1637 * (pci_find_device() doesn't work yet)
1638 *
1639 * We can also enable the sis96x bit in the discovery register..
1640 */
1641#define SIS_DETECT_REGISTER 0x40
1642
1643static void quirk_sis_503(struct pci_dev *dev)
1644{
1645 u8 reg;
1646 u16 devid;
1647
1648 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1649 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1650 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1651 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1652 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1653 return;
1654 }
1655
1656 /*
1657 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case
1658 * it has already been processed. (Depends on link order, which is
1659 * apparently not guaranteed)
1660 */
1661 dev->device = devid;
1662 quirk_sis_96x_smbus(dev);
1663}
1664DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1665DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1666
1667/*
1668 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1669 * and MC97 modem controller are disabled when a second PCI soundcard is
1670 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1671 * -- bjd
1672 */
1673static void asus_hides_ac97_lpc(struct pci_dev *dev)
1674{
1675 u8 val;
1676 int asus_hides_ac97 = 0;
1677
1678 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1679 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1680 asus_hides_ac97 = 1;
1681 }
1682
1683 if (!asus_hides_ac97)
1684 return;
1685
1686 pci_read_config_byte(dev, 0x50, &val);
1687 if (val & 0xc0) {
1688 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1689 pci_read_config_byte(dev, 0x50, &val);
1690 if (val & 0xc0)
1691 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1692 val);
1693 else
1694 pci_info(dev, "Enabled onboard AC97/MC97 devices\n");
1695 }
1696}
1697DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1698DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1699
1700#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1701
1702/*
1703 * If we are using libata we can drive this chip properly but must do this
1704 * early on to make the additional device appear during the PCI scanning.
1705 */
1706static void quirk_jmicron_ata(struct pci_dev *pdev)
1707{
1708 u32 conf1, conf5, class;
1709 u8 hdr;
1710
1711 /* Only poke fn 0 */
1712 if (PCI_FUNC(pdev->devfn))
1713 return;
1714
1715 pci_read_config_dword(pdev, 0x40, &conf1);
1716 pci_read_config_dword(pdev, 0x80, &conf5);
1717
1718 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1719 conf5 &= ~(1 << 24); /* Clear bit 24 */
1720
1721 switch (pdev->device) {
1722 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1723 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1724 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1725 /* The controller should be in single function ahci mode */
1726 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1727 break;
1728
1729 case PCI_DEVICE_ID_JMICRON_JMB365:
1730 case PCI_DEVICE_ID_JMICRON_JMB366:
1731 /* Redirect IDE second PATA port to the right spot */
1732 conf5 |= (1 << 24);
1733 /* Fall through */
1734 case PCI_DEVICE_ID_JMICRON_JMB361:
1735 case PCI_DEVICE_ID_JMICRON_JMB363:
1736 case PCI_DEVICE_ID_JMICRON_JMB369:
1737 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1738 /* Set the class codes correctly and then direct IDE 0 */
1739 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1740 break;
1741
1742 case PCI_DEVICE_ID_JMICRON_JMB368:
1743 /* The controller should be in single function IDE mode */
1744 conf1 |= 0x00C00000; /* Set 22, 23 */
1745 break;
1746 }
1747
1748 pci_write_config_dword(pdev, 0x40, conf1);
1749 pci_write_config_dword(pdev, 0x80, conf5);
1750
1751 /* Update pdev accordingly */
1752 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1753 pdev->hdr_type = hdr & 0x7f;
1754 pdev->multifunction = !!(hdr & 0x80);
1755
1756 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1757 pdev->class = class >> 8;
1758}
1759DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1760DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1761DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1762DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1763DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1764DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1765DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1766DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1767DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1768DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1769DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1770DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1771DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1772DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1773DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1774DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1775DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1776DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1777
1778#endif
1779
1780static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1781{
1782 if (dev->multifunction) {
1783 device_disable_async_suspend(&dev->dev);
1784 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1785 }
1786}
1787DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1788DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1789DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1790DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1791
1792#ifdef CONFIG_X86_IO_APIC
1793static void quirk_alder_ioapic(struct pci_dev *pdev)
1794{
1795 int i;
1796
1797 if ((pdev->class >> 8) != 0xff00)
1798 return;
1799
1800 /*
1801 * The first BAR is the location of the IO-APIC... we must
1802 * not touch this (and it's already covered by the fixmap), so
1803 * forcibly insert it into the resource tree.
1804 */
1805 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1806 insert_resource(&iomem_resource, &pdev->resource[0]);
1807
1808 /*
1809 * The next five BARs all seem to be rubbish, so just clean
1810 * them out.
1811 */
1812 for (i = 1; i < 6; i++)
1813 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1814}
1815DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1816#endif
1817
1818static void quirk_pcie_mch(struct pci_dev *pdev)
1819{
1820 pdev->no_msi = 1;
1821}
1822DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1823DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1824DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1825
1826DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
1827
1828/*
1829 * It's possible for the MSI to get corrupted if SHPC and ACPI are used
1830 * together on certain PXH-based systems.
1831 */
1832static void quirk_pcie_pxh(struct pci_dev *dev)
1833{
1834 dev->no_msi = 1;
1835 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n");
1836}
1837DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1838DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1839DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1840DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1841DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1842
1843/*
1844 * Some Intel PCI Express chipsets have trouble with downstream device
1845 * power management.
1846 */
1847static void quirk_intel_pcie_pm(struct pci_dev *dev)
1848{
1849 pci_pm_d3_delay = 120;
1850 dev->no_d1d2 = 1;
1851}
1852DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1853DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1854DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1855DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1856DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1857DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1858DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1859DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1860DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1861DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1862DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1863DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1864DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1865DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1866DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1867DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1868DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1869DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1870DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1871DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1872DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1873
1874static void quirk_radeon_pm(struct pci_dev *dev)
1875{
1876 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1877 dev->subsystem_device == 0x00e2) {
1878 if (dev->d3_delay < 20) {
1879 dev->d3_delay = 20;
1880 pci_info(dev, "extending delay after power-on from D3 to %d msec\n",
1881 dev->d3_delay);
1882 }
1883 }
1884}
1885DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
1886
1887#ifdef CONFIG_X86_IO_APIC
1888static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
1889{
1890 noioapicreroute = 1;
1891 pr_info("%s detected: disable boot interrupt reroute\n", d->ident);
1892
1893 return 0;
1894}
1895
1896static const struct dmi_system_id boot_interrupt_dmi_table[] = {
1897 /*
1898 * Systems to exclude from boot interrupt reroute quirks
1899 */
1900 {
1901 .callback = dmi_disable_ioapicreroute,
1902 .ident = "ASUSTek Computer INC. M2N-LR",
1903 .matches = {
1904 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."),
1905 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
1906 },
1907 },
1908 {}
1909};
1910
1911/*
1912 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1913 * remap the original interrupt in the Linux kernel to the boot interrupt, so
1914 * that a PCI device's interrupt handler is installed on the boot interrupt
1915 * line instead.
1916 */
1917static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1918{
1919 dmi_check_system(boot_interrupt_dmi_table);
1920 if (noioapicquirk || noioapicreroute)
1921 return;
1922
1923 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1924 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n",
1925 dev->vendor, dev->device);
1926}
1927DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1928DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1929DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1930DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1931DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1932DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1933DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1934DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1935DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1936DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1937DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1938DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1939DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1940DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1941DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1942DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1943
1944/*
1945 * On some chipsets we can disable the generation of legacy INTx boot
1946 * interrupts.
1947 */
1948
1949/*
1950 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
1951 * 300641-004US, section 5.7.3.
1952 */
1953#define INTEL_6300_IOAPIC_ABAR 0x40
1954#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1955
1956static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1957{
1958 u16 pci_config_word;
1959
1960 if (noioapicquirk)
1961 return;
1962
1963 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1964 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1965 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1966
1967 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
1968 dev->vendor, dev->device);
1969}
1970DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1971DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1972
1973/* Disable boot interrupts on HT-1000 */
1974#define BC_HT1000_FEATURE_REG 0x64
1975#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1976#define BC_HT1000_MAP_IDX 0xC00
1977#define BC_HT1000_MAP_DATA 0xC01
1978
1979static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1980{
1981 u32 pci_config_dword;
1982 u8 irq;
1983
1984 if (noioapicquirk)
1985 return;
1986
1987 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1988 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1989 BC_HT1000_PIC_REGS_ENABLE);
1990
1991 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1992 outb(irq, BC_HT1000_MAP_IDX);
1993 outb(0x00, BC_HT1000_MAP_DATA);
1994 }
1995
1996 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1997
1998 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
1999 dev->vendor, dev->device);
2000}
2001DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
2002DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
2003
2004/* Disable boot interrupts on AMD and ATI chipsets */
2005
2006/*
2007 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
2008 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
2009 * (due to an erratum).
2010 */
2011#define AMD_813X_MISC 0x40
2012#define AMD_813X_NOIOAMODE (1<<0)
2013#define AMD_813X_REV_B1 0x12
2014#define AMD_813X_REV_B2 0x13
2015
2016static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
2017{
2018 u32 pci_config_dword;
2019
2020 if (noioapicquirk)
2021 return;
2022 if ((dev->revision == AMD_813X_REV_B1) ||
2023 (dev->revision == AMD_813X_REV_B2))
2024 return;
2025
2026 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
2027 pci_config_dword &= ~AMD_813X_NOIOAMODE;
2028 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
2029
2030 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2031 dev->vendor, dev->device);
2032}
2033DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2034DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2035DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2036DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2037
2038#define AMD_8111_PCI_IRQ_ROUTING 0x56
2039
2040static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
2041{
2042 u16 pci_config_word;
2043
2044 if (noioapicquirk)
2045 return;
2046
2047 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
2048 if (!pci_config_word) {
2049 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n",
2050 dev->vendor, dev->device);
2051 return;
2052 }
2053 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
2054 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2055 dev->vendor, dev->device);
2056}
2057DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
2058DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
2059#endif /* CONFIG_X86_IO_APIC */
2060
2061/*
2062 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2063 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
2064 * Re-allocate the region if needed...
2065 */
2066static void quirk_tc86c001_ide(struct pci_dev *dev)
2067{
2068 struct resource *r = &dev->resource[0];
2069
2070 if (r->start & 0x8) {
2071 r->flags |= IORESOURCE_UNSET;
2072 r->start = 0;
2073 r->end = 0xf;
2074 }
2075}
2076DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
2077 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
2078 quirk_tc86c001_ide);
2079
2080/*
2081 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
2082 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
2083 * being read correctly if bit 7 of the base address is set.
2084 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
2085 * Re-allocate the regions to a 256-byte boundary if necessary.
2086 */
2087static void quirk_plx_pci9050(struct pci_dev *dev)
2088{
2089 unsigned int bar;
2090
2091 /* Fixed in revision 2 (PCI 9052). */
2092 if (dev->revision >= 2)
2093 return;
2094 for (bar = 0; bar <= 1; bar++)
2095 if (pci_resource_len(dev, bar) == 0x80 &&
2096 (pci_resource_start(dev, bar) & 0x80)) {
2097 struct resource *r = &dev->resource[bar];
2098 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
2099 bar);
2100 r->flags |= IORESOURCE_UNSET;
2101 r->start = 0;
2102 r->end = 0xff;
2103 }
2104}
2105DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2106 quirk_plx_pci9050);
2107/*
2108 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
2109 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
2110 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
2111 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
2112 *
2113 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
2114 * driver.
2115 */
2116DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
2117DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
2118
2119static void quirk_netmos(struct pci_dev *dev)
2120{
2121 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
2122 unsigned int num_serial = dev->subsystem_device & 0xf;
2123
2124 /*
2125 * These Netmos parts are multiport serial devices with optional
2126 * parallel ports. Even when parallel ports are present, they
2127 * are identified as class SERIAL, which means the serial driver
2128 * will claim them. To prevent this, mark them as class OTHER.
2129 * These combo devices should be claimed by parport_serial.
2130 *
2131 * The subdevice ID is of the form 0x00PS, where <P> is the number
2132 * of parallel ports and <S> is the number of serial ports.
2133 */
2134 switch (dev->device) {
2135 case PCI_DEVICE_ID_NETMOS_9835:
2136 /* Well, this rule doesn't hold for the following 9835 device */
2137 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
2138 dev->subsystem_device == 0x0299)
2139 return;
2140 /* else, fall through */
2141 case PCI_DEVICE_ID_NETMOS_9735:
2142 case PCI_DEVICE_ID_NETMOS_9745:
2143 case PCI_DEVICE_ID_NETMOS_9845:
2144 case PCI_DEVICE_ID_NETMOS_9855:
2145 if (num_parallel) {
2146 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
2147 dev->device, num_parallel, num_serial);
2148 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
2149 (dev->class & 0xff);
2150 }
2151 }
2152}
2153DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
2154 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
2155
2156static void quirk_e100_interrupt(struct pci_dev *dev)
2157{
2158 u16 command, pmcsr;
2159 u8 __iomem *csr;
2160 u8 cmd_hi;
2161
2162 switch (dev->device) {
2163 /* PCI IDs taken from drivers/net/e100.c */
2164 case 0x1029:
2165 case 0x1030 ... 0x1034:
2166 case 0x1038 ... 0x103E:
2167 case 0x1050 ... 0x1057:
2168 case 0x1059:
2169 case 0x1064 ... 0x106B:
2170 case 0x1091 ... 0x1095:
2171 case 0x1209:
2172 case 0x1229:
2173 case 0x2449:
2174 case 0x2459:
2175 case 0x245D:
2176 case 0x27DC:
2177 break;
2178 default:
2179 return;
2180 }
2181
2182 /*
2183 * Some firmware hands off the e100 with interrupts enabled,
2184 * which can cause a flood of interrupts if packets are
2185 * received before the driver attaches to the device. So
2186 * disable all e100 interrupts here. The driver will
2187 * re-enable them when it's ready.
2188 */
2189 pci_read_config_word(dev, PCI_COMMAND, &command);
2190
2191 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
2192 return;
2193
2194 /*
2195 * Check that the device is in the D0 power state. If it's not,
2196 * there is no point to look any further.
2197 */
2198 if (dev->pm_cap) {
2199 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2200 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
2201 return;
2202 }
2203
2204 /* Convert from PCI bus to resource space. */
2205 csr = ioremap(pci_resource_start(dev, 0), 8);
2206 if (!csr) {
2207 pci_warn(dev, "Can't map e100 registers\n");
2208 return;
2209 }
2210
2211 cmd_hi = readb(csr + 3);
2212 if (cmd_hi == 0) {
2213 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n");
2214 writeb(1, csr + 3);
2215 }
2216
2217 iounmap(csr);
2218}
2219DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2220 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
2221
2222/*
2223 * The 82575 and 82598 may experience data corruption issues when transitioning
2224 * out of L0S. To prevent this we need to disable L0S on the PCIe link.
2225 */
2226static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2227{
2228 pci_info(dev, "Disabling L0s\n");
2229 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2230}
2231DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2232DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2233DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2234DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2235DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2236DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2237DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2238DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2239DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2240DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2241DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2242DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2243DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2244DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2245
2246/*
2247 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2248 * Link bit cleared after starting the link retrain process to allow this
2249 * process to finish.
2250 *
2251 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the
2252 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf.
2253 */
2254static void quirk_enable_clear_retrain_link(struct pci_dev *dev)
2255{
2256 dev->clear_retrain_link = 1;
2257 pci_info(dev, "Enable PCIe Retrain Link quirk\n");
2258}
2259DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe110, quirk_enable_clear_retrain_link);
2260DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe111, quirk_enable_clear_retrain_link);
2261DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe130, quirk_enable_clear_retrain_link);
2262
2263static void fixup_rev1_53c810(struct pci_dev *dev)
2264{
2265 u32 class = dev->class;
2266
2267 /*
2268 * rev 1 ncr53c810 chips don't set the class at all which means
2269 * they don't get their resources remapped. Fix that here.
2270 */
2271 if (class)
2272 return;
2273
2274 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2275 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2276 class, dev->class);
2277}
2278DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2279
2280/* Enable 1k I/O space granularity on the Intel P64H2 */
2281static void quirk_p64h2_1k_io(struct pci_dev *dev)
2282{
2283 u16 en1k;
2284
2285 pci_read_config_word(dev, 0x40, &en1k);
2286
2287 if (en1k & 0x200) {
2288 pci_info(dev, "Enable I/O Space to 1KB granularity\n");
2289 dev->io_window_1k = 1;
2290 }
2291}
2292DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2293
2294/*
2295 * Under some circumstances, AER is not linked with extended capabilities.
2296 * Force it to be linked by setting the corresponding control bit in the
2297 * config space.
2298 */
2299static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2300{
2301 uint8_t b;
2302
2303 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2304 if (!(b & 0x20)) {
2305 pci_write_config_byte(dev, 0xf41, b | 0x20);
2306 pci_info(dev, "Linking AER extended capability\n");
2307 }
2308 }
2309}
2310DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2311 quirk_nvidia_ck804_pcie_aer_ext_cap);
2312DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2313 quirk_nvidia_ck804_pcie_aer_ext_cap);
2314
2315static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2316{
2317 /*
2318 * Disable PCI Bus Parking and PCI Master read caching on CX700
2319 * which causes unspecified timing errors with a VT6212L on the PCI
2320 * bus leading to USB2.0 packet loss.
2321 *
2322 * This quirk is only enabled if a second (on the external PCI bus)
2323 * VT6212L is found -- the CX700 core itself also contains a USB
2324 * host controller with the same PCI ID as the VT6212L.
2325 */
2326
2327 /* Count VT6212L instances */
2328 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2329 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2330 uint8_t b;
2331
2332 /*
2333 * p should contain the first (internal) VT6212L -- see if we have
2334 * an external one by searching again.
2335 */
2336 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2337 if (!p)
2338 return;
2339 pci_dev_put(p);
2340
2341 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2342 if (b & 0x40) {
2343 /* Turn off PCI Bus Parking */
2344 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2345
2346 pci_info(dev, "Disabling VIA CX700 PCI parking\n");
2347 }
2348 }
2349
2350 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2351 if (b != 0) {
2352 /* Turn off PCI Master read caching */
2353 pci_write_config_byte(dev, 0x72, 0x0);
2354
2355 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2356 pci_write_config_byte(dev, 0x75, 0x1);
2357
2358 /* Disable "Read FIFO Timer" */
2359 pci_write_config_byte(dev, 0x77, 0x0);
2360
2361 pci_info(dev, "Disabling VIA CX700 PCI caching\n");
2362 }
2363 }
2364}
2365DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2366
2367static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2368{
2369 u32 rev;
2370
2371 pci_read_config_dword(dev, 0xf4, &rev);
2372
2373 /* Only CAP the MRRS if the device is a 5719 A0 */
2374 if (rev == 0x05719000) {
2375 int readrq = pcie_get_readrq(dev);
2376 if (readrq > 2048)
2377 pcie_set_readrq(dev, 2048);
2378 }
2379}
2380DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2381 PCI_DEVICE_ID_TIGON3_5719,
2382 quirk_brcm_5719_limit_mrrs);
2383
2384#ifdef CONFIG_PCIE_IPROC_PLATFORM
2385static void quirk_paxc_bridge(struct pci_dev *pdev)
2386{
2387 /*
2388 * The PCI config space is shared with the PAXC root port and the first
2389 * Ethernet device. So, we need to workaround this by telling the PCI
2390 * code that the bridge is not an Ethernet device.
2391 */
2392 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2393 pdev->class = PCI_CLASS_BRIDGE_PCI << 8;
2394
2395 /*
2396 * MPSS is not being set properly (as it is currently 0). This is
2397 * because that area of the PCI config space is hard coded to zero, and
2398 * is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS)
2399 * so that the MPS can be set to the real max value.
2400 */
2401 pdev->pcie_mpss = 2;
2402}
2403DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);
2404DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);
2405DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd750, quirk_paxc_bridge);
2406DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd802, quirk_paxc_bridge);
2407DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd804, quirk_paxc_bridge);
2408#endif
2409
2410/*
2411 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to
2412 * hide device 6 which configures the overflow device access containing the
2413 * DRBs - this is where we expose device 6.
2414 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2415 */
2416static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2417{
2418 u8 reg;
2419
2420 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) {
2421 pci_info(dev, "Enabling MCH 'Overflow' Device\n");
2422 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2423 }
2424}
2425DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2426 quirk_unhide_mch_dev6);
2427DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2428 quirk_unhide_mch_dev6);
2429
2430#ifdef CONFIG_PCI_MSI
2431/*
2432 * Some chipsets do not support MSI. We cannot easily rely on setting
2433 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some
2434 * other buses controlled by the chipset even if Linux is not aware of it.
2435 * Instead of setting the flag on all buses in the machine, simply disable
2436 * MSI globally.
2437 */
2438static void quirk_disable_all_msi(struct pci_dev *dev)
2439{
2440 pci_no_msi();
2441 pci_warn(dev, "MSI quirk detected; MSI disabled\n");
2442}
2443DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2444DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2445DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2446DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2447DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2448DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2449DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2450DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2451
2452/* Disable MSI on chipsets that are known to not support it */
2453static void quirk_disable_msi(struct pci_dev *dev)
2454{
2455 if (dev->subordinate) {
2456 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2457 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2458 }
2459}
2460DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2461DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2462DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2463
2464/*
2465 * The APC bridge device in AMD 780 family northbridges has some random
2466 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2467 * we use the possible vendor/device IDs of the host bridge for the
2468 * declared quirk, and search for the APC bridge by slot number.
2469 */
2470static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2471{
2472 struct pci_dev *apc_bridge;
2473
2474 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2475 if (apc_bridge) {
2476 if (apc_bridge->device == 0x9602)
2477 quirk_disable_msi(apc_bridge);
2478 pci_dev_put(apc_bridge);
2479 }
2480}
2481DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2482DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2483
2484/*
2485 * Go through the list of HyperTransport capabilities and return 1 if a HT
2486 * MSI capability is found and enabled.
2487 */
2488static int msi_ht_cap_enabled(struct pci_dev *dev)
2489{
2490 int pos, ttl = PCI_FIND_CAP_TTL;
2491
2492 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2493 while (pos && ttl--) {
2494 u8 flags;
2495
2496 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2497 &flags) == 0) {
2498 pci_info(dev, "Found %s HT MSI Mapping\n",
2499 flags & HT_MSI_FLAGS_ENABLE ?
2500 "enabled" : "disabled");
2501 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2502 }
2503
2504 pos = pci_find_next_ht_capability(dev, pos,
2505 HT_CAPTYPE_MSI_MAPPING);
2506 }
2507 return 0;
2508}
2509
2510/* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */
2511static void quirk_msi_ht_cap(struct pci_dev *dev)
2512{
2513 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2514 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2515 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2516 }
2517}
2518DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2519 quirk_msi_ht_cap);
2520
2521/*
2522 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported
2523 * if the MSI capability is set in any of these mappings.
2524 */
2525static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2526{
2527 struct pci_dev *pdev;
2528
2529 if (!dev->subordinate)
2530 return;
2531
2532 /*
2533 * Check HT MSI cap on this chipset and the root one. A single one
2534 * having MSI is enough to be sure that MSI is supported.
2535 */
2536 pdev = pci_get_slot(dev->bus, 0);
2537 if (!pdev)
2538 return;
2539 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2540 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2541 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2542 }
2543 pci_dev_put(pdev);
2544}
2545DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2546 quirk_nvidia_ck804_msi_ht_cap);
2547
2548/* Force enable MSI mapping capability on HT bridges */
2549static void ht_enable_msi_mapping(struct pci_dev *dev)
2550{
2551 int pos, ttl = PCI_FIND_CAP_TTL;
2552
2553 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2554 while (pos && ttl--) {
2555 u8 flags;
2556
2557 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2558 &flags) == 0) {
2559 pci_info(dev, "Enabling HT MSI Mapping\n");
2560
2561 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2562 flags | HT_MSI_FLAGS_ENABLE);
2563 }
2564 pos = pci_find_next_ht_capability(dev, pos,
2565 HT_CAPTYPE_MSI_MAPPING);
2566 }
2567}
2568DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2569 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2570 ht_enable_msi_mapping);
2571DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2572 ht_enable_msi_mapping);
2573
2574/*
2575 * The P5N32-SLI motherboards from Asus have a problem with MSI
2576 * for the MCP55 NIC. It is not yet determined whether the MSI problem
2577 * also affects other devices. As for now, turn off MSI for this device.
2578 */
2579static void nvenet_msi_disable(struct pci_dev *dev)
2580{
2581 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2582
2583 if (board_name &&
2584 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2585 strstr(board_name, "P5N32-E SLI"))) {
2586 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
2587 dev->no_msi = 1;
2588 }
2589}
2590DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2591 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2592 nvenet_msi_disable);
2593
2594/*
2595 * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled,
2596 * then the device can't use INTx interrupts. Tegra's PCIe root ports don't
2597 * generate MSI interrupts for PME and AER events instead only INTx interrupts
2598 * are generated. Though Tegra's PCIe root ports can generate MSI interrupts
2599 * for other events, since PCIe specificiation doesn't support using a mix of
2600 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
2601 * service drivers registering their respective ISRs for MSIs.
2602 */
2603static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev)
2604{
2605 dev->no_msi = 1;
2606}
2607DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0,
2608 PCI_CLASS_BRIDGE_PCI, 8,
2609 pci_quirk_nvidia_tegra_disable_rp_msi);
2610DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1,
2611 PCI_CLASS_BRIDGE_PCI, 8,
2612 pci_quirk_nvidia_tegra_disable_rp_msi);
2613DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2,
2614 PCI_CLASS_BRIDGE_PCI, 8,
2615 pci_quirk_nvidia_tegra_disable_rp_msi);
2616DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0,
2617 PCI_CLASS_BRIDGE_PCI, 8,
2618 pci_quirk_nvidia_tegra_disable_rp_msi);
2619DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1,
2620 PCI_CLASS_BRIDGE_PCI, 8,
2621 pci_quirk_nvidia_tegra_disable_rp_msi);
2622DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c,
2623 PCI_CLASS_BRIDGE_PCI, 8,
2624 pci_quirk_nvidia_tegra_disable_rp_msi);
2625DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d,
2626 PCI_CLASS_BRIDGE_PCI, 8,
2627 pci_quirk_nvidia_tegra_disable_rp_msi);
2628DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12,
2629 PCI_CLASS_BRIDGE_PCI, 8,
2630 pci_quirk_nvidia_tegra_disable_rp_msi);
2631DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13,
2632 PCI_CLASS_BRIDGE_PCI, 8,
2633 pci_quirk_nvidia_tegra_disable_rp_msi);
2634DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae,
2635 PCI_CLASS_BRIDGE_PCI, 8,
2636 pci_quirk_nvidia_tegra_disable_rp_msi);
2637DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf,
2638 PCI_CLASS_BRIDGE_PCI, 8,
2639 pci_quirk_nvidia_tegra_disable_rp_msi);
2640DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,
2641 PCI_CLASS_BRIDGE_PCI, 8,
2642 pci_quirk_nvidia_tegra_disable_rp_msi);
2643DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,
2644 PCI_CLASS_BRIDGE_PCI, 8,
2645 pci_quirk_nvidia_tegra_disable_rp_msi);
2646
2647/*
2648 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2649 * config register. This register controls the routing of legacy
2650 * interrupts from devices that route through the MCP55. If this register
2651 * is misprogrammed, interrupts are only sent to the BSP, unlike
2652 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2653 * having this register set properly prevents kdump from booting up
2654 * properly, so let's make sure that we have it set correctly.
2655 * Note that this is an undocumented register.
2656 */
2657static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2658{
2659 u32 cfg;
2660
2661 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2662 return;
2663
2664 pci_read_config_dword(dev, 0x74, &cfg);
2665
2666 if (cfg & ((1 << 2) | (1 << 15))) {
2667 pr_info("Rewriting IRQ routing register on MCP55\n");
2668 cfg &= ~((1 << 2) | (1 << 15));
2669 pci_write_config_dword(dev, 0x74, cfg);
2670 }
2671}
2672DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2673 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2674 nvbridge_check_legacy_irq_routing);
2675DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2676 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2677 nvbridge_check_legacy_irq_routing);
2678
2679static int ht_check_msi_mapping(struct pci_dev *dev)
2680{
2681 int pos, ttl = PCI_FIND_CAP_TTL;
2682 int found = 0;
2683
2684 /* Check if there is HT MSI cap or enabled on this device */
2685 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2686 while (pos && ttl--) {
2687 u8 flags;
2688
2689 if (found < 1)
2690 found = 1;
2691 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2692 &flags) == 0) {
2693 if (flags & HT_MSI_FLAGS_ENABLE) {
2694 if (found < 2) {
2695 found = 2;
2696 break;
2697 }
2698 }
2699 }
2700 pos = pci_find_next_ht_capability(dev, pos,
2701 HT_CAPTYPE_MSI_MAPPING);
2702 }
2703
2704 return found;
2705}
2706
2707static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2708{
2709 struct pci_dev *dev;
2710 int pos;
2711 int i, dev_no;
2712 int found = 0;
2713
2714 dev_no = host_bridge->devfn >> 3;
2715 for (i = dev_no + 1; i < 0x20; i++) {
2716 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2717 if (!dev)
2718 continue;
2719
2720 /* found next host bridge? */
2721 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2722 if (pos != 0) {
2723 pci_dev_put(dev);
2724 break;
2725 }
2726
2727 if (ht_check_msi_mapping(dev)) {
2728 found = 1;
2729 pci_dev_put(dev);
2730 break;
2731 }
2732 pci_dev_put(dev);
2733 }
2734
2735 return found;
2736}
2737
2738#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2739#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2740
2741static int is_end_of_ht_chain(struct pci_dev *dev)
2742{
2743 int pos, ctrl_off;
2744 int end = 0;
2745 u16 flags, ctrl;
2746
2747 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2748
2749 if (!pos)
2750 goto out;
2751
2752 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2753
2754 ctrl_off = ((flags >> 10) & 1) ?
2755 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2756 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2757
2758 if (ctrl & (1 << 6))
2759 end = 1;
2760
2761out:
2762 return end;
2763}
2764
2765static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2766{
2767 struct pci_dev *host_bridge;
2768 int pos;
2769 int i, dev_no;
2770 int found = 0;
2771
2772 dev_no = dev->devfn >> 3;
2773 for (i = dev_no; i >= 0; i--) {
2774 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2775 if (!host_bridge)
2776 continue;
2777
2778 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2779 if (pos != 0) {
2780 found = 1;
2781 break;
2782 }
2783 pci_dev_put(host_bridge);
2784 }
2785
2786 if (!found)
2787 return;
2788
2789 /* don't enable end_device/host_bridge with leaf directly here */
2790 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2791 host_bridge_with_leaf(host_bridge))
2792 goto out;
2793
2794 /* root did that ! */
2795 if (msi_ht_cap_enabled(host_bridge))
2796 goto out;
2797
2798 ht_enable_msi_mapping(dev);
2799
2800out:
2801 pci_dev_put(host_bridge);
2802}
2803
2804static void ht_disable_msi_mapping(struct pci_dev *dev)
2805{
2806 int pos, ttl = PCI_FIND_CAP_TTL;
2807
2808 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2809 while (pos && ttl--) {
2810 u8 flags;
2811
2812 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2813 &flags) == 0) {
2814 pci_info(dev, "Disabling HT MSI Mapping\n");
2815
2816 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2817 flags & ~HT_MSI_FLAGS_ENABLE);
2818 }
2819 pos = pci_find_next_ht_capability(dev, pos,
2820 HT_CAPTYPE_MSI_MAPPING);
2821 }
2822}
2823
2824static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2825{
2826 struct pci_dev *host_bridge;
2827 int pos;
2828 int found;
2829
2830 if (!pci_msi_enabled())
2831 return;
2832
2833 /* check if there is HT MSI cap or enabled on this device */
2834 found = ht_check_msi_mapping(dev);
2835
2836 /* no HT MSI CAP */
2837 if (found == 0)
2838 return;
2839
2840 /*
2841 * HT MSI mapping should be disabled on devices that are below
2842 * a non-Hypertransport host bridge. Locate the host bridge...
2843 */
2844 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
2845 PCI_DEVFN(0, 0));
2846 if (host_bridge == NULL) {
2847 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2848 return;
2849 }
2850
2851 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2852 if (pos != 0) {
2853 /* Host bridge is to HT */
2854 if (found == 1) {
2855 /* it is not enabled, try to enable it */
2856 if (all)
2857 ht_enable_msi_mapping(dev);
2858 else
2859 nv_ht_enable_msi_mapping(dev);
2860 }
2861 goto out;
2862 }
2863
2864 /* HT MSI is not enabled */
2865 if (found == 1)
2866 goto out;
2867
2868 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2869 ht_disable_msi_mapping(dev);
2870
2871out:
2872 pci_dev_put(host_bridge);
2873}
2874
2875static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2876{
2877 return __nv_msi_ht_cap_quirk(dev, 1);
2878}
2879DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2880DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2881
2882static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2883{
2884 return __nv_msi_ht_cap_quirk(dev, 0);
2885}
2886DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2887DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2888
2889static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2890{
2891 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2892}
2893
2894static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2895{
2896 struct pci_dev *p;
2897
2898 /*
2899 * SB700 MSI issue will be fixed at HW level from revision A21;
2900 * we need check PCI REVISION ID of SMBus controller to get SB700
2901 * revision.
2902 */
2903 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2904 NULL);
2905 if (!p)
2906 return;
2907
2908 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2909 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2910 pci_dev_put(p);
2911}
2912
2913static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2914{
2915 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2916 if (dev->revision < 0x18) {
2917 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n");
2918 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2919 }
2920}
2921DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2922 PCI_DEVICE_ID_TIGON3_5780,
2923 quirk_msi_intx_disable_bug);
2924DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2925 PCI_DEVICE_ID_TIGON3_5780S,
2926 quirk_msi_intx_disable_bug);
2927DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2928 PCI_DEVICE_ID_TIGON3_5714,
2929 quirk_msi_intx_disable_bug);
2930DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2931 PCI_DEVICE_ID_TIGON3_5714S,
2932 quirk_msi_intx_disable_bug);
2933DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2934 PCI_DEVICE_ID_TIGON3_5715,
2935 quirk_msi_intx_disable_bug);
2936DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2937 PCI_DEVICE_ID_TIGON3_5715S,
2938 quirk_msi_intx_disable_bug);
2939
2940DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2941 quirk_msi_intx_disable_ati_bug);
2942DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2943 quirk_msi_intx_disable_ati_bug);
2944DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2945 quirk_msi_intx_disable_ati_bug);
2946DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2947 quirk_msi_intx_disable_ati_bug);
2948DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2949 quirk_msi_intx_disable_ati_bug);
2950
2951DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2952 quirk_msi_intx_disable_bug);
2953DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2954 quirk_msi_intx_disable_bug);
2955DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2956 quirk_msi_intx_disable_bug);
2957
2958DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2959 quirk_msi_intx_disable_bug);
2960DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2961 quirk_msi_intx_disable_bug);
2962DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2963 quirk_msi_intx_disable_bug);
2964DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2965 quirk_msi_intx_disable_bug);
2966DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2967 quirk_msi_intx_disable_bug);
2968DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2969 quirk_msi_intx_disable_bug);
2970DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
2971 quirk_msi_intx_disable_qca_bug);
2972DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
2973 quirk_msi_intx_disable_qca_bug);
2974DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
2975 quirk_msi_intx_disable_qca_bug);
2976DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
2977 quirk_msi_intx_disable_qca_bug);
2978DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2979 quirk_msi_intx_disable_qca_bug);
2980
2981/*
2982 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
2983 * should be disabled on platforms where the device (mistakenly) advertises it.
2984 *
2985 * Notice that this quirk also disables MSI (which may work, but hasn't been
2986 * tested), since currently there is no standard way to disable only MSI-X.
2987 *
2988 * The 0031 device id is reused for other non Root Port device types,
2989 * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
2990 */
2991static void quirk_al_msi_disable(struct pci_dev *dev)
2992{
2993 dev->no_msi = 1;
2994 pci_warn(dev, "Disabling MSI/MSI-X\n");
2995}
2996DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
2997 PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable);
2998#endif /* CONFIG_PCI_MSI */
2999
3000/*
3001 * Allow manual resource allocation for PCI hotplug bridges via
3002 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
3003 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to
3004 * allocate resources when hotplug device is inserted and PCI bus is
3005 * rescanned.
3006 */
3007static void quirk_hotplug_bridge(struct pci_dev *dev)
3008{
3009 dev->is_hotplug_bridge = 1;
3010}
3011DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
3012
3013/*
3014 * This is a quirk for the Ricoh MMC controller found as a part of some
3015 * multifunction chips.
3016 *
3017 * This is very similar and based on the ricoh_mmc driver written by
3018 * Philip Langdale. Thank you for these magic sequences.
3019 *
3020 * These chips implement the four main memory card controllers (SD, MMC,
3021 * MS, xD) and one or both of CardBus or FireWire.
3022 *
3023 * It happens that they implement SD and MMC support as separate
3024 * controllers (and PCI functions). The Linux SDHCI driver supports MMC
3025 * cards but the chip detects MMC cards in hardware and directs them to the
3026 * MMC controller - so the SDHCI driver never sees them.
3027 *
3028 * To get around this, we must disable the useless MMC controller. At that
3029 * point, the SDHCI controller will start seeing them. It seems to be the
3030 * case that the relevant PCI registers to deactivate the MMC controller
3031 * live on PCI function 0, which might be the CardBus controller or the
3032 * FireWire controller, depending on the particular chip in question
3033 *
3034 * This has to be done early, because as soon as we disable the MMC controller
3035 * other PCI functions shift up one level, e.g. function #2 becomes function
3036 * #1, and this will confuse the PCI core.
3037 */
3038#ifdef CONFIG_MMC_RICOH_MMC
3039static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
3040{
3041 u8 write_enable;
3042 u8 write_target;
3043 u8 disable;
3044
3045 /*
3046 * Disable via CardBus interface
3047 *
3048 * This must be done via function #0
3049 */
3050 if (PCI_FUNC(dev->devfn))
3051 return;
3052
3053 pci_read_config_byte(dev, 0xB7, &disable);
3054 if (disable & 0x02)
3055 return;
3056
3057 pci_read_config_byte(dev, 0x8E, &write_enable);
3058 pci_write_config_byte(dev, 0x8E, 0xAA);
3059 pci_read_config_byte(dev, 0x8D, &write_target);
3060 pci_write_config_byte(dev, 0x8D, 0xB7);
3061 pci_write_config_byte(dev, 0xB7, disable | 0x02);
3062 pci_write_config_byte(dev, 0x8E, write_enable);
3063 pci_write_config_byte(dev, 0x8D, write_target);
3064
3065 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n");
3066 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3067}
3068DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3069DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3070
3071static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
3072{
3073 u8 write_enable;
3074 u8 disable;
3075
3076 /*
3077 * Disable via FireWire interface
3078 *
3079 * This must be done via function #0
3080 */
3081 if (PCI_FUNC(dev->devfn))
3082 return;
3083 /*
3084 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
3085 * certain types of SD/MMC cards. Lowering the SD base clock
3086 * frequency from 200Mhz to 50Mhz fixes this issue.
3087 *
3088 * 0x150 - SD2.0 mode enable for changing base clock
3089 * frequency to 50Mhz
3090 * 0xe1 - Base clock frequency
3091 * 0x32 - 50Mhz new clock frequency
3092 * 0xf9 - Key register for 0x150
3093 * 0xfc - key register for 0xe1
3094 */
3095 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
3096 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
3097 pci_write_config_byte(dev, 0xf9, 0xfc);
3098 pci_write_config_byte(dev, 0x150, 0x10);
3099 pci_write_config_byte(dev, 0xf9, 0x00);
3100 pci_write_config_byte(dev, 0xfc, 0x01);
3101 pci_write_config_byte(dev, 0xe1, 0x32);
3102 pci_write_config_byte(dev, 0xfc, 0x00);
3103
3104 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n");
3105 }
3106
3107 pci_read_config_byte(dev, 0xCB, &disable);
3108
3109 if (disable & 0x02)
3110 return;
3111
3112 pci_read_config_byte(dev, 0xCA, &write_enable);
3113 pci_write_config_byte(dev, 0xCA, 0x57);
3114 pci_write_config_byte(dev, 0xCB, disable | 0x02);
3115 pci_write_config_byte(dev, 0xCA, write_enable);
3116
3117 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n");
3118 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3119
3120}
3121DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3122DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3123DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3124DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3125DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3126DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3127#endif /*CONFIG_MMC_RICOH_MMC*/
3128
3129#ifdef CONFIG_DMAR_TABLE
3130#define VTUNCERRMSK_REG 0x1ac
3131#define VTD_MSK_SPEC_ERRORS (1 << 31)
3132/*
3133 * This is a quirk for masking VT-d spec-defined errors to platform error
3134 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets
3135 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
3136 * on the RAS config settings of the platform) when a VT-d fault happens.
3137 * The resulting SMI caused the system to hang.
3138 *
3139 * VT-d spec-related errors are already handled by the VT-d OS code, so no
3140 * need to report the same error through other channels.
3141 */
3142static void vtd_mask_spec_errors(struct pci_dev *dev)
3143{
3144 u32 word;
3145
3146 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
3147 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
3148}
3149DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
3150DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
3151#endif
3152
3153static void fixup_ti816x_class(struct pci_dev *dev)
3154{
3155 u32 class = dev->class;
3156
3157 /* TI 816x devices do not have class code set when in PCIe boot mode */
3158 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
3159 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
3160 class, dev->class);
3161}
3162DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
3163 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
3164
3165/*
3166 * Some PCIe devices do not work reliably with the claimed maximum
3167 * payload size supported.
3168 */
3169static void fixup_mpss_256(struct pci_dev *dev)
3170{
3171 dev->pcie_mpss = 1; /* 256 bytes */
3172}
3173DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3174 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
3175DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3176 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
3177DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3178 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
3179
3180/*
3181 * Intel 5000 and 5100 Memory controllers have an erratum with read completion
3182 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
3183 * Since there is no way of knowing what the PCIe MPS on each fabric will be
3184 * until all of the devices are discovered and buses walked, read completion
3185 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3186 * it is possible to hotplug a device with MPS of 256B.
3187 */
3188static void quirk_intel_mc_errata(struct pci_dev *dev)
3189{
3190 int err;
3191 u16 rcc;
3192
3193 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
3194 pcie_bus_config == PCIE_BUS_DEFAULT)
3195 return;
3196
3197 /*
3198 * Intel erratum specifies bits to change but does not say what
3199 * they are. Keeping them magical until such time as the registers
3200 * and values can be explained.
3201 */
3202 err = pci_read_config_word(dev, 0x48, &rcc);
3203 if (err) {
3204 pci_err(dev, "Error attempting to read the read completion coalescing register\n");
3205 return;
3206 }
3207
3208 if (!(rcc & (1 << 10)))
3209 return;
3210
3211 rcc &= ~(1 << 10);
3212
3213 err = pci_write_config_word(dev, 0x48, rcc);
3214 if (err) {
3215 pci_err(dev, "Error attempting to write the read completion coalescing register\n");
3216 return;
3217 }
3218
3219 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n");
3220}
3221/* Intel 5000 series memory controllers and ports 2-7 */
3222DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3223DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3224DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3225DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3226DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3227DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3228DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3229DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3230DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3231DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3232DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3233DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3234DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3235DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3236/* Intel 5100 series memory controllers and ports 2-7 */
3237DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3238DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3239DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3240DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3241DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3242DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3243DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3244DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3245DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3246DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3247DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3248
3249/*
3250 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
3251 * To work around this, query the size it should be configured to by the
3252 * device and modify the resource end to correspond to this new size.
3253 */
3254static void quirk_intel_ntb(struct pci_dev *dev)
3255{
3256 int rc;
3257 u8 val;
3258
3259 rc = pci_read_config_byte(dev, 0x00D0, &val);
3260 if (rc)
3261 return;
3262
3263 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3264
3265 rc = pci_read_config_byte(dev, 0x00D1, &val);
3266 if (rc)
3267 return;
3268
3269 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3270}
3271DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3272DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3273
3274/*
3275 * Some BIOS implementations leave the Intel GPU interrupts enabled, even
3276 * though no one is handling them (e.g., if the i915 driver is never
3277 * loaded). Additionally the interrupt destination is not set up properly
3278 * and the interrupt ends up -somewhere-.
3279 *
3280 * These spurious interrupts are "sticky" and the kernel disables the
3281 * (shared) interrupt line after 100,000+ generated interrupts.
3282 *
3283 * Fix it by disabling the still enabled interrupts. This resolves crashes
3284 * often seen on monitor unplug.
3285 */
3286#define I915_DEIER_REG 0x4400c
3287static void disable_igfx_irq(struct pci_dev *dev)
3288{
3289 void __iomem *regs = pci_iomap(dev, 0, 0);
3290 if (regs == NULL) {
3291 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n");
3292 return;
3293 }
3294
3295 /* Check if any interrupt line is still enabled */
3296 if (readl(regs + I915_DEIER_REG) != 0) {
3297 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3298
3299 writel(0, regs + I915_DEIER_REG);
3300 }
3301
3302 pci_iounmap(dev, regs);
3303}
3304DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
3305DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
3306DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
3307DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3308DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
3309DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3310DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3311
3312/*
3313 * PCI devices which are on Intel chips can skip the 10ms delay
3314 * before entering D3 mode.
3315 */
3316static void quirk_remove_d3_delay(struct pci_dev *dev)
3317{
3318 dev->d3_delay = 0;
3319}
3320/* C600 Series devices do not need 10ms d3_delay */
3321DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
3322DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
3323DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
3324/* Lynxpoint-H PCH devices do not need 10ms d3_delay */
3325DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
3326DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
3327DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
3328DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
3329DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
3330DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
3331DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
3332DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
3333DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
3334DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
3335DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
3336/* Intel Cherrytrail devices do not need 10ms d3_delay */
3337DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
3338DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
3339DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
3340DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
3341DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
3342DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
3343DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
3344DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
3345DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);
3346
3347/*
3348 * Some devices may pass our check in pci_intx_mask_supported() if
3349 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3350 * support this feature.
3351 */
3352static void quirk_broken_intx_masking(struct pci_dev *dev)
3353{
3354 dev->broken_intx_masking = 1;
3355}
3356DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3357 quirk_broken_intx_masking);
3358DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3359 quirk_broken_intx_masking);
3360DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
3361 quirk_broken_intx_masking);
3362
3363/*
3364 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3365 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3366 *
3367 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3368 */
3369DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3370 quirk_broken_intx_masking);
3371
3372/*
3373 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3374 * DisINTx can be set but the interrupt status bit is non-functional.
3375 */
3376DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking);
3377DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking);
3378DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking);
3379DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking);
3380DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking);
3381DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking);
3382DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking);
3383DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking);
3384DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking);
3385DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking);
3386DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking);
3387DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking);
3388DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking);
3389DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking);
3390DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking);
3391DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking);
3392
3393static u16 mellanox_broken_intx_devs[] = {
3394 PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
3395 PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
3396 PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
3397 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
3398 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
3399 PCI_DEVICE_ID_MELLANOX_HERMON_EN,
3400 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
3401 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
3402 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
3403 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
3404 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
3405 PCI_DEVICE_ID_MELLANOX_CONNECTX2,
3406 PCI_DEVICE_ID_MELLANOX_CONNECTX3,
3407 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
3408};
3409
3410#define CONNECTX_4_CURR_MAX_MINOR 99
3411#define CONNECTX_4_INTX_SUPPORT_MINOR 14
3412
3413/*
3414 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3415 * If so, don't mark it as broken.
3416 * FW minor > 99 means older FW version format and no INTx masking support.
3417 * FW minor < 14 means new FW version format and no INTx masking support.
3418 */
3419static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3420{
3421 __be32 __iomem *fw_ver;
3422 u16 fw_major;
3423 u16 fw_minor;
3424 u16 fw_subminor;
3425 u32 fw_maj_min;
3426 u32 fw_sub_min;
3427 int i;
3428
3429 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
3430 if (pdev->device == mellanox_broken_intx_devs[i]) {
3431 pdev->broken_intx_masking = 1;
3432 return;
3433 }
3434 }
3435
3436 /*
3437 * Getting here means Connect-IB cards and up. Connect-IB has no INTx
3438 * support so shouldn't be checked further
3439 */
3440 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
3441 return;
3442
3443 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
3444 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
3445 return;
3446
3447 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3448 if (pci_enable_device_mem(pdev)) {
3449 pci_warn(pdev, "Can't enable device memory\n");
3450 return;
3451 }
3452
3453 fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
3454 if (!fw_ver) {
3455 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n");
3456 goto out;
3457 }
3458
3459 /* Reading from resource space should be 32b aligned */
3460 fw_maj_min = ioread32be(fw_ver);
3461 fw_sub_min = ioread32be(fw_ver + 1);
3462 fw_major = fw_maj_min & 0xffff;
3463 fw_minor = fw_maj_min >> 16;
3464 fw_subminor = fw_sub_min & 0xffff;
3465 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
3466 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
3467 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3468 fw_major, fw_minor, fw_subminor, pdev->device ==
3469 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
3470 pdev->broken_intx_masking = 1;
3471 }
3472
3473 iounmap(fw_ver);
3474
3475out:
3476 pci_disable_device(pdev);
3477}
3478DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3479 mellanox_check_broken_intx_masking);
3480
3481static void quirk_no_bus_reset(struct pci_dev *dev)
3482{
3483 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3484}
3485
3486/*
3487 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3488 * The device will throw a Link Down error on AER-capable systems and
3489 * regardless of AER, config space of the device is never accessible again
3490 * and typically causes the system to hang or reset when access is attempted.
3491 * http://www.spinics.net/lists/linux-pci/msg34797.html
3492 */
3493DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3494DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3495DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3496DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3497DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
3498
3499/*
3500 * Root port on some Cavium CN8xxx chips do not successfully complete a bus
3501 * reset when used with certain child devices. After the reset, config
3502 * accesses to the child may fail.
3503 */
3504DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
3505
3506static void quirk_no_pm_reset(struct pci_dev *dev)
3507{
3508 /*
3509 * We can't do a bus reset on root bus devices, but an ineffective
3510 * PM reset may be better than nothing.
3511 */
3512 if (!pci_is_root_bus(dev->bus))
3513 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3514}
3515
3516/*
3517 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3518 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3519 * to have no effect on the device: it retains the framebuffer contents and
3520 * monitor sync. Advertising this support makes other layers, like VFIO,
3521 * assume pci_reset_function() is viable for this device. Mark it as
3522 * unavailable to skip it when testing reset methods.
3523 */
3524DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3525 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3526
3527/*
3528 * Thunderbolt controllers with broken MSI hotplug signaling:
3529 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3530 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3531 */
3532static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
3533{
3534 if (pdev->is_hotplug_bridge &&
3535 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3536 pdev->revision <= 1))
3537 pdev->no_msi = 1;
3538}
3539DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3540 quirk_thunderbolt_hotplug_msi);
3541DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
3542 quirk_thunderbolt_hotplug_msi);
3543DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
3544 quirk_thunderbolt_hotplug_msi);
3545DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3546 quirk_thunderbolt_hotplug_msi);
3547DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3548 quirk_thunderbolt_hotplug_msi);
3549
3550#ifdef CONFIG_ACPI
3551/*
3552 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3553 *
3554 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3555 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3556 * be present after resume if a device was plugged in before suspend.
3557 *
3558 * The Thunderbolt controller consists of a PCIe switch with downstream
3559 * bridges leading to the NHI and to the tunnel PCI bridges.
3560 *
3561 * This quirk cuts power to the whole chip. Therefore we have to apply it
3562 * during suspend_noirq of the upstream bridge.
3563 *
3564 * Power is automagically restored before resume. No action is needed.
3565 */
3566static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3567{
3568 acpi_handle bridge, SXIO, SXFP, SXLV;
3569
3570 if (!x86_apple_machine)
3571 return;
3572 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3573 return;
3574 bridge = ACPI_HANDLE(&dev->dev);
3575 if (!bridge)
3576 return;
3577
3578 /*
3579 * SXIO and SXLV are present only on machines requiring this quirk.
3580 * Thunderbolt bridges in external devices might have the same
3581 * device ID as those on the host, but they will not have the
3582 * associated ACPI methods. This implicitly checks that we are at
3583 * the right bridge.
3584 */
3585 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3586 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3587 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3588 return;
3589 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n");
3590
3591 /* magic sequence */
3592 acpi_execute_simple_method(SXIO, NULL, 1);
3593 acpi_execute_simple_method(SXFP, NULL, 0);
3594 msleep(300);
3595 acpi_execute_simple_method(SXLV, NULL, 0);
3596 acpi_execute_simple_method(SXIO, NULL, 0);
3597 acpi_execute_simple_method(SXLV, NULL, 0);
3598}
3599DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3600 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3601 quirk_apple_poweroff_thunderbolt);
3602
3603/*
3604 * Apple: Wait for the Thunderbolt controller to reestablish PCI tunnels
3605 *
3606 * During suspend the Thunderbolt controller is reset and all PCI
3607 * tunnels are lost. The NHI driver will try to reestablish all tunnels
3608 * during resume. We have to manually wait for the NHI since there is
3609 * no parent child relationship between the NHI and the tunneled
3610 * bridges.
3611 */
3612static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3613{
3614 struct pci_dev *sibling = NULL;
3615 struct pci_dev *nhi = NULL;
3616
3617 if (!x86_apple_machine)
3618 return;
3619 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3620 return;
3621
3622 /*
3623 * Find the NHI and confirm that we are a bridge on the Thunderbolt
3624 * host controller and not on a Thunderbolt endpoint.
3625 */
3626 sibling = pci_get_slot(dev->bus, 0x0);
3627 if (sibling == dev)
3628 goto out; /* we are the downstream bridge to the NHI */
3629 if (!sibling || !sibling->subordinate)
3630 goto out;
3631 nhi = pci_get_slot(sibling->subordinate, 0x0);
3632 if (!nhi)
3633 goto out;
3634 if (nhi->vendor != PCI_VENDOR_ID_INTEL
3635 || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE &&
3636 nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
3637 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI &&
3638 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
3639 || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
3640 goto out;
3641 pci_info(dev, "quirk: waiting for Thunderbolt to reestablish PCI tunnels...\n");
3642 device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3643out:
3644 pci_dev_put(nhi);
3645 pci_dev_put(sibling);
3646}
3647DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3648 PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3649 quirk_apple_wait_for_thunderbolt);
3650DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3651 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3652 quirk_apple_wait_for_thunderbolt);
3653DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3654 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE,
3655 quirk_apple_wait_for_thunderbolt);
3656DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3657 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE,
3658 quirk_apple_wait_for_thunderbolt);
3659#endif
3660
3661/*
3662 * Following are device-specific reset methods which can be used to
3663 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3664 * not available.
3665 */
3666static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3667{
3668 /*
3669 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3670 *
3671 * The 82599 supports FLR on VFs, but FLR support is reported only
3672 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3673 * Thus we must call pcie_flr() directly without first checking if it is
3674 * supported.
3675 */
3676 if (!probe)
3677 pcie_flr(dev);
3678 return 0;
3679}
3680
3681#define SOUTH_CHICKEN2 0xc2004
3682#define PCH_PP_STATUS 0xc7200
3683#define PCH_PP_CONTROL 0xc7204
3684#define MSG_CTL 0x45010
3685#define NSDE_PWR_STATE 0xd0100
3686#define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3687
3688static int reset_ivb_igd(struct pci_dev *dev, int probe)
3689{
3690 void __iomem *mmio_base;
3691 unsigned long timeout;
3692 u32 val;
3693
3694 if (probe)
3695 return 0;
3696
3697 mmio_base = pci_iomap(dev, 0, 0);
3698 if (!mmio_base)
3699 return -ENOMEM;
3700
3701 iowrite32(0x00000002, mmio_base + MSG_CTL);
3702
3703 /*
3704 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3705 * driver loaded sets the right bits. However, this's a reset and
3706 * the bits have been set by i915 previously, so we clobber
3707 * SOUTH_CHICKEN2 register directly here.
3708 */
3709 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3710
3711 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3712 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3713
3714 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3715 do {
3716 val = ioread32(mmio_base + PCH_PP_STATUS);
3717 if ((val & 0xb0000000) == 0)
3718 goto reset_complete;
3719 msleep(10);
3720 } while (time_before(jiffies, timeout));
3721 pci_warn(dev, "timeout during reset\n");
3722
3723reset_complete:
3724 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3725
3726 pci_iounmap(dev, mmio_base);
3727 return 0;
3728}
3729
3730/* Device-specific reset method for Chelsio T4-based adapters */
3731static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3732{
3733 u16 old_command;
3734 u16 msix_flags;
3735
3736 /*
3737 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3738 * that we have no device-specific reset method.
3739 */
3740 if ((dev->device & 0xf000) != 0x4000)
3741 return -ENOTTY;
3742
3743 /*
3744 * If this is the "probe" phase, return 0 indicating that we can
3745 * reset this device.
3746 */
3747 if (probe)
3748 return 0;
3749
3750 /*
3751 * T4 can wedge if there are DMAs in flight within the chip and Bus
3752 * Master has been disabled. We need to have it on till the Function
3753 * Level Reset completes. (BUS_MASTER is disabled in
3754 * pci_reset_function()).
3755 */
3756 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3757 pci_write_config_word(dev, PCI_COMMAND,
3758 old_command | PCI_COMMAND_MASTER);
3759
3760 /*
3761 * Perform the actual device function reset, saving and restoring
3762 * configuration information around the reset.
3763 */
3764 pci_save_state(dev);
3765
3766 /*
3767 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3768 * are disabled when an MSI-X interrupt message needs to be delivered.
3769 * So we briefly re-enable MSI-X interrupts for the duration of the
3770 * FLR. The pci_restore_state() below will restore the original
3771 * MSI-X state.
3772 */
3773 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3774 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3775 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3776 msix_flags |
3777 PCI_MSIX_FLAGS_ENABLE |
3778 PCI_MSIX_FLAGS_MASKALL);
3779
3780 pcie_flr(dev);
3781
3782 /*
3783 * Restore the configuration information (BAR values, etc.) including
3784 * the original PCI Configuration Space Command word, and return
3785 * success.
3786 */
3787 pci_restore_state(dev);
3788 pci_write_config_word(dev, PCI_COMMAND, old_command);
3789 return 0;
3790}
3791
3792#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3793#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3794#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3795
3796/*
3797 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after
3798 * FLR where config space reads from the device return -1. We seem to be
3799 * able to avoid this condition if we disable the NVMe controller prior to
3800 * FLR. This quirk is generic for any NVMe class device requiring similar
3801 * assistance to quiesce the device prior to FLR.
3802 *
3803 * NVMe specification: https://nvmexpress.org/resources/specifications/
3804 * Revision 1.0e:
3805 * Chapter 2: Required and optional PCI config registers
3806 * Chapter 3: NVMe control registers
3807 * Chapter 7.3: Reset behavior
3808 */
3809static int nvme_disable_and_flr(struct pci_dev *dev, int probe)
3810{
3811 void __iomem *bar;
3812 u16 cmd;
3813 u32 cfg;
3814
3815 if (dev->class != PCI_CLASS_STORAGE_EXPRESS ||
3816 !pcie_has_flr(dev) || !pci_resource_start(dev, 0))
3817 return -ENOTTY;
3818
3819 if (probe)
3820 return 0;
3821
3822 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg));
3823 if (!bar)
3824 return -ENOTTY;
3825
3826 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3827 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY);
3828
3829 cfg = readl(bar + NVME_REG_CC);
3830
3831 /* Disable controller if enabled */
3832 if (cfg & NVME_CC_ENABLE) {
3833 u32 cap = readl(bar + NVME_REG_CAP);
3834 unsigned long timeout;
3835
3836 /*
3837 * Per nvme_disable_ctrl() skip shutdown notification as it
3838 * could complete commands to the admin queue. We only intend
3839 * to quiesce the device before reset.
3840 */
3841 cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE);
3842
3843 writel(cfg, bar + NVME_REG_CC);
3844
3845 /*
3846 * Some controllers require an additional delay here, see
3847 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet
3848 * supported by this quirk.
3849 */
3850
3851 /* Cap register provides max timeout in 500ms increments */
3852 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
3853
3854 for (;;) {
3855 u32 status = readl(bar + NVME_REG_CSTS);
3856
3857 /* Ready status becomes zero on disable complete */
3858 if (!(status & NVME_CSTS_RDY))
3859 break;
3860
3861 msleep(100);
3862
3863 if (time_after(jiffies, timeout)) {
3864 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n");
3865 break;
3866 }
3867 }
3868 }
3869
3870 pci_iounmap(dev, bar);
3871
3872 pcie_flr(dev);
3873
3874 return 0;
3875}
3876
3877/*
3878 * Intel DC P3700 NVMe controller will timeout waiting for ready status
3879 * to change after NVMe enable if the driver starts interacting with the
3880 * device too soon after FLR. A 250ms delay after FLR has heuristically
3881 * proven to produce reliably working results for device assignment cases.
3882 */
3883static int delay_250ms_after_flr(struct pci_dev *dev, int probe)
3884{
3885 if (!pcie_has_flr(dev))
3886 return -ENOTTY;
3887
3888 if (probe)
3889 return 0;
3890
3891 pcie_flr(dev);
3892
3893 msleep(250);
3894
3895 return 0;
3896}
3897
3898static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3899 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3900 reset_intel_82599_sfp_virtfn },
3901 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3902 reset_ivb_igd },
3903 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3904 reset_ivb_igd },
3905 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr },
3906 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr },
3907 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3908 reset_chelsio_generic_dev },
3909 { 0 }
3910};
3911
3912/*
3913 * These device-specific reset methods are here rather than in a driver
3914 * because when a host assigns a device to a guest VM, the host may need
3915 * to reset the device but probably doesn't have a driver for it.
3916 */
3917int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3918{
3919 const struct pci_dev_reset_methods *i;
3920
3921 for (i = pci_dev_reset_methods; i->reset; i++) {
3922 if ((i->vendor == dev->vendor ||
3923 i->vendor == (u16)PCI_ANY_ID) &&
3924 (i->device == dev->device ||
3925 i->device == (u16)PCI_ANY_ID))
3926 return i->reset(dev, probe);
3927 }
3928
3929 return -ENOTTY;
3930}
3931
3932static void quirk_dma_func0_alias(struct pci_dev *dev)
3933{
3934 if (PCI_FUNC(dev->devfn) != 0)
3935 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
3936}
3937
3938/*
3939 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3940 *
3941 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
3942 */
3943DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
3944DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
3945
3946static void quirk_dma_func1_alias(struct pci_dev *dev)
3947{
3948 if (PCI_FUNC(dev->devfn) != 1)
3949 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1));
3950}
3951
3952/*
3953 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
3954 * SKUs function 1 is present and is a legacy IDE controller, in other
3955 * SKUs this function is not present, making this a ghost requester.
3956 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
3957 */
3958DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
3959 quirk_dma_func1_alias);
3960DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
3961 quirk_dma_func1_alias);
3962DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
3963 quirk_dma_func1_alias);
3964/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
3965DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
3966 quirk_dma_func1_alias);
3967DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170,
3968 quirk_dma_func1_alias);
3969/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
3970DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
3971 quirk_dma_func1_alias);
3972/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
3973DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
3974 quirk_dma_func1_alias);
3975/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
3976DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
3977 quirk_dma_func1_alias);
3978/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */
3979DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183,
3980 quirk_dma_func1_alias);
3981/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
3982DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
3983 quirk_dma_func1_alias);
3984/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
3985DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
3986 quirk_dma_func1_alias);
3987/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
3988DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
3989 quirk_dma_func1_alias);
3990DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
3991 quirk_dma_func1_alias);
3992DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
3993 quirk_dma_func1_alias);
3994/* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
3995DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
3996 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
3997 quirk_dma_func1_alias);
3998/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
3999DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4000 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
4001 quirk_dma_func1_alias);
4002
4003/*
4004 * Some devices DMA with the wrong devfn, not just the wrong function.
4005 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
4006 * the alias is "fixed" and independent of the device devfn.
4007 *
4008 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
4009 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
4010 * single device on the secondary bus. In reality, the single exposed
4011 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
4012 * that provides a bridge to the internal bus of the I/O processor. The
4013 * controller supports private devices, which can be hidden from PCI config
4014 * space. In the case of the Adaptec 3405, a private device at 01.0
4015 * appears to be the DMA engine, which therefore needs to become a DMA
4016 * alias for the device.
4017 */
4018static const struct pci_device_id fixed_dma_alias_tbl[] = {
4019 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4020 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
4021 .driver_data = PCI_DEVFN(1, 0) },
4022 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4023 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
4024 .driver_data = PCI_DEVFN(1, 0) },
4025 { 0 }
4026};
4027
4028static void quirk_fixed_dma_alias(struct pci_dev *dev)
4029{
4030 const struct pci_device_id *id;
4031
4032 id = pci_match_id(fixed_dma_alias_tbl, dev);
4033 if (id)
4034 pci_add_dma_alias(dev, id->driver_data);
4035}
4036
4037DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
4038
4039/*
4040 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
4041 * using the wrong DMA alias for the device. Some of these devices can be
4042 * used as either forward or reverse bridges, so we need to test whether the
4043 * device is operating in the correct mode. We could probably apply this
4044 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
4045 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
4046 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
4047 */
4048static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
4049{
4050 if (!pci_is_root_bus(pdev->bus) &&
4051 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4052 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
4053 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
4054 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
4055}
4056/* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
4057DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
4058 quirk_use_pcie_bridge_dma_alias);
4059/* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
4060DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
4061/* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
4062DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
4063/* ITE 8893 has the same problem as the 8892 */
4064DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
4065/* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
4066DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
4067
4068/*
4069 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
4070 * be added as aliases to the DMA device in order to allow buffer access
4071 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4072 * programmed in the EEPROM.
4073 */
4074static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
4075{
4076 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0));
4077 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0));
4078 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3));
4079}
4080DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
4081DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
4082
4083/*
4084 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
4085 * associated not at the root bus, but at a bridge below. This quirk avoids
4086 * generating invalid DMA aliases.
4087 */
4088static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
4089{
4090 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
4091}
4092DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
4093 quirk_bridge_cavm_thrx2_pcie_root);
4094DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
4095 quirk_bridge_cavm_thrx2_pcie_root);
4096
4097/*
4098 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4099 * class code. Fix it.
4100 */
4101static void quirk_tw686x_class(struct pci_dev *pdev)
4102{
4103 u32 class = pdev->class;
4104
4105 /* Use "Multimedia controller" class */
4106 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
4107 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
4108 class, pdev->class);
4109}
4110DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
4111 quirk_tw686x_class);
4112DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
4113 quirk_tw686x_class);
4114DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
4115 quirk_tw686x_class);
4116DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
4117 quirk_tw686x_class);
4118
4119/*
4120 * Some devices have problems with Transaction Layer Packets with the Relaxed
4121 * Ordering Attribute set. Such devices should mark themselves and other
4122 * device drivers should check before sending TLPs with RO set.
4123 */
4124static void quirk_relaxedordering_disable(struct pci_dev *dev)
4125{
4126 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
4127 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
4128}
4129
4130/*
4131 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
4132 * Complex have a Flow Control Credit issue which can cause performance
4133 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
4134 */
4135DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
4136 quirk_relaxedordering_disable);
4137DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
4138 quirk_relaxedordering_disable);
4139DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
4140 quirk_relaxedordering_disable);
4141DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
4142 quirk_relaxedordering_disable);
4143DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
4144 quirk_relaxedordering_disable);
4145DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
4146 quirk_relaxedordering_disable);
4147DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
4148 quirk_relaxedordering_disable);
4149DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
4150 quirk_relaxedordering_disable);
4151DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
4152 quirk_relaxedordering_disable);
4153DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
4154 quirk_relaxedordering_disable);
4155DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
4156 quirk_relaxedordering_disable);
4157DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
4158 quirk_relaxedordering_disable);
4159DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
4160 quirk_relaxedordering_disable);
4161DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
4162 quirk_relaxedordering_disable);
4163DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
4164 quirk_relaxedordering_disable);
4165DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
4166 quirk_relaxedordering_disable);
4167DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
4168 quirk_relaxedordering_disable);
4169DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
4170 quirk_relaxedordering_disable);
4171DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
4172 quirk_relaxedordering_disable);
4173DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
4174 quirk_relaxedordering_disable);
4175DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
4176 quirk_relaxedordering_disable);
4177DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
4178 quirk_relaxedordering_disable);
4179DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
4180 quirk_relaxedordering_disable);
4181DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
4182 quirk_relaxedordering_disable);
4183DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
4184 quirk_relaxedordering_disable);
4185DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
4186 quirk_relaxedordering_disable);
4187DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
4188 quirk_relaxedordering_disable);
4189DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
4190 quirk_relaxedordering_disable);
4191
4192/*
4193 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex
4194 * where Upstream Transaction Layer Packets with the Relaxed Ordering
4195 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
4196 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
4197 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4198 * November 10, 2010). As a result, on this platform we can't use Relaxed
4199 * Ordering for Upstream TLPs.
4200 */
4201DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
4202 quirk_relaxedordering_disable);
4203DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
4204 quirk_relaxedordering_disable);
4205DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
4206 quirk_relaxedordering_disable);
4207
4208/*
4209 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4210 * values for the Attribute as were supplied in the header of the
4211 * corresponding Request, except as explicitly allowed when IDO is used."
4212 *
4213 * If a non-compliant device generates a completion with a different
4214 * attribute than the request, the receiver may accept it (which itself
4215 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4216 * Malformed TLP or an Unexpected Completion, which will probably lead to a
4217 * device access timeout.
4218 *
4219 * If the non-compliant device generates completions with zero attributes
4220 * (instead of copying the attributes from the request), we can work around
4221 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
4222 * upstream devices so they always generate requests with zero attributes.
4223 *
4224 * This affects other devices under the same Root Port, but since these
4225 * attributes are performance hints, there should be no functional problem.
4226 *
4227 * Note that Configuration Space accesses are never supposed to have TLP
4228 * Attributes, so we're safe waiting till after any Configuration Space
4229 * accesses to do the Root Port fixup.
4230 */
4231static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
4232{
4233 struct pci_dev *root_port = pci_find_pcie_root_port(pdev);
4234
4235 if (!root_port) {
4236 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n");
4237 return;
4238 }
4239
4240 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4241 dev_name(&pdev->dev));
4242 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
4243 PCI_EXP_DEVCTL_RELAX_EN |
4244 PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
4245}
4246
4247/*
4248 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4249 * Completion it generates.
4250 */
4251static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4252{
4253 /*
4254 * This mask/compare operation selects for Physical Function 4 on a
4255 * T5. We only need to fix up the Root Port once for any of the
4256 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4257 * 0x54xx so we use that one.
4258 */
4259 if ((pdev->device & 0xff00) == 0x5400)
4260 quirk_disable_root_port_attributes(pdev);
4261}
4262DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4263 quirk_chelsio_T5_disable_root_port_attributes);
4264
4265/*
4266 * AMD has indicated that the devices below do not support peer-to-peer
4267 * in any system where they are found in the southbridge with an AMD
4268 * IOMMU in the system. Multifunction devices that do not support
4269 * peer-to-peer between functions can claim to support a subset of ACS.
4270 * Such devices effectively enable request redirect (RR) and completion
4271 * redirect (CR) since all transactions are redirected to the upstream
4272 * root complex.
4273 *
4274 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
4275 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
4276 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
4277 *
4278 * 1002:4385 SBx00 SMBus Controller
4279 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4280 * 1002:4383 SBx00 Azalia (Intel HDA)
4281 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4282 * 1002:4384 SBx00 PCI to PCI Bridge
4283 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
4284 *
4285 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4286 *
4287 * 1022:780f [AMD] FCH PCI Bridge
4288 * 1022:7809 [AMD] FCH USB OHCI Controller
4289 */
4290static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
4291{
4292#ifdef CONFIG_ACPI
4293 struct acpi_table_header *header = NULL;
4294 acpi_status status;
4295
4296 /* Targeting multifunction devices on the SB (appears on root bus) */
4297 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
4298 return -ENODEV;
4299
4300 /* The IVRS table describes the AMD IOMMU */
4301 status = acpi_get_table("IVRS", 0, &header);
4302 if (ACPI_FAILURE(status))
4303 return -ENODEV;
4304
4305 /* Filter out flags not applicable to multifunction */
4306 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
4307
4308 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
4309#else
4310 return -ENODEV;
4311#endif
4312}
4313
4314static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
4315{
4316 /*
4317 * Effectively selects all downstream ports for whole ThunderX 1
4318 * family by 0xf800 mask (which represents 8 SoCs), while the lower
4319 * bits of device ID are used to indicate which subdevice is used
4320 * within the SoC.
4321 */
4322 return (pci_is_pcie(dev) &&
4323 (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) &&
4324 ((dev->device & 0xf800) == 0xa000));
4325}
4326
4327static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4328{
4329 /*
4330 * Cavium root ports don't advertise an ACS capability. However,
4331 * the RTL internally implements similar protection as if ACS had
4332 * Request Redirection, Completion Redirection, Source Validation,
4333 * and Upstream Forwarding features enabled. Assert that the
4334 * hardware implements and enables equivalent ACS functionality for
4335 * these flags.
4336 */
4337 acs_flags &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF);
4338
4339 if (!pci_quirk_cavium_acs_match(dev))
4340 return -ENOTTY;
4341
4342 return acs_flags ? 0 : 1;
4343}
4344
4345static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
4346{
4347 /*
4348 * X-Gene Root Ports matching this quirk do not allow peer-to-peer
4349 * transactions with others, allowing masking out these bits as if they
4350 * were unimplemented in the ACS capability.
4351 */
4352 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4353
4354 return acs_flags ? 0 : 1;
4355}
4356
4357/*
4358 * Many Intel PCH root ports do provide ACS-like features to disable peer
4359 * transactions and validate bus numbers in requests, but do not provide an
4360 * actual PCIe ACS capability. This is the list of device IDs known to fall
4361 * into that category as provided by Intel in Red Hat bugzilla 1037684.
4362 */
4363static const u16 pci_quirk_intel_pch_acs_ids[] = {
4364 /* Ibexpeak PCH */
4365 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4366 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4367 /* Cougarpoint PCH */
4368 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4369 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4370 /* Pantherpoint PCH */
4371 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4372 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4373 /* Lynxpoint-H PCH */
4374 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4375 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4376 /* Lynxpoint-LP PCH */
4377 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4378 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4379 /* Wildcat PCH */
4380 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4381 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4382 /* Patsburg (X79) PCH */
4383 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4384 /* Wellsburg (X99) PCH */
4385 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4386 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4387 /* Lynx Point (9 series) PCH */
4388 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4389};
4390
4391static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
4392{
4393 int i;
4394
4395 /* Filter out a few obvious non-matches first */
4396 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4397 return false;
4398
4399 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
4400 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4401 return true;
4402
4403 return false;
4404}
4405
4406#define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)
4407
4408static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
4409{
4410 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
4411 INTEL_PCH_ACS_FLAGS : 0;
4412
4413 if (!pci_quirk_intel_pch_acs_match(dev))
4414 return -ENOTTY;
4415
4416 return acs_flags & ~flags ? 0 : 1;
4417}
4418
4419/*
4420 * These QCOM root ports do provide ACS-like features to disable peer
4421 * transactions and validate bus numbers in requests, but do not provide an
4422 * actual PCIe ACS capability. Hardware supports source validation but it
4423 * will report the issue as Completer Abort instead of ACS Violation.
4424 * Hardware doesn't support peer-to-peer and each root port is a root
4425 * complex with unique segment numbers. It is not possible for one root
4426 * port to pass traffic to another root port. All PCIe transactions are
4427 * terminated inside the root port.
4428 */
4429static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4430{
4431 u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV);
4432 int ret = acs_flags & ~flags ? 0 : 1;
4433
4434 pci_info(dev, "Using QCOM ACS Quirk (%d)\n", ret);
4435
4436 return ret;
4437}
4438
4439static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags)
4440{
4441 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4442 return -ENOTTY;
4443
4444 /*
4445 * Amazon's Annapurna Labs root ports don't include an ACS capability,
4446 * but do include ACS-like functionality. The hardware doesn't support
4447 * peer-to-peer transactions via the root port and each has a unique
4448 * segment number.
4449 *
4450 * Additionally, the root ports cannot send traffic to each other.
4451 */
4452 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4453
4454 return acs_flags ? 0 : 1;
4455}
4456
4457/*
4458 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4459 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4460 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4461 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4462 * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4463 * control register is at offset 8 instead of 6 and we should probably use
4464 * dword accesses to them. This applies to the following PCI Device IDs, as
4465 * found in volume 1 of the datasheet[2]:
4466 *
4467 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4468 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4469 *
4470 * N.B. This doesn't fix what lspci shows.
4471 *
4472 * The 100 series chipset specification update includes this as errata #23[3].
4473 *
4474 * The 200 series chipset (Union Point) has the same bug according to the
4475 * specification update (Intel 200 Series Chipset Family Platform Controller
4476 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4477 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4478 * chipset include:
4479 *
4480 * 0xa290-0xa29f PCI Express Root port #{0-16}
4481 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4482 *
4483 * Mobile chipsets are also affected, 7th & 8th Generation
4484 * Specification update confirms ACS errata 22, status no fix: (7th Generation
4485 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
4486 * Processor Family I/O for U Quad Core Platforms Specification Update,
4487 * August 2017, Revision 002, Document#: 334660-002)[6]
4488 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
4489 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
4490 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4491 *
4492 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4493 *
4494 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4495 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4496 * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4497 * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4498 * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4499 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
4500 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
4501 */
4502static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4503{
4504 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4505 return false;
4506
4507 switch (dev->device) {
4508 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4509 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4510 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
4511 return true;
4512 }
4513
4514 return false;
4515}
4516
4517#define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4518
4519static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4520{
4521 int pos;
4522 u32 cap, ctrl;
4523
4524 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4525 return -ENOTTY;
4526
4527 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4528 if (!pos)
4529 return -ENOTTY;
4530
4531 /* see pci_acs_flags_enabled() */
4532 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4533 acs_flags &= (cap | PCI_ACS_EC);
4534
4535 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4536
4537 return acs_flags & ~ctrl ? 0 : 1;
4538}
4539
4540static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
4541{
4542 /*
4543 * SV, TB, and UF are not relevant to multifunction endpoints.
4544 *
4545 * Multifunction devices are only required to implement RR, CR, and DT
4546 * in their ACS capability if they support peer-to-peer transactions.
4547 * Devices matching this quirk have been verified by the vendor to not
4548 * perform peer-to-peer with other functions, allowing us to mask out
4549 * these bits as if they were unimplemented in the ACS capability.
4550 */
4551 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4552 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4553
4554 return acs_flags ? 0 : 1;
4555}
4556
4557static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags)
4558{
4559 /*
4560 * iProc PAXB Root Ports don't advertise an ACS capability, but
4561 * they do not allow peer-to-peer transactions between Root Ports.
4562 * Allow each Root Port to be in a separate IOMMU group by masking
4563 * SV/RR/CR/UF bits.
4564 */
4565 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4566
4567 return acs_flags ? 0 : 1;
4568}
4569
4570static const struct pci_dev_acs_enabled {
4571 u16 vendor;
4572 u16 device;
4573 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
4574} pci_dev_acs_enabled[] = {
4575 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
4576 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
4577 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
4578 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
4579 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
4580 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
4581 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
4582 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
4583 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
4584 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
4585 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
4586 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
4587 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
4588 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
4589 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
4590 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
4591 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
4592 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
4593 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
4594 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
4595 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
4596 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
4597 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
4598 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
4599 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
4600 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
4601 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
4602 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
4603 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
4604 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
4605 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
4606 /* 82580 */
4607 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
4608 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
4609 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
4610 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
4611 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
4612 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
4613 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
4614 /* 82576 */
4615 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
4616 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
4617 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
4618 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
4619 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
4620 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
4621 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
4622 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
4623 /* 82575 */
4624 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
4625 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
4626 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
4627 /* I350 */
4628 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
4629 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
4630 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
4631 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
4632 /* 82571 (Quads omitted due to non-ACS switch) */
4633 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4634 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4635 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4636 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
4637 /* I219 */
4638 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4639 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
4640 /* QCOM QDF2xxx root ports */
4641 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },
4642 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
4643 /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */
4644 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs },
4645 /* Intel PCH root ports */
4646 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
4647 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
4648 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4649 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4650 /* Cavium ThunderX */
4651 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
4652 /* APM X-Gene */
4653 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
4654 /* Ampere Computing */
4655 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
4656 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
4657 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs },
4658 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs },
4659 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs },
4660 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
4661 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
4662 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
4663 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
4664 /* Amazon Annapurna Labs */
4665 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
4666 { 0 }
4667};
4668
4669int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
4670{
4671 const struct pci_dev_acs_enabled *i;
4672 int ret;
4673
4674 /*
4675 * Allow devices that do not expose standard PCIe ACS capabilities
4676 * or control to indicate their support here. Multi-function express
4677 * devices which do not allow internal peer-to-peer between functions,
4678 * but do not implement PCIe ACS may wish to return true here.
4679 */
4680 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
4681 if ((i->vendor == dev->vendor ||
4682 i->vendor == (u16)PCI_ANY_ID) &&
4683 (i->device == dev->device ||
4684 i->device == (u16)PCI_ANY_ID)) {
4685 ret = i->acs_enabled(dev, acs_flags);
4686 if (ret >= 0)
4687 return ret;
4688 }
4689 }
4690
4691 return -ENOTTY;
4692}
4693
4694/* Config space offset of Root Complex Base Address register */
4695#define INTEL_LPC_RCBA_REG 0xf0
4696/* 31:14 RCBA address */
4697#define INTEL_LPC_RCBA_MASK 0xffffc000
4698/* RCBA Enable */
4699#define INTEL_LPC_RCBA_ENABLE (1 << 0)
4700
4701/* Backbone Scratch Pad Register */
4702#define INTEL_BSPR_REG 0x1104
4703/* Backbone Peer Non-Posted Disable */
4704#define INTEL_BSPR_REG_BPNPD (1 << 8)
4705/* Backbone Peer Posted Disable */
4706#define INTEL_BSPR_REG_BPPD (1 << 9)
4707
4708/* Upstream Peer Decode Configuration Register */
4709#define INTEL_UPDCR_REG 0x1114
4710/* 5:0 Peer Decode Enable bits */
4711#define INTEL_UPDCR_REG_MASK 0x3f
4712
4713static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
4714{
4715 u32 rcba, bspr, updcr;
4716 void __iomem *rcba_mem;
4717
4718 /*
4719 * Read the RCBA register from the LPC (D31:F0). PCH root ports
4720 * are D28:F* and therefore get probed before LPC, thus we can't
4721 * use pci_get_slot()/pci_read_config_dword() here.
4722 */
4723 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
4724 INTEL_LPC_RCBA_REG, &rcba);
4725 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
4726 return -EINVAL;
4727
4728 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
4729 PAGE_ALIGN(INTEL_UPDCR_REG));
4730 if (!rcba_mem)
4731 return -ENOMEM;
4732
4733 /*
4734 * The BSPR can disallow peer cycles, but it's set by soft strap and
4735 * therefore read-only. If both posted and non-posted peer cycles are
4736 * disallowed, we're ok. If either are allowed, then we need to use
4737 * the UPDCR to disable peer decodes for each port. This provides the
4738 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4739 */
4740 bspr = readl(rcba_mem + INTEL_BSPR_REG);
4741 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
4742 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
4743 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
4744 if (updcr & INTEL_UPDCR_REG_MASK) {
4745 pci_info(dev, "Disabling UPDCR peer decodes\n");
4746 updcr &= ~INTEL_UPDCR_REG_MASK;
4747 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
4748 }
4749 }
4750
4751 iounmap(rcba_mem);
4752 return 0;
4753}
4754
4755/* Miscellaneous Port Configuration register */
4756#define INTEL_MPC_REG 0xd8
4757/* MPC: Invalid Receive Bus Number Check Enable */
4758#define INTEL_MPC_REG_IRBNCE (1 << 26)
4759
4760static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
4761{
4762 u32 mpc;
4763
4764 /*
4765 * When enabled, the IRBNCE bit of the MPC register enables the
4766 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
4767 * ensures that requester IDs fall within the bus number range
4768 * of the bridge. Enable if not already.
4769 */
4770 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
4771 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
4772 pci_info(dev, "Enabling MPC IRBNCE\n");
4773 mpc |= INTEL_MPC_REG_IRBNCE;
4774 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
4775 }
4776}
4777
4778static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
4779{
4780 if (!pci_quirk_intel_pch_acs_match(dev))
4781 return -ENOTTY;
4782
4783 if (pci_quirk_enable_intel_lpc_acs(dev)) {
4784 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n");
4785 return 0;
4786 }
4787
4788 pci_quirk_enable_intel_rp_mpc_acs(dev);
4789
4790 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
4791
4792 pci_info(dev, "Intel PCH root port ACS workaround enabled\n");
4793
4794 return 0;
4795}
4796
4797static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
4798{
4799 int pos;
4800 u32 cap, ctrl;
4801
4802 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4803 return -ENOTTY;
4804
4805 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4806 if (!pos)
4807 return -ENOTTY;
4808
4809 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4810 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4811
4812 ctrl |= (cap & PCI_ACS_SV);
4813 ctrl |= (cap & PCI_ACS_RR);
4814 ctrl |= (cap & PCI_ACS_CR);
4815 ctrl |= (cap & PCI_ACS_UF);
4816
4817 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
4818
4819 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n");
4820
4821 return 0;
4822}
4823
4824static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev)
4825{
4826 int pos;
4827 u32 cap, ctrl;
4828
4829 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4830 return -ENOTTY;
4831
4832 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4833 if (!pos)
4834 return -ENOTTY;
4835
4836 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4837 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4838
4839 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
4840
4841 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
4842
4843 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n");
4844
4845 return 0;
4846}
4847
4848static const struct pci_dev_acs_ops {
4849 u16 vendor;
4850 u16 device;
4851 int (*enable_acs)(struct pci_dev *dev);
4852 int (*disable_acs_redir)(struct pci_dev *dev);
4853} pci_dev_acs_ops[] = {
4854 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
4855 .enable_acs = pci_quirk_enable_intel_pch_acs,
4856 },
4857 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
4858 .enable_acs = pci_quirk_enable_intel_spt_pch_acs,
4859 .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir,
4860 },
4861};
4862
4863int pci_dev_specific_enable_acs(struct pci_dev *dev)
4864{
4865 const struct pci_dev_acs_ops *p;
4866 int i, ret;
4867
4868 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
4869 p = &pci_dev_acs_ops[i];
4870 if ((p->vendor == dev->vendor ||
4871 p->vendor == (u16)PCI_ANY_ID) &&
4872 (p->device == dev->device ||
4873 p->device == (u16)PCI_ANY_ID) &&
4874 p->enable_acs) {
4875 ret = p->enable_acs(dev);
4876 if (ret >= 0)
4877 return ret;
4878 }
4879 }
4880
4881 return -ENOTTY;
4882}
4883
4884int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
4885{
4886 const struct pci_dev_acs_ops *p;
4887 int i, ret;
4888
4889 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
4890 p = &pci_dev_acs_ops[i];
4891 if ((p->vendor == dev->vendor ||
4892 p->vendor == (u16)PCI_ANY_ID) &&
4893 (p->device == dev->device ||
4894 p->device == (u16)PCI_ANY_ID) &&
4895 p->disable_acs_redir) {
4896 ret = p->disable_acs_redir(dev);
4897 if (ret >= 0)
4898 return ret;
4899 }
4900 }
4901
4902 return -ENOTTY;
4903}
4904
4905/*
4906 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
4907 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
4908 * Next Capability pointer in the MSI Capability Structure should point to
4909 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
4910 * the list.
4911 */
4912static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
4913{
4914 int pos, i = 0;
4915 u8 next_cap;
4916 u16 reg16, *cap;
4917 struct pci_cap_saved_state *state;
4918
4919 /* Bail if the hardware bug is fixed */
4920 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
4921 return;
4922
4923 /* Bail if MSI Capability Structure is not found for some reason */
4924 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
4925 if (!pos)
4926 return;
4927
4928 /*
4929 * Bail if Next Capability pointer in the MSI Capability Structure
4930 * is not the expected incorrect 0x00.
4931 */
4932 pci_read_config_byte(pdev, pos + 1, &next_cap);
4933 if (next_cap)
4934 return;
4935
4936 /*
4937 * PCIe Capability Structure is expected to be at 0x50 and should
4938 * terminate the list (Next Capability pointer is 0x00). Verify
4939 * Capability Id and Next Capability pointer is as expected.
4940 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
4941 * to correctly set kernel data structures which have already been
4942 * set incorrectly due to the hardware bug.
4943 */
4944 pos = 0x50;
4945 pci_read_config_word(pdev, pos, ®16);
4946 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
4947 u32 status;
4948#ifndef PCI_EXP_SAVE_REGS
4949#define PCI_EXP_SAVE_REGS 7
4950#endif
4951 int size = PCI_EXP_SAVE_REGS * sizeof(u16);
4952
4953 pdev->pcie_cap = pos;
4954 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
4955 pdev->pcie_flags_reg = reg16;
4956 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
4957 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
4958
4959 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
4960 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
4961 PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
4962 pdev->cfg_size = PCI_CFG_SPACE_SIZE;
4963
4964 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
4965 return;
4966
4967 /* Save PCIe cap */
4968 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
4969 if (!state)
4970 return;
4971
4972 state->cap.cap_nr = PCI_CAP_ID_EXP;
4973 state->cap.cap_extended = 0;
4974 state->cap.size = size;
4975 cap = (u16 *)&state->cap.data[0];
4976 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
4977 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
4978 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
4979 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
4980 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
4981 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
4982 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
4983 hlist_add_head(&state->next, &pdev->saved_cap_space);
4984 }
4985}
4986DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
4987
4988/* FLR may cause some 82579 devices to hang */
4989static void quirk_intel_no_flr(struct pci_dev *dev)
4990{
4991 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
4992}
4993DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr);
4994DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr);
4995
4996static void quirk_no_ext_tags(struct pci_dev *pdev)
4997{
4998 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
4999
5000 if (!bridge)
5001 return;
5002
5003 bridge->no_ext_tags = 1;
5004 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n");
5005
5006 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
5007}
5008DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
5009DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
5010DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
5011DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
5012DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
5013DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
5014DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);
5015
5016#ifdef CONFIG_PCI_ATS
5017/*
5018 * Some devices have a broken ATS implementation causing IOMMU stalls.
5019 * Don't use ATS for those devices.
5020 */
5021static void quirk_no_ats(struct pci_dev *pdev)
5022{
5023 pci_info(pdev, "disabling ATS (broken on this device)\n");
5024 pdev->ats_cap = 0;
5025}
5026
5027/* AMD Stoney platform GPU */
5028DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats);
5029DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_no_ats);
5030#endif /* CONFIG_PCI_ATS */
5031
5032/* Freescale PCIe doesn't support MSI in RC mode */
5033static void quirk_fsl_no_msi(struct pci_dev *pdev)
5034{
5035 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
5036 pdev->no_msi = 1;
5037}
5038DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
5039
5040/*
5041 * Although not allowed by the spec, some multi-function devices have
5042 * dependencies of one function (consumer) on another (supplier). For the
5043 * consumer to work in D0, the supplier must also be in D0. Create a
5044 * device link from the consumer to the supplier to enforce this
5045 * dependency. Runtime PM is allowed by default on the consumer to prevent
5046 * it from permanently keeping the supplier awake.
5047 */
5048static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer,
5049 unsigned int supplier, unsigned int class,
5050 unsigned int class_shift)
5051{
5052 struct pci_dev *supplier_pdev;
5053
5054 if (PCI_FUNC(pdev->devfn) != consumer)
5055 return;
5056
5057 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
5058 pdev->bus->number,
5059 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier));
5060 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) {
5061 pci_dev_put(supplier_pdev);
5062 return;
5063 }
5064
5065 if (device_link_add(&pdev->dev, &supplier_pdev->dev,
5066 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME))
5067 pci_info(pdev, "D0 power state depends on %s\n",
5068 pci_name(supplier_pdev));
5069 else
5070 pci_err(pdev, "Cannot enforce power dependency on %s\n",
5071 pci_name(supplier_pdev));
5072
5073 pm_runtime_allow(&pdev->dev);
5074 pci_dev_put(supplier_pdev);
5075}
5076
5077/*
5078 * Create device link for GPUs with integrated HDA controller for streaming
5079 * audio to attached displays.
5080 */
5081static void quirk_gpu_hda(struct pci_dev *hda)
5082{
5083 pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16);
5084}
5085DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5086 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5087DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID,
5088 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5089DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5090 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5091
5092/*
5093 * Create device link for NVIDIA GPU with integrated USB xHCI Host
5094 * controller to VGA.
5095 */
5096static void quirk_gpu_usb(struct pci_dev *usb)
5097{
5098 pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16);
5099}
5100DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5101 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
5102
5103/*
5104 * Create device link for NVIDIA GPU with integrated Type-C UCSI controller
5105 * to VGA. Currently there is no class code defined for UCSI device over PCI
5106 * so using UNKNOWN class for now and it will be updated when UCSI
5107 * over PCI gets a class code.
5108 */
5109#define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
5110static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi)
5111{
5112 pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16);
5113}
5114DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5115 PCI_CLASS_SERIAL_UNKNOWN, 8,
5116 quirk_gpu_usb_typec_ucsi);
5117
5118/*
5119 * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it
5120 * disabled. https://devtalk.nvidia.com/default/topic/1024022
5121 */
5122static void quirk_nvidia_hda(struct pci_dev *gpu)
5123{
5124 u8 hdr_type;
5125 u32 val;
5126
5127 /* There was no integrated HDA controller before MCP89 */
5128 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M)
5129 return;
5130
5131 /* Bit 25 at offset 0x488 enables the HDA controller */
5132 pci_read_config_dword(gpu, 0x488, &val);
5133 if (val & BIT(25))
5134 return;
5135
5136 pci_info(gpu, "Enabling HDA controller\n");
5137 pci_write_config_dword(gpu, 0x488, val | BIT(25));
5138
5139 /* The GPU becomes a multi-function device when the HDA is enabled */
5140 pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type);
5141 gpu->multifunction = !!(hdr_type & 0x80);
5142}
5143DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5144 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5145DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5146 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5147
5148/*
5149 * Some IDT switches incorrectly flag an ACS Source Validation error on
5150 * completions for config read requests even though PCIe r4.0, sec
5151 * 6.12.1.1, says that completions are never affected by ACS Source
5152 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
5153 *
5154 * Item #36 - Downstream port applies ACS Source Validation to Completions
5155 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that
5156 * completions are never affected by ACS Source Validation. However,
5157 * completions received by a downstream port of the PCIe switch from a
5158 * device that has not yet captured a PCIe bus number are incorrectly
5159 * dropped by ACS Source Validation by the switch downstream port.
5160 *
5161 * The workaround suggested by IDT is to issue a config write to the
5162 * downstream device before issuing the first config read. This allows the
5163 * downstream device to capture its bus and device numbers (see PCIe r4.0,
5164 * sec 2.2.9), thus avoiding the ACS error on the completion.
5165 *
5166 * However, we don't know when the device is ready to accept the config
5167 * write, so we do config reads until we receive a non-Config Request Retry
5168 * Status, then do the config write.
5169 *
5170 * To avoid hitting the erratum when doing the config reads, we disable ACS
5171 * SV around this process.
5172 */
5173int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout)
5174{
5175 int pos;
5176 u16 ctrl = 0;
5177 bool found;
5178 struct pci_dev *bridge = bus->self;
5179
5180 pos = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ACS);
5181
5182 /* Disable ACS SV before initial config reads */
5183 if (pos) {
5184 pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl);
5185 if (ctrl & PCI_ACS_SV)
5186 pci_write_config_word(bridge, pos + PCI_ACS_CTRL,
5187 ctrl & ~PCI_ACS_SV);
5188 }
5189
5190 found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
5191
5192 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */
5193 if (found)
5194 pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0);
5195
5196 /* Re-enable ACS_SV if it was previously enabled */
5197 if (ctrl & PCI_ACS_SV)
5198 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl);
5199
5200 return found;
5201}
5202
5203/*
5204 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
5205 * NT endpoints via the internal switch fabric. These IDs replace the
5206 * originating requestor ID TLPs which access host memory on peer NTB
5207 * ports. Therefore, all proxy IDs must be aliased to the NTB device
5208 * to permit access when the IOMMU is turned on.
5209 */
5210static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
5211{
5212 void __iomem *mmio;
5213 struct ntb_info_regs __iomem *mmio_ntb;
5214 struct ntb_ctrl_regs __iomem *mmio_ctrl;
5215 u64 partition_map;
5216 u8 partition;
5217 int pp;
5218
5219 if (pci_enable_device(pdev)) {
5220 pci_err(pdev, "Cannot enable Switchtec device\n");
5221 return;
5222 }
5223
5224 mmio = pci_iomap(pdev, 0, 0);
5225 if (mmio == NULL) {
5226 pci_disable_device(pdev);
5227 pci_err(pdev, "Cannot iomap Switchtec device\n");
5228 return;
5229 }
5230
5231 pci_info(pdev, "Setting Switchtec proxy ID aliases\n");
5232
5233 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET;
5234 mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET;
5235
5236 partition = ioread8(&mmio_ntb->partition_id);
5237
5238 partition_map = ioread32(&mmio_ntb->ep_map);
5239 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32;
5240 partition_map &= ~(1ULL << partition);
5241
5242 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) {
5243 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl;
5244 u32 table_sz = 0;
5245 int te;
5246
5247 if (!(partition_map & (1ULL << pp)))
5248 continue;
5249
5250 pci_dbg(pdev, "Processing partition %d\n", pp);
5251
5252 mmio_peer_ctrl = &mmio_ctrl[pp];
5253
5254 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size);
5255 if (!table_sz) {
5256 pci_warn(pdev, "Partition %d table_sz 0\n", pp);
5257 continue;
5258 }
5259
5260 if (table_sz > 512) {
5261 pci_warn(pdev,
5262 "Invalid Switchtec partition %d table_sz %d\n",
5263 pp, table_sz);
5264 continue;
5265 }
5266
5267 for (te = 0; te < table_sz; te++) {
5268 u32 rid_entry;
5269 u8 devfn;
5270
5271 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]);
5272 devfn = (rid_entry >> 1) & 0xFF;
5273 pci_dbg(pdev,
5274 "Aliasing Partition %d Proxy ID %02x.%d\n",
5275 pp, PCI_SLOT(devfn), PCI_FUNC(devfn));
5276 pci_add_dma_alias(pdev, devfn);
5277 }
5278 }
5279
5280 pci_iounmap(pdev, mmio);
5281 pci_disable_device(pdev);
5282}
5283#define SWITCHTEC_QUIRK(vid) \
5284 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \
5285 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias)
5286
5287SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */
5288SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */
5289SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */
5290SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */
5291SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */
5292SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */
5293SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */
5294SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */
5295SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */
5296SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */
5297SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */
5298SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */
5299SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */
5300SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */
5301SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */
5302SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */
5303SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */
5304SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */
5305SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */
5306SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */
5307SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */
5308SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */
5309SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */
5310SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */
5311SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */
5312SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */
5313SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */
5314SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */
5315SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */
5316SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */
5317
5318/*
5319 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does
5320 * not always reset the secondary Nvidia GPU between reboots if the system
5321 * is configured to use Hybrid Graphics mode. This results in the GPU
5322 * being left in whatever state it was in during the *previous* boot, which
5323 * causes spurious interrupts from the GPU, which in turn causes us to
5324 * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly,
5325 * this also completely breaks nouveau.
5326 *
5327 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a
5328 * clean state and fixes all these issues.
5329 *
5330 * When the machine is configured in Dedicated display mode, the issue
5331 * doesn't occur. Fortunately the GPU advertises NoReset+ when in this
5332 * mode, so we can detect that and avoid resetting it.
5333 */
5334static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev)
5335{
5336 void __iomem *map;
5337 int ret;
5338
5339 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO ||
5340 pdev->subsystem_device != 0x222e ||
5341 !pdev->reset_fn)
5342 return;
5343
5344 if (pci_enable_device_mem(pdev))
5345 return;
5346
5347 /*
5348 * Based on nvkm_device_ctor() in
5349 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
5350 */
5351 map = pci_iomap(pdev, 0, 0x23000);
5352 if (!map) {
5353 pci_err(pdev, "Can't map MMIO space\n");
5354 goto out_disable;
5355 }
5356
5357 /*
5358 * Make sure the GPU looks like it's been POSTed before resetting
5359 * it.
5360 */
5361 if (ioread32(map + 0x2240c) & 0x2) {
5362 pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n");
5363 ret = pci_reset_bus(pdev);
5364 if (ret < 0)
5365 pci_err(pdev, "Failed to reset GPU: %d\n", ret);
5366 }
5367
5368 iounmap(map);
5369out_disable:
5370 pci_disable_device(pdev);
5371}
5372DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1,
5373 PCI_CLASS_DISPLAY_VGA, 8,
5374 quirk_reset_lenovo_thinkpad_p50_nvgpu);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * This file contains work-arounds for many known PCI hardware bugs.
4 * Devices present only on certain architectures (host bridges et cetera)
5 * should be handled in arch-specific code.
6 *
7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 *
9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 *
11 * Init/reset quirks for USB host controllers should be in the USB quirks
12 * file, where their drivers can use them.
13 */
14
15#include <linux/bitfield.h>
16#include <linux/types.h>
17#include <linux/kernel.h>
18#include <linux/export.h>
19#include <linux/pci.h>
20#include <linux/isa-dma.h> /* isa_dma_bridge_buggy */
21#include <linux/init.h>
22#include <linux/delay.h>
23#include <linux/acpi.h>
24#include <linux/dmi.h>
25#include <linux/ioport.h>
26#include <linux/sched.h>
27#include <linux/ktime.h>
28#include <linux/mm.h>
29#include <linux/nvme.h>
30#include <linux/platform_data/x86/apple.h>
31#include <linux/pm_runtime.h>
32#include <linux/suspend.h>
33#include <linux/switchtec.h>
34#include "pci.h"
35
36/*
37 * Retrain the link of a downstream PCIe port by hand if necessary.
38 *
39 * This is needed at least where a downstream port of the ASMedia ASM2824
40 * Gen 3 switch is wired to the upstream port of the Pericom PI7C9X2G304
41 * Gen 2 switch, and observed with the Delock Riser Card PCI Express x1 >
42 * 2 x PCIe x1 device, P/N 41433, plugged into the SiFive HiFive Unmatched
43 * board.
44 *
45 * In such a configuration the switches are supposed to negotiate the link
46 * speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link
47 * continues switching between the two speeds indefinitely and the data
48 * link layer never reaches the active state, with link training reported
49 * repeatedly active ~84% of the time. Forcing the target link speed to
50 * 2.5GT/s with the upstream ASM2824 device makes the two switches talk to
51 * each other correctly however. And more interestingly retraining with a
52 * higher target link speed afterwards lets the two successfully negotiate
53 * 5.0GT/s.
54 *
55 * With the ASM2824 we can rely on the otherwise optional Data Link Layer
56 * Link Active status bit and in the failed link training scenario it will
57 * be off along with the Link Bandwidth Management Status indicating that
58 * hardware has changed the link speed or width in an attempt to correct
59 * unreliable link operation. For a port that has been left unconnected
60 * both bits will be clear. So use this information to detect the problem
61 * rather than polling the Link Training bit and watching out for flips or
62 * at least the active status.
63 *
64 * Since the exact nature of the problem isn't known and in principle this
65 * could trigger where an ASM2824 device is downstream rather upstream,
66 * apply this erratum workaround to any downstream ports as long as they
67 * support Link Active reporting and have the Link Control 2 register.
68 * Restrict the speed to 2.5GT/s then with the Target Link Speed field,
69 * request a retrain and wait 200ms for the data link to go up.
70 *
71 * If this turns out successful and we know by the Vendor:Device ID it is
72 * safe to do so, then lift the restriction, letting the devices negotiate
73 * a higher speed. Also check for a similar 2.5GT/s speed restriction the
74 * firmware may have already arranged and lift it with ports that already
75 * report their data link being up.
76 *
77 * Return TRUE if the link has been successfully retrained, otherwise FALSE.
78 */
79bool pcie_failed_link_retrain(struct pci_dev *dev)
80{
81 static const struct pci_device_id ids[] = {
82 { PCI_VDEVICE(ASMEDIA, 0x2824) }, /* ASMedia ASM2824 */
83 {}
84 };
85 u16 lnksta, lnkctl2;
86
87 if (!pci_is_pcie(dev) || !pcie_downstream_port(dev) ||
88 !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting)
89 return false;
90
91 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &lnkctl2);
92 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
93 if ((lnksta & (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_DLLLA)) ==
94 PCI_EXP_LNKSTA_LBMS) {
95 pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n");
96
97 lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS;
98 lnkctl2 |= PCI_EXP_LNKCTL2_TLS_2_5GT;
99 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, lnkctl2);
100
101 if (pcie_retrain_link(dev, false)) {
102 pci_info(dev, "retraining failed\n");
103 return false;
104 }
105
106 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
107 }
108
109 if ((lnksta & PCI_EXP_LNKSTA_DLLLA) &&
110 (lnkctl2 & PCI_EXP_LNKCTL2_TLS) == PCI_EXP_LNKCTL2_TLS_2_5GT &&
111 pci_match_id(ids, dev)) {
112 u32 lnkcap;
113
114 pci_info(dev, "removing 2.5GT/s downstream link speed restriction\n");
115 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
116 lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS;
117 lnkctl2 |= lnkcap & PCI_EXP_LNKCAP_SLS;
118 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, lnkctl2);
119
120 if (pcie_retrain_link(dev, false)) {
121 pci_info(dev, "retraining failed\n");
122 return false;
123 }
124 }
125
126 return true;
127}
128
129static ktime_t fixup_debug_start(struct pci_dev *dev,
130 void (*fn)(struct pci_dev *dev))
131{
132 if (initcall_debug)
133 pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current));
134
135 return ktime_get();
136}
137
138static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
139 void (*fn)(struct pci_dev *dev))
140{
141 ktime_t delta, rettime;
142 unsigned long long duration;
143
144 rettime = ktime_get();
145 delta = ktime_sub(rettime, calltime);
146 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
147 if (initcall_debug || duration > 10000)
148 pci_info(dev, "%pS took %lld usecs\n", fn, duration);
149}
150
151static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
152 struct pci_fixup *end)
153{
154 ktime_t calltime;
155
156 for (; f < end; f++)
157 if ((f->class == (u32) (dev->class >> f->class_shift) ||
158 f->class == (u32) PCI_ANY_ID) &&
159 (f->vendor == dev->vendor ||
160 f->vendor == (u16) PCI_ANY_ID) &&
161 (f->device == dev->device ||
162 f->device == (u16) PCI_ANY_ID)) {
163 void (*hook)(struct pci_dev *dev);
164#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
165 hook = offset_to_ptr(&f->hook_offset);
166#else
167 hook = f->hook;
168#endif
169 calltime = fixup_debug_start(dev, hook);
170 hook(dev);
171 fixup_debug_report(dev, calltime, hook);
172 }
173}
174
175extern struct pci_fixup __start_pci_fixups_early[];
176extern struct pci_fixup __end_pci_fixups_early[];
177extern struct pci_fixup __start_pci_fixups_header[];
178extern struct pci_fixup __end_pci_fixups_header[];
179extern struct pci_fixup __start_pci_fixups_final[];
180extern struct pci_fixup __end_pci_fixups_final[];
181extern struct pci_fixup __start_pci_fixups_enable[];
182extern struct pci_fixup __end_pci_fixups_enable[];
183extern struct pci_fixup __start_pci_fixups_resume[];
184extern struct pci_fixup __end_pci_fixups_resume[];
185extern struct pci_fixup __start_pci_fixups_resume_early[];
186extern struct pci_fixup __end_pci_fixups_resume_early[];
187extern struct pci_fixup __start_pci_fixups_suspend[];
188extern struct pci_fixup __end_pci_fixups_suspend[];
189extern struct pci_fixup __start_pci_fixups_suspend_late[];
190extern struct pci_fixup __end_pci_fixups_suspend_late[];
191
192static bool pci_apply_fixup_final_quirks;
193
194void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
195{
196 struct pci_fixup *start, *end;
197
198 switch (pass) {
199 case pci_fixup_early:
200 start = __start_pci_fixups_early;
201 end = __end_pci_fixups_early;
202 break;
203
204 case pci_fixup_header:
205 start = __start_pci_fixups_header;
206 end = __end_pci_fixups_header;
207 break;
208
209 case pci_fixup_final:
210 if (!pci_apply_fixup_final_quirks)
211 return;
212 start = __start_pci_fixups_final;
213 end = __end_pci_fixups_final;
214 break;
215
216 case pci_fixup_enable:
217 start = __start_pci_fixups_enable;
218 end = __end_pci_fixups_enable;
219 break;
220
221 case pci_fixup_resume:
222 start = __start_pci_fixups_resume;
223 end = __end_pci_fixups_resume;
224 break;
225
226 case pci_fixup_resume_early:
227 start = __start_pci_fixups_resume_early;
228 end = __end_pci_fixups_resume_early;
229 break;
230
231 case pci_fixup_suspend:
232 start = __start_pci_fixups_suspend;
233 end = __end_pci_fixups_suspend;
234 break;
235
236 case pci_fixup_suspend_late:
237 start = __start_pci_fixups_suspend_late;
238 end = __end_pci_fixups_suspend_late;
239 break;
240
241 default:
242 /* stupid compiler warning, you would think with an enum... */
243 return;
244 }
245 pci_do_fixups(dev, start, end);
246}
247EXPORT_SYMBOL(pci_fixup_device);
248
249static int __init pci_apply_final_quirks(void)
250{
251 struct pci_dev *dev = NULL;
252 u8 cls = 0;
253 u8 tmp;
254
255 if (pci_cache_line_size)
256 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2);
257
258 pci_apply_fixup_final_quirks = true;
259 for_each_pci_dev(dev) {
260 pci_fixup_device(pci_fixup_final, dev);
261 /*
262 * If arch hasn't set it explicitly yet, use the CLS
263 * value shared by all PCI devices. If there's a
264 * mismatch, fall back to the default value.
265 */
266 if (!pci_cache_line_size) {
267 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
268 if (!cls)
269 cls = tmp;
270 if (!tmp || cls == tmp)
271 continue;
272
273 pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n",
274 cls << 2, tmp << 2,
275 pci_dfl_cache_line_size << 2);
276 pci_cache_line_size = pci_dfl_cache_line_size;
277 }
278 }
279
280 if (!pci_cache_line_size) {
281 pr_info("PCI: CLS %u bytes, default %u\n", cls << 2,
282 pci_dfl_cache_line_size << 2);
283 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
284 }
285
286 return 0;
287}
288fs_initcall_sync(pci_apply_final_quirks);
289
290/*
291 * Decoding should be disabled for a PCI device during BAR sizing to avoid
292 * conflict. But doing so may cause problems on host bridge and perhaps other
293 * key system devices. For devices that need to have mmio decoding always-on,
294 * we need to set the dev->mmio_always_on bit.
295 */
296static void quirk_mmio_always_on(struct pci_dev *dev)
297{
298 dev->mmio_always_on = 1;
299}
300DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
301 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
302
303/*
304 * The Mellanox Tavor device gives false positive parity errors. Disable
305 * parity error reporting.
306 */
307DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, pci_disable_parity);
308DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, pci_disable_parity);
309
310/*
311 * Deal with broken BIOSes that neglect to enable passive release,
312 * which can cause problems in combination with the 82441FX/PPro MTRRs
313 */
314static void quirk_passive_release(struct pci_dev *dev)
315{
316 struct pci_dev *d = NULL;
317 unsigned char dlc;
318
319 /*
320 * We have to make sure a particular bit is set in the PIIX3
321 * ISA bridge, so we have to go out and find it.
322 */
323 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
324 pci_read_config_byte(d, 0x82, &dlc);
325 if (!(dlc & 1<<1)) {
326 pci_info(d, "PIIX3: Enabling Passive Release\n");
327 dlc |= 1<<1;
328 pci_write_config_byte(d, 0x82, dlc);
329 }
330 }
331}
332DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
333DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
334
335#ifdef CONFIG_X86_32
336/*
337 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a
338 * workaround but VIA don't answer queries. If you happen to have good
339 * contacts at VIA ask them for me please -- Alan
340 *
341 * This appears to be BIOS not version dependent. So presumably there is a
342 * chipset level fix.
343 */
344static void quirk_isa_dma_hangs(struct pci_dev *dev)
345{
346 if (!isa_dma_bridge_buggy) {
347 isa_dma_bridge_buggy = 1;
348 pci_info(dev, "Activating ISA DMA hang workarounds\n");
349 }
350}
351/*
352 * It's not totally clear which chipsets are the problematic ones. We know
353 * 82C586 and 82C596 variants are affected.
354 */
355DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
356DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
357DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
358DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
359DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
360DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
361DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
362#endif
363
364#ifdef CONFIG_HAS_IOPORT
365/*
366 * Intel NM10 "Tiger Point" LPC PM1a_STS.BM_STS must be clear
367 * for some HT machines to use C4 w/o hanging.
368 */
369static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
370{
371 u32 pmbase;
372 u16 pm1a;
373
374 pci_read_config_dword(dev, 0x40, &pmbase);
375 pmbase = pmbase & 0xff80;
376 pm1a = inw(pmbase);
377
378 if (pm1a & 0x10) {
379 pci_info(dev, FW_BUG "Tiger Point LPC.BM_STS cleared\n");
380 outw(0x10, pmbase);
381 }
382}
383DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
384#endif
385
386/* Chipsets where PCI->PCI transfers vanish or hang */
387static void quirk_nopcipci(struct pci_dev *dev)
388{
389 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
390 pci_info(dev, "Disabling direct PCI/PCI transfers\n");
391 pci_pci_problems |= PCIPCI_FAIL;
392 }
393}
394DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
395DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
396
397static void quirk_nopciamd(struct pci_dev *dev)
398{
399 u8 rev;
400 pci_read_config_byte(dev, 0x08, &rev);
401 if (rev == 0x13) {
402 /* Erratum 24 */
403 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
404 pci_pci_problems |= PCIAGP_FAIL;
405 }
406}
407DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
408
409/* Triton requires workarounds to be used by the drivers */
410static void quirk_triton(struct pci_dev *dev)
411{
412 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
413 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
414 pci_pci_problems |= PCIPCI_TRITON;
415 }
416}
417DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
418DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
419DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
420DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
421
422/*
423 * VIA Apollo KT133 needs PCI latency patch
424 * Made according to a Windows driver-based patch by George E. Breese;
425 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
426 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
427 * which Mr Breese based his work.
428 *
429 * Updated based on further information from the site and also on
430 * information provided by VIA
431 */
432static void quirk_vialatency(struct pci_dev *dev)
433{
434 struct pci_dev *p;
435 u8 busarb;
436
437 /*
438 * Ok, we have a potential problem chipset here. Now see if we have
439 * a buggy southbridge.
440 */
441 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
442 if (p != NULL) {
443
444 /*
445 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A;
446 * thanks Dan Hollis.
447 * Check for buggy part revisions
448 */
449 if (p->revision < 0x40 || p->revision > 0x42)
450 goto exit;
451 } else {
452 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
453 if (p == NULL) /* No problem parts */
454 goto exit;
455
456 /* Check for buggy part revisions */
457 if (p->revision < 0x10 || p->revision > 0x12)
458 goto exit;
459 }
460
461 /*
462 * Ok we have the problem. Now set the PCI master grant to occur
463 * every master grant. The apparent bug is that under high PCI load
464 * (quite common in Linux of course) you can get data loss when the
465 * CPU is held off the bus for 3 bus master requests. This happens
466 * to include the IDE controllers....
467 *
468 * VIA only apply this fix when an SB Live! is present but under
469 * both Linux and Windows this isn't enough, and we have seen
470 * corruption without SB Live! but with things like 3 UDMA IDE
471 * controllers. So we ignore that bit of the VIA recommendation..
472 */
473 pci_read_config_byte(dev, 0x76, &busarb);
474
475 /*
476 * Set bit 4 and bit 5 of byte 76 to 0x01
477 * "Master priority rotation on every PCI master grant"
478 */
479 busarb &= ~(1<<5);
480 busarb |= (1<<4);
481 pci_write_config_byte(dev, 0x76, busarb);
482 pci_info(dev, "Applying VIA southbridge workaround\n");
483exit:
484 pci_dev_put(p);
485}
486DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
487DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
488DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
489/* Must restore this on a resume from RAM */
490DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
491DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
492DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
493
494/* VIA Apollo VP3 needs ETBF on BT848/878 */
495static void quirk_viaetbf(struct pci_dev *dev)
496{
497 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
498 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
499 pci_pci_problems |= PCIPCI_VIAETBF;
500 }
501}
502DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
503
504static void quirk_vsfx(struct pci_dev *dev)
505{
506 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
507 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
508 pci_pci_problems |= PCIPCI_VSFX;
509 }
510}
511DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
512
513/*
514 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP
515 * space. Latency must be set to 0xA and Triton workaround applied too.
516 * [Info kindly provided by ALi]
517 */
518static void quirk_alimagik(struct pci_dev *dev)
519{
520 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
521 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
522 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
523 }
524}
525DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
526DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
527
528/* Natoma has some interesting boundary conditions with Zoran stuff at least */
529static void quirk_natoma(struct pci_dev *dev)
530{
531 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
532 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
533 pci_pci_problems |= PCIPCI_NATOMA;
534 }
535}
536DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
537DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
538DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
539DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
540DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
541DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
542
543/*
544 * This chip can cause PCI parity errors if config register 0xA0 is read
545 * while DMAs are occurring.
546 */
547static void quirk_citrine(struct pci_dev *dev)
548{
549 dev->cfg_size = 0xA0;
550}
551DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
552
553/*
554 * This chip can cause bus lockups if config addresses above 0x600
555 * are read or written.
556 */
557static void quirk_nfp6000(struct pci_dev *dev)
558{
559 dev->cfg_size = 0x600;
560}
561DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
562DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
563DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000);
564DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
565
566/* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
567static void quirk_extend_bar_to_page(struct pci_dev *dev)
568{
569 int i;
570
571 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
572 struct resource *r = &dev->resource[i];
573 const char *r_name = pci_resource_name(dev, i);
574
575 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
576 r->end = PAGE_SIZE - 1;
577 r->start = 0;
578 r->flags |= IORESOURCE_UNSET;
579 pci_info(dev, "%s %pR: expanded to page size\n",
580 r_name, r);
581 }
582 }
583}
584DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
585
586/*
587 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
588 * If it's needed, re-allocate the region.
589 */
590static void quirk_s3_64M(struct pci_dev *dev)
591{
592 struct resource *r = &dev->resource[0];
593
594 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
595 r->flags |= IORESOURCE_UNSET;
596 r->start = 0;
597 r->end = 0x3ffffff;
598 }
599}
600DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
601DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
602
603static void quirk_io(struct pci_dev *dev, int pos, unsigned int size,
604 const char *name)
605{
606 u32 region;
607 struct pci_bus_region bus_region;
608 struct resource *res = dev->resource + pos;
609 const char *res_name = pci_resource_name(dev, pos);
610
611 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion);
612
613 if (!region)
614 return;
615
616 res->name = pci_name(dev);
617 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
618 res->flags |=
619 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
620 region &= ~(size - 1);
621
622 /* Convert from PCI bus to resource space */
623 bus_region.start = region;
624 bus_region.end = region + size - 1;
625 pcibios_bus_to_resource(dev->bus, res, &bus_region);
626
627 pci_info(dev, FW_BUG "%s %pR: %s quirk\n", res_name, res, name);
628}
629
630/*
631 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
632 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
633 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
634 * (which conflicts w/ BAR1's memory range).
635 *
636 * CS553x's ISA PCI BARs may also be read-only (ref:
637 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
638 */
639static void quirk_cs5536_vsa(struct pci_dev *dev)
640{
641 static char *name = "CS5536 ISA bridge";
642
643 if (pci_resource_len(dev, 0) != 8) {
644 quirk_io(dev, 0, 8, name); /* SMB */
645 quirk_io(dev, 1, 256, name); /* GPIO */
646 quirk_io(dev, 2, 64, name); /* MFGPT */
647 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n",
648 name);
649 }
650}
651DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
652
653static void quirk_io_region(struct pci_dev *dev, int port,
654 unsigned int size, int nr, const char *name)
655{
656 u16 region;
657 struct pci_bus_region bus_region;
658 struct resource *res = dev->resource + nr;
659
660 pci_read_config_word(dev, port, ®ion);
661 region &= ~(size - 1);
662
663 if (!region)
664 return;
665
666 res->name = pci_name(dev);
667 res->flags = IORESOURCE_IO;
668
669 /* Convert from PCI bus to resource space */
670 bus_region.start = region;
671 bus_region.end = region + size - 1;
672 pcibios_bus_to_resource(dev->bus, res, &bus_region);
673
674 /*
675 * "res" is typically a bridge window resource that's not being
676 * used for a bridge window, so it's just a place to stash this
677 * non-standard resource. Printing "nr" or pci_resource_name() of
678 * it doesn't really make sense.
679 */
680 if (!pci_claim_resource(dev, nr))
681 pci_info(dev, "quirk: %pR claimed by %s\n", res, name);
682}
683
684/*
685 * ATI Northbridge setups MCE the processor if you even read somewhere
686 * between 0x3b0->0x3bb or read 0x3d3
687 */
688static void quirk_ati_exploding_mce(struct pci_dev *dev)
689{
690 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
691 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
692 request_region(0x3b0, 0x0C, "RadeonIGP");
693 request_region(0x3d3, 0x01, "RadeonIGP");
694}
695DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
696
697/*
698 * In the AMD NL platform, this device ([1022:7912]) has a class code of
699 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
700 * claim it. The same applies on the VanGogh platform device ([1022:163a]).
701 *
702 * But the dwc3 driver is a more specific driver for this device, and we'd
703 * prefer to use it instead of xhci. To prevent xhci from claiming the
704 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
705 * defines as "USB device (not host controller)". The dwc3 driver can then
706 * claim it based on its Vendor and Device ID.
707 */
708static void quirk_amd_dwc_class(struct pci_dev *pdev)
709{
710 u32 class = pdev->class;
711
712 if (class != PCI_CLASS_SERIAL_USB_DEVICE) {
713 /* Use "USB Device (not host controller)" class */
714 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
715 pci_info(pdev,
716 "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
717 class, pdev->class);
718 }
719}
720DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
721 quirk_amd_dwc_class);
722DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VANGOGH_USB,
723 quirk_amd_dwc_class);
724
725/*
726 * Synopsys USB 3.x host HAPS platform has a class code of
727 * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these
728 * devices should use dwc3-haps driver. Change these devices' class code to
729 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
730 * them.
731 */
732static void quirk_synopsys_haps(struct pci_dev *pdev)
733{
734 u32 class = pdev->class;
735
736 switch (pdev->device) {
737 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3:
738 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI:
739 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31:
740 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
741 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
742 class, pdev->class);
743 break;
744 }
745}
746DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID,
747 PCI_CLASS_SERIAL_USB_XHCI, 0,
748 quirk_synopsys_haps);
749
750/*
751 * Let's make the southbridge information explicit instead of having to
752 * worry about people probing the ACPI areas, for example.. (Yes, it
753 * happens, and if you read the wrong ACPI register it will put the machine
754 * to sleep with no way of waking it up again. Bummer).
755 *
756 * ALI M7101: Two IO regions pointed to by words at
757 * 0xE0 (64 bytes of ACPI registers)
758 * 0xE2 (32 bytes of SMB registers)
759 */
760static void quirk_ali7101_acpi(struct pci_dev *dev)
761{
762 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
763 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
764}
765DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
766
767static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
768{
769 u32 devres;
770 u32 mask, size, base;
771
772 pci_read_config_dword(dev, port, &devres);
773 if ((devres & enable) != enable)
774 return;
775 mask = (devres >> 16) & 15;
776 base = devres & 0xffff;
777 size = 16;
778 for (;;) {
779 unsigned int bit = size >> 1;
780 if ((bit & mask) == bit)
781 break;
782 size = bit;
783 }
784 /*
785 * For now we only print it out. Eventually we'll want to
786 * reserve it (at least if it's in the 0x1000+ range), but
787 * let's get enough confirmation reports first.
788 */
789 base &= -size;
790 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
791}
792
793static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
794{
795 u32 devres;
796 u32 mask, size, base;
797
798 pci_read_config_dword(dev, port, &devres);
799 if ((devres & enable) != enable)
800 return;
801 base = devres & 0xffff0000;
802 mask = (devres & 0x3f) << 16;
803 size = 128 << 16;
804 for (;;) {
805 unsigned int bit = size >> 1;
806 if ((bit & mask) == bit)
807 break;
808 size = bit;
809 }
810
811 /*
812 * For now we only print it out. Eventually we'll want to
813 * reserve it, but let's get enough confirmation reports first.
814 */
815 base &= -size;
816 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
817}
818
819/*
820 * PIIX4 ACPI: Two IO regions pointed to by longwords at
821 * 0x40 (64 bytes of ACPI registers)
822 * 0x90 (16 bytes of SMB registers)
823 * and a few strange programmable PIIX4 device resources.
824 */
825static void quirk_piix4_acpi(struct pci_dev *dev)
826{
827 u32 res_a;
828
829 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
830 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
831
832 /* Device resource A has enables for some of the other ones */
833 pci_read_config_dword(dev, 0x5c, &res_a);
834
835 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
836 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
837
838 /* Device resource D is just bitfields for static resources */
839
840 /* Device 12 enabled? */
841 if (res_a & (1 << 29)) {
842 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
843 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
844 }
845 /* Device 13 enabled? */
846 if (res_a & (1 << 30)) {
847 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
848 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
849 }
850 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
851 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
852}
853DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
854DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
855
856#define ICH_PMBASE 0x40
857#define ICH_ACPI_CNTL 0x44
858#define ICH4_ACPI_EN 0x10
859#define ICH6_ACPI_EN 0x80
860#define ICH4_GPIOBASE 0x58
861#define ICH4_GPIO_CNTL 0x5c
862#define ICH4_GPIO_EN 0x10
863#define ICH6_GPIOBASE 0x48
864#define ICH6_GPIO_CNTL 0x4c
865#define ICH6_GPIO_EN 0x10
866
867/*
868 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
869 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
870 * 0x58 (64 bytes of GPIO I/O space)
871 */
872static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
873{
874 u8 enable;
875
876 /*
877 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
878 * with low legacy (and fixed) ports. We don't know the decoding
879 * priority and can't tell whether the legacy device or the one created
880 * here is really at that address. This happens on boards with broken
881 * BIOSes.
882 */
883 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
884 if (enable & ICH4_ACPI_EN)
885 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
886 "ICH4 ACPI/GPIO/TCO");
887
888 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
889 if (enable & ICH4_GPIO_EN)
890 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
891 "ICH4 GPIO");
892}
893DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
894DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
895DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
896DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
897DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
898DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
899DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
900DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
901DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
902DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
903
904static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
905{
906 u8 enable;
907
908 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
909 if (enable & ICH6_ACPI_EN)
910 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
911 "ICH6 ACPI/GPIO/TCO");
912
913 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
914 if (enable & ICH6_GPIO_EN)
915 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
916 "ICH6 GPIO");
917}
918
919static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned int reg,
920 const char *name, int dynsize)
921{
922 u32 val;
923 u32 size, base;
924
925 pci_read_config_dword(dev, reg, &val);
926
927 /* Enabled? */
928 if (!(val & 1))
929 return;
930 base = val & 0xfffc;
931 if (dynsize) {
932 /*
933 * This is not correct. It is 16, 32 or 64 bytes depending on
934 * register D31:F0:ADh bits 5:4.
935 *
936 * But this gets us at least _part_ of it.
937 */
938 size = 16;
939 } else {
940 size = 128;
941 }
942 base &= ~(size-1);
943
944 /*
945 * Just print it out for now. We should reserve it after more
946 * debugging.
947 */
948 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
949}
950
951static void quirk_ich6_lpc(struct pci_dev *dev)
952{
953 /* Shared ACPI/GPIO decode with all ICH6+ */
954 ich6_lpc_acpi_gpio(dev);
955
956 /* ICH6-specific generic IO decode */
957 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
958 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
959}
960DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
961DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
962
963static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned int reg,
964 const char *name)
965{
966 u32 val;
967 u32 mask, base;
968
969 pci_read_config_dword(dev, reg, &val);
970
971 /* Enabled? */
972 if (!(val & 1))
973 return;
974
975 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */
976 base = val & 0xfffc;
977 mask = (val >> 16) & 0xfc;
978 mask |= 3;
979
980 /*
981 * Just print it out for now. We should reserve it after more
982 * debugging.
983 */
984 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
985}
986
987/* ICH7-10 has the same common LPC generic IO decode registers */
988static void quirk_ich7_lpc(struct pci_dev *dev)
989{
990 /* We share the common ACPI/GPIO decode with ICH6 */
991 ich6_lpc_acpi_gpio(dev);
992
993 /* And have 4 ICH7+ generic decodes */
994 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
995 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
996 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
997 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
998}
999DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
1000DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
1001DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
1002DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
1003DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
1004DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
1005DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
1006DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
1007DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
1008DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
1009DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
1010DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
1011DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
1012
1013/*
1014 * VIA ACPI: One IO region pointed to by longword at
1015 * 0x48 or 0x20 (256 bytes of ACPI registers)
1016 */
1017static void quirk_vt82c586_acpi(struct pci_dev *dev)
1018{
1019 if (dev->revision & 0x10)
1020 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
1021 "vt82c586 ACPI");
1022}
1023DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
1024
1025/*
1026 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
1027 * 0x48 (256 bytes of ACPI registers)
1028 * 0x70 (128 bytes of hardware monitoring register)
1029 * 0x90 (16 bytes of SMB registers)
1030 */
1031static void quirk_vt82c686_acpi(struct pci_dev *dev)
1032{
1033 quirk_vt82c586_acpi(dev);
1034
1035 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
1036 "vt82c686 HW-mon");
1037
1038 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
1039}
1040DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
1041
1042/*
1043 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
1044 * 0x88 (128 bytes of power management registers)
1045 * 0xd0 (16 bytes of SMB registers)
1046 */
1047static void quirk_vt8235_acpi(struct pci_dev *dev)
1048{
1049 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
1050 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
1051}
1052DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
1053
1054/*
1055 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
1056 * back-to-back: Disable fast back-to-back on the secondary bus segment
1057 */
1058static void quirk_xio2000a(struct pci_dev *dev)
1059{
1060 struct pci_dev *pdev;
1061 u16 command;
1062
1063 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
1064 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
1065 pci_read_config_word(pdev, PCI_COMMAND, &command);
1066 if (command & PCI_COMMAND_FAST_BACK)
1067 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
1068 }
1069}
1070DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
1071 quirk_xio2000a);
1072
1073#ifdef CONFIG_X86_IO_APIC
1074
1075#include <asm/io_apic.h>
1076
1077/*
1078 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
1079 * devices to the external APIC.
1080 *
1081 * TODO: When we have device-specific interrupt routers, this code will go
1082 * away from quirks.
1083 */
1084static void quirk_via_ioapic(struct pci_dev *dev)
1085{
1086 u8 tmp;
1087
1088 if (nr_ioapics < 1)
1089 tmp = 0; /* nothing routed to external APIC */
1090 else
1091 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
1092
1093 pci_info(dev, "%s VIA external APIC routing\n",
1094 tmp ? "Enabling" : "Disabling");
1095
1096 /* Offset 0x58: External APIC IRQ output control */
1097 pci_write_config_byte(dev, 0x58, tmp);
1098}
1099DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
1100DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
1101
1102/*
1103 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
1104 * This leads to doubled level interrupt rates.
1105 * Set this bit to get rid of cycle wastage.
1106 * Otherwise uncritical.
1107 */
1108static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
1109{
1110 u8 misc_control2;
1111#define BYPASS_APIC_DEASSERT 8
1112
1113 pci_read_config_byte(dev, 0x5B, &misc_control2);
1114 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
1115 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
1116 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
1117 }
1118}
1119DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
1120DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
1121
1122/*
1123 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
1124 * We check all revs >= B0 (yet not in the pre production!) as the bug
1125 * is currently marked NoFix
1126 *
1127 * We have multiple reports of hangs with this chipset that went away with
1128 * noapic specified. For the moment we assume it's the erratum. We may be wrong
1129 * of course. However the advice is demonstrably good even if so.
1130 */
1131static void quirk_amd_ioapic(struct pci_dev *dev)
1132{
1133 if (dev->revision >= 0x02) {
1134 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
1135 pci_warn(dev, " : booting with the \"noapic\" option\n");
1136 }
1137}
1138DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
1139#endif /* CONFIG_X86_IO_APIC */
1140
1141#if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
1142
1143static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
1144{
1145 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */
1146 if (dev->subsystem_device == 0xa118)
1147 dev->sriov->link = dev->devfn;
1148}
1149DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
1150#endif
1151
1152/*
1153 * Some settings of MMRBC can lead to data corruption so block changes.
1154 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1155 */
1156static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
1157{
1158 if (dev->subordinate && dev->revision <= 0x12) {
1159 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
1160 dev->revision);
1161 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
1162 }
1163}
1164DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
1165
1166/*
1167 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up
1168 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register
1169 * at all. Therefore it seems like setting the pci_dev's IRQ to the value
1170 * of the ACPI SCI interrupt is only done for convenience.
1171 * -jgarzik
1172 */
1173static void quirk_via_acpi(struct pci_dev *d)
1174{
1175 u8 irq;
1176
1177 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */
1178 pci_read_config_byte(d, 0x42, &irq);
1179 irq &= 0xf;
1180 if (irq && (irq != 2))
1181 d->irq = irq;
1182}
1183DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
1184DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
1185
1186/* VIA bridges which have VLink */
1187static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
1188
1189static void quirk_via_bridge(struct pci_dev *dev)
1190{
1191 /* See what bridge we have and find the device ranges */
1192 switch (dev->device) {
1193 case PCI_DEVICE_ID_VIA_82C686:
1194 /*
1195 * The VT82C686 is special; it attaches to PCI and can have
1196 * any device number. All its subdevices are functions of
1197 * that single device.
1198 */
1199 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
1200 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
1201 break;
1202 case PCI_DEVICE_ID_VIA_8237:
1203 case PCI_DEVICE_ID_VIA_8237A:
1204 via_vlink_dev_lo = 15;
1205 break;
1206 case PCI_DEVICE_ID_VIA_8235:
1207 via_vlink_dev_lo = 16;
1208 break;
1209 case PCI_DEVICE_ID_VIA_8231:
1210 case PCI_DEVICE_ID_VIA_8233_0:
1211 case PCI_DEVICE_ID_VIA_8233A:
1212 case PCI_DEVICE_ID_VIA_8233C_0:
1213 via_vlink_dev_lo = 17;
1214 break;
1215 }
1216}
1217DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
1218DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
1219DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
1220DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
1221DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
1222DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
1223DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
1224DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
1225
1226/*
1227 * quirk_via_vlink - VIA VLink IRQ number update
1228 * @dev: PCI device
1229 *
1230 * If the device we are dealing with is on a PIC IRQ we need to ensure that
1231 * the IRQ line register which usually is not relevant for PCI cards, is
1232 * actually written so that interrupts get sent to the right place.
1233 *
1234 * We only do this on systems where a VIA south bridge was detected, and
1235 * only for VIA devices on the motherboard (see quirk_via_bridge above).
1236 */
1237static void quirk_via_vlink(struct pci_dev *dev)
1238{
1239 u8 irq, new_irq;
1240
1241 /* Check if we have VLink at all */
1242 if (via_vlink_dev_lo == -1)
1243 return;
1244
1245 new_irq = dev->irq;
1246
1247 /* Don't quirk interrupts outside the legacy IRQ range */
1248 if (!new_irq || new_irq > 15)
1249 return;
1250
1251 /* Internal device ? */
1252 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
1253 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1254 return;
1255
1256 /*
1257 * This is an internal VLink device on a PIC interrupt. The BIOS
1258 * ought to have set this but may not have, so we redo it.
1259 */
1260 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1261 if (new_irq != irq) {
1262 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n",
1263 irq, new_irq);
1264 udelay(15); /* unknown if delay really needed */
1265 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
1266 }
1267}
1268DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
1269
1270/*
1271 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID
1272 * of VT82C597 for backward compatibility. We need to switch it off to be
1273 * able to recognize the real type of the chip.
1274 */
1275static void quirk_vt82c598_id(struct pci_dev *dev)
1276{
1277 pci_write_config_byte(dev, 0xfc, 0);
1278 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
1279}
1280DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
1281
1282/*
1283 * CardBus controllers have a legacy base address that enables them to
1284 * respond as i82365 pcmcia controllers. We don't want them to do this
1285 * even if the Linux CardBus driver is not loaded, because the Linux i82365
1286 * driver does not (and should not) handle CardBus.
1287 */
1288static void quirk_cardbus_legacy(struct pci_dev *dev)
1289{
1290 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
1291}
1292DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1293 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1294DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
1295 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1296
1297/*
1298 * Following the PCI ordering rules is optional on the AMD762. I'm not sure
1299 * what the designers were smoking but let's not inhale...
1300 *
1301 * To be fair to AMD, it follows the spec by default, it's BIOS people who
1302 * turn it off!
1303 */
1304static void quirk_amd_ordering(struct pci_dev *dev)
1305{
1306 u32 pcic;
1307 pci_read_config_dword(dev, 0x4C, &pcic);
1308 if ((pcic & 6) != 6) {
1309 pcic |= 6;
1310 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1311 pci_write_config_dword(dev, 0x4C, pcic);
1312 pci_read_config_dword(dev, 0x84, &pcic);
1313 pcic |= (1 << 23); /* Required in this mode */
1314 pci_write_config_dword(dev, 0x84, pcic);
1315 }
1316}
1317DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1318DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1319
1320/*
1321 * DreamWorks-provided workaround for Dunord I-3000 problem
1322 *
1323 * This card decodes and responds to addresses not apparently assigned to
1324 * it. We force a larger allocation to ensure that nothing gets put too
1325 * close to it.
1326 */
1327static void quirk_dunord(struct pci_dev *dev)
1328{
1329 struct resource *r = &dev->resource[1];
1330
1331 r->flags |= IORESOURCE_UNSET;
1332 r->start = 0;
1333 r->end = 0xffffff;
1334}
1335DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1336
1337/*
1338 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1339 * decoding (transparent), and does indicate this in the ProgIf.
1340 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1341 */
1342static void quirk_transparent_bridge(struct pci_dev *dev)
1343{
1344 dev->transparent = 1;
1345}
1346DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1347DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1348
1349/*
1350 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
1351 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets
1352 * found at http://www.national.com/analog for info on what these bits do.
1353 * <christer@weinigel.se>
1354 */
1355static void quirk_mediagx_master(struct pci_dev *dev)
1356{
1357 u8 reg;
1358
1359 pci_read_config_byte(dev, 0x41, ®);
1360 if (reg & 2) {
1361 reg &= ~2;
1362 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1363 reg);
1364 pci_write_config_byte(dev, 0x41, reg);
1365 }
1366}
1367DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1368DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1369
1370/*
1371 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but
1372 * in the odd case it is not the results are corruption hence the presence
1373 * of a Linux check.
1374 */
1375static void quirk_disable_pxb(struct pci_dev *pdev)
1376{
1377 u16 config;
1378
1379 if (pdev->revision != 0x04) /* Only C0 requires this */
1380 return;
1381 pci_read_config_word(pdev, 0x40, &config);
1382 if (config & (1<<6)) {
1383 config &= ~(1<<6);
1384 pci_write_config_word(pdev, 0x40, config);
1385 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n");
1386 }
1387}
1388DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1389DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1390
1391static void quirk_amd_ide_mode(struct pci_dev *pdev)
1392{
1393 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1394 u8 tmp;
1395
1396 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1397 if (tmp == 0x01) {
1398 pci_read_config_byte(pdev, 0x40, &tmp);
1399 pci_write_config_byte(pdev, 0x40, tmp|1);
1400 pci_write_config_byte(pdev, 0x9, 1);
1401 pci_write_config_byte(pdev, 0xa, 6);
1402 pci_write_config_byte(pdev, 0x40, tmp);
1403
1404 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1405 pci_info(pdev, "set SATA to AHCI mode\n");
1406 }
1407}
1408DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1409DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1410DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1411DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1412DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1413DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1414DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1415DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1416
1417/* Serverworks CSB5 IDE does not fully support native mode */
1418static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1419{
1420 u8 prog;
1421 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1422 if (prog & 5) {
1423 prog &= ~5;
1424 pdev->class &= ~5;
1425 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1426 /* PCI layer will sort out resources */
1427 }
1428}
1429DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1430
1431/* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
1432static void quirk_ide_samemode(struct pci_dev *pdev)
1433{
1434 u8 prog;
1435
1436 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1437
1438 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1439 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n");
1440 prog &= ~5;
1441 pdev->class &= ~5;
1442 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1443 }
1444}
1445DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1446
1447/* Some ATA devices break if put into D3 */
1448static void quirk_no_ata_d3(struct pci_dev *pdev)
1449{
1450 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1451}
1452/* Quirk the legacy ATA devices only. The AHCI ones are ok */
1453DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1454 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1455DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1456 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1457/* ALi loses some register settings that we cannot then restore */
1458DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1459 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1460/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1461 occur when mode detecting */
1462DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1463 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1464
1465/*
1466 * This was originally an Alpha-specific thing, but it really fits here.
1467 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1468 */
1469static void quirk_eisa_bridge(struct pci_dev *dev)
1470{
1471 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1472}
1473DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1474
1475/*
1476 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1477 * is not activated. The myth is that Asus said that they do not want the
1478 * users to be irritated by just another PCI Device in the Win98 device
1479 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1480 * package 2.7.0 for details)
1481 *
1482 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1483 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1484 * becomes necessary to do this tweak in two steps -- the chosen trigger
1485 * is either the Host bridge (preferred) or on-board VGA controller.
1486 *
1487 * Note that we used to unhide the SMBus that way on Toshiba laptops
1488 * (Satellite A40 and Tecra M2) but then found that the thermal management
1489 * was done by SMM code, which could cause unsynchronized concurrent
1490 * accesses to the SMBus registers, with potentially bad effects. Thus you
1491 * should be very careful when adding new entries: if SMM is accessing the
1492 * Intel SMBus, this is a very good reason to leave it hidden.
1493 *
1494 * Likewise, many recent laptops use ACPI for thermal management. If the
1495 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1496 * natively, and keeping the SMBus hidden is the right thing to do. If you
1497 * are about to add an entry in the table below, please first disassemble
1498 * the DSDT and double-check that there is no code accessing the SMBus.
1499 */
1500static int asus_hides_smbus;
1501
1502static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1503{
1504 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1505 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1506 switch (dev->subsystem_device) {
1507 case 0x8025: /* P4B-LX */
1508 case 0x8070: /* P4B */
1509 case 0x8088: /* P4B533 */
1510 case 0x1626: /* L3C notebook */
1511 asus_hides_smbus = 1;
1512 }
1513 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1514 switch (dev->subsystem_device) {
1515 case 0x80b1: /* P4GE-V */
1516 case 0x80b2: /* P4PE */
1517 case 0x8093: /* P4B533-V */
1518 asus_hides_smbus = 1;
1519 }
1520 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1521 switch (dev->subsystem_device) {
1522 case 0x8030: /* P4T533 */
1523 asus_hides_smbus = 1;
1524 }
1525 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1526 switch (dev->subsystem_device) {
1527 case 0x8070: /* P4G8X Deluxe */
1528 asus_hides_smbus = 1;
1529 }
1530 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1531 switch (dev->subsystem_device) {
1532 case 0x80c9: /* PU-DLS */
1533 asus_hides_smbus = 1;
1534 }
1535 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1536 switch (dev->subsystem_device) {
1537 case 0x1751: /* M2N notebook */
1538 case 0x1821: /* M5N notebook */
1539 case 0x1897: /* A6L notebook */
1540 asus_hides_smbus = 1;
1541 }
1542 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1543 switch (dev->subsystem_device) {
1544 case 0x184b: /* W1N notebook */
1545 case 0x186a: /* M6Ne notebook */
1546 asus_hides_smbus = 1;
1547 }
1548 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1549 switch (dev->subsystem_device) {
1550 case 0x80f2: /* P4P800-X */
1551 asus_hides_smbus = 1;
1552 }
1553 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1554 switch (dev->subsystem_device) {
1555 case 0x1882: /* M6V notebook */
1556 case 0x1977: /* A6VA notebook */
1557 asus_hides_smbus = 1;
1558 }
1559 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1560 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1561 switch (dev->subsystem_device) {
1562 case 0x088C: /* HP Compaq nc8000 */
1563 case 0x0890: /* HP Compaq nc6000 */
1564 asus_hides_smbus = 1;
1565 }
1566 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1567 switch (dev->subsystem_device) {
1568 case 0x12bc: /* HP D330L */
1569 case 0x12bd: /* HP D530 */
1570 case 0x006a: /* HP Compaq nx9500 */
1571 asus_hides_smbus = 1;
1572 }
1573 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1574 switch (dev->subsystem_device) {
1575 case 0x12bf: /* HP xw4100 */
1576 asus_hides_smbus = 1;
1577 }
1578 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1579 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1580 switch (dev->subsystem_device) {
1581 case 0xC00C: /* Samsung P35 notebook */
1582 asus_hides_smbus = 1;
1583 }
1584 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1585 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1586 switch (dev->subsystem_device) {
1587 case 0x0058: /* Compaq Evo N620c */
1588 asus_hides_smbus = 1;
1589 }
1590 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1591 switch (dev->subsystem_device) {
1592 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1593 /* Motherboard doesn't have Host bridge
1594 * subvendor/subdevice IDs, therefore checking
1595 * its on-board VGA controller */
1596 asus_hides_smbus = 1;
1597 }
1598 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1599 switch (dev->subsystem_device) {
1600 case 0x00b8: /* Compaq Evo D510 CMT */
1601 case 0x00b9: /* Compaq Evo D510 SFF */
1602 case 0x00ba: /* Compaq Evo D510 USDT */
1603 /* Motherboard doesn't have Host bridge
1604 * subvendor/subdevice IDs and on-board VGA
1605 * controller is disabled if an AGP card is
1606 * inserted, therefore checking USB UHCI
1607 * Controller #1 */
1608 asus_hides_smbus = 1;
1609 }
1610 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1611 switch (dev->subsystem_device) {
1612 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1613 /* Motherboard doesn't have host bridge
1614 * subvendor/subdevice IDs, therefore checking
1615 * its on-board VGA controller */
1616 asus_hides_smbus = 1;
1617 }
1618 }
1619}
1620DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1621DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1622DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1623DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1624DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1625DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1626DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1627DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1628DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1629DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1630
1631DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1632DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1633DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1634
1635static void asus_hides_smbus_lpc(struct pci_dev *dev)
1636{
1637 u16 val;
1638
1639 if (likely(!asus_hides_smbus))
1640 return;
1641
1642 pci_read_config_word(dev, 0xF2, &val);
1643 if (val & 0x8) {
1644 pci_write_config_word(dev, 0xF2, val & (~0x8));
1645 pci_read_config_word(dev, 0xF2, &val);
1646 if (val & 0x8)
1647 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1648 val);
1649 else
1650 pci_info(dev, "Enabled i801 SMBus device\n");
1651 }
1652}
1653DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1654DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1655DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1656DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1657DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1658DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1659DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1660DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1661DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1662DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1663DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1664DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1665DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1666DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1667
1668/* It appears we just have one such device. If not, we have a warning */
1669static void __iomem *asus_rcba_base;
1670static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1671{
1672 u32 rcba;
1673
1674 if (likely(!asus_hides_smbus))
1675 return;
1676 WARN_ON(asus_rcba_base);
1677
1678 pci_read_config_dword(dev, 0xF0, &rcba);
1679 /* use bits 31:14, 16 kB aligned */
1680 asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000);
1681 if (asus_rcba_base == NULL)
1682 return;
1683}
1684
1685static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1686{
1687 u32 val;
1688
1689 if (likely(!asus_hides_smbus || !asus_rcba_base))
1690 return;
1691
1692 /* read the Function Disable register, dword mode only */
1693 val = readl(asus_rcba_base + 0x3418);
1694
1695 /* enable the SMBus device */
1696 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
1697}
1698
1699static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1700{
1701 if (likely(!asus_hides_smbus || !asus_rcba_base))
1702 return;
1703
1704 iounmap(asus_rcba_base);
1705 asus_rcba_base = NULL;
1706 pci_info(dev, "Enabled ICH6/i801 SMBus device\n");
1707}
1708
1709static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1710{
1711 asus_hides_smbus_lpc_ich6_suspend(dev);
1712 asus_hides_smbus_lpc_ich6_resume_early(dev);
1713 asus_hides_smbus_lpc_ich6_resume(dev);
1714}
1715DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1716DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1717DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1718DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1719
1720/* SiS 96x south bridge: BIOS typically hides SMBus device... */
1721static void quirk_sis_96x_smbus(struct pci_dev *dev)
1722{
1723 u8 val = 0;
1724 pci_read_config_byte(dev, 0x77, &val);
1725 if (val & 0x10) {
1726 pci_info(dev, "Enabling SiS 96x SMBus\n");
1727 pci_write_config_byte(dev, 0x77, val & ~0x10);
1728 }
1729}
1730DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1731DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1732DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1733DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1734DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1735DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1736DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1737DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1738
1739/*
1740 * ... This is further complicated by the fact that some SiS96x south
1741 * bridges pretend to be 85C503/5513 instead. In that case see if we
1742 * spotted a compatible north bridge to make sure.
1743 * (pci_find_device() doesn't work yet)
1744 *
1745 * We can also enable the sis96x bit in the discovery register..
1746 */
1747#define SIS_DETECT_REGISTER 0x40
1748
1749static void quirk_sis_503(struct pci_dev *dev)
1750{
1751 u8 reg;
1752 u16 devid;
1753
1754 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1755 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1756 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1757 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1758 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1759 return;
1760 }
1761
1762 /*
1763 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case
1764 * it has already been processed. (Depends on link order, which is
1765 * apparently not guaranteed)
1766 */
1767 dev->device = devid;
1768 quirk_sis_96x_smbus(dev);
1769}
1770DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1771DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1772
1773/*
1774 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1775 * and MC97 modem controller are disabled when a second PCI soundcard is
1776 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1777 * -- bjd
1778 */
1779static void asus_hides_ac97_lpc(struct pci_dev *dev)
1780{
1781 u8 val;
1782 int asus_hides_ac97 = 0;
1783
1784 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1785 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1786 asus_hides_ac97 = 1;
1787 }
1788
1789 if (!asus_hides_ac97)
1790 return;
1791
1792 pci_read_config_byte(dev, 0x50, &val);
1793 if (val & 0xc0) {
1794 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1795 pci_read_config_byte(dev, 0x50, &val);
1796 if (val & 0xc0)
1797 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1798 val);
1799 else
1800 pci_info(dev, "Enabled onboard AC97/MC97 devices\n");
1801 }
1802}
1803DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1804DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1805
1806#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1807
1808/*
1809 * If we are using libata we can drive this chip properly but must do this
1810 * early on to make the additional device appear during the PCI scanning.
1811 */
1812static void quirk_jmicron_ata(struct pci_dev *pdev)
1813{
1814 u32 conf1, conf5, class;
1815 u8 hdr;
1816
1817 /* Only poke fn 0 */
1818 if (PCI_FUNC(pdev->devfn))
1819 return;
1820
1821 pci_read_config_dword(pdev, 0x40, &conf1);
1822 pci_read_config_dword(pdev, 0x80, &conf5);
1823
1824 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1825 conf5 &= ~(1 << 24); /* Clear bit 24 */
1826
1827 switch (pdev->device) {
1828 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1829 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1830 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1831 /* The controller should be in single function ahci mode */
1832 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1833 break;
1834
1835 case PCI_DEVICE_ID_JMICRON_JMB365:
1836 case PCI_DEVICE_ID_JMICRON_JMB366:
1837 /* Redirect IDE second PATA port to the right spot */
1838 conf5 |= (1 << 24);
1839 fallthrough;
1840 case PCI_DEVICE_ID_JMICRON_JMB361:
1841 case PCI_DEVICE_ID_JMICRON_JMB363:
1842 case PCI_DEVICE_ID_JMICRON_JMB369:
1843 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1844 /* Set the class codes correctly and then direct IDE 0 */
1845 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1846 break;
1847
1848 case PCI_DEVICE_ID_JMICRON_JMB368:
1849 /* The controller should be in single function IDE mode */
1850 conf1 |= 0x00C00000; /* Set 22, 23 */
1851 break;
1852 }
1853
1854 pci_write_config_dword(pdev, 0x40, conf1);
1855 pci_write_config_dword(pdev, 0x80, conf5);
1856
1857 /* Update pdev accordingly */
1858 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1859 pdev->hdr_type = hdr & PCI_HEADER_TYPE_MASK;
1860 pdev->multifunction = FIELD_GET(PCI_HEADER_TYPE_MFD, hdr);
1861
1862 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1863 pdev->class = class >> 8;
1864}
1865DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1866DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1867DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1868DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1869DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1870DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1871DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1872DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1873DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1874DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1875DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1876DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1877DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1878DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1879DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1880DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1881DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1882DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1883
1884#endif
1885
1886static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1887{
1888 if (dev->multifunction) {
1889 device_disable_async_suspend(&dev->dev);
1890 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1891 }
1892}
1893DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1894DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1895DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1896DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1897
1898#ifdef CONFIG_X86_IO_APIC
1899static void quirk_alder_ioapic(struct pci_dev *pdev)
1900{
1901 int i;
1902
1903 if ((pdev->class >> 8) != 0xff00)
1904 return;
1905
1906 /*
1907 * The first BAR is the location of the IO-APIC... we must
1908 * not touch this (and it's already covered by the fixmap), so
1909 * forcibly insert it into the resource tree.
1910 */
1911 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1912 insert_resource(&iomem_resource, &pdev->resource[0]);
1913
1914 /*
1915 * The next five BARs all seem to be rubbish, so just clean
1916 * them out.
1917 */
1918 for (i = 1; i < PCI_STD_NUM_BARS; i++)
1919 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1920}
1921DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1922#endif
1923
1924static void quirk_no_msi(struct pci_dev *dev)
1925{
1926 pci_info(dev, "avoiding MSI to work around a hardware defect\n");
1927 dev->no_msi = 1;
1928}
1929DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4386, quirk_no_msi);
1930DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4387, quirk_no_msi);
1931DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4388, quirk_no_msi);
1932DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4389, quirk_no_msi);
1933DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438a, quirk_no_msi);
1934DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438b, quirk_no_msi);
1935
1936static void quirk_pcie_mch(struct pci_dev *pdev)
1937{
1938 pdev->no_msi = 1;
1939}
1940DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1941DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1942DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1943
1944DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
1945
1946/*
1947 * HiSilicon KunPeng920 and KunPeng930 have devices appear as PCI but are
1948 * actually on the AMBA bus. These fake PCI devices can support SVA via
1949 * SMMU stall feature, by setting dma-can-stall for ACPI platforms.
1950 *
1951 * Normally stalling must not be enabled for PCI devices, since it would
1952 * break the PCI requirement for free-flowing writes and may lead to
1953 * deadlock. We expect PCI devices to support ATS and PRI if they want to
1954 * be fault-tolerant, so there's no ACPI binding to describe anything else,
1955 * even when a "PCI" device turns out to be a regular old SoC device
1956 * dressed up as a RCiEP and normal rules don't apply.
1957 */
1958static void quirk_huawei_pcie_sva(struct pci_dev *pdev)
1959{
1960 struct property_entry properties[] = {
1961 PROPERTY_ENTRY_BOOL("dma-can-stall"),
1962 {},
1963 };
1964
1965 if (pdev->revision != 0x21 && pdev->revision != 0x30)
1966 return;
1967
1968 pdev->pasid_no_tlp = 1;
1969
1970 /*
1971 * Set the dma-can-stall property on ACPI platforms. Device tree
1972 * can set it directly.
1973 */
1974 if (!pdev->dev.of_node &&
1975 device_create_managed_software_node(&pdev->dev, properties, NULL))
1976 pci_warn(pdev, "could not add stall property");
1977}
1978DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa250, quirk_huawei_pcie_sva);
1979DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa251, quirk_huawei_pcie_sva);
1980DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa255, quirk_huawei_pcie_sva);
1981DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa256, quirk_huawei_pcie_sva);
1982DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa258, quirk_huawei_pcie_sva);
1983DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa259, quirk_huawei_pcie_sva);
1984
1985/*
1986 * It's possible for the MSI to get corrupted if SHPC and ACPI are used
1987 * together on certain PXH-based systems.
1988 */
1989static void quirk_pcie_pxh(struct pci_dev *dev)
1990{
1991 dev->no_msi = 1;
1992 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n");
1993}
1994DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1995DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1996DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1997DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1998DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1999
2000/*
2001 * Some Intel PCI Express chipsets have trouble with downstream device
2002 * power management.
2003 */
2004static void quirk_intel_pcie_pm(struct pci_dev *dev)
2005{
2006 pci_pm_d3hot_delay = 120;
2007 dev->no_d1d2 = 1;
2008}
2009DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
2010DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
2011DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
2012DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
2013DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
2014DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
2015DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
2016DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
2017DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
2018DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
2019DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
2020DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
2021DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
2022DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
2023DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
2024DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
2025DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
2026DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
2027DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
2028DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
2029DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
2030
2031static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay)
2032{
2033 if (dev->d3hot_delay >= delay)
2034 return;
2035
2036 dev->d3hot_delay = delay;
2037 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n",
2038 dev->d3hot_delay);
2039}
2040
2041static void quirk_radeon_pm(struct pci_dev *dev)
2042{
2043 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
2044 dev->subsystem_device == 0x00e2)
2045 quirk_d3hot_delay(dev, 20);
2046}
2047DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
2048
2049/*
2050 * NVIDIA Ampere-based HDA controllers can wedge the whole device if a bus
2051 * reset is performed too soon after transition to D0, extend d3hot_delay
2052 * to previous effective default for all NVIDIA HDA controllers.
2053 */
2054static void quirk_nvidia_hda_pm(struct pci_dev *dev)
2055{
2056 quirk_d3hot_delay(dev, 20);
2057}
2058DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
2059 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8,
2060 quirk_nvidia_hda_pm);
2061
2062/*
2063 * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle.
2064 * https://bugzilla.kernel.org/show_bug.cgi?id=205587
2065 *
2066 * The kernel attempts to transition these devices to D3cold, but that seems
2067 * to be ineffective on the platforms in question; the PCI device appears to
2068 * remain on in D3hot state. The D3hot-to-D0 transition then requires an
2069 * extended delay in order to succeed.
2070 */
2071static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev)
2072{
2073 quirk_d3hot_delay(dev, 20);
2074}
2075DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot);
2076DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot);
2077DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot);
2078
2079#ifdef CONFIG_X86_IO_APIC
2080static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
2081{
2082 noioapicreroute = 1;
2083 pr_info("%s detected: disable boot interrupt reroute\n", d->ident);
2084
2085 return 0;
2086}
2087
2088static const struct dmi_system_id boot_interrupt_dmi_table[] = {
2089 /*
2090 * Systems to exclude from boot interrupt reroute quirks
2091 */
2092 {
2093 .callback = dmi_disable_ioapicreroute,
2094 .ident = "ASUSTek Computer INC. M2N-LR",
2095 .matches = {
2096 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."),
2097 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
2098 },
2099 },
2100 {}
2101};
2102
2103/*
2104 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
2105 * remap the original interrupt in the Linux kernel to the boot interrupt, so
2106 * that a PCI device's interrupt handler is installed on the boot interrupt
2107 * line instead.
2108 */
2109static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
2110{
2111 dmi_check_system(boot_interrupt_dmi_table);
2112 if (noioapicquirk || noioapicreroute)
2113 return;
2114
2115 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
2116 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n",
2117 dev->vendor, dev->device);
2118}
2119DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
2120DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
2121DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
2122DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
2123DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
2124DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
2125DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
2126DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
2127DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
2128DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
2129DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
2130DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
2131DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
2132DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
2133DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
2134DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
2135
2136/*
2137 * On some chipsets we can disable the generation of legacy INTx boot
2138 * interrupts.
2139 */
2140
2141/*
2142 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
2143 * 300641-004US, section 5.7.3.
2144 *
2145 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003.
2146 * Core IO on Xeon E5 v2, see Intel order no 329188-003.
2147 * Core IO on Xeon E7 v2, see Intel order no 329595-002.
2148 * Core IO on Xeon E5 v3, see Intel order no 330784-003.
2149 * Core IO on Xeon E7 v3, see Intel order no 332315-001US.
2150 * Core IO on Xeon E5 v4, see Intel order no 333810-002US.
2151 * Core IO on Xeon E7 v4, see Intel order no 332315-001US.
2152 * Core IO on Xeon D-1500, see Intel order no 332051-001.
2153 * Core IO on Xeon Scalable, see Intel order no 610950.
2154 */
2155#define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */
2156#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
2157
2158#define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */
2159#define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25)
2160
2161static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
2162{
2163 u16 pci_config_word;
2164 u32 pci_config_dword;
2165
2166 if (noioapicquirk)
2167 return;
2168
2169 switch (dev->device) {
2170 case PCI_DEVICE_ID_INTEL_ESB_10:
2171 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR,
2172 &pci_config_word);
2173 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
2174 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR,
2175 pci_config_word);
2176 break;
2177 case 0x3c28: /* Xeon E5 1600/2600/4600 */
2178 case 0x0e28: /* Xeon E5/E7 V2 */
2179 case 0x2f28: /* Xeon E5/E7 V3,V4 */
2180 case 0x6f28: /* Xeon D-1500 */
2181 case 0x2034: /* Xeon Scalable Family */
2182 pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
2183 &pci_config_dword);
2184 pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH;
2185 pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
2186 pci_config_dword);
2187 break;
2188 default:
2189 return;
2190 }
2191 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2192 dev->vendor, dev->device);
2193}
2194/*
2195 * Device 29 Func 5 Device IDs of IO-APIC
2196 * containing ABAR—APIC1 Alternate Base Address Register
2197 */
2198DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10,
2199 quirk_disable_intel_boot_interrupt);
2200DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10,
2201 quirk_disable_intel_boot_interrupt);
2202
2203/*
2204 * Device 5 Func 0 Device IDs of Core IO modules/hubs
2205 * containing Coherent Interface Protocol Interrupt Control
2206 *
2207 * Device IDs obtained from volume 2 datasheets of commented
2208 * families above.
2209 */
2210DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28,
2211 quirk_disable_intel_boot_interrupt);
2212DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28,
2213 quirk_disable_intel_boot_interrupt);
2214DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28,
2215 quirk_disable_intel_boot_interrupt);
2216DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28,
2217 quirk_disable_intel_boot_interrupt);
2218DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034,
2219 quirk_disable_intel_boot_interrupt);
2220DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28,
2221 quirk_disable_intel_boot_interrupt);
2222DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28,
2223 quirk_disable_intel_boot_interrupt);
2224DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28,
2225 quirk_disable_intel_boot_interrupt);
2226DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28,
2227 quirk_disable_intel_boot_interrupt);
2228DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034,
2229 quirk_disable_intel_boot_interrupt);
2230
2231/* Disable boot interrupts on HT-1000 */
2232#define BC_HT1000_FEATURE_REG 0x64
2233#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
2234#define BC_HT1000_MAP_IDX 0xC00
2235#define BC_HT1000_MAP_DATA 0xC01
2236
2237static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
2238{
2239 u32 pci_config_dword;
2240 u8 irq;
2241
2242 if (noioapicquirk)
2243 return;
2244
2245 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
2246 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
2247 BC_HT1000_PIC_REGS_ENABLE);
2248
2249 for (irq = 0x10; irq < 0x10 + 32; irq++) {
2250 outb(irq, BC_HT1000_MAP_IDX);
2251 outb(0x00, BC_HT1000_MAP_DATA);
2252 }
2253
2254 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
2255
2256 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2257 dev->vendor, dev->device);
2258}
2259DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
2260DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
2261
2262/* Disable boot interrupts on AMD and ATI chipsets */
2263
2264/*
2265 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
2266 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
2267 * (due to an erratum).
2268 */
2269#define AMD_813X_MISC 0x40
2270#define AMD_813X_NOIOAMODE (1<<0)
2271#define AMD_813X_REV_B1 0x12
2272#define AMD_813X_REV_B2 0x13
2273
2274static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
2275{
2276 u32 pci_config_dword;
2277
2278 if (noioapicquirk)
2279 return;
2280 if ((dev->revision == AMD_813X_REV_B1) ||
2281 (dev->revision == AMD_813X_REV_B2))
2282 return;
2283
2284 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
2285 pci_config_dword &= ~AMD_813X_NOIOAMODE;
2286 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
2287
2288 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2289 dev->vendor, dev->device);
2290}
2291DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2292DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2293DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2294DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2295
2296#define AMD_8111_PCI_IRQ_ROUTING 0x56
2297
2298static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
2299{
2300 u16 pci_config_word;
2301
2302 if (noioapicquirk)
2303 return;
2304
2305 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
2306 if (!pci_config_word) {
2307 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n",
2308 dev->vendor, dev->device);
2309 return;
2310 }
2311 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
2312 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2313 dev->vendor, dev->device);
2314}
2315DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
2316DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
2317#endif /* CONFIG_X86_IO_APIC */
2318
2319/*
2320 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2321 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
2322 * Re-allocate the region if needed...
2323 */
2324static void quirk_tc86c001_ide(struct pci_dev *dev)
2325{
2326 struct resource *r = &dev->resource[0];
2327
2328 if (r->start & 0x8) {
2329 r->flags |= IORESOURCE_UNSET;
2330 r->start = 0;
2331 r->end = 0xf;
2332 }
2333}
2334DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
2335 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
2336 quirk_tc86c001_ide);
2337
2338/*
2339 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
2340 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
2341 * being read correctly if bit 7 of the base address is set.
2342 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
2343 * Re-allocate the regions to a 256-byte boundary if necessary.
2344 */
2345static void quirk_plx_pci9050(struct pci_dev *dev)
2346{
2347 unsigned int bar;
2348
2349 /* Fixed in revision 2 (PCI 9052). */
2350 if (dev->revision >= 2)
2351 return;
2352 for (bar = 0; bar <= 1; bar++)
2353 if (pci_resource_len(dev, bar) == 0x80 &&
2354 (pci_resource_start(dev, bar) & 0x80)) {
2355 struct resource *r = &dev->resource[bar];
2356 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
2357 bar);
2358 r->flags |= IORESOURCE_UNSET;
2359 r->start = 0;
2360 r->end = 0xff;
2361 }
2362}
2363DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2364 quirk_plx_pci9050);
2365/*
2366 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
2367 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
2368 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
2369 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
2370 *
2371 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
2372 * driver.
2373 */
2374DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
2375DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
2376
2377static void quirk_netmos(struct pci_dev *dev)
2378{
2379 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
2380 unsigned int num_serial = dev->subsystem_device & 0xf;
2381
2382 /*
2383 * These Netmos parts are multiport serial devices with optional
2384 * parallel ports. Even when parallel ports are present, they
2385 * are identified as class SERIAL, which means the serial driver
2386 * will claim them. To prevent this, mark them as class OTHER.
2387 * These combo devices should be claimed by parport_serial.
2388 *
2389 * The subdevice ID is of the form 0x00PS, where <P> is the number
2390 * of parallel ports and <S> is the number of serial ports.
2391 */
2392 switch (dev->device) {
2393 case PCI_DEVICE_ID_NETMOS_9835:
2394 /* Well, this rule doesn't hold for the following 9835 device */
2395 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
2396 dev->subsystem_device == 0x0299)
2397 return;
2398 fallthrough;
2399 case PCI_DEVICE_ID_NETMOS_9735:
2400 case PCI_DEVICE_ID_NETMOS_9745:
2401 case PCI_DEVICE_ID_NETMOS_9845:
2402 case PCI_DEVICE_ID_NETMOS_9855:
2403 if (num_parallel) {
2404 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
2405 dev->device, num_parallel, num_serial);
2406 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
2407 (dev->class & 0xff);
2408 }
2409 }
2410}
2411DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
2412 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
2413
2414static void quirk_e100_interrupt(struct pci_dev *dev)
2415{
2416 u16 command, pmcsr;
2417 u8 __iomem *csr;
2418 u8 cmd_hi;
2419
2420 switch (dev->device) {
2421 /* PCI IDs taken from drivers/net/e100.c */
2422 case 0x1029:
2423 case 0x1030 ... 0x1034:
2424 case 0x1038 ... 0x103E:
2425 case 0x1050 ... 0x1057:
2426 case 0x1059:
2427 case 0x1064 ... 0x106B:
2428 case 0x1091 ... 0x1095:
2429 case 0x1209:
2430 case 0x1229:
2431 case 0x2449:
2432 case 0x2459:
2433 case 0x245D:
2434 case 0x27DC:
2435 break;
2436 default:
2437 return;
2438 }
2439
2440 /*
2441 * Some firmware hands off the e100 with interrupts enabled,
2442 * which can cause a flood of interrupts if packets are
2443 * received before the driver attaches to the device. So
2444 * disable all e100 interrupts here. The driver will
2445 * re-enable them when it's ready.
2446 */
2447 pci_read_config_word(dev, PCI_COMMAND, &command);
2448
2449 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
2450 return;
2451
2452 /*
2453 * Check that the device is in the D0 power state. If it's not,
2454 * there is no point to look any further.
2455 */
2456 if (dev->pm_cap) {
2457 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2458 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
2459 return;
2460 }
2461
2462 /* Convert from PCI bus to resource space. */
2463 csr = ioremap(pci_resource_start(dev, 0), 8);
2464 if (!csr) {
2465 pci_warn(dev, "Can't map e100 registers\n");
2466 return;
2467 }
2468
2469 cmd_hi = readb(csr + 3);
2470 if (cmd_hi == 0) {
2471 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n");
2472 writeb(1, csr + 3);
2473 }
2474
2475 iounmap(csr);
2476}
2477DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2478 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
2479
2480/*
2481 * The 82575 and 82598 may experience data corruption issues when transitioning
2482 * out of L0S. To prevent this we need to disable L0S on the PCIe link.
2483 */
2484static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2485{
2486 pci_info(dev, "Disabling L0s\n");
2487 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2488}
2489DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2490DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2491DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2492DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2493DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2494DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2495DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2496DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2497DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2498DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2499DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2500DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2501DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2502DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2503
2504static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev)
2505{
2506 pci_info(dev, "Disabling ASPM L0s/L1\n");
2507 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
2508}
2509
2510/*
2511 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the
2512 * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected;
2513 * disable both L0s and L1 for now to be safe.
2514 */
2515DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1);
2516
2517/*
2518 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2519 * Link bit cleared after starting the link retrain process to allow this
2520 * process to finish.
2521 *
2522 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the
2523 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf.
2524 */
2525static void quirk_enable_clear_retrain_link(struct pci_dev *dev)
2526{
2527 dev->clear_retrain_link = 1;
2528 pci_info(dev, "Enable PCIe Retrain Link quirk\n");
2529}
2530DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe110, quirk_enable_clear_retrain_link);
2531DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe111, quirk_enable_clear_retrain_link);
2532DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe130, quirk_enable_clear_retrain_link);
2533
2534static void fixup_rev1_53c810(struct pci_dev *dev)
2535{
2536 u32 class = dev->class;
2537
2538 /*
2539 * rev 1 ncr53c810 chips don't set the class at all which means
2540 * they don't get their resources remapped. Fix that here.
2541 */
2542 if (class)
2543 return;
2544
2545 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2546 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2547 class, dev->class);
2548}
2549DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2550
2551/* Enable 1k I/O space granularity on the Intel P64H2 */
2552static void quirk_p64h2_1k_io(struct pci_dev *dev)
2553{
2554 u16 en1k;
2555
2556 pci_read_config_word(dev, 0x40, &en1k);
2557
2558 if (en1k & 0x200) {
2559 pci_info(dev, "Enable I/O Space to 1KB granularity\n");
2560 dev->io_window_1k = 1;
2561 }
2562}
2563DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2564
2565/*
2566 * Under some circumstances, AER is not linked with extended capabilities.
2567 * Force it to be linked by setting the corresponding control bit in the
2568 * config space.
2569 */
2570static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2571{
2572 uint8_t b;
2573
2574 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2575 if (!(b & 0x20)) {
2576 pci_write_config_byte(dev, 0xf41, b | 0x20);
2577 pci_info(dev, "Linking AER extended capability\n");
2578 }
2579 }
2580}
2581DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2582 quirk_nvidia_ck804_pcie_aer_ext_cap);
2583DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2584 quirk_nvidia_ck804_pcie_aer_ext_cap);
2585
2586static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2587{
2588 /*
2589 * Disable PCI Bus Parking and PCI Master read caching on CX700
2590 * which causes unspecified timing errors with a VT6212L on the PCI
2591 * bus leading to USB2.0 packet loss.
2592 *
2593 * This quirk is only enabled if a second (on the external PCI bus)
2594 * VT6212L is found -- the CX700 core itself also contains a USB
2595 * host controller with the same PCI ID as the VT6212L.
2596 */
2597
2598 /* Count VT6212L instances */
2599 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2600 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2601 uint8_t b;
2602
2603 /*
2604 * p should contain the first (internal) VT6212L -- see if we have
2605 * an external one by searching again.
2606 */
2607 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2608 if (!p)
2609 return;
2610 pci_dev_put(p);
2611
2612 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2613 if (b & 0x40) {
2614 /* Turn off PCI Bus Parking */
2615 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2616
2617 pci_info(dev, "Disabling VIA CX700 PCI parking\n");
2618 }
2619 }
2620
2621 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2622 if (b != 0) {
2623 /* Turn off PCI Master read caching */
2624 pci_write_config_byte(dev, 0x72, 0x0);
2625
2626 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2627 pci_write_config_byte(dev, 0x75, 0x1);
2628
2629 /* Disable "Read FIFO Timer" */
2630 pci_write_config_byte(dev, 0x77, 0x0);
2631
2632 pci_info(dev, "Disabling VIA CX700 PCI caching\n");
2633 }
2634 }
2635}
2636DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2637
2638static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2639{
2640 u32 rev;
2641
2642 pci_read_config_dword(dev, 0xf4, &rev);
2643
2644 /* Only CAP the MRRS if the device is a 5719 A0 */
2645 if (rev == 0x05719000) {
2646 int readrq = pcie_get_readrq(dev);
2647 if (readrq > 2048)
2648 pcie_set_readrq(dev, 2048);
2649 }
2650}
2651DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2652 PCI_DEVICE_ID_TIGON3_5719,
2653 quirk_brcm_5719_limit_mrrs);
2654
2655/*
2656 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to
2657 * hide device 6 which configures the overflow device access containing the
2658 * DRBs - this is where we expose device 6.
2659 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2660 */
2661static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2662{
2663 u8 reg;
2664
2665 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) {
2666 pci_info(dev, "Enabling MCH 'Overflow' Device\n");
2667 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2668 }
2669}
2670DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2671 quirk_unhide_mch_dev6);
2672DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2673 quirk_unhide_mch_dev6);
2674
2675#ifdef CONFIG_PCI_MSI
2676/*
2677 * Some chipsets do not support MSI. We cannot easily rely on setting
2678 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some
2679 * other buses controlled by the chipset even if Linux is not aware of it.
2680 * Instead of setting the flag on all buses in the machine, simply disable
2681 * MSI globally.
2682 */
2683static void quirk_disable_all_msi(struct pci_dev *dev)
2684{
2685 pci_no_msi();
2686 pci_warn(dev, "MSI quirk detected; MSI disabled\n");
2687}
2688DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2689DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2690DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2691DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2692DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2693DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2694DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2695DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2696DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa5e3, quirk_disable_all_msi);
2697
2698/* Disable MSI on chipsets that are known to not support it */
2699static void quirk_disable_msi(struct pci_dev *dev)
2700{
2701 if (dev->subordinate) {
2702 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2703 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2704 }
2705}
2706DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2707DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2708DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2709
2710/*
2711 * The APC bridge device in AMD 780 family northbridges has some random
2712 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2713 * we use the possible vendor/device IDs of the host bridge for the
2714 * declared quirk, and search for the APC bridge by slot number.
2715 */
2716static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2717{
2718 struct pci_dev *apc_bridge;
2719
2720 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2721 if (apc_bridge) {
2722 if (apc_bridge->device == 0x9602)
2723 quirk_disable_msi(apc_bridge);
2724 pci_dev_put(apc_bridge);
2725 }
2726}
2727DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2728DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2729
2730/*
2731 * Go through the list of HyperTransport capabilities and return 1 if a HT
2732 * MSI capability is found and enabled.
2733 */
2734static int msi_ht_cap_enabled(struct pci_dev *dev)
2735{
2736 int pos, ttl = PCI_FIND_CAP_TTL;
2737
2738 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2739 while (pos && ttl--) {
2740 u8 flags;
2741
2742 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2743 &flags) == 0) {
2744 pci_info(dev, "Found %s HT MSI Mapping\n",
2745 flags & HT_MSI_FLAGS_ENABLE ?
2746 "enabled" : "disabled");
2747 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2748 }
2749
2750 pos = pci_find_next_ht_capability(dev, pos,
2751 HT_CAPTYPE_MSI_MAPPING);
2752 }
2753 return 0;
2754}
2755
2756/* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */
2757static void quirk_msi_ht_cap(struct pci_dev *dev)
2758{
2759 if (!msi_ht_cap_enabled(dev))
2760 quirk_disable_msi(dev);
2761}
2762DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2763 quirk_msi_ht_cap);
2764
2765/*
2766 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported
2767 * if the MSI capability is set in any of these mappings.
2768 */
2769static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2770{
2771 struct pci_dev *pdev;
2772
2773 /*
2774 * Check HT MSI cap on this chipset and the root one. A single one
2775 * having MSI is enough to be sure that MSI is supported.
2776 */
2777 pdev = pci_get_slot(dev->bus, 0);
2778 if (!pdev)
2779 return;
2780 if (!msi_ht_cap_enabled(pdev))
2781 quirk_msi_ht_cap(dev);
2782 pci_dev_put(pdev);
2783}
2784DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2785 quirk_nvidia_ck804_msi_ht_cap);
2786
2787/* Force enable MSI mapping capability on HT bridges */
2788static void ht_enable_msi_mapping(struct pci_dev *dev)
2789{
2790 int pos, ttl = PCI_FIND_CAP_TTL;
2791
2792 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2793 while (pos && ttl--) {
2794 u8 flags;
2795
2796 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2797 &flags) == 0) {
2798 pci_info(dev, "Enabling HT MSI Mapping\n");
2799
2800 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2801 flags | HT_MSI_FLAGS_ENABLE);
2802 }
2803 pos = pci_find_next_ht_capability(dev, pos,
2804 HT_CAPTYPE_MSI_MAPPING);
2805 }
2806}
2807DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2808 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2809 ht_enable_msi_mapping);
2810DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2811 ht_enable_msi_mapping);
2812
2813/*
2814 * The P5N32-SLI motherboards from Asus have a problem with MSI
2815 * for the MCP55 NIC. It is not yet determined whether the MSI problem
2816 * also affects other devices. As for now, turn off MSI for this device.
2817 */
2818static void nvenet_msi_disable(struct pci_dev *dev)
2819{
2820 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2821
2822 if (board_name &&
2823 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2824 strstr(board_name, "P5N32-E SLI"))) {
2825 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
2826 dev->no_msi = 1;
2827 }
2828}
2829DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2830 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2831 nvenet_msi_disable);
2832
2833/*
2834 * PCIe spec r6.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled, the device
2835 * can't use INTx interrupts. Tegra's PCIe Root Ports don't generate MSI
2836 * interrupts for PME and AER events; instead only INTx interrupts are
2837 * generated. Though Tegra's PCIe Root Ports can generate MSI interrupts
2838 * for other events, since PCIe specification doesn't support using a mix of
2839 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
2840 * service drivers registering their respective ISRs for MSIs.
2841 */
2842static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev)
2843{
2844 dev->no_msi = 1;
2845}
2846DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0,
2847 PCI_CLASS_BRIDGE_PCI, 8,
2848 pci_quirk_nvidia_tegra_disable_rp_msi);
2849DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1,
2850 PCI_CLASS_BRIDGE_PCI, 8,
2851 pci_quirk_nvidia_tegra_disable_rp_msi);
2852DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2,
2853 PCI_CLASS_BRIDGE_PCI, 8,
2854 pci_quirk_nvidia_tegra_disable_rp_msi);
2855DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0,
2856 PCI_CLASS_BRIDGE_PCI, 8,
2857 pci_quirk_nvidia_tegra_disable_rp_msi);
2858DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1,
2859 PCI_CLASS_BRIDGE_PCI, 8,
2860 pci_quirk_nvidia_tegra_disable_rp_msi);
2861DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c,
2862 PCI_CLASS_BRIDGE_PCI, 8,
2863 pci_quirk_nvidia_tegra_disable_rp_msi);
2864DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d,
2865 PCI_CLASS_BRIDGE_PCI, 8,
2866 pci_quirk_nvidia_tegra_disable_rp_msi);
2867DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12,
2868 PCI_CLASS_BRIDGE_PCI, 8,
2869 pci_quirk_nvidia_tegra_disable_rp_msi);
2870DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13,
2871 PCI_CLASS_BRIDGE_PCI, 8,
2872 pci_quirk_nvidia_tegra_disable_rp_msi);
2873DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae,
2874 PCI_CLASS_BRIDGE_PCI, 8,
2875 pci_quirk_nvidia_tegra_disable_rp_msi);
2876DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf,
2877 PCI_CLASS_BRIDGE_PCI, 8,
2878 pci_quirk_nvidia_tegra_disable_rp_msi);
2879DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,
2880 PCI_CLASS_BRIDGE_PCI, 8,
2881 pci_quirk_nvidia_tegra_disable_rp_msi);
2882DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,
2883 PCI_CLASS_BRIDGE_PCI, 8,
2884 pci_quirk_nvidia_tegra_disable_rp_msi);
2885DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229a,
2886 PCI_CLASS_BRIDGE_PCI, 8,
2887 pci_quirk_nvidia_tegra_disable_rp_msi);
2888DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229c,
2889 PCI_CLASS_BRIDGE_PCI, 8,
2890 pci_quirk_nvidia_tegra_disable_rp_msi);
2891DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229e,
2892 PCI_CLASS_BRIDGE_PCI, 8,
2893 pci_quirk_nvidia_tegra_disable_rp_msi);
2894
2895/*
2896 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2897 * config register. This register controls the routing of legacy
2898 * interrupts from devices that route through the MCP55. If this register
2899 * is misprogrammed, interrupts are only sent to the BSP, unlike
2900 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2901 * having this register set properly prevents kdump from booting up
2902 * properly, so let's make sure that we have it set correctly.
2903 * Note that this is an undocumented register.
2904 */
2905static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2906{
2907 u32 cfg;
2908
2909 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2910 return;
2911
2912 pci_read_config_dword(dev, 0x74, &cfg);
2913
2914 if (cfg & ((1 << 2) | (1 << 15))) {
2915 pr_info("Rewriting IRQ routing register on MCP55\n");
2916 cfg &= ~((1 << 2) | (1 << 15));
2917 pci_write_config_dword(dev, 0x74, cfg);
2918 }
2919}
2920DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2921 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2922 nvbridge_check_legacy_irq_routing);
2923DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2924 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2925 nvbridge_check_legacy_irq_routing);
2926
2927static int ht_check_msi_mapping(struct pci_dev *dev)
2928{
2929 int pos, ttl = PCI_FIND_CAP_TTL;
2930 int found = 0;
2931
2932 /* Check if there is HT MSI cap or enabled on this device */
2933 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2934 while (pos && ttl--) {
2935 u8 flags;
2936
2937 if (found < 1)
2938 found = 1;
2939 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2940 &flags) == 0) {
2941 if (flags & HT_MSI_FLAGS_ENABLE) {
2942 if (found < 2) {
2943 found = 2;
2944 break;
2945 }
2946 }
2947 }
2948 pos = pci_find_next_ht_capability(dev, pos,
2949 HT_CAPTYPE_MSI_MAPPING);
2950 }
2951
2952 return found;
2953}
2954
2955static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2956{
2957 struct pci_dev *dev;
2958 int pos;
2959 int i, dev_no;
2960 int found = 0;
2961
2962 dev_no = host_bridge->devfn >> 3;
2963 for (i = dev_no + 1; i < 0x20; i++) {
2964 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2965 if (!dev)
2966 continue;
2967
2968 /* found next host bridge? */
2969 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2970 if (pos != 0) {
2971 pci_dev_put(dev);
2972 break;
2973 }
2974
2975 if (ht_check_msi_mapping(dev)) {
2976 found = 1;
2977 pci_dev_put(dev);
2978 break;
2979 }
2980 pci_dev_put(dev);
2981 }
2982
2983 return found;
2984}
2985
2986#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2987#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2988
2989static int is_end_of_ht_chain(struct pci_dev *dev)
2990{
2991 int pos, ctrl_off;
2992 int end = 0;
2993 u16 flags, ctrl;
2994
2995 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2996
2997 if (!pos)
2998 goto out;
2999
3000 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
3001
3002 ctrl_off = ((flags >> 10) & 1) ?
3003 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
3004 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
3005
3006 if (ctrl & (1 << 6))
3007 end = 1;
3008
3009out:
3010 return end;
3011}
3012
3013static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
3014{
3015 struct pci_dev *host_bridge;
3016 int pos;
3017 int i, dev_no;
3018 int found = 0;
3019
3020 dev_no = dev->devfn >> 3;
3021 for (i = dev_no; i >= 0; i--) {
3022 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
3023 if (!host_bridge)
3024 continue;
3025
3026 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
3027 if (pos != 0) {
3028 found = 1;
3029 break;
3030 }
3031 pci_dev_put(host_bridge);
3032 }
3033
3034 if (!found)
3035 return;
3036
3037 /* don't enable end_device/host_bridge with leaf directly here */
3038 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
3039 host_bridge_with_leaf(host_bridge))
3040 goto out;
3041
3042 /* root did that ! */
3043 if (msi_ht_cap_enabled(host_bridge))
3044 goto out;
3045
3046 ht_enable_msi_mapping(dev);
3047
3048out:
3049 pci_dev_put(host_bridge);
3050}
3051
3052static void ht_disable_msi_mapping(struct pci_dev *dev)
3053{
3054 int pos, ttl = PCI_FIND_CAP_TTL;
3055
3056 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
3057 while (pos && ttl--) {
3058 u8 flags;
3059
3060 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
3061 &flags) == 0) {
3062 pci_info(dev, "Disabling HT MSI Mapping\n");
3063
3064 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
3065 flags & ~HT_MSI_FLAGS_ENABLE);
3066 }
3067 pos = pci_find_next_ht_capability(dev, pos,
3068 HT_CAPTYPE_MSI_MAPPING);
3069 }
3070}
3071
3072static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
3073{
3074 struct pci_dev *host_bridge;
3075 int pos;
3076 int found;
3077
3078 if (!pci_msi_enabled())
3079 return;
3080
3081 /* check if there is HT MSI cap or enabled on this device */
3082 found = ht_check_msi_mapping(dev);
3083
3084 /* no HT MSI CAP */
3085 if (found == 0)
3086 return;
3087
3088 /*
3089 * HT MSI mapping should be disabled on devices that are below
3090 * a non-HyperTransport host bridge. Locate the host bridge.
3091 */
3092 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
3093 PCI_DEVFN(0, 0));
3094 if (host_bridge == NULL) {
3095 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
3096 return;
3097 }
3098
3099 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
3100 if (pos != 0) {
3101 /* Host bridge is to HT */
3102 if (found == 1) {
3103 /* it is not enabled, try to enable it */
3104 if (all)
3105 ht_enable_msi_mapping(dev);
3106 else
3107 nv_ht_enable_msi_mapping(dev);
3108 }
3109 goto out;
3110 }
3111
3112 /* HT MSI is not enabled */
3113 if (found == 1)
3114 goto out;
3115
3116 /* Host bridge is not to HT, disable HT MSI mapping on this device */
3117 ht_disable_msi_mapping(dev);
3118
3119out:
3120 pci_dev_put(host_bridge);
3121}
3122
3123static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
3124{
3125 return __nv_msi_ht_cap_quirk(dev, 1);
3126}
3127DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
3128DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
3129
3130static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
3131{
3132 return __nv_msi_ht_cap_quirk(dev, 0);
3133}
3134DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
3135DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
3136
3137static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
3138{
3139 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
3140}
3141
3142static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
3143{
3144 struct pci_dev *p;
3145
3146 /*
3147 * SB700 MSI issue will be fixed at HW level from revision A21;
3148 * we need check PCI REVISION ID of SMBus controller to get SB700
3149 * revision.
3150 */
3151 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3152 NULL);
3153 if (!p)
3154 return;
3155
3156 if ((p->revision < 0x3B) && (p->revision >= 0x30))
3157 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
3158 pci_dev_put(p);
3159}
3160
3161static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
3162{
3163 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
3164 if (dev->revision < 0x18) {
3165 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n");
3166 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
3167 }
3168}
3169DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3170 PCI_DEVICE_ID_TIGON3_5780,
3171 quirk_msi_intx_disable_bug);
3172DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3173 PCI_DEVICE_ID_TIGON3_5780S,
3174 quirk_msi_intx_disable_bug);
3175DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3176 PCI_DEVICE_ID_TIGON3_5714,
3177 quirk_msi_intx_disable_bug);
3178DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3179 PCI_DEVICE_ID_TIGON3_5714S,
3180 quirk_msi_intx_disable_bug);
3181DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3182 PCI_DEVICE_ID_TIGON3_5715,
3183 quirk_msi_intx_disable_bug);
3184DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3185 PCI_DEVICE_ID_TIGON3_5715S,
3186 quirk_msi_intx_disable_bug);
3187
3188DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
3189 quirk_msi_intx_disable_ati_bug);
3190DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
3191 quirk_msi_intx_disable_ati_bug);
3192DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
3193 quirk_msi_intx_disable_ati_bug);
3194DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
3195 quirk_msi_intx_disable_ati_bug);
3196DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
3197 quirk_msi_intx_disable_ati_bug);
3198
3199DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
3200 quirk_msi_intx_disable_bug);
3201DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
3202 quirk_msi_intx_disable_bug);
3203DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
3204 quirk_msi_intx_disable_bug);
3205
3206DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
3207 quirk_msi_intx_disable_bug);
3208DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
3209 quirk_msi_intx_disable_bug);
3210DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
3211 quirk_msi_intx_disable_bug);
3212DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
3213 quirk_msi_intx_disable_bug);
3214DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
3215 quirk_msi_intx_disable_bug);
3216DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
3217 quirk_msi_intx_disable_bug);
3218DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
3219 quirk_msi_intx_disable_qca_bug);
3220DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
3221 quirk_msi_intx_disable_qca_bug);
3222DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
3223 quirk_msi_intx_disable_qca_bug);
3224DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
3225 quirk_msi_intx_disable_qca_bug);
3226DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
3227 quirk_msi_intx_disable_qca_bug);
3228
3229/*
3230 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
3231 * should be disabled on platforms where the device (mistakenly) advertises it.
3232 *
3233 * Notice that this quirk also disables MSI (which may work, but hasn't been
3234 * tested), since currently there is no standard way to disable only MSI-X.
3235 *
3236 * The 0031 device id is reused for other non Root Port device types,
3237 * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
3238 */
3239static void quirk_al_msi_disable(struct pci_dev *dev)
3240{
3241 dev->no_msi = 1;
3242 pci_warn(dev, "Disabling MSI/MSI-X\n");
3243}
3244DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
3245 PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable);
3246#endif /* CONFIG_PCI_MSI */
3247
3248/*
3249 * Allow manual resource allocation for PCI hotplug bridges via
3250 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
3251 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to
3252 * allocate resources when hotplug device is inserted and PCI bus is
3253 * rescanned.
3254 */
3255static void quirk_hotplug_bridge(struct pci_dev *dev)
3256{
3257 dev->is_hotplug_bridge = 1;
3258}
3259DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
3260
3261/*
3262 * This is a quirk for the Ricoh MMC controller found as a part of some
3263 * multifunction chips.
3264 *
3265 * This is very similar and based on the ricoh_mmc driver written by
3266 * Philip Langdale. Thank you for these magic sequences.
3267 *
3268 * These chips implement the four main memory card controllers (SD, MMC,
3269 * MS, xD) and one or both of CardBus or FireWire.
3270 *
3271 * It happens that they implement SD and MMC support as separate
3272 * controllers (and PCI functions). The Linux SDHCI driver supports MMC
3273 * cards but the chip detects MMC cards in hardware and directs them to the
3274 * MMC controller - so the SDHCI driver never sees them.
3275 *
3276 * To get around this, we must disable the useless MMC controller. At that
3277 * point, the SDHCI controller will start seeing them. It seems to be the
3278 * case that the relevant PCI registers to deactivate the MMC controller
3279 * live on PCI function 0, which might be the CardBus controller or the
3280 * FireWire controller, depending on the particular chip in question
3281 *
3282 * This has to be done early, because as soon as we disable the MMC controller
3283 * other PCI functions shift up one level, e.g. function #2 becomes function
3284 * #1, and this will confuse the PCI core.
3285 */
3286#ifdef CONFIG_MMC_RICOH_MMC
3287static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
3288{
3289 u8 write_enable;
3290 u8 write_target;
3291 u8 disable;
3292
3293 /*
3294 * Disable via CardBus interface
3295 *
3296 * This must be done via function #0
3297 */
3298 if (PCI_FUNC(dev->devfn))
3299 return;
3300
3301 pci_read_config_byte(dev, 0xB7, &disable);
3302 if (disable & 0x02)
3303 return;
3304
3305 pci_read_config_byte(dev, 0x8E, &write_enable);
3306 pci_write_config_byte(dev, 0x8E, 0xAA);
3307 pci_read_config_byte(dev, 0x8D, &write_target);
3308 pci_write_config_byte(dev, 0x8D, 0xB7);
3309 pci_write_config_byte(dev, 0xB7, disable | 0x02);
3310 pci_write_config_byte(dev, 0x8E, write_enable);
3311 pci_write_config_byte(dev, 0x8D, write_target);
3312
3313 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n");
3314 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3315}
3316DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3317DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3318
3319static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
3320{
3321 u8 write_enable;
3322 u8 disable;
3323
3324 /*
3325 * Disable via FireWire interface
3326 *
3327 * This must be done via function #0
3328 */
3329 if (PCI_FUNC(dev->devfn))
3330 return;
3331 /*
3332 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
3333 * certain types of SD/MMC cards. Lowering the SD base clock
3334 * frequency from 200Mhz to 50Mhz fixes this issue.
3335 *
3336 * 0x150 - SD2.0 mode enable for changing base clock
3337 * frequency to 50Mhz
3338 * 0xe1 - Base clock frequency
3339 * 0x32 - 50Mhz new clock frequency
3340 * 0xf9 - Key register for 0x150
3341 * 0xfc - key register for 0xe1
3342 */
3343 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
3344 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
3345 pci_write_config_byte(dev, 0xf9, 0xfc);
3346 pci_write_config_byte(dev, 0x150, 0x10);
3347 pci_write_config_byte(dev, 0xf9, 0x00);
3348 pci_write_config_byte(dev, 0xfc, 0x01);
3349 pci_write_config_byte(dev, 0xe1, 0x32);
3350 pci_write_config_byte(dev, 0xfc, 0x00);
3351
3352 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n");
3353 }
3354
3355 pci_read_config_byte(dev, 0xCB, &disable);
3356
3357 if (disable & 0x02)
3358 return;
3359
3360 pci_read_config_byte(dev, 0xCA, &write_enable);
3361 pci_write_config_byte(dev, 0xCA, 0x57);
3362 pci_write_config_byte(dev, 0xCB, disable | 0x02);
3363 pci_write_config_byte(dev, 0xCA, write_enable);
3364
3365 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n");
3366 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3367
3368}
3369DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3370DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3371DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3372DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3373DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3374DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3375#endif /*CONFIG_MMC_RICOH_MMC*/
3376
3377#ifdef CONFIG_DMAR_TABLE
3378#define VTUNCERRMSK_REG 0x1ac
3379#define VTD_MSK_SPEC_ERRORS (1 << 31)
3380/*
3381 * This is a quirk for masking VT-d spec-defined errors to platform error
3382 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets
3383 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
3384 * on the RAS config settings of the platform) when a VT-d fault happens.
3385 * The resulting SMI caused the system to hang.
3386 *
3387 * VT-d spec-related errors are already handled by the VT-d OS code, so no
3388 * need to report the same error through other channels.
3389 */
3390static void vtd_mask_spec_errors(struct pci_dev *dev)
3391{
3392 u32 word;
3393
3394 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
3395 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
3396}
3397DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
3398DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
3399#endif
3400
3401static void fixup_ti816x_class(struct pci_dev *dev)
3402{
3403 u32 class = dev->class;
3404
3405 /* TI 816x devices do not have class code set when in PCIe boot mode */
3406 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
3407 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
3408 class, dev->class);
3409}
3410DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
3411 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
3412
3413/*
3414 * Some PCIe devices do not work reliably with the claimed maximum
3415 * payload size supported.
3416 */
3417static void fixup_mpss_256(struct pci_dev *dev)
3418{
3419 dev->pcie_mpss = 1; /* 256 bytes */
3420}
3421DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3422 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
3423DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3424 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
3425DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3426 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
3427DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256);
3428
3429/*
3430 * Intel 5000 and 5100 Memory controllers have an erratum with read completion
3431 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
3432 * Since there is no way of knowing what the PCIe MPS on each fabric will be
3433 * until all of the devices are discovered and buses walked, read completion
3434 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3435 * it is possible to hotplug a device with MPS of 256B.
3436 */
3437static void quirk_intel_mc_errata(struct pci_dev *dev)
3438{
3439 int err;
3440 u16 rcc;
3441
3442 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
3443 pcie_bus_config == PCIE_BUS_DEFAULT)
3444 return;
3445
3446 /*
3447 * Intel erratum specifies bits to change but does not say what
3448 * they are. Keeping them magical until such time as the registers
3449 * and values can be explained.
3450 */
3451 err = pci_read_config_word(dev, 0x48, &rcc);
3452 if (err) {
3453 pci_err(dev, "Error attempting to read the read completion coalescing register\n");
3454 return;
3455 }
3456
3457 if (!(rcc & (1 << 10)))
3458 return;
3459
3460 rcc &= ~(1 << 10);
3461
3462 err = pci_write_config_word(dev, 0x48, rcc);
3463 if (err) {
3464 pci_err(dev, "Error attempting to write the read completion coalescing register\n");
3465 return;
3466 }
3467
3468 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n");
3469}
3470/* Intel 5000 series memory controllers and ports 2-7 */
3471DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3472DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3473DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3474DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3475DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3476DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3477DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3478DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3479DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3480DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3481DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3482DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3483DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3484DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3485/* Intel 5100 series memory controllers and ports 2-7 */
3486DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3487DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3488DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3489DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3490DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3491DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3492DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3493DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3494DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3495DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3496DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3497
3498/*
3499 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
3500 * To work around this, query the size it should be configured to by the
3501 * device and modify the resource end to correspond to this new size.
3502 */
3503static void quirk_intel_ntb(struct pci_dev *dev)
3504{
3505 int rc;
3506 u8 val;
3507
3508 rc = pci_read_config_byte(dev, 0x00D0, &val);
3509 if (rc)
3510 return;
3511
3512 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3513
3514 rc = pci_read_config_byte(dev, 0x00D1, &val);
3515 if (rc)
3516 return;
3517
3518 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3519}
3520DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3521DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3522
3523/*
3524 * Some BIOS implementations leave the Intel GPU interrupts enabled, even
3525 * though no one is handling them (e.g., if the i915 driver is never
3526 * loaded). Additionally the interrupt destination is not set up properly
3527 * and the interrupt ends up -somewhere-.
3528 *
3529 * These spurious interrupts are "sticky" and the kernel disables the
3530 * (shared) interrupt line after 100,000+ generated interrupts.
3531 *
3532 * Fix it by disabling the still enabled interrupts. This resolves crashes
3533 * often seen on monitor unplug.
3534 */
3535#define I915_DEIER_REG 0x4400c
3536static void disable_igfx_irq(struct pci_dev *dev)
3537{
3538 void __iomem *regs = pci_iomap(dev, 0, 0);
3539 if (regs == NULL) {
3540 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n");
3541 return;
3542 }
3543
3544 /* Check if any interrupt line is still enabled */
3545 if (readl(regs + I915_DEIER_REG) != 0) {
3546 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3547
3548 writel(0, regs + I915_DEIER_REG);
3549 }
3550
3551 pci_iounmap(dev, regs);
3552}
3553DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
3554DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
3555DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
3556DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3557DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
3558DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3559DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3560
3561/*
3562 * PCI devices which are on Intel chips can skip the 10ms delay
3563 * before entering D3 mode.
3564 */
3565static void quirk_remove_d3hot_delay(struct pci_dev *dev)
3566{
3567 dev->d3hot_delay = 0;
3568}
3569/* C600 Series devices do not need 10ms d3hot_delay */
3570DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay);
3571DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay);
3572DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay);
3573/* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */
3574DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay);
3575DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay);
3576DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay);
3577DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay);
3578DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay);
3579DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay);
3580DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay);
3581DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay);
3582DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay);
3583DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay);
3584DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay);
3585/* Intel Cherrytrail devices do not need 10ms d3hot_delay */
3586DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay);
3587DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay);
3588DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay);
3589DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay);
3590DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay);
3591DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay);
3592DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay);
3593DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay);
3594DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay);
3595
3596/*
3597 * Some devices may pass our check in pci_intx_mask_supported() if
3598 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3599 * support this feature.
3600 */
3601static void quirk_broken_intx_masking(struct pci_dev *dev)
3602{
3603 dev->broken_intx_masking = 1;
3604}
3605DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3606 quirk_broken_intx_masking);
3607DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3608 quirk_broken_intx_masking);
3609DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
3610 quirk_broken_intx_masking);
3611
3612/*
3613 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3614 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3615 *
3616 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3617 */
3618DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3619 quirk_broken_intx_masking);
3620
3621/*
3622 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3623 * DisINTx can be set but the interrupt status bit is non-functional.
3624 */
3625DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking);
3626DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking);
3627DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking);
3628DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking);
3629DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking);
3630DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking);
3631DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking);
3632DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking);
3633DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking);
3634DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking);
3635DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking);
3636DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking);
3637DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking);
3638DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking);
3639DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking);
3640DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking);
3641
3642static u16 mellanox_broken_intx_devs[] = {
3643 PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
3644 PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
3645 PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
3646 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
3647 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
3648 PCI_DEVICE_ID_MELLANOX_HERMON_EN,
3649 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
3650 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
3651 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
3652 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
3653 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
3654 PCI_DEVICE_ID_MELLANOX_CONNECTX2,
3655 PCI_DEVICE_ID_MELLANOX_CONNECTX3,
3656 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
3657};
3658
3659#define CONNECTX_4_CURR_MAX_MINOR 99
3660#define CONNECTX_4_INTX_SUPPORT_MINOR 14
3661
3662/*
3663 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3664 * If so, don't mark it as broken.
3665 * FW minor > 99 means older FW version format and no INTx masking support.
3666 * FW minor < 14 means new FW version format and no INTx masking support.
3667 */
3668static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3669{
3670 __be32 __iomem *fw_ver;
3671 u16 fw_major;
3672 u16 fw_minor;
3673 u16 fw_subminor;
3674 u32 fw_maj_min;
3675 u32 fw_sub_min;
3676 int i;
3677
3678 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
3679 if (pdev->device == mellanox_broken_intx_devs[i]) {
3680 pdev->broken_intx_masking = 1;
3681 return;
3682 }
3683 }
3684
3685 /*
3686 * Getting here means Connect-IB cards and up. Connect-IB has no INTx
3687 * support so shouldn't be checked further
3688 */
3689 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
3690 return;
3691
3692 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
3693 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
3694 return;
3695
3696 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3697 if (pci_enable_device_mem(pdev)) {
3698 pci_warn(pdev, "Can't enable device memory\n");
3699 return;
3700 }
3701
3702 fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
3703 if (!fw_ver) {
3704 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n");
3705 goto out;
3706 }
3707
3708 /* Reading from resource space should be 32b aligned */
3709 fw_maj_min = ioread32be(fw_ver);
3710 fw_sub_min = ioread32be(fw_ver + 1);
3711 fw_major = fw_maj_min & 0xffff;
3712 fw_minor = fw_maj_min >> 16;
3713 fw_subminor = fw_sub_min & 0xffff;
3714 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
3715 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
3716 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3717 fw_major, fw_minor, fw_subminor, pdev->device ==
3718 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
3719 pdev->broken_intx_masking = 1;
3720 }
3721
3722 iounmap(fw_ver);
3723
3724out:
3725 pci_disable_device(pdev);
3726}
3727DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3728 mellanox_check_broken_intx_masking);
3729
3730static void quirk_no_bus_reset(struct pci_dev *dev)
3731{
3732 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3733}
3734
3735/*
3736 * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be
3737 * prevented for those affected devices.
3738 */
3739static void quirk_nvidia_no_bus_reset(struct pci_dev *dev)
3740{
3741 if ((dev->device & 0xffc0) == 0x2340)
3742 quirk_no_bus_reset(dev);
3743}
3744DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
3745 quirk_nvidia_no_bus_reset);
3746
3747/*
3748 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3749 * The device will throw a Link Down error on AER-capable systems and
3750 * regardless of AER, config space of the device is never accessible again
3751 * and typically causes the system to hang or reset when access is attempted.
3752 * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/
3753 */
3754DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3755DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3756DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3757DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3758DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
3759DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset);
3760
3761/*
3762 * Root port on some Cavium CN8xxx chips do not successfully complete a bus
3763 * reset when used with certain child devices. After the reset, config
3764 * accesses to the child may fail.
3765 */
3766DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
3767
3768/*
3769 * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS
3770 * automatically disables LTSSM when Secondary Bus Reset is received and
3771 * the device stops working. Prevent bus reset for these devices. With
3772 * this change, the device can be assigned to VMs with VFIO, but it will
3773 * leak state between VMs. Reference
3774 * https://e2e.ti.com/support/processors/f/791/t/954382
3775 */
3776DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset);
3777
3778static void quirk_no_pm_reset(struct pci_dev *dev)
3779{
3780 /*
3781 * We can't do a bus reset on root bus devices, but an ineffective
3782 * PM reset may be better than nothing.
3783 */
3784 if (!pci_is_root_bus(dev->bus))
3785 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3786}
3787
3788/*
3789 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3790 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3791 * to have no effect on the device: it retains the framebuffer contents and
3792 * monitor sync. Advertising this support makes other layers, like VFIO,
3793 * assume pci_reset_function() is viable for this device. Mark it as
3794 * unavailable to skip it when testing reset methods.
3795 */
3796DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3797 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3798
3799/*
3800 * Spectrum-{1,2,3,4} devices report that a D3hot->D0 transition causes a reset
3801 * (i.e., they advertise NoSoftRst-). However, this transition does not have
3802 * any effect on the device: It continues to be operational and network ports
3803 * remain up. Advertising this support makes it seem as if a PM reset is viable
3804 * for these devices. Mark it as unavailable to skip it when testing reset
3805 * methods.
3806 */
3807DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcb84, quirk_no_pm_reset);
3808DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf6c, quirk_no_pm_reset);
3809DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf70, quirk_no_pm_reset);
3810DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf80, quirk_no_pm_reset);
3811
3812/*
3813 * Thunderbolt controllers with broken MSI hotplug signaling:
3814 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3815 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3816 */
3817static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
3818{
3819 if (pdev->is_hotplug_bridge &&
3820 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3821 pdev->revision <= 1))
3822 pdev->no_msi = 1;
3823}
3824DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3825 quirk_thunderbolt_hotplug_msi);
3826DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
3827 quirk_thunderbolt_hotplug_msi);
3828DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
3829 quirk_thunderbolt_hotplug_msi);
3830DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3831 quirk_thunderbolt_hotplug_msi);
3832DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3833 quirk_thunderbolt_hotplug_msi);
3834
3835#ifdef CONFIG_ACPI
3836/*
3837 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3838 *
3839 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3840 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3841 * be present after resume if a device was plugged in before suspend.
3842 *
3843 * The Thunderbolt controller consists of a PCIe switch with downstream
3844 * bridges leading to the NHI and to the tunnel PCI bridges.
3845 *
3846 * This quirk cuts power to the whole chip. Therefore we have to apply it
3847 * during suspend_noirq of the upstream bridge.
3848 *
3849 * Power is automagically restored before resume. No action is needed.
3850 */
3851static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3852{
3853 acpi_handle bridge, SXIO, SXFP, SXLV;
3854
3855 if (!x86_apple_machine)
3856 return;
3857 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3858 return;
3859
3860 /*
3861 * SXIO/SXFP/SXLF turns off power to the Thunderbolt controller.
3862 * We don't know how to turn it back on again, but firmware does,
3863 * so we can only use SXIO/SXFP/SXLF if we're suspending via
3864 * firmware.
3865 */
3866 if (!pm_suspend_via_firmware())
3867 return;
3868
3869 bridge = ACPI_HANDLE(&dev->dev);
3870 if (!bridge)
3871 return;
3872
3873 /*
3874 * SXIO and SXLV are present only on machines requiring this quirk.
3875 * Thunderbolt bridges in external devices might have the same
3876 * device ID as those on the host, but they will not have the
3877 * associated ACPI methods. This implicitly checks that we are at
3878 * the right bridge.
3879 */
3880 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3881 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3882 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3883 return;
3884 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n");
3885
3886 /* magic sequence */
3887 acpi_execute_simple_method(SXIO, NULL, 1);
3888 acpi_execute_simple_method(SXFP, NULL, 0);
3889 msleep(300);
3890 acpi_execute_simple_method(SXLV, NULL, 0);
3891 acpi_execute_simple_method(SXIO, NULL, 0);
3892 acpi_execute_simple_method(SXLV, NULL, 0);
3893}
3894DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3895 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3896 quirk_apple_poweroff_thunderbolt);
3897#endif
3898
3899/*
3900 * Following are device-specific reset methods which can be used to
3901 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3902 * not available.
3903 */
3904static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, bool probe)
3905{
3906 /*
3907 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3908 *
3909 * The 82599 supports FLR on VFs, but FLR support is reported only
3910 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3911 * Thus we must call pcie_flr() directly without first checking if it is
3912 * supported.
3913 */
3914 if (!probe)
3915 pcie_flr(dev);
3916 return 0;
3917}
3918
3919#define SOUTH_CHICKEN2 0xc2004
3920#define PCH_PP_STATUS 0xc7200
3921#define PCH_PP_CONTROL 0xc7204
3922#define MSG_CTL 0x45010
3923#define NSDE_PWR_STATE 0xd0100
3924#define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3925
3926static int reset_ivb_igd(struct pci_dev *dev, bool probe)
3927{
3928 void __iomem *mmio_base;
3929 unsigned long timeout;
3930 u32 val;
3931
3932 if (probe)
3933 return 0;
3934
3935 mmio_base = pci_iomap(dev, 0, 0);
3936 if (!mmio_base)
3937 return -ENOMEM;
3938
3939 iowrite32(0x00000002, mmio_base + MSG_CTL);
3940
3941 /*
3942 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3943 * driver loaded sets the right bits. However, this's a reset and
3944 * the bits have been set by i915 previously, so we clobber
3945 * SOUTH_CHICKEN2 register directly here.
3946 */
3947 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3948
3949 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3950 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3951
3952 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3953 do {
3954 val = ioread32(mmio_base + PCH_PP_STATUS);
3955 if ((val & 0xb0000000) == 0)
3956 goto reset_complete;
3957 msleep(10);
3958 } while (time_before(jiffies, timeout));
3959 pci_warn(dev, "timeout during reset\n");
3960
3961reset_complete:
3962 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3963
3964 pci_iounmap(dev, mmio_base);
3965 return 0;
3966}
3967
3968/* Device-specific reset method for Chelsio T4-based adapters */
3969static int reset_chelsio_generic_dev(struct pci_dev *dev, bool probe)
3970{
3971 u16 old_command;
3972 u16 msix_flags;
3973
3974 /*
3975 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3976 * that we have no device-specific reset method.
3977 */
3978 if ((dev->device & 0xf000) != 0x4000)
3979 return -ENOTTY;
3980
3981 /*
3982 * If this is the "probe" phase, return 0 indicating that we can
3983 * reset this device.
3984 */
3985 if (probe)
3986 return 0;
3987
3988 /*
3989 * T4 can wedge if there are DMAs in flight within the chip and Bus
3990 * Master has been disabled. We need to have it on till the Function
3991 * Level Reset completes. (BUS_MASTER is disabled in
3992 * pci_reset_function()).
3993 */
3994 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3995 pci_write_config_word(dev, PCI_COMMAND,
3996 old_command | PCI_COMMAND_MASTER);
3997
3998 /*
3999 * Perform the actual device function reset, saving and restoring
4000 * configuration information around the reset.
4001 */
4002 pci_save_state(dev);
4003
4004 /*
4005 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
4006 * are disabled when an MSI-X interrupt message needs to be delivered.
4007 * So we briefly re-enable MSI-X interrupts for the duration of the
4008 * FLR. The pci_restore_state() below will restore the original
4009 * MSI-X state.
4010 */
4011 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
4012 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
4013 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
4014 msix_flags |
4015 PCI_MSIX_FLAGS_ENABLE |
4016 PCI_MSIX_FLAGS_MASKALL);
4017
4018 pcie_flr(dev);
4019
4020 /*
4021 * Restore the configuration information (BAR values, etc.) including
4022 * the original PCI Configuration Space Command word, and return
4023 * success.
4024 */
4025 pci_restore_state(dev);
4026 pci_write_config_word(dev, PCI_COMMAND, old_command);
4027 return 0;
4028}
4029
4030#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
4031#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
4032#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
4033
4034/*
4035 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after
4036 * FLR where config space reads from the device return -1. We seem to be
4037 * able to avoid this condition if we disable the NVMe controller prior to
4038 * FLR. This quirk is generic for any NVMe class device requiring similar
4039 * assistance to quiesce the device prior to FLR.
4040 *
4041 * NVMe specification: https://nvmexpress.org/resources/specifications/
4042 * Revision 1.0e:
4043 * Chapter 2: Required and optional PCI config registers
4044 * Chapter 3: NVMe control registers
4045 * Chapter 7.3: Reset behavior
4046 */
4047static int nvme_disable_and_flr(struct pci_dev *dev, bool probe)
4048{
4049 void __iomem *bar;
4050 u16 cmd;
4051 u32 cfg;
4052
4053 if (dev->class != PCI_CLASS_STORAGE_EXPRESS ||
4054 pcie_reset_flr(dev, PCI_RESET_PROBE) || !pci_resource_start(dev, 0))
4055 return -ENOTTY;
4056
4057 if (probe)
4058 return 0;
4059
4060 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg));
4061 if (!bar)
4062 return -ENOTTY;
4063
4064 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4065 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY);
4066
4067 cfg = readl(bar + NVME_REG_CC);
4068
4069 /* Disable controller if enabled */
4070 if (cfg & NVME_CC_ENABLE) {
4071 u32 cap = readl(bar + NVME_REG_CAP);
4072 unsigned long timeout;
4073
4074 /*
4075 * Per nvme_disable_ctrl() skip shutdown notification as it
4076 * could complete commands to the admin queue. We only intend
4077 * to quiesce the device before reset.
4078 */
4079 cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE);
4080
4081 writel(cfg, bar + NVME_REG_CC);
4082
4083 /*
4084 * Some controllers require an additional delay here, see
4085 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet
4086 * supported by this quirk.
4087 */
4088
4089 /* Cap register provides max timeout in 500ms increments */
4090 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
4091
4092 for (;;) {
4093 u32 status = readl(bar + NVME_REG_CSTS);
4094
4095 /* Ready status becomes zero on disable complete */
4096 if (!(status & NVME_CSTS_RDY))
4097 break;
4098
4099 msleep(100);
4100
4101 if (time_after(jiffies, timeout)) {
4102 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n");
4103 break;
4104 }
4105 }
4106 }
4107
4108 pci_iounmap(dev, bar);
4109
4110 pcie_flr(dev);
4111
4112 return 0;
4113}
4114
4115/*
4116 * Some NVMe controllers such as Intel DC P3700 and Solidigm P44 Pro will
4117 * timeout waiting for ready status to change after NVMe enable if the driver
4118 * starts interacting with the device too soon after FLR. A 250ms delay after
4119 * FLR has heuristically proven to produce reliably working results for device
4120 * assignment cases.
4121 */
4122static int delay_250ms_after_flr(struct pci_dev *dev, bool probe)
4123{
4124 if (probe)
4125 return pcie_reset_flr(dev, PCI_RESET_PROBE);
4126
4127 pcie_reset_flr(dev, PCI_RESET_DO_RESET);
4128
4129 msleep(250);
4130
4131 return 0;
4132}
4133
4134#define PCI_DEVICE_ID_HINIC_VF 0x375E
4135#define HINIC_VF_FLR_TYPE 0x1000
4136#define HINIC_VF_FLR_CAP_BIT (1UL << 30)
4137#define HINIC_VF_OP 0xE80
4138#define HINIC_VF_FLR_PROC_BIT (1UL << 18)
4139#define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */
4140
4141/* Device-specific reset method for Huawei Intelligent NIC virtual functions */
4142static int reset_hinic_vf_dev(struct pci_dev *pdev, bool probe)
4143{
4144 unsigned long timeout;
4145 void __iomem *bar;
4146 u32 val;
4147
4148 if (probe)
4149 return 0;
4150
4151 bar = pci_iomap(pdev, 0, 0);
4152 if (!bar)
4153 return -ENOTTY;
4154
4155 /* Get and check firmware capabilities */
4156 val = ioread32be(bar + HINIC_VF_FLR_TYPE);
4157 if (!(val & HINIC_VF_FLR_CAP_BIT)) {
4158 pci_iounmap(pdev, bar);
4159 return -ENOTTY;
4160 }
4161
4162 /* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */
4163 val = ioread32be(bar + HINIC_VF_OP);
4164 val = val | HINIC_VF_FLR_PROC_BIT;
4165 iowrite32be(val, bar + HINIC_VF_OP);
4166
4167 pcie_flr(pdev);
4168
4169 /*
4170 * The device must recapture its Bus and Device Numbers after FLR
4171 * in order generate Completions. Issue a config write to let the
4172 * device capture this information.
4173 */
4174 pci_write_config_word(pdev, PCI_VENDOR_ID, 0);
4175
4176 /* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */
4177 timeout = jiffies + msecs_to_jiffies(HINIC_OPERATION_TIMEOUT);
4178 do {
4179 val = ioread32be(bar + HINIC_VF_OP);
4180 if (!(val & HINIC_VF_FLR_PROC_BIT))
4181 goto reset_complete;
4182 msleep(20);
4183 } while (time_before(jiffies, timeout));
4184
4185 val = ioread32be(bar + HINIC_VF_OP);
4186 if (!(val & HINIC_VF_FLR_PROC_BIT))
4187 goto reset_complete;
4188
4189 pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val);
4190
4191reset_complete:
4192 pci_iounmap(pdev, bar);
4193
4194 return 0;
4195}
4196
4197static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
4198 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
4199 reset_intel_82599_sfp_virtfn },
4200 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
4201 reset_ivb_igd },
4202 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
4203 reset_ivb_igd },
4204 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr },
4205 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr },
4206 { PCI_VENDOR_ID_INTEL, 0x0a54, delay_250ms_after_flr },
4207 { PCI_VENDOR_ID_SOLIDIGM, 0xf1ac, delay_250ms_after_flr },
4208 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4209 reset_chelsio_generic_dev },
4210 { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF,
4211 reset_hinic_vf_dev },
4212 { 0 }
4213};
4214
4215/*
4216 * These device-specific reset methods are here rather than in a driver
4217 * because when a host assigns a device to a guest VM, the host may need
4218 * to reset the device but probably doesn't have a driver for it.
4219 */
4220int pci_dev_specific_reset(struct pci_dev *dev, bool probe)
4221{
4222 const struct pci_dev_reset_methods *i;
4223
4224 for (i = pci_dev_reset_methods; i->reset; i++) {
4225 if ((i->vendor == dev->vendor ||
4226 i->vendor == (u16)PCI_ANY_ID) &&
4227 (i->device == dev->device ||
4228 i->device == (u16)PCI_ANY_ID))
4229 return i->reset(dev, probe);
4230 }
4231
4232 return -ENOTTY;
4233}
4234
4235static void quirk_dma_func0_alias(struct pci_dev *dev)
4236{
4237 if (PCI_FUNC(dev->devfn) != 0)
4238 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1);
4239}
4240
4241/*
4242 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
4243 *
4244 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
4245 */
4246DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
4247DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
4248
4249static void quirk_dma_func1_alias(struct pci_dev *dev)
4250{
4251 if (PCI_FUNC(dev->devfn) != 1)
4252 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1);
4253}
4254
4255/*
4256 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
4257 * SKUs function 1 is present and is a legacy IDE controller, in other
4258 * SKUs this function is not present, making this a ghost requester.
4259 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
4260 */
4261DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
4262 quirk_dma_func1_alias);
4263DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
4264 quirk_dma_func1_alias);
4265/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c136 */
4266DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125,
4267 quirk_dma_func1_alias);
4268DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
4269 quirk_dma_func1_alias);
4270/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
4271DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
4272 quirk_dma_func1_alias);
4273DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170,
4274 quirk_dma_func1_alias);
4275/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
4276DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
4277 quirk_dma_func1_alias);
4278/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
4279DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
4280 quirk_dma_func1_alias);
4281/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
4282DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
4283 quirk_dma_func1_alias);
4284/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */
4285DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183,
4286 quirk_dma_func1_alias);
4287/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
4288DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
4289 quirk_dma_func1_alias);
4290/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */
4291DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215,
4292 quirk_dma_func1_alias);
4293/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
4294DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
4295 quirk_dma_func1_alias);
4296/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
4297DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
4298 quirk_dma_func1_alias);
4299DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9235,
4300 quirk_dma_func1_alias);
4301DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
4302 quirk_dma_func1_alias);
4303DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
4304 quirk_dma_func1_alias);
4305/* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
4306DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
4307 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
4308 quirk_dma_func1_alias);
4309/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
4310DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4311 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
4312 quirk_dma_func1_alias);
4313
4314/*
4315 * Some devices DMA with the wrong devfn, not just the wrong function.
4316 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
4317 * the alias is "fixed" and independent of the device devfn.
4318 *
4319 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
4320 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
4321 * single device on the secondary bus. In reality, the single exposed
4322 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
4323 * that provides a bridge to the internal bus of the I/O processor. The
4324 * controller supports private devices, which can be hidden from PCI config
4325 * space. In the case of the Adaptec 3405, a private device at 01.0
4326 * appears to be the DMA engine, which therefore needs to become a DMA
4327 * alias for the device.
4328 */
4329static const struct pci_device_id fixed_dma_alias_tbl[] = {
4330 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4331 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
4332 .driver_data = PCI_DEVFN(1, 0) },
4333 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4334 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
4335 .driver_data = PCI_DEVFN(1, 0) },
4336 { 0 }
4337};
4338
4339static void quirk_fixed_dma_alias(struct pci_dev *dev)
4340{
4341 const struct pci_device_id *id;
4342
4343 id = pci_match_id(fixed_dma_alias_tbl, dev);
4344 if (id)
4345 pci_add_dma_alias(dev, id->driver_data, 1);
4346}
4347DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
4348
4349/*
4350 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
4351 * using the wrong DMA alias for the device. Some of these devices can be
4352 * used as either forward or reverse bridges, so we need to test whether the
4353 * device is operating in the correct mode. We could probably apply this
4354 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
4355 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
4356 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
4357 */
4358static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
4359{
4360 if (!pci_is_root_bus(pdev->bus) &&
4361 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4362 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
4363 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
4364 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
4365}
4366/* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
4367DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
4368 quirk_use_pcie_bridge_dma_alias);
4369/* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
4370DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
4371/* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
4372DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
4373/* ITE 8893 has the same problem as the 8892 */
4374DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
4375/* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
4376DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
4377
4378/*
4379 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
4380 * be added as aliases to the DMA device in order to allow buffer access
4381 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4382 * programmed in the EEPROM.
4383 */
4384static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
4385{
4386 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1);
4387 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1);
4388 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1);
4389}
4390DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
4391DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
4392
4393/*
4394 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices
4395 * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx).
4396 *
4397 * Similarly to MIC x200, we need to add DMA aliases to allow buffer access
4398 * when IOMMU is enabled. These aliases allow computational unit access to
4399 * host memory. These aliases mark the whole VCA device as one IOMMU
4400 * group.
4401 *
4402 * All possible slot numbers (0x20) are used, since we are unable to tell
4403 * what slot is used on other side. This quirk is intended for both host
4404 * and computational unit sides. The VCA devices have up to five functions
4405 * (four for DMA channels and one additional).
4406 */
4407static void quirk_pex_vca_alias(struct pci_dev *pdev)
4408{
4409 const unsigned int num_pci_slots = 0x20;
4410 unsigned int slot;
4411
4412 for (slot = 0; slot < num_pci_slots; slot++)
4413 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5);
4414}
4415DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias);
4416DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias);
4417DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias);
4418DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias);
4419DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias);
4420DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias);
4421
4422/*
4423 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
4424 * associated not at the root bus, but at a bridge below. This quirk avoids
4425 * generating invalid DMA aliases.
4426 */
4427static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
4428{
4429 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
4430}
4431DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
4432 quirk_bridge_cavm_thrx2_pcie_root);
4433DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
4434 quirk_bridge_cavm_thrx2_pcie_root);
4435
4436/*
4437 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4438 * class code. Fix it.
4439 */
4440static void quirk_tw686x_class(struct pci_dev *pdev)
4441{
4442 u32 class = pdev->class;
4443
4444 /* Use "Multimedia controller" class */
4445 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
4446 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
4447 class, pdev->class);
4448}
4449DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
4450 quirk_tw686x_class);
4451DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
4452 quirk_tw686x_class);
4453DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
4454 quirk_tw686x_class);
4455DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
4456 quirk_tw686x_class);
4457
4458/*
4459 * Some devices have problems with Transaction Layer Packets with the Relaxed
4460 * Ordering Attribute set. Such devices should mark themselves and other
4461 * device drivers should check before sending TLPs with RO set.
4462 */
4463static void quirk_relaxedordering_disable(struct pci_dev *dev)
4464{
4465 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
4466 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
4467}
4468
4469/*
4470 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
4471 * Complex have a Flow Control Credit issue which can cause performance
4472 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
4473 */
4474DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
4475 quirk_relaxedordering_disable);
4476DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
4477 quirk_relaxedordering_disable);
4478DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
4479 quirk_relaxedordering_disable);
4480DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
4481 quirk_relaxedordering_disable);
4482DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
4483 quirk_relaxedordering_disable);
4484DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
4485 quirk_relaxedordering_disable);
4486DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
4487 quirk_relaxedordering_disable);
4488DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
4489 quirk_relaxedordering_disable);
4490DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
4491 quirk_relaxedordering_disable);
4492DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
4493 quirk_relaxedordering_disable);
4494DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
4495 quirk_relaxedordering_disable);
4496DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
4497 quirk_relaxedordering_disable);
4498DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
4499 quirk_relaxedordering_disable);
4500DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
4501 quirk_relaxedordering_disable);
4502DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
4503 quirk_relaxedordering_disable);
4504DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
4505 quirk_relaxedordering_disable);
4506DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
4507 quirk_relaxedordering_disable);
4508DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
4509 quirk_relaxedordering_disable);
4510DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
4511 quirk_relaxedordering_disable);
4512DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
4513 quirk_relaxedordering_disable);
4514DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
4515 quirk_relaxedordering_disable);
4516DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
4517 quirk_relaxedordering_disable);
4518DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
4519 quirk_relaxedordering_disable);
4520DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
4521 quirk_relaxedordering_disable);
4522DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
4523 quirk_relaxedordering_disable);
4524DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
4525 quirk_relaxedordering_disable);
4526DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
4527 quirk_relaxedordering_disable);
4528DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
4529 quirk_relaxedordering_disable);
4530
4531/*
4532 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex
4533 * where Upstream Transaction Layer Packets with the Relaxed Ordering
4534 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
4535 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
4536 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4537 * November 10, 2010). As a result, on this platform we can't use Relaxed
4538 * Ordering for Upstream TLPs.
4539 */
4540DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
4541 quirk_relaxedordering_disable);
4542DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
4543 quirk_relaxedordering_disable);
4544DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
4545 quirk_relaxedordering_disable);
4546
4547/*
4548 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4549 * values for the Attribute as were supplied in the header of the
4550 * corresponding Request, except as explicitly allowed when IDO is used."
4551 *
4552 * If a non-compliant device generates a completion with a different
4553 * attribute than the request, the receiver may accept it (which itself
4554 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4555 * Malformed TLP or an Unexpected Completion, which will probably lead to a
4556 * device access timeout.
4557 *
4558 * If the non-compliant device generates completions with zero attributes
4559 * (instead of copying the attributes from the request), we can work around
4560 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
4561 * upstream devices so they always generate requests with zero attributes.
4562 *
4563 * This affects other devices under the same Root Port, but since these
4564 * attributes are performance hints, there should be no functional problem.
4565 *
4566 * Note that Configuration Space accesses are never supposed to have TLP
4567 * Attributes, so we're safe waiting till after any Configuration Space
4568 * accesses to do the Root Port fixup.
4569 */
4570static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
4571{
4572 struct pci_dev *root_port = pcie_find_root_port(pdev);
4573
4574 if (!root_port) {
4575 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n");
4576 return;
4577 }
4578
4579 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4580 dev_name(&pdev->dev));
4581 pcie_capability_clear_word(root_port, PCI_EXP_DEVCTL,
4582 PCI_EXP_DEVCTL_RELAX_EN |
4583 PCI_EXP_DEVCTL_NOSNOOP_EN);
4584}
4585
4586/*
4587 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4588 * Completion it generates.
4589 */
4590static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4591{
4592 /*
4593 * This mask/compare operation selects for Physical Function 4 on a
4594 * T5. We only need to fix up the Root Port once for any of the
4595 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4596 * 0x54xx so we use that one.
4597 */
4598 if ((pdev->device & 0xff00) == 0x5400)
4599 quirk_disable_root_port_attributes(pdev);
4600}
4601DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4602 quirk_chelsio_T5_disable_root_port_attributes);
4603
4604/*
4605 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
4606 * by a device
4607 * @acs_ctrl_req: Bitmask of desired ACS controls
4608 * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by
4609 * the hardware design
4610 *
4611 * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included
4612 * in @acs_ctrl_ena, i.e., the device provides all the access controls the
4613 * caller desires. Return 0 otherwise.
4614 */
4615static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena)
4616{
4617 if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req)
4618 return 1;
4619 return 0;
4620}
4621
4622/*
4623 * AMD has indicated that the devices below do not support peer-to-peer
4624 * in any system where they are found in the southbridge with an AMD
4625 * IOMMU in the system. Multifunction devices that do not support
4626 * peer-to-peer between functions can claim to support a subset of ACS.
4627 * Such devices effectively enable request redirect (RR) and completion
4628 * redirect (CR) since all transactions are redirected to the upstream
4629 * root complex.
4630 *
4631 * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/
4632 * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/
4633 * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/
4634 *
4635 * 1002:4385 SBx00 SMBus Controller
4636 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4637 * 1002:4383 SBx00 Azalia (Intel HDA)
4638 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4639 * 1002:4384 SBx00 PCI to PCI Bridge
4640 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
4641 *
4642 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4643 *
4644 * 1022:780f [AMD] FCH PCI Bridge
4645 * 1022:7809 [AMD] FCH USB OHCI Controller
4646 */
4647static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
4648{
4649#ifdef CONFIG_ACPI
4650 struct acpi_table_header *header = NULL;
4651 acpi_status status;
4652
4653 /* Targeting multifunction devices on the SB (appears on root bus) */
4654 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
4655 return -ENODEV;
4656
4657 /* The IVRS table describes the AMD IOMMU */
4658 status = acpi_get_table("IVRS", 0, &header);
4659 if (ACPI_FAILURE(status))
4660 return -ENODEV;
4661
4662 acpi_put_table(header);
4663
4664 /* Filter out flags not applicable to multifunction */
4665 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
4666
4667 return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR);
4668#else
4669 return -ENODEV;
4670#endif
4671}
4672
4673static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
4674{
4675 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4676 return false;
4677
4678 switch (dev->device) {
4679 /*
4680 * Effectively selects all downstream ports for whole ThunderX1
4681 * (which represents 8 SoCs).
4682 */
4683 case 0xa000 ... 0xa7ff: /* ThunderX1 */
4684 case 0xaf84: /* ThunderX2 */
4685 case 0xb884: /* ThunderX3 */
4686 return true;
4687 default:
4688 return false;
4689 }
4690}
4691
4692static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4693{
4694 if (!pci_quirk_cavium_acs_match(dev))
4695 return -ENOTTY;
4696
4697 /*
4698 * Cavium Root Ports don't advertise an ACS capability. However,
4699 * the RTL internally implements similar protection as if ACS had
4700 * Source Validation, Request Redirection, Completion Redirection,
4701 * and Upstream Forwarding features enabled. Assert that the
4702 * hardware implements and enables equivalent ACS functionality for
4703 * these flags.
4704 */
4705 return pci_acs_ctrl_enabled(acs_flags,
4706 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4707}
4708
4709static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
4710{
4711 /*
4712 * X-Gene Root Ports matching this quirk do not allow peer-to-peer
4713 * transactions with others, allowing masking out these bits as if they
4714 * were unimplemented in the ACS capability.
4715 */
4716 return pci_acs_ctrl_enabled(acs_flags,
4717 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4718}
4719
4720/*
4721 * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability.
4722 * But the implementation could block peer-to-peer transactions between them
4723 * and provide ACS-like functionality.
4724 */
4725static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags)
4726{
4727 if (!pci_is_pcie(dev) ||
4728 ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) &&
4729 (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)))
4730 return -ENOTTY;
4731
4732 /*
4733 * Future Zhaoxin Root Ports and Switch Downstream Ports will
4734 * implement ACS capability in accordance with the PCIe Spec.
4735 */
4736 switch (dev->device) {
4737 case 0x0710 ... 0x071e:
4738 case 0x0721:
4739 case 0x0723 ... 0x0752:
4740 return pci_acs_ctrl_enabled(acs_flags,
4741 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4742 }
4743
4744 return false;
4745}
4746
4747/*
4748 * Many Intel PCH Root Ports do provide ACS-like features to disable peer
4749 * transactions and validate bus numbers in requests, but do not provide an
4750 * actual PCIe ACS capability. This is the list of device IDs known to fall
4751 * into that category as provided by Intel in Red Hat bugzilla 1037684.
4752 */
4753static const u16 pci_quirk_intel_pch_acs_ids[] = {
4754 /* Ibexpeak PCH */
4755 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4756 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4757 /* Cougarpoint PCH */
4758 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4759 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4760 /* Pantherpoint PCH */
4761 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4762 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4763 /* Lynxpoint-H PCH */
4764 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4765 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4766 /* Lynxpoint-LP PCH */
4767 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4768 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4769 /* Wildcat PCH */
4770 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4771 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4772 /* Patsburg (X79) PCH */
4773 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4774 /* Wellsburg (X99) PCH */
4775 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4776 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4777 /* Lynx Point (9 series) PCH */
4778 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4779};
4780
4781static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
4782{
4783 int i;
4784
4785 /* Filter out a few obvious non-matches first */
4786 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4787 return false;
4788
4789 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
4790 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4791 return true;
4792
4793 return false;
4794}
4795
4796static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
4797{
4798 if (!pci_quirk_intel_pch_acs_match(dev))
4799 return -ENOTTY;
4800
4801 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK)
4802 return pci_acs_ctrl_enabled(acs_flags,
4803 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4804
4805 return pci_acs_ctrl_enabled(acs_flags, 0);
4806}
4807
4808/*
4809 * These QCOM Root Ports do provide ACS-like features to disable peer
4810 * transactions and validate bus numbers in requests, but do not provide an
4811 * actual PCIe ACS capability. Hardware supports source validation but it
4812 * will report the issue as Completer Abort instead of ACS Violation.
4813 * Hardware doesn't support peer-to-peer and each Root Port is a Root
4814 * Complex with unique segment numbers. It is not possible for one Root
4815 * Port to pass traffic to another Root Port. All PCIe transactions are
4816 * terminated inside the Root Port.
4817 */
4818static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4819{
4820 return pci_acs_ctrl_enabled(acs_flags,
4821 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4822}
4823
4824/*
4825 * Each of these NXP Root Ports is in a Root Complex with a unique segment
4826 * number and does provide isolation features to disable peer transactions
4827 * and validate bus numbers in requests, but does not provide an ACS
4828 * capability.
4829 */
4830static int pci_quirk_nxp_rp_acs(struct pci_dev *dev, u16 acs_flags)
4831{
4832 return pci_acs_ctrl_enabled(acs_flags,
4833 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4834}
4835
4836static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags)
4837{
4838 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4839 return -ENOTTY;
4840
4841 /*
4842 * Amazon's Annapurna Labs root ports don't include an ACS capability,
4843 * but do include ACS-like functionality. The hardware doesn't support
4844 * peer-to-peer transactions via the root port and each has a unique
4845 * segment number.
4846 *
4847 * Additionally, the root ports cannot send traffic to each other.
4848 */
4849 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4850
4851 return acs_flags ? 0 : 1;
4852}
4853
4854/*
4855 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4856 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4857 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4858 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4859 * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4860 * control register is at offset 8 instead of 6 and we should probably use
4861 * dword accesses to them. This applies to the following PCI Device IDs, as
4862 * found in volume 1 of the datasheet[2]:
4863 *
4864 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4865 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4866 *
4867 * N.B. This doesn't fix what lspci shows.
4868 *
4869 * The 100 series chipset specification update includes this as errata #23[3].
4870 *
4871 * The 200 series chipset (Union Point) has the same bug according to the
4872 * specification update (Intel 200 Series Chipset Family Platform Controller
4873 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4874 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4875 * chipset include:
4876 *
4877 * 0xa290-0xa29f PCI Express Root port #{0-16}
4878 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4879 *
4880 * Mobile chipsets are also affected, 7th & 8th Generation
4881 * Specification update confirms ACS errata 22, status no fix: (7th Generation
4882 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
4883 * Processor Family I/O for U Quad Core Platforms Specification Update,
4884 * August 2017, Revision 002, Document#: 334660-002)[6]
4885 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
4886 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
4887 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4888 *
4889 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4890 *
4891 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4892 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4893 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4894 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4895 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4896 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
4897 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
4898 */
4899static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4900{
4901 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4902 return false;
4903
4904 switch (dev->device) {
4905 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4906 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4907 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
4908 return true;
4909 }
4910
4911 return false;
4912}
4913
4914#define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4915
4916static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4917{
4918 int pos;
4919 u32 cap, ctrl;
4920
4921 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4922 return -ENOTTY;
4923
4924 pos = dev->acs_cap;
4925 if (!pos)
4926 return -ENOTTY;
4927
4928 /* see pci_acs_flags_enabled() */
4929 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4930 acs_flags &= (cap | PCI_ACS_EC);
4931
4932 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4933
4934 return pci_acs_ctrl_enabled(acs_flags, ctrl);
4935}
4936
4937static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
4938{
4939 /*
4940 * SV, TB, and UF are not relevant to multifunction endpoints.
4941 *
4942 * Multifunction devices are only required to implement RR, CR, and DT
4943 * in their ACS capability if they support peer-to-peer transactions.
4944 * Devices matching this quirk have been verified by the vendor to not
4945 * perform peer-to-peer with other functions, allowing us to mask out
4946 * these bits as if they were unimplemented in the ACS capability.
4947 */
4948 return pci_acs_ctrl_enabled(acs_flags,
4949 PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4950 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4951}
4952
4953static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags)
4954{
4955 /*
4956 * Intel RCiEP's are required to allow p2p only on translated
4957 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16,
4958 * "Root-Complex Peer to Peer Considerations".
4959 */
4960 if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END)
4961 return -ENOTTY;
4962
4963 return pci_acs_ctrl_enabled(acs_flags,
4964 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4965}
4966
4967static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags)
4968{
4969 /*
4970 * iProc PAXB Root Ports don't advertise an ACS capability, but
4971 * they do not allow peer-to-peer transactions between Root Ports.
4972 * Allow each Root Port to be in a separate IOMMU group by masking
4973 * SV/RR/CR/UF bits.
4974 */
4975 return pci_acs_ctrl_enabled(acs_flags,
4976 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4977}
4978
4979/*
4980 * Wangxun 10G/1G NICs have no ACS capability, and on multi-function
4981 * devices, peer-to-peer transactions are not be used between the functions.
4982 * So add an ACS quirk for below devices to isolate functions.
4983 * SFxxx 1G NICs(em).
4984 * RP1000/RP2000 10G NICs(sp).
4985 */
4986static int pci_quirk_wangxun_nic_acs(struct pci_dev *dev, u16 acs_flags)
4987{
4988 switch (dev->device) {
4989 case 0x0100 ... 0x010F:
4990 case 0x1001:
4991 case 0x2001:
4992 return pci_acs_ctrl_enabled(acs_flags,
4993 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4994 }
4995
4996 return false;
4997}
4998
4999static const struct pci_dev_acs_enabled {
5000 u16 vendor;
5001 u16 device;
5002 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
5003} pci_dev_acs_enabled[] = {
5004 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
5005 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
5006 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
5007 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
5008 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
5009 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
5010 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
5011 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
5012 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
5013 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
5014 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
5015 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
5016 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
5017 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
5018 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
5019 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
5020 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
5021 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
5022 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
5023 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
5024 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
5025 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
5026 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
5027 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
5028 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
5029 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
5030 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
5031 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
5032 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
5033 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
5034 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
5035 /* 82580 */
5036 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
5037 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
5038 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
5039 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
5040 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
5041 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
5042 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
5043 /* 82576 */
5044 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
5045 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
5046 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
5047 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
5048 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
5049 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
5050 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
5051 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
5052 /* 82575 */
5053 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
5054 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
5055 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
5056 /* I350 */
5057 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
5058 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
5059 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
5060 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
5061 /* 82571 (Quads omitted due to non-ACS switch) */
5062 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
5063 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
5064 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
5065 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
5066 /* I219 */
5067 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
5068 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
5069 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs },
5070 /* QCOM QDF2xxx root ports */
5071 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },
5072 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
5073 /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */
5074 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs },
5075 /* Intel PCH root ports */
5076 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
5077 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
5078 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
5079 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
5080 /* Cavium ThunderX */
5081 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
5082 /* Cavium multi-function devices */
5083 { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs },
5084 { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs },
5085 { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs },
5086 /* APM X-Gene */
5087 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
5088 /* Ampere Computing */
5089 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
5090 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
5091 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs },
5092 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs },
5093 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs },
5094 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
5095 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
5096 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
5097 /* Broadcom multi-function device */
5098 { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs },
5099 { PCI_VENDOR_ID_BROADCOM, 0x1750, pci_quirk_mf_endpoint_acs },
5100 { PCI_VENDOR_ID_BROADCOM, 0x1751, pci_quirk_mf_endpoint_acs },
5101 { PCI_VENDOR_ID_BROADCOM, 0x1752, pci_quirk_mf_endpoint_acs },
5102 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
5103 /* Amazon Annapurna Labs */
5104 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
5105 /* Zhaoxin multi-function devices */
5106 { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs },
5107 { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs },
5108 { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs },
5109 /* NXP root ports, xx=16, 12, or 08 cores */
5110 /* LX2xx0A : without security features + CAN-FD */
5111 { PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs },
5112 { PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs },
5113 { PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs },
5114 /* LX2xx0C : security features + CAN-FD */
5115 { PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs },
5116 { PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs },
5117 { PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs },
5118 /* LX2xx0E : security features + CAN */
5119 { PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs },
5120 { PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs },
5121 { PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs },
5122 /* LX2xx0N : without security features + CAN */
5123 { PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs },
5124 { PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs },
5125 { PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs },
5126 /* LX2xx2A : without security features + CAN-FD */
5127 { PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs },
5128 { PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs },
5129 { PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs },
5130 /* LX2xx2C : security features + CAN-FD */
5131 { PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs },
5132 { PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs },
5133 { PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs },
5134 /* LX2xx2E : security features + CAN */
5135 { PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs },
5136 { PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs },
5137 { PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs },
5138 /* LX2xx2N : without security features + CAN */
5139 { PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs },
5140 { PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs },
5141 { PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs },
5142 /* Zhaoxin Root/Downstream Ports */
5143 { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs },
5144 /* Wangxun nics */
5145 { PCI_VENDOR_ID_WANGXUN, PCI_ANY_ID, pci_quirk_wangxun_nic_acs },
5146 { 0 }
5147};
5148
5149/*
5150 * pci_dev_specific_acs_enabled - check whether device provides ACS controls
5151 * @dev: PCI device
5152 * @acs_flags: Bitmask of desired ACS controls
5153 *
5154 * Returns:
5155 * -ENOTTY: No quirk applies to this device; we can't tell whether the
5156 * device provides the desired controls
5157 * 0: Device does not provide all the desired controls
5158 * >0: Device provides all the controls in @acs_flags
5159 */
5160int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
5161{
5162 const struct pci_dev_acs_enabled *i;
5163 int ret;
5164
5165 /*
5166 * Allow devices that do not expose standard PCIe ACS capabilities
5167 * or control to indicate their support here. Multi-function express
5168 * devices which do not allow internal peer-to-peer between functions,
5169 * but do not implement PCIe ACS may wish to return true here.
5170 */
5171 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
5172 if ((i->vendor == dev->vendor ||
5173 i->vendor == (u16)PCI_ANY_ID) &&
5174 (i->device == dev->device ||
5175 i->device == (u16)PCI_ANY_ID)) {
5176 ret = i->acs_enabled(dev, acs_flags);
5177 if (ret >= 0)
5178 return ret;
5179 }
5180 }
5181
5182 return -ENOTTY;
5183}
5184
5185/* Config space offset of Root Complex Base Address register */
5186#define INTEL_LPC_RCBA_REG 0xf0
5187/* 31:14 RCBA address */
5188#define INTEL_LPC_RCBA_MASK 0xffffc000
5189/* RCBA Enable */
5190#define INTEL_LPC_RCBA_ENABLE (1 << 0)
5191
5192/* Backbone Scratch Pad Register */
5193#define INTEL_BSPR_REG 0x1104
5194/* Backbone Peer Non-Posted Disable */
5195#define INTEL_BSPR_REG_BPNPD (1 << 8)
5196/* Backbone Peer Posted Disable */
5197#define INTEL_BSPR_REG_BPPD (1 << 9)
5198
5199/* Upstream Peer Decode Configuration Register */
5200#define INTEL_UPDCR_REG 0x1014
5201/* 5:0 Peer Decode Enable bits */
5202#define INTEL_UPDCR_REG_MASK 0x3f
5203
5204static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
5205{
5206 u32 rcba, bspr, updcr;
5207 void __iomem *rcba_mem;
5208
5209 /*
5210 * Read the RCBA register from the LPC (D31:F0). PCH root ports
5211 * are D28:F* and therefore get probed before LPC, thus we can't
5212 * use pci_get_slot()/pci_read_config_dword() here.
5213 */
5214 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
5215 INTEL_LPC_RCBA_REG, &rcba);
5216 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
5217 return -EINVAL;
5218
5219 rcba_mem = ioremap(rcba & INTEL_LPC_RCBA_MASK,
5220 PAGE_ALIGN(INTEL_UPDCR_REG));
5221 if (!rcba_mem)
5222 return -ENOMEM;
5223
5224 /*
5225 * The BSPR can disallow peer cycles, but it's set by soft strap and
5226 * therefore read-only. If both posted and non-posted peer cycles are
5227 * disallowed, we're ok. If either are allowed, then we need to use
5228 * the UPDCR to disable peer decodes for each port. This provides the
5229 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
5230 */
5231 bspr = readl(rcba_mem + INTEL_BSPR_REG);
5232 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
5233 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
5234 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
5235 if (updcr & INTEL_UPDCR_REG_MASK) {
5236 pci_info(dev, "Disabling UPDCR peer decodes\n");
5237 updcr &= ~INTEL_UPDCR_REG_MASK;
5238 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
5239 }
5240 }
5241
5242 iounmap(rcba_mem);
5243 return 0;
5244}
5245
5246/* Miscellaneous Port Configuration register */
5247#define INTEL_MPC_REG 0xd8
5248/* MPC: Invalid Receive Bus Number Check Enable */
5249#define INTEL_MPC_REG_IRBNCE (1 << 26)
5250
5251static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
5252{
5253 u32 mpc;
5254
5255 /*
5256 * When enabled, the IRBNCE bit of the MPC register enables the
5257 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
5258 * ensures that requester IDs fall within the bus number range
5259 * of the bridge. Enable if not already.
5260 */
5261 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
5262 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
5263 pci_info(dev, "Enabling MPC IRBNCE\n");
5264 mpc |= INTEL_MPC_REG_IRBNCE;
5265 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
5266 }
5267}
5268
5269/*
5270 * Currently this quirk does the equivalent of
5271 * PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
5272 *
5273 * TODO: This quirk also needs to do equivalent of PCI_ACS_TB,
5274 * if dev->external_facing || dev->untrusted
5275 */
5276static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
5277{
5278 if (!pci_quirk_intel_pch_acs_match(dev))
5279 return -ENOTTY;
5280
5281 if (pci_quirk_enable_intel_lpc_acs(dev)) {
5282 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n");
5283 return 0;
5284 }
5285
5286 pci_quirk_enable_intel_rp_mpc_acs(dev);
5287
5288 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
5289
5290 pci_info(dev, "Intel PCH root port ACS workaround enabled\n");
5291
5292 return 0;
5293}
5294
5295static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
5296{
5297 int pos;
5298 u32 cap, ctrl;
5299
5300 if (!pci_quirk_intel_spt_pch_acs_match(dev))
5301 return -ENOTTY;
5302
5303 pos = dev->acs_cap;
5304 if (!pos)
5305 return -ENOTTY;
5306
5307 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
5308 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
5309
5310 ctrl |= (cap & PCI_ACS_SV);
5311 ctrl |= (cap & PCI_ACS_RR);
5312 ctrl |= (cap & PCI_ACS_CR);
5313 ctrl |= (cap & PCI_ACS_UF);
5314
5315 if (pci_ats_disabled() || dev->external_facing || dev->untrusted)
5316 ctrl |= (cap & PCI_ACS_TB);
5317
5318 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
5319
5320 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n");
5321
5322 return 0;
5323}
5324
5325static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev)
5326{
5327 int pos;
5328 u32 cap, ctrl;
5329
5330 if (!pci_quirk_intel_spt_pch_acs_match(dev))
5331 return -ENOTTY;
5332
5333 pos = dev->acs_cap;
5334 if (!pos)
5335 return -ENOTTY;
5336
5337 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
5338 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
5339
5340 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
5341
5342 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
5343
5344 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n");
5345
5346 return 0;
5347}
5348
5349static const struct pci_dev_acs_ops {
5350 u16 vendor;
5351 u16 device;
5352 int (*enable_acs)(struct pci_dev *dev);
5353 int (*disable_acs_redir)(struct pci_dev *dev);
5354} pci_dev_acs_ops[] = {
5355 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
5356 .enable_acs = pci_quirk_enable_intel_pch_acs,
5357 },
5358 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
5359 .enable_acs = pci_quirk_enable_intel_spt_pch_acs,
5360 .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir,
5361 },
5362};
5363
5364int pci_dev_specific_enable_acs(struct pci_dev *dev)
5365{
5366 const struct pci_dev_acs_ops *p;
5367 int i, ret;
5368
5369 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
5370 p = &pci_dev_acs_ops[i];
5371 if ((p->vendor == dev->vendor ||
5372 p->vendor == (u16)PCI_ANY_ID) &&
5373 (p->device == dev->device ||
5374 p->device == (u16)PCI_ANY_ID) &&
5375 p->enable_acs) {
5376 ret = p->enable_acs(dev);
5377 if (ret >= 0)
5378 return ret;
5379 }
5380 }
5381
5382 return -ENOTTY;
5383}
5384
5385int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
5386{
5387 const struct pci_dev_acs_ops *p;
5388 int i, ret;
5389
5390 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
5391 p = &pci_dev_acs_ops[i];
5392 if ((p->vendor == dev->vendor ||
5393 p->vendor == (u16)PCI_ANY_ID) &&
5394 (p->device == dev->device ||
5395 p->device == (u16)PCI_ANY_ID) &&
5396 p->disable_acs_redir) {
5397 ret = p->disable_acs_redir(dev);
5398 if (ret >= 0)
5399 return ret;
5400 }
5401 }
5402
5403 return -ENOTTY;
5404}
5405
5406/*
5407 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
5408 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
5409 * Next Capability pointer in the MSI Capability Structure should point to
5410 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
5411 * the list.
5412 */
5413static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
5414{
5415 int pos, i = 0, ret;
5416 u8 next_cap;
5417 u16 reg16, *cap;
5418 struct pci_cap_saved_state *state;
5419
5420 /* Bail if the hardware bug is fixed */
5421 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
5422 return;
5423
5424 /* Bail if MSI Capability Structure is not found for some reason */
5425 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
5426 if (!pos)
5427 return;
5428
5429 /*
5430 * Bail if Next Capability pointer in the MSI Capability Structure
5431 * is not the expected incorrect 0x00.
5432 */
5433 pci_read_config_byte(pdev, pos + 1, &next_cap);
5434 if (next_cap)
5435 return;
5436
5437 /*
5438 * PCIe Capability Structure is expected to be at 0x50 and should
5439 * terminate the list (Next Capability pointer is 0x00). Verify
5440 * Capability Id and Next Capability pointer is as expected.
5441 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
5442 * to correctly set kernel data structures which have already been
5443 * set incorrectly due to the hardware bug.
5444 */
5445 pos = 0x50;
5446 pci_read_config_word(pdev, pos, ®16);
5447 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
5448 u32 status;
5449#ifndef PCI_EXP_SAVE_REGS
5450#define PCI_EXP_SAVE_REGS 7
5451#endif
5452 int size = PCI_EXP_SAVE_REGS * sizeof(u16);
5453
5454 pdev->pcie_cap = pos;
5455 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
5456 pdev->pcie_flags_reg = reg16;
5457 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
5458 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
5459
5460 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
5461 ret = pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status);
5462 if ((ret != PCIBIOS_SUCCESSFUL) || (PCI_POSSIBLE_ERROR(status)))
5463 pdev->cfg_size = PCI_CFG_SPACE_SIZE;
5464
5465 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
5466 return;
5467
5468 /* Save PCIe cap */
5469 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
5470 if (!state)
5471 return;
5472
5473 state->cap.cap_nr = PCI_CAP_ID_EXP;
5474 state->cap.cap_extended = 0;
5475 state->cap.size = size;
5476 cap = (u16 *)&state->cap.data[0];
5477 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
5478 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
5479 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
5480 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
5481 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
5482 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
5483 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
5484 hlist_add_head(&state->next, &pdev->saved_cap_space);
5485 }
5486}
5487DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
5488
5489/*
5490 * FLR may cause the following to devices to hang:
5491 *
5492 * AMD Starship/Matisse HD Audio Controller 0x1487
5493 * AMD Starship USB 3.0 Host Controller 0x148c
5494 * AMD Matisse USB 3.0 Host Controller 0x149c
5495 * Intel 82579LM Gigabit Ethernet Controller 0x1502
5496 * Intel 82579V Gigabit Ethernet Controller 0x1503
5497 *
5498 */
5499static void quirk_no_flr(struct pci_dev *dev)
5500{
5501 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
5502}
5503DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr);
5504DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr);
5505DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr);
5506DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x7901, quirk_no_flr);
5507DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr);
5508DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr);
5509
5510/* FLR may cause the SolidRun SNET DPU (rev 0x1) to hang */
5511static void quirk_no_flr_snet(struct pci_dev *dev)
5512{
5513 if (dev->revision == 0x1)
5514 quirk_no_flr(dev);
5515}
5516DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLIDRUN, 0x1000, quirk_no_flr_snet);
5517
5518static void quirk_no_ext_tags(struct pci_dev *pdev)
5519{
5520 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
5521
5522 if (!bridge)
5523 return;
5524
5525 bridge->no_ext_tags = 1;
5526 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n");
5527
5528 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
5529}
5530DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
5531DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
5532DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
5533DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
5534DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
5535DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
5536DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);
5537
5538#ifdef CONFIG_PCI_ATS
5539static void quirk_no_ats(struct pci_dev *pdev)
5540{
5541 pci_info(pdev, "disabling ATS\n");
5542 pdev->ats_cap = 0;
5543}
5544
5545/*
5546 * Some devices require additional driver setup to enable ATS. Don't use
5547 * ATS for those devices as ATS will be enabled before the driver has had a
5548 * chance to load and configure the device.
5549 */
5550static void quirk_amd_harvest_no_ats(struct pci_dev *pdev)
5551{
5552 if (pdev->device == 0x15d8) {
5553 if (pdev->revision == 0xcf &&
5554 pdev->subsystem_vendor == 0xea50 &&
5555 (pdev->subsystem_device == 0xce19 ||
5556 pdev->subsystem_device == 0xcc10 ||
5557 pdev->subsystem_device == 0xcc08))
5558 quirk_no_ats(pdev);
5559 } else {
5560 quirk_no_ats(pdev);
5561 }
5562}
5563
5564/* AMD Stoney platform GPU */
5565DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats);
5566/* AMD Iceland dGPU */
5567DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats);
5568/* AMD Navi10 dGPU */
5569DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7310, quirk_amd_harvest_no_ats);
5570DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats);
5571DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7318, quirk_amd_harvest_no_ats);
5572DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7319, quirk_amd_harvest_no_ats);
5573DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731a, quirk_amd_harvest_no_ats);
5574DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731b, quirk_amd_harvest_no_ats);
5575DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731e, quirk_amd_harvest_no_ats);
5576DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731f, quirk_amd_harvest_no_ats);
5577/* AMD Navi14 dGPU */
5578DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats);
5579DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats);
5580DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7347, quirk_amd_harvest_no_ats);
5581DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x734f, quirk_amd_harvest_no_ats);
5582/* AMD Raven platform iGPU */
5583DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats);
5584
5585/*
5586 * Intel IPU E2000 revisions before C0 implement incorrect endianness
5587 * in ATS Invalidate Request message body. Disable ATS for those devices.
5588 */
5589static void quirk_intel_e2000_no_ats(struct pci_dev *pdev)
5590{
5591 if (pdev->revision < 0x20)
5592 quirk_no_ats(pdev);
5593}
5594DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1451, quirk_intel_e2000_no_ats);
5595DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1452, quirk_intel_e2000_no_ats);
5596DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1453, quirk_intel_e2000_no_ats);
5597DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1454, quirk_intel_e2000_no_ats);
5598DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1455, quirk_intel_e2000_no_ats);
5599DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1457, quirk_intel_e2000_no_ats);
5600DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1459, quirk_intel_e2000_no_ats);
5601DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145a, quirk_intel_e2000_no_ats);
5602DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145c, quirk_intel_e2000_no_ats);
5603#endif /* CONFIG_PCI_ATS */
5604
5605/* Freescale PCIe doesn't support MSI in RC mode */
5606static void quirk_fsl_no_msi(struct pci_dev *pdev)
5607{
5608 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
5609 pdev->no_msi = 1;
5610}
5611DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
5612
5613/*
5614 * Although not allowed by the spec, some multi-function devices have
5615 * dependencies of one function (consumer) on another (supplier). For the
5616 * consumer to work in D0, the supplier must also be in D0. Create a
5617 * device link from the consumer to the supplier to enforce this
5618 * dependency. Runtime PM is allowed by default on the consumer to prevent
5619 * it from permanently keeping the supplier awake.
5620 */
5621static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer,
5622 unsigned int supplier, unsigned int class,
5623 unsigned int class_shift)
5624{
5625 struct pci_dev *supplier_pdev;
5626
5627 if (PCI_FUNC(pdev->devfn) != consumer)
5628 return;
5629
5630 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
5631 pdev->bus->number,
5632 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier));
5633 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) {
5634 pci_dev_put(supplier_pdev);
5635 return;
5636 }
5637
5638 if (device_link_add(&pdev->dev, &supplier_pdev->dev,
5639 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME))
5640 pci_info(pdev, "D0 power state depends on %s\n",
5641 pci_name(supplier_pdev));
5642 else
5643 pci_err(pdev, "Cannot enforce power dependency on %s\n",
5644 pci_name(supplier_pdev));
5645
5646 pm_runtime_allow(&pdev->dev);
5647 pci_dev_put(supplier_pdev);
5648}
5649
5650/*
5651 * Create device link for GPUs with integrated HDA controller for streaming
5652 * audio to attached displays.
5653 */
5654static void quirk_gpu_hda(struct pci_dev *hda)
5655{
5656 pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16);
5657}
5658DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5659 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5660DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID,
5661 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5662DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5663 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5664
5665/*
5666 * Create device link for GPUs with integrated USB xHCI Host
5667 * controller to VGA.
5668 */
5669static void quirk_gpu_usb(struct pci_dev *usb)
5670{
5671 pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16);
5672}
5673DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5674 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
5675DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5676 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
5677
5678/*
5679 * Create device link for GPUs with integrated Type-C UCSI controller
5680 * to VGA. Currently there is no class code defined for UCSI device over PCI
5681 * so using UNKNOWN class for now and it will be updated when UCSI
5682 * over PCI gets a class code.
5683 */
5684#define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
5685static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi)
5686{
5687 pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16);
5688}
5689DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5690 PCI_CLASS_SERIAL_UNKNOWN, 8,
5691 quirk_gpu_usb_typec_ucsi);
5692DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5693 PCI_CLASS_SERIAL_UNKNOWN, 8,
5694 quirk_gpu_usb_typec_ucsi);
5695
5696/*
5697 * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it
5698 * disabled. https://devtalk.nvidia.com/default/topic/1024022
5699 */
5700static void quirk_nvidia_hda(struct pci_dev *gpu)
5701{
5702 u8 hdr_type;
5703 u32 val;
5704
5705 /* There was no integrated HDA controller before MCP89 */
5706 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M)
5707 return;
5708
5709 /* Bit 25 at offset 0x488 enables the HDA controller */
5710 pci_read_config_dword(gpu, 0x488, &val);
5711 if (val & BIT(25))
5712 return;
5713
5714 pci_info(gpu, "Enabling HDA controller\n");
5715 pci_write_config_dword(gpu, 0x488, val | BIT(25));
5716
5717 /* The GPU becomes a multi-function device when the HDA is enabled */
5718 pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type);
5719 gpu->multifunction = FIELD_GET(PCI_HEADER_TYPE_MFD, hdr_type);
5720}
5721DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5722 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5723DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5724 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5725
5726/*
5727 * Some IDT switches incorrectly flag an ACS Source Validation error on
5728 * completions for config read requests even though PCIe r4.0, sec
5729 * 6.12.1.1, says that completions are never affected by ACS Source
5730 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
5731 *
5732 * Item #36 - Downstream port applies ACS Source Validation to Completions
5733 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that
5734 * completions are never affected by ACS Source Validation. However,
5735 * completions received by a downstream port of the PCIe switch from a
5736 * device that has not yet captured a PCIe bus number are incorrectly
5737 * dropped by ACS Source Validation by the switch downstream port.
5738 *
5739 * The workaround suggested by IDT is to issue a config write to the
5740 * downstream device before issuing the first config read. This allows the
5741 * downstream device to capture its bus and device numbers (see PCIe r4.0,
5742 * sec 2.2.9), thus avoiding the ACS error on the completion.
5743 *
5744 * However, we don't know when the device is ready to accept the config
5745 * write, so we do config reads until we receive a non-Config Request Retry
5746 * Status, then do the config write.
5747 *
5748 * To avoid hitting the erratum when doing the config reads, we disable ACS
5749 * SV around this process.
5750 */
5751int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout)
5752{
5753 int pos;
5754 u16 ctrl = 0;
5755 bool found;
5756 struct pci_dev *bridge = bus->self;
5757
5758 pos = bridge->acs_cap;
5759
5760 /* Disable ACS SV before initial config reads */
5761 if (pos) {
5762 pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl);
5763 if (ctrl & PCI_ACS_SV)
5764 pci_write_config_word(bridge, pos + PCI_ACS_CTRL,
5765 ctrl & ~PCI_ACS_SV);
5766 }
5767
5768 found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
5769
5770 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */
5771 if (found)
5772 pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0);
5773
5774 /* Re-enable ACS_SV if it was previously enabled */
5775 if (ctrl & PCI_ACS_SV)
5776 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl);
5777
5778 return found;
5779}
5780
5781/*
5782 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
5783 * NT endpoints via the internal switch fabric. These IDs replace the
5784 * originating Requester ID TLPs which access host memory on peer NTB
5785 * ports. Therefore, all proxy IDs must be aliased to the NTB device
5786 * to permit access when the IOMMU is turned on.
5787 */
5788static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
5789{
5790 void __iomem *mmio;
5791 struct ntb_info_regs __iomem *mmio_ntb;
5792 struct ntb_ctrl_regs __iomem *mmio_ctrl;
5793 u64 partition_map;
5794 u8 partition;
5795 int pp;
5796
5797 if (pci_enable_device(pdev)) {
5798 pci_err(pdev, "Cannot enable Switchtec device\n");
5799 return;
5800 }
5801
5802 mmio = pci_iomap(pdev, 0, 0);
5803 if (mmio == NULL) {
5804 pci_disable_device(pdev);
5805 pci_err(pdev, "Cannot iomap Switchtec device\n");
5806 return;
5807 }
5808
5809 pci_info(pdev, "Setting Switchtec proxy ID aliases\n");
5810
5811 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET;
5812 mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET;
5813
5814 partition = ioread8(&mmio_ntb->partition_id);
5815
5816 partition_map = ioread32(&mmio_ntb->ep_map);
5817 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32;
5818 partition_map &= ~(1ULL << partition);
5819
5820 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) {
5821 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl;
5822 u32 table_sz = 0;
5823 int te;
5824
5825 if (!(partition_map & (1ULL << pp)))
5826 continue;
5827
5828 pci_dbg(pdev, "Processing partition %d\n", pp);
5829
5830 mmio_peer_ctrl = &mmio_ctrl[pp];
5831
5832 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size);
5833 if (!table_sz) {
5834 pci_warn(pdev, "Partition %d table_sz 0\n", pp);
5835 continue;
5836 }
5837
5838 if (table_sz > 512) {
5839 pci_warn(pdev,
5840 "Invalid Switchtec partition %d table_sz %d\n",
5841 pp, table_sz);
5842 continue;
5843 }
5844
5845 for (te = 0; te < table_sz; te++) {
5846 u32 rid_entry;
5847 u8 devfn;
5848
5849 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]);
5850 devfn = (rid_entry >> 1) & 0xFF;
5851 pci_dbg(pdev,
5852 "Aliasing Partition %d Proxy ID %02x.%d\n",
5853 pp, PCI_SLOT(devfn), PCI_FUNC(devfn));
5854 pci_add_dma_alias(pdev, devfn, 1);
5855 }
5856 }
5857
5858 pci_iounmap(pdev, mmio);
5859 pci_disable_device(pdev);
5860}
5861#define SWITCHTEC_QUIRK(vid) \
5862 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \
5863 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias)
5864
5865SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */
5866SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */
5867SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */
5868SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */
5869SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */
5870SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */
5871SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */
5872SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */
5873SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */
5874SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */
5875SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */
5876SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */
5877SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */
5878SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */
5879SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */
5880SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */
5881SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */
5882SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */
5883SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */
5884SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */
5885SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */
5886SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */
5887SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */
5888SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */
5889SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */
5890SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */
5891SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */
5892SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */
5893SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */
5894SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */
5895SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */
5896SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */
5897SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */
5898SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */
5899SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */
5900SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */
5901SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */
5902SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */
5903SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */
5904SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */
5905SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */
5906SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */
5907SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */
5908SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */
5909SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */
5910SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */
5911SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */
5912SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */
5913SWITCHTEC_QUIRK(0x4352); /* PFXA 52XG4 */
5914SWITCHTEC_QUIRK(0x4336); /* PFXA 36XG4 */
5915SWITCHTEC_QUIRK(0x4328); /* PFXA 28XG4 */
5916SWITCHTEC_QUIRK(0x4452); /* PSXA 52XG4 */
5917SWITCHTEC_QUIRK(0x4436); /* PSXA 36XG4 */
5918SWITCHTEC_QUIRK(0x4428); /* PSXA 28XG4 */
5919SWITCHTEC_QUIRK(0x4552); /* PAXA 52XG4 */
5920SWITCHTEC_QUIRK(0x4536); /* PAXA 36XG4 */
5921SWITCHTEC_QUIRK(0x4528); /* PAXA 28XG4 */
5922SWITCHTEC_QUIRK(0x5000); /* PFX 100XG5 */
5923SWITCHTEC_QUIRK(0x5084); /* PFX 84XG5 */
5924SWITCHTEC_QUIRK(0x5068); /* PFX 68XG5 */
5925SWITCHTEC_QUIRK(0x5052); /* PFX 52XG5 */
5926SWITCHTEC_QUIRK(0x5036); /* PFX 36XG5 */
5927SWITCHTEC_QUIRK(0x5028); /* PFX 28XG5 */
5928SWITCHTEC_QUIRK(0x5100); /* PSX 100XG5 */
5929SWITCHTEC_QUIRK(0x5184); /* PSX 84XG5 */
5930SWITCHTEC_QUIRK(0x5168); /* PSX 68XG5 */
5931SWITCHTEC_QUIRK(0x5152); /* PSX 52XG5 */
5932SWITCHTEC_QUIRK(0x5136); /* PSX 36XG5 */
5933SWITCHTEC_QUIRK(0x5128); /* PSX 28XG5 */
5934SWITCHTEC_QUIRK(0x5200); /* PAX 100XG5 */
5935SWITCHTEC_QUIRK(0x5284); /* PAX 84XG5 */
5936SWITCHTEC_QUIRK(0x5268); /* PAX 68XG5 */
5937SWITCHTEC_QUIRK(0x5252); /* PAX 52XG5 */
5938SWITCHTEC_QUIRK(0x5236); /* PAX 36XG5 */
5939SWITCHTEC_QUIRK(0x5228); /* PAX 28XG5 */
5940SWITCHTEC_QUIRK(0x5300); /* PFXA 100XG5 */
5941SWITCHTEC_QUIRK(0x5384); /* PFXA 84XG5 */
5942SWITCHTEC_QUIRK(0x5368); /* PFXA 68XG5 */
5943SWITCHTEC_QUIRK(0x5352); /* PFXA 52XG5 */
5944SWITCHTEC_QUIRK(0x5336); /* PFXA 36XG5 */
5945SWITCHTEC_QUIRK(0x5328); /* PFXA 28XG5 */
5946SWITCHTEC_QUIRK(0x5400); /* PSXA 100XG5 */
5947SWITCHTEC_QUIRK(0x5484); /* PSXA 84XG5 */
5948SWITCHTEC_QUIRK(0x5468); /* PSXA 68XG5 */
5949SWITCHTEC_QUIRK(0x5452); /* PSXA 52XG5 */
5950SWITCHTEC_QUIRK(0x5436); /* PSXA 36XG5 */
5951SWITCHTEC_QUIRK(0x5428); /* PSXA 28XG5 */
5952SWITCHTEC_QUIRK(0x5500); /* PAXA 100XG5 */
5953SWITCHTEC_QUIRK(0x5584); /* PAXA 84XG5 */
5954SWITCHTEC_QUIRK(0x5568); /* PAXA 68XG5 */
5955SWITCHTEC_QUIRK(0x5552); /* PAXA 52XG5 */
5956SWITCHTEC_QUIRK(0x5536); /* PAXA 36XG5 */
5957SWITCHTEC_QUIRK(0x5528); /* PAXA 28XG5 */
5958
5959/*
5960 * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints.
5961 * These IDs are used to forward responses to the originator on the other
5962 * side of the NTB. Alias all possible IDs to the NTB to permit access when
5963 * the IOMMU is turned on.
5964 */
5965static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev)
5966{
5967 pci_info(pdev, "Setting PLX NTB proxy ID aliases\n");
5968 /* PLX NTB may use all 256 devfns */
5969 pci_add_dma_alias(pdev, 0, 256);
5970}
5971DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias);
5972DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias);
5973
5974/*
5975 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does
5976 * not always reset the secondary Nvidia GPU between reboots if the system
5977 * is configured to use Hybrid Graphics mode. This results in the GPU
5978 * being left in whatever state it was in during the *previous* boot, which
5979 * causes spurious interrupts from the GPU, which in turn causes us to
5980 * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly,
5981 * this also completely breaks nouveau.
5982 *
5983 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a
5984 * clean state and fixes all these issues.
5985 *
5986 * When the machine is configured in Dedicated display mode, the issue
5987 * doesn't occur. Fortunately the GPU advertises NoReset+ when in this
5988 * mode, so we can detect that and avoid resetting it.
5989 */
5990static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev)
5991{
5992 void __iomem *map;
5993 int ret;
5994
5995 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO ||
5996 pdev->subsystem_device != 0x222e ||
5997 !pci_reset_supported(pdev))
5998 return;
5999
6000 if (pci_enable_device_mem(pdev))
6001 return;
6002
6003 /*
6004 * Based on nvkm_device_ctor() in
6005 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
6006 */
6007 map = pci_iomap(pdev, 0, 0x23000);
6008 if (!map) {
6009 pci_err(pdev, "Can't map MMIO space\n");
6010 goto out_disable;
6011 }
6012
6013 /*
6014 * Make sure the GPU looks like it's been POSTed before resetting
6015 * it.
6016 */
6017 if (ioread32(map + 0x2240c) & 0x2) {
6018 pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n");
6019 ret = pci_reset_bus(pdev);
6020 if (ret < 0)
6021 pci_err(pdev, "Failed to reset GPU: %d\n", ret);
6022 }
6023
6024 iounmap(map);
6025out_disable:
6026 pci_disable_device(pdev);
6027}
6028DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1,
6029 PCI_CLASS_DISPLAY_VGA, 8,
6030 quirk_reset_lenovo_thinkpad_p50_nvgpu);
6031
6032/*
6033 * Device [1b21:2142]
6034 * When in D0, PME# doesn't get asserted when plugging USB 3.0 device.
6035 */
6036static void pci_fixup_no_d0_pme(struct pci_dev *dev)
6037{
6038 pci_info(dev, "PME# does not work under D0, disabling it\n");
6039 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT);
6040}
6041DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme);
6042
6043/*
6044 * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI]
6045 *
6046 * These devices advertise PME# support in all power states but don't
6047 * reliably assert it.
6048 *
6049 * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf)
6050 * says "The MSI Function is not implemented on this device" in chapters
6051 * 7.3.27, 7.3.29-7.3.31.
6052 */
6053static void pci_fixup_no_msi_no_pme(struct pci_dev *dev)
6054{
6055#ifdef CONFIG_PCI_MSI
6056 pci_info(dev, "MSI is not implemented on this device, disabling it\n");
6057 dev->no_msi = 1;
6058#endif
6059 pci_info(dev, "PME# is unreliable, disabling it\n");
6060 dev->pme_support = 0;
6061}
6062DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme);
6063DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme);
6064
6065static void apex_pci_fixup_class(struct pci_dev *pdev)
6066{
6067 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class;
6068}
6069DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a,
6070 PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class);
6071
6072/*
6073 * Pericom PI7C9X2G404/PI7C9X2G304/PI7C9X2G303 switch erratum E5 -
6074 * ACS P2P Request Redirect is not functional
6075 *
6076 * When ACS P2P Request Redirect is enabled and bandwidth is not balanced
6077 * between upstream and downstream ports, packets are queued in an internal
6078 * buffer until CPLD packet. The workaround is to use the switch in store and
6079 * forward mode.
6080 */
6081#define PI7C9X2Gxxx_MODE_REG 0x74
6082#define PI7C9X2Gxxx_STORE_FORWARD_MODE BIT(0)
6083static void pci_fixup_pericom_acs_store_forward(struct pci_dev *pdev)
6084{
6085 struct pci_dev *upstream;
6086 u16 val;
6087
6088 /* Downstream ports only */
6089 if (pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM)
6090 return;
6091
6092 /* Check for ACS P2P Request Redirect use */
6093 if (!pdev->acs_cap)
6094 return;
6095 pci_read_config_word(pdev, pdev->acs_cap + PCI_ACS_CTRL, &val);
6096 if (!(val & PCI_ACS_RR))
6097 return;
6098
6099 upstream = pci_upstream_bridge(pdev);
6100 if (!upstream)
6101 return;
6102
6103 pci_read_config_word(upstream, PI7C9X2Gxxx_MODE_REG, &val);
6104 if (!(val & PI7C9X2Gxxx_STORE_FORWARD_MODE)) {
6105 pci_info(upstream, "Setting PI7C9X2Gxxx store-forward mode to avoid ACS erratum\n");
6106 pci_write_config_word(upstream, PI7C9X2Gxxx_MODE_REG, val |
6107 PI7C9X2Gxxx_STORE_FORWARD_MODE);
6108 }
6109}
6110/*
6111 * Apply fixup on enable and on resume, in order to apply the fix up whenever
6112 * ACS configuration changes or switch mode is reset
6113 */
6114DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2404,
6115 pci_fixup_pericom_acs_store_forward);
6116DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2404,
6117 pci_fixup_pericom_acs_store_forward);
6118DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2304,
6119 pci_fixup_pericom_acs_store_forward);
6120DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2304,
6121 pci_fixup_pericom_acs_store_forward);
6122DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2303,
6123 pci_fixup_pericom_acs_store_forward);
6124DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2303,
6125 pci_fixup_pericom_acs_store_forward);
6126
6127static void nvidia_ion_ahci_fixup(struct pci_dev *pdev)
6128{
6129 pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING;
6130}
6131DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup);
6132
6133static void rom_bar_overlap_defect(struct pci_dev *dev)
6134{
6135 pci_info(dev, "working around ROM BAR overlap defect\n");
6136 dev->rom_bar_overlap = 1;
6137}
6138DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1533, rom_bar_overlap_defect);
6139DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1536, rom_bar_overlap_defect);
6140DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1537, rom_bar_overlap_defect);
6141DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1538, rom_bar_overlap_defect);
6142
6143#ifdef CONFIG_PCIEASPM
6144/*
6145 * Several Intel DG2 graphics devices advertise that they can only tolerate
6146 * 1us latency when transitioning from L1 to L0, which may prevent ASPM L1
6147 * from being enabled. But in fact these devices can tolerate unlimited
6148 * latency. Override their Device Capabilities value to allow ASPM L1 to
6149 * be enabled.
6150 */
6151static void aspm_l1_acceptable_latency(struct pci_dev *dev)
6152{
6153 u32 l1_lat = FIELD_GET(PCI_EXP_DEVCAP_L1, dev->devcap);
6154
6155 if (l1_lat < 7) {
6156 dev->devcap |= FIELD_PREP(PCI_EXP_DEVCAP_L1, 7);
6157 pci_info(dev, "ASPM: overriding L1 acceptable latency from %#x to 0x7\n",
6158 l1_lat);
6159 }
6160}
6161DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f80, aspm_l1_acceptable_latency);
6162DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f81, aspm_l1_acceptable_latency);
6163DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f82, aspm_l1_acceptable_latency);
6164DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f83, aspm_l1_acceptable_latency);
6165DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f84, aspm_l1_acceptable_latency);
6166DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f85, aspm_l1_acceptable_latency);
6167DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f86, aspm_l1_acceptable_latency);
6168DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f87, aspm_l1_acceptable_latency);
6169DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f88, aspm_l1_acceptable_latency);
6170DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5690, aspm_l1_acceptable_latency);
6171DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5691, aspm_l1_acceptable_latency);
6172DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5692, aspm_l1_acceptable_latency);
6173DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5693, aspm_l1_acceptable_latency);
6174DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5694, aspm_l1_acceptable_latency);
6175DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5695, aspm_l1_acceptable_latency);
6176DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a0, aspm_l1_acceptable_latency);
6177DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a1, aspm_l1_acceptable_latency);
6178DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a2, aspm_l1_acceptable_latency);
6179DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a3, aspm_l1_acceptable_latency);
6180DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a4, aspm_l1_acceptable_latency);
6181DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a5, aspm_l1_acceptable_latency);
6182DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a6, aspm_l1_acceptable_latency);
6183DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b0, aspm_l1_acceptable_latency);
6184DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency);
6185DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency);
6186DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency);
6187#endif
6188
6189#ifdef CONFIG_PCIE_DPC
6190/*
6191 * Intel Ice Lake, Tiger Lake and Alder Lake BIOS has a bug that clears
6192 * the DPC RP PIO Log Size of the integrated Thunderbolt PCIe Root
6193 * Ports.
6194 */
6195static void dpc_log_size(struct pci_dev *dev)
6196{
6197 u16 dpc, val;
6198
6199 dpc = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC);
6200 if (!dpc)
6201 return;
6202
6203 pci_read_config_word(dev, dpc + PCI_EXP_DPC_CAP, &val);
6204 if (!(val & PCI_EXP_DPC_CAP_RP_EXT))
6205 return;
6206
6207 if (FIELD_GET(PCI_EXP_DPC_RP_PIO_LOG_SIZE, val) == 0) {
6208 pci_info(dev, "Overriding RP PIO Log Size to 4\n");
6209 dev->dpc_rp_log_size = 4;
6210 }
6211}
6212DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size);
6213DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size);
6214DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size);
6215DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size);
6216DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1d, dpc_log_size);
6217DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1f, dpc_log_size);
6218DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a21, dpc_log_size);
6219DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a23, dpc_log_size);
6220DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size);
6221DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size);
6222DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size);
6223DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a29, dpc_log_size);
6224DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2b, dpc_log_size);
6225DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size);
6226DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size);
6227DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size);
6228#endif
6229
6230/*
6231 * For a PCI device with multiple downstream devices, its driver may use
6232 * a flattened device tree to describe the downstream devices.
6233 * To overlay the flattened device tree, the PCI device and all its ancestor
6234 * devices need to have device tree nodes on system base device tree. Thus,
6235 * before driver probing, it might need to add a device tree node as the final
6236 * fixup.
6237 */
6238DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node);
6239DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node);
6240DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node);
6241
6242/*
6243 * Devices known to require a longer delay before first config space access
6244 * after reset recovery or resume from D3cold:
6245 *
6246 * VideoPropulsion (aka Genroco) Torrent QN16e MPEG QAM Modulator
6247 */
6248static void pci_fixup_d3cold_delay_1sec(struct pci_dev *pdev)
6249{
6250 pdev->d3cold_delay = 1000;
6251}
6252DECLARE_PCI_FIXUP_FINAL(0x5555, 0x0004, pci_fixup_d3cold_delay_1sec);