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1/*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/backlight.h>
25#include <linux/delay.h>
26#include <linux/gpio/consumer.h>
27#include <linux/module.h>
28#include <linux/of_platform.h>
29#include <linux/platform_device.h>
30#include <linux/regulator/consumer.h>
31
32#include <video/display_timing.h>
33#include <video/of_display_timing.h>
34#include <video/videomode.h>
35
36#include <drm/drm_crtc.h>
37#include <drm/drm_device.h>
38#include <drm/drm_mipi_dsi.h>
39#include <drm/drm_panel.h>
40
41/**
42 * @modes: Pointer to array of fixed modes appropriate for this panel. If
43 * only one mode then this can just be the address of this the mode.
44 * NOTE: cannot be used with "timings" and also if this is specified
45 * then you cannot override the mode in the device tree.
46 * @num_modes: Number of elements in modes array.
47 * @timings: Pointer to array of display timings. NOTE: cannot be used with
48 * "modes" and also these will be used to validate a device tree
49 * override if one is present.
50 * @num_timings: Number of elements in timings array.
51 * @bpc: Bits per color.
52 * @size: Structure containing the physical size of this panel.
53 * @delay: Structure containing various delay values for this panel.
54 * @bus_format: See MEDIA_BUS_FMT_... defines.
55 * @bus_flags: See DRM_BUS_FLAG_... defines.
56 */
57struct panel_desc {
58 const struct drm_display_mode *modes;
59 unsigned int num_modes;
60 const struct display_timing *timings;
61 unsigned int num_timings;
62
63 unsigned int bpc;
64
65 /**
66 * @width: width (in millimeters) of the panel's active display area
67 * @height: height (in millimeters) of the panel's active display area
68 */
69 struct {
70 unsigned int width;
71 unsigned int height;
72 } size;
73
74 /**
75 * @prepare: the time (in milliseconds) that it takes for the panel to
76 * become ready and start receiving video data
77 * @hpd_absent_delay: Add this to the prepare delay if we know Hot
78 * Plug Detect isn't used.
79 * @enable: the time (in milliseconds) that it takes for the panel to
80 * display the first valid frame after starting to receive
81 * video data
82 * @disable: the time (in milliseconds) that it takes for the panel to
83 * turn the display off (no content is visible)
84 * @unprepare: the time (in milliseconds) that it takes for the panel
85 * to power itself down completely
86 */
87 struct {
88 unsigned int prepare;
89 unsigned int hpd_absent_delay;
90 unsigned int enable;
91 unsigned int disable;
92 unsigned int unprepare;
93 } delay;
94
95 u32 bus_format;
96 u32 bus_flags;
97};
98
99struct panel_simple {
100 struct drm_panel base;
101 bool prepared;
102 bool enabled;
103 bool no_hpd;
104
105 const struct panel_desc *desc;
106
107 struct backlight_device *backlight;
108 struct regulator *supply;
109 struct i2c_adapter *ddc;
110
111 struct gpio_desc *enable_gpio;
112
113 struct drm_display_mode override_mode;
114};
115
116static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
117{
118 return container_of(panel, struct panel_simple, base);
119}
120
121static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel)
122{
123 struct drm_connector *connector = panel->base.connector;
124 struct drm_device *drm = panel->base.drm;
125 struct drm_display_mode *mode;
126 unsigned int i, num = 0;
127
128 for (i = 0; i < panel->desc->num_timings; i++) {
129 const struct display_timing *dt = &panel->desc->timings[i];
130 struct videomode vm;
131
132 videomode_from_timing(dt, &vm);
133 mode = drm_mode_create(drm);
134 if (!mode) {
135 dev_err(drm->dev, "failed to add mode %ux%u\n",
136 dt->hactive.typ, dt->vactive.typ);
137 continue;
138 }
139
140 drm_display_mode_from_videomode(&vm, mode);
141
142 mode->type |= DRM_MODE_TYPE_DRIVER;
143
144 if (panel->desc->num_timings == 1)
145 mode->type |= DRM_MODE_TYPE_PREFERRED;
146
147 drm_mode_probed_add(connector, mode);
148 num++;
149 }
150
151 return num;
152}
153
154static unsigned int panel_simple_get_display_modes(struct panel_simple *panel)
155{
156 struct drm_connector *connector = panel->base.connector;
157 struct drm_device *drm = panel->base.drm;
158 struct drm_display_mode *mode;
159 unsigned int i, num = 0;
160
161 for (i = 0; i < panel->desc->num_modes; i++) {
162 const struct drm_display_mode *m = &panel->desc->modes[i];
163
164 mode = drm_mode_duplicate(drm, m);
165 if (!mode) {
166 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
167 m->hdisplay, m->vdisplay, m->vrefresh);
168 continue;
169 }
170
171 mode->type |= DRM_MODE_TYPE_DRIVER;
172
173 if (panel->desc->num_modes == 1)
174 mode->type |= DRM_MODE_TYPE_PREFERRED;
175
176 drm_mode_set_name(mode);
177
178 drm_mode_probed_add(connector, mode);
179 num++;
180 }
181
182 return num;
183}
184
185static int panel_simple_get_non_edid_modes(struct panel_simple *panel)
186{
187 struct drm_connector *connector = panel->base.connector;
188 struct drm_device *drm = panel->base.drm;
189 struct drm_display_mode *mode;
190 bool has_override = panel->override_mode.type;
191 unsigned int num = 0;
192
193 if (!panel->desc)
194 return 0;
195
196 if (has_override) {
197 mode = drm_mode_duplicate(drm, &panel->override_mode);
198 if (mode) {
199 drm_mode_probed_add(connector, mode);
200 num = 1;
201 } else {
202 dev_err(drm->dev, "failed to add override mode\n");
203 }
204 }
205
206 /* Only add timings if override was not there or failed to validate */
207 if (num == 0 && panel->desc->num_timings)
208 num = panel_simple_get_timings_modes(panel);
209
210 /*
211 * Only add fixed modes if timings/override added no mode.
212 *
213 * We should only ever have either the display timings specified
214 * or a fixed mode. Anything else is rather bogus.
215 */
216 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
217 if (num == 0)
218 num = panel_simple_get_display_modes(panel);
219
220 connector->display_info.bpc = panel->desc->bpc;
221 connector->display_info.width_mm = panel->desc->size.width;
222 connector->display_info.height_mm = panel->desc->size.height;
223 if (panel->desc->bus_format)
224 drm_display_info_set_bus_formats(&connector->display_info,
225 &panel->desc->bus_format, 1);
226 connector->display_info.bus_flags = panel->desc->bus_flags;
227
228 return num;
229}
230
231static int panel_simple_disable(struct drm_panel *panel)
232{
233 struct panel_simple *p = to_panel_simple(panel);
234
235 if (!p->enabled)
236 return 0;
237
238 if (p->backlight) {
239 p->backlight->props.power = FB_BLANK_POWERDOWN;
240 p->backlight->props.state |= BL_CORE_FBBLANK;
241 backlight_update_status(p->backlight);
242 }
243
244 if (p->desc->delay.disable)
245 msleep(p->desc->delay.disable);
246
247 p->enabled = false;
248
249 return 0;
250}
251
252static int panel_simple_unprepare(struct drm_panel *panel)
253{
254 struct panel_simple *p = to_panel_simple(panel);
255
256 if (!p->prepared)
257 return 0;
258
259 gpiod_set_value_cansleep(p->enable_gpio, 0);
260
261 regulator_disable(p->supply);
262
263 if (p->desc->delay.unprepare)
264 msleep(p->desc->delay.unprepare);
265
266 p->prepared = false;
267
268 return 0;
269}
270
271static int panel_simple_prepare(struct drm_panel *panel)
272{
273 struct panel_simple *p = to_panel_simple(panel);
274 unsigned int delay;
275 int err;
276
277 if (p->prepared)
278 return 0;
279
280 err = regulator_enable(p->supply);
281 if (err < 0) {
282 dev_err(panel->dev, "failed to enable supply: %d\n", err);
283 return err;
284 }
285
286 gpiod_set_value_cansleep(p->enable_gpio, 1);
287
288 delay = p->desc->delay.prepare;
289 if (p->no_hpd)
290 delay += p->desc->delay.hpd_absent_delay;
291 if (delay)
292 msleep(delay);
293
294 p->prepared = true;
295
296 return 0;
297}
298
299static int panel_simple_enable(struct drm_panel *panel)
300{
301 struct panel_simple *p = to_panel_simple(panel);
302
303 if (p->enabled)
304 return 0;
305
306 if (p->desc->delay.enable)
307 msleep(p->desc->delay.enable);
308
309 if (p->backlight) {
310 p->backlight->props.state &= ~BL_CORE_FBBLANK;
311 p->backlight->props.power = FB_BLANK_UNBLANK;
312 backlight_update_status(p->backlight);
313 }
314
315 p->enabled = true;
316
317 return 0;
318}
319
320static int panel_simple_get_modes(struct drm_panel *panel)
321{
322 struct panel_simple *p = to_panel_simple(panel);
323 int num = 0;
324
325 /* probe EDID if a DDC bus is available */
326 if (p->ddc) {
327 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
328 drm_connector_update_edid_property(panel->connector, edid);
329 if (edid) {
330 num += drm_add_edid_modes(panel->connector, edid);
331 kfree(edid);
332 }
333 }
334
335 /* add hard-coded panel modes */
336 num += panel_simple_get_non_edid_modes(p);
337
338 return num;
339}
340
341static int panel_simple_get_timings(struct drm_panel *panel,
342 unsigned int num_timings,
343 struct display_timing *timings)
344{
345 struct panel_simple *p = to_panel_simple(panel);
346 unsigned int i;
347
348 if (p->desc->num_timings < num_timings)
349 num_timings = p->desc->num_timings;
350
351 if (timings)
352 for (i = 0; i < num_timings; i++)
353 timings[i] = p->desc->timings[i];
354
355 return p->desc->num_timings;
356}
357
358static const struct drm_panel_funcs panel_simple_funcs = {
359 .disable = panel_simple_disable,
360 .unprepare = panel_simple_unprepare,
361 .prepare = panel_simple_prepare,
362 .enable = panel_simple_enable,
363 .get_modes = panel_simple_get_modes,
364 .get_timings = panel_simple_get_timings,
365};
366
367#define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
368 (to_check->field.typ >= bounds->field.min && \
369 to_check->field.typ <= bounds->field.max)
370static void panel_simple_parse_panel_timing_node(struct device *dev,
371 struct panel_simple *panel,
372 const struct display_timing *ot)
373{
374 const struct panel_desc *desc = panel->desc;
375 struct videomode vm;
376 unsigned int i;
377
378 if (WARN_ON(desc->num_modes)) {
379 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
380 return;
381 }
382 if (WARN_ON(!desc->num_timings)) {
383 dev_err(dev, "Reject override mode: no timings specified\n");
384 return;
385 }
386
387 for (i = 0; i < panel->desc->num_timings; i++) {
388 const struct display_timing *dt = &panel->desc->timings[i];
389
390 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
391 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
392 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
393 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
394 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
395 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
396 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
397 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
398 continue;
399
400 if (ot->flags != dt->flags)
401 continue;
402
403 videomode_from_timing(ot, &vm);
404 drm_display_mode_from_videomode(&vm, &panel->override_mode);
405 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
406 DRM_MODE_TYPE_PREFERRED;
407 break;
408 }
409
410 if (WARN_ON(!panel->override_mode.type))
411 dev_err(dev, "Reject override mode: No display_timing found\n");
412}
413
414static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
415{
416 struct device_node *backlight, *ddc;
417 struct panel_simple *panel;
418 struct display_timing dt;
419 int err;
420
421 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
422 if (!panel)
423 return -ENOMEM;
424
425 panel->enabled = false;
426 panel->prepared = false;
427 panel->desc = desc;
428
429 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
430
431 panel->supply = devm_regulator_get(dev, "power");
432 if (IS_ERR(panel->supply))
433 return PTR_ERR(panel->supply);
434
435 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
436 GPIOD_OUT_LOW);
437 if (IS_ERR(panel->enable_gpio)) {
438 err = PTR_ERR(panel->enable_gpio);
439 if (err != -EPROBE_DEFER)
440 dev_err(dev, "failed to request GPIO: %d\n", err);
441 return err;
442 }
443
444 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
445 if (backlight) {
446 panel->backlight = of_find_backlight_by_node(backlight);
447 of_node_put(backlight);
448
449 if (!panel->backlight)
450 return -EPROBE_DEFER;
451 }
452
453 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
454 if (ddc) {
455 panel->ddc = of_find_i2c_adapter_by_node(ddc);
456 of_node_put(ddc);
457
458 if (!panel->ddc) {
459 err = -EPROBE_DEFER;
460 goto free_backlight;
461 }
462 }
463
464 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
465 panel_simple_parse_panel_timing_node(dev, panel, &dt);
466
467 drm_panel_init(&panel->base);
468 panel->base.dev = dev;
469 panel->base.funcs = &panel_simple_funcs;
470
471 err = drm_panel_add(&panel->base);
472 if (err < 0)
473 goto free_ddc;
474
475 dev_set_drvdata(dev, panel);
476
477 return 0;
478
479free_ddc:
480 if (panel->ddc)
481 put_device(&panel->ddc->dev);
482free_backlight:
483 if (panel->backlight)
484 put_device(&panel->backlight->dev);
485
486 return err;
487}
488
489static int panel_simple_remove(struct device *dev)
490{
491 struct panel_simple *panel = dev_get_drvdata(dev);
492
493 drm_panel_remove(&panel->base);
494
495 panel_simple_disable(&panel->base);
496 panel_simple_unprepare(&panel->base);
497
498 if (panel->ddc)
499 put_device(&panel->ddc->dev);
500
501 if (panel->backlight)
502 put_device(&panel->backlight->dev);
503
504 return 0;
505}
506
507static void panel_simple_shutdown(struct device *dev)
508{
509 struct panel_simple *panel = dev_get_drvdata(dev);
510
511 panel_simple_disable(&panel->base);
512 panel_simple_unprepare(&panel->base);
513}
514
515static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
516 .clock = 9000,
517 .hdisplay = 480,
518 .hsync_start = 480 + 2,
519 .hsync_end = 480 + 2 + 41,
520 .htotal = 480 + 2 + 41 + 2,
521 .vdisplay = 272,
522 .vsync_start = 272 + 2,
523 .vsync_end = 272 + 2 + 10,
524 .vtotal = 272 + 2 + 10 + 2,
525 .vrefresh = 60,
526 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
527};
528
529static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
530 .modes = &ire_am_480272h3tmqw_t01h_mode,
531 .num_modes = 1,
532 .bpc = 8,
533 .size = {
534 .width = 105,
535 .height = 67,
536 },
537 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
538};
539
540static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
541 .clock = 33333,
542 .hdisplay = 800,
543 .hsync_start = 800 + 0,
544 .hsync_end = 800 + 0 + 255,
545 .htotal = 800 + 0 + 255 + 0,
546 .vdisplay = 480,
547 .vsync_start = 480 + 2,
548 .vsync_end = 480 + 2 + 45,
549 .vtotal = 480 + 2 + 45 + 0,
550 .vrefresh = 60,
551 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
552};
553
554static const struct panel_desc ampire_am800480r3tmqwa1h = {
555 .modes = &ire_am800480r3tmqwa1h_mode,
556 .num_modes = 1,
557 .bpc = 6,
558 .size = {
559 .width = 152,
560 .height = 91,
561 },
562 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
563};
564
565static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
566 .pixelclock = { 26400000, 33300000, 46800000 },
567 .hactive = { 800, 800, 800 },
568 .hfront_porch = { 16, 210, 354 },
569 .hback_porch = { 45, 36, 6 },
570 .hsync_len = { 1, 10, 40 },
571 .vactive = { 480, 480, 480 },
572 .vfront_porch = { 7, 22, 147 },
573 .vback_porch = { 22, 13, 3 },
574 .vsync_len = { 1, 10, 20 },
575 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
576 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
577};
578
579static const struct panel_desc armadeus_st0700_adapt = {
580 .timings = &santek_st0700i5y_rbslw_f_timing,
581 .num_timings = 1,
582 .bpc = 6,
583 .size = {
584 .width = 154,
585 .height = 86,
586 },
587 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
588 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
589};
590
591static const struct drm_display_mode auo_b101aw03_mode = {
592 .clock = 51450,
593 .hdisplay = 1024,
594 .hsync_start = 1024 + 156,
595 .hsync_end = 1024 + 156 + 8,
596 .htotal = 1024 + 156 + 8 + 156,
597 .vdisplay = 600,
598 .vsync_start = 600 + 16,
599 .vsync_end = 600 + 16 + 6,
600 .vtotal = 600 + 16 + 6 + 16,
601 .vrefresh = 60,
602};
603
604static const struct panel_desc auo_b101aw03 = {
605 .modes = &auo_b101aw03_mode,
606 .num_modes = 1,
607 .bpc = 6,
608 .size = {
609 .width = 223,
610 .height = 125,
611 },
612};
613
614static const struct display_timing auo_b101ean01_timing = {
615 .pixelclock = { 65300000, 72500000, 75000000 },
616 .hactive = { 1280, 1280, 1280 },
617 .hfront_porch = { 18, 119, 119 },
618 .hback_porch = { 21, 21, 21 },
619 .hsync_len = { 32, 32, 32 },
620 .vactive = { 800, 800, 800 },
621 .vfront_porch = { 4, 4, 4 },
622 .vback_porch = { 8, 8, 8 },
623 .vsync_len = { 18, 20, 20 },
624};
625
626static const struct panel_desc auo_b101ean01 = {
627 .timings = &auo_b101ean01_timing,
628 .num_timings = 1,
629 .bpc = 6,
630 .size = {
631 .width = 217,
632 .height = 136,
633 },
634};
635
636static const struct drm_display_mode auo_b101xtn01_mode = {
637 .clock = 72000,
638 .hdisplay = 1366,
639 .hsync_start = 1366 + 20,
640 .hsync_end = 1366 + 20 + 70,
641 .htotal = 1366 + 20 + 70,
642 .vdisplay = 768,
643 .vsync_start = 768 + 14,
644 .vsync_end = 768 + 14 + 42,
645 .vtotal = 768 + 14 + 42,
646 .vrefresh = 60,
647 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
648};
649
650static const struct panel_desc auo_b101xtn01 = {
651 .modes = &auo_b101xtn01_mode,
652 .num_modes = 1,
653 .bpc = 6,
654 .size = {
655 .width = 223,
656 .height = 125,
657 },
658};
659
660static const struct drm_display_mode auo_b116xw03_mode = {
661 .clock = 70589,
662 .hdisplay = 1366,
663 .hsync_start = 1366 + 40,
664 .hsync_end = 1366 + 40 + 40,
665 .htotal = 1366 + 40 + 40 + 32,
666 .vdisplay = 768,
667 .vsync_start = 768 + 10,
668 .vsync_end = 768 + 10 + 12,
669 .vtotal = 768 + 10 + 12 + 6,
670 .vrefresh = 60,
671};
672
673static const struct panel_desc auo_b116xw03 = {
674 .modes = &auo_b116xw03_mode,
675 .num_modes = 1,
676 .bpc = 6,
677 .size = {
678 .width = 256,
679 .height = 144,
680 },
681};
682
683static const struct drm_display_mode auo_b133xtn01_mode = {
684 .clock = 69500,
685 .hdisplay = 1366,
686 .hsync_start = 1366 + 48,
687 .hsync_end = 1366 + 48 + 32,
688 .htotal = 1366 + 48 + 32 + 20,
689 .vdisplay = 768,
690 .vsync_start = 768 + 3,
691 .vsync_end = 768 + 3 + 6,
692 .vtotal = 768 + 3 + 6 + 13,
693 .vrefresh = 60,
694};
695
696static const struct panel_desc auo_b133xtn01 = {
697 .modes = &auo_b133xtn01_mode,
698 .num_modes = 1,
699 .bpc = 6,
700 .size = {
701 .width = 293,
702 .height = 165,
703 },
704};
705
706static const struct drm_display_mode auo_b133htn01_mode = {
707 .clock = 150660,
708 .hdisplay = 1920,
709 .hsync_start = 1920 + 172,
710 .hsync_end = 1920 + 172 + 80,
711 .htotal = 1920 + 172 + 80 + 60,
712 .vdisplay = 1080,
713 .vsync_start = 1080 + 25,
714 .vsync_end = 1080 + 25 + 10,
715 .vtotal = 1080 + 25 + 10 + 10,
716 .vrefresh = 60,
717};
718
719static const struct panel_desc auo_b133htn01 = {
720 .modes = &auo_b133htn01_mode,
721 .num_modes = 1,
722 .bpc = 6,
723 .size = {
724 .width = 293,
725 .height = 165,
726 },
727 .delay = {
728 .prepare = 105,
729 .enable = 20,
730 .unprepare = 50,
731 },
732};
733
734static const struct display_timing auo_g070vvn01_timings = {
735 .pixelclock = { 33300000, 34209000, 45000000 },
736 .hactive = { 800, 800, 800 },
737 .hfront_porch = { 20, 40, 200 },
738 .hback_porch = { 87, 40, 1 },
739 .hsync_len = { 1, 48, 87 },
740 .vactive = { 480, 480, 480 },
741 .vfront_porch = { 5, 13, 200 },
742 .vback_porch = { 31, 31, 29 },
743 .vsync_len = { 1, 1, 3 },
744};
745
746static const struct panel_desc auo_g070vvn01 = {
747 .timings = &auo_g070vvn01_timings,
748 .num_timings = 1,
749 .bpc = 8,
750 .size = {
751 .width = 152,
752 .height = 91,
753 },
754 .delay = {
755 .prepare = 200,
756 .enable = 50,
757 .disable = 50,
758 .unprepare = 1000,
759 },
760};
761
762static const struct drm_display_mode auo_g101evn010_mode = {
763 .clock = 68930,
764 .hdisplay = 1280,
765 .hsync_start = 1280 + 82,
766 .hsync_end = 1280 + 82 + 2,
767 .htotal = 1280 + 82 + 2 + 84,
768 .vdisplay = 800,
769 .vsync_start = 800 + 8,
770 .vsync_end = 800 + 8 + 2,
771 .vtotal = 800 + 8 + 2 + 6,
772 .vrefresh = 60,
773};
774
775static const struct panel_desc auo_g101evn010 = {
776 .modes = &auo_g101evn010_mode,
777 .num_modes = 1,
778 .bpc = 6,
779 .size = {
780 .width = 216,
781 .height = 135,
782 },
783 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
784};
785
786static const struct drm_display_mode auo_g104sn02_mode = {
787 .clock = 40000,
788 .hdisplay = 800,
789 .hsync_start = 800 + 40,
790 .hsync_end = 800 + 40 + 216,
791 .htotal = 800 + 40 + 216 + 128,
792 .vdisplay = 600,
793 .vsync_start = 600 + 10,
794 .vsync_end = 600 + 10 + 35,
795 .vtotal = 600 + 10 + 35 + 2,
796 .vrefresh = 60,
797};
798
799static const struct panel_desc auo_g104sn02 = {
800 .modes = &auo_g104sn02_mode,
801 .num_modes = 1,
802 .bpc = 8,
803 .size = {
804 .width = 211,
805 .height = 158,
806 },
807};
808
809static const struct display_timing auo_g133han01_timings = {
810 .pixelclock = { 134000000, 141200000, 149000000 },
811 .hactive = { 1920, 1920, 1920 },
812 .hfront_porch = { 39, 58, 77 },
813 .hback_porch = { 59, 88, 117 },
814 .hsync_len = { 28, 42, 56 },
815 .vactive = { 1080, 1080, 1080 },
816 .vfront_porch = { 3, 8, 11 },
817 .vback_porch = { 5, 14, 19 },
818 .vsync_len = { 4, 14, 19 },
819};
820
821static const struct panel_desc auo_g133han01 = {
822 .timings = &auo_g133han01_timings,
823 .num_timings = 1,
824 .bpc = 8,
825 .size = {
826 .width = 293,
827 .height = 165,
828 },
829 .delay = {
830 .prepare = 200,
831 .enable = 50,
832 .disable = 50,
833 .unprepare = 1000,
834 },
835 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
836};
837
838static const struct display_timing auo_g185han01_timings = {
839 .pixelclock = { 120000000, 144000000, 175000000 },
840 .hactive = { 1920, 1920, 1920 },
841 .hfront_porch = { 36, 120, 148 },
842 .hback_porch = { 24, 88, 108 },
843 .hsync_len = { 20, 48, 64 },
844 .vactive = { 1080, 1080, 1080 },
845 .vfront_porch = { 6, 10, 40 },
846 .vback_porch = { 2, 5, 20 },
847 .vsync_len = { 2, 5, 20 },
848};
849
850static const struct panel_desc auo_g185han01 = {
851 .timings = &auo_g185han01_timings,
852 .num_timings = 1,
853 .bpc = 8,
854 .size = {
855 .width = 409,
856 .height = 230,
857 },
858 .delay = {
859 .prepare = 50,
860 .enable = 200,
861 .disable = 110,
862 .unprepare = 1000,
863 },
864 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
865};
866
867static const struct display_timing auo_p320hvn03_timings = {
868 .pixelclock = { 106000000, 148500000, 164000000 },
869 .hactive = { 1920, 1920, 1920 },
870 .hfront_porch = { 25, 50, 130 },
871 .hback_porch = { 25, 50, 130 },
872 .hsync_len = { 20, 40, 105 },
873 .vactive = { 1080, 1080, 1080 },
874 .vfront_porch = { 8, 17, 150 },
875 .vback_porch = { 8, 17, 150 },
876 .vsync_len = { 4, 11, 100 },
877};
878
879static const struct panel_desc auo_p320hvn03 = {
880 .timings = &auo_p320hvn03_timings,
881 .num_timings = 1,
882 .bpc = 8,
883 .size = {
884 .width = 698,
885 .height = 393,
886 },
887 .delay = {
888 .prepare = 1,
889 .enable = 450,
890 .unprepare = 500,
891 },
892 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
893};
894
895static const struct drm_display_mode auo_t215hvn01_mode = {
896 .clock = 148800,
897 .hdisplay = 1920,
898 .hsync_start = 1920 + 88,
899 .hsync_end = 1920 + 88 + 44,
900 .htotal = 1920 + 88 + 44 + 148,
901 .vdisplay = 1080,
902 .vsync_start = 1080 + 4,
903 .vsync_end = 1080 + 4 + 5,
904 .vtotal = 1080 + 4 + 5 + 36,
905 .vrefresh = 60,
906};
907
908static const struct panel_desc auo_t215hvn01 = {
909 .modes = &auo_t215hvn01_mode,
910 .num_modes = 1,
911 .bpc = 8,
912 .size = {
913 .width = 430,
914 .height = 270,
915 },
916 .delay = {
917 .disable = 5,
918 .unprepare = 1000,
919 }
920};
921
922static const struct drm_display_mode avic_tm070ddh03_mode = {
923 .clock = 51200,
924 .hdisplay = 1024,
925 .hsync_start = 1024 + 160,
926 .hsync_end = 1024 + 160 + 4,
927 .htotal = 1024 + 160 + 4 + 156,
928 .vdisplay = 600,
929 .vsync_start = 600 + 17,
930 .vsync_end = 600 + 17 + 1,
931 .vtotal = 600 + 17 + 1 + 17,
932 .vrefresh = 60,
933};
934
935static const struct panel_desc avic_tm070ddh03 = {
936 .modes = &avic_tm070ddh03_mode,
937 .num_modes = 1,
938 .bpc = 8,
939 .size = {
940 .width = 154,
941 .height = 90,
942 },
943 .delay = {
944 .prepare = 20,
945 .enable = 200,
946 .disable = 200,
947 },
948};
949
950static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
951 .clock = 30000,
952 .hdisplay = 800,
953 .hsync_start = 800 + 40,
954 .hsync_end = 800 + 40 + 48,
955 .htotal = 800 + 40 + 48 + 40,
956 .vdisplay = 480,
957 .vsync_start = 480 + 13,
958 .vsync_end = 480 + 13 + 3,
959 .vtotal = 480 + 13 + 3 + 29,
960};
961
962static const struct panel_desc bananapi_s070wv20_ct16 = {
963 .modes = &bananapi_s070wv20_ct16_mode,
964 .num_modes = 1,
965 .bpc = 6,
966 .size = {
967 .width = 154,
968 .height = 86,
969 },
970};
971
972static const struct drm_display_mode boe_hv070wsa_mode = {
973 .clock = 42105,
974 .hdisplay = 1024,
975 .hsync_start = 1024 + 30,
976 .hsync_end = 1024 + 30 + 30,
977 .htotal = 1024 + 30 + 30 + 30,
978 .vdisplay = 600,
979 .vsync_start = 600 + 10,
980 .vsync_end = 600 + 10 + 10,
981 .vtotal = 600 + 10 + 10 + 10,
982 .vrefresh = 60,
983};
984
985static const struct panel_desc boe_hv070wsa = {
986 .modes = &boe_hv070wsa_mode,
987 .num_modes = 1,
988 .size = {
989 .width = 154,
990 .height = 90,
991 },
992};
993
994static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
995 {
996 .clock = 71900,
997 .hdisplay = 1280,
998 .hsync_start = 1280 + 48,
999 .hsync_end = 1280 + 48 + 32,
1000 .htotal = 1280 + 48 + 32 + 80,
1001 .vdisplay = 800,
1002 .vsync_start = 800 + 3,
1003 .vsync_end = 800 + 3 + 5,
1004 .vtotal = 800 + 3 + 5 + 24,
1005 .vrefresh = 60,
1006 },
1007 {
1008 .clock = 57500,
1009 .hdisplay = 1280,
1010 .hsync_start = 1280 + 48,
1011 .hsync_end = 1280 + 48 + 32,
1012 .htotal = 1280 + 48 + 32 + 80,
1013 .vdisplay = 800,
1014 .vsync_start = 800 + 3,
1015 .vsync_end = 800 + 3 + 5,
1016 .vtotal = 800 + 3 + 5 + 24,
1017 .vrefresh = 48,
1018 },
1019};
1020
1021static const struct panel_desc boe_nv101wxmn51 = {
1022 .modes = boe_nv101wxmn51_modes,
1023 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
1024 .bpc = 8,
1025 .size = {
1026 .width = 217,
1027 .height = 136,
1028 },
1029 .delay = {
1030 .prepare = 210,
1031 .enable = 50,
1032 .unprepare = 160,
1033 },
1034};
1035
1036static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1037 .clock = 9000,
1038 .hdisplay = 480,
1039 .hsync_start = 480 + 5,
1040 .hsync_end = 480 + 5 + 5,
1041 .htotal = 480 + 5 + 5 + 40,
1042 .vdisplay = 272,
1043 .vsync_start = 272 + 8,
1044 .vsync_end = 272 + 8 + 8,
1045 .vtotal = 272 + 8 + 8 + 8,
1046 .vrefresh = 60,
1047 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1048};
1049
1050static const struct panel_desc cdtech_s043wq26h_ct7 = {
1051 .modes = &cdtech_s043wq26h_ct7_mode,
1052 .num_modes = 1,
1053 .bpc = 8,
1054 .size = {
1055 .width = 95,
1056 .height = 54,
1057 },
1058 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1059};
1060
1061static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1062 .clock = 35000,
1063 .hdisplay = 800,
1064 .hsync_start = 800 + 40,
1065 .hsync_end = 800 + 40 + 40,
1066 .htotal = 800 + 40 + 40 + 48,
1067 .vdisplay = 480,
1068 .vsync_start = 480 + 29,
1069 .vsync_end = 480 + 29 + 13,
1070 .vtotal = 480 + 29 + 13 + 3,
1071 .vrefresh = 60,
1072 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1073};
1074
1075static const struct panel_desc cdtech_s070wv95_ct16 = {
1076 .modes = &cdtech_s070wv95_ct16_mode,
1077 .num_modes = 1,
1078 .bpc = 8,
1079 .size = {
1080 .width = 154,
1081 .height = 85,
1082 },
1083};
1084
1085static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1086 .clock = 66770,
1087 .hdisplay = 800,
1088 .hsync_start = 800 + 49,
1089 .hsync_end = 800 + 49 + 33,
1090 .htotal = 800 + 49 + 33 + 17,
1091 .vdisplay = 1280,
1092 .vsync_start = 1280 + 1,
1093 .vsync_end = 1280 + 1 + 7,
1094 .vtotal = 1280 + 1 + 7 + 15,
1095 .vrefresh = 60,
1096 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1097};
1098
1099static const struct panel_desc chunghwa_claa070wp03xg = {
1100 .modes = &chunghwa_claa070wp03xg_mode,
1101 .num_modes = 1,
1102 .bpc = 6,
1103 .size = {
1104 .width = 94,
1105 .height = 150,
1106 },
1107};
1108
1109static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1110 .clock = 72070,
1111 .hdisplay = 1366,
1112 .hsync_start = 1366 + 58,
1113 .hsync_end = 1366 + 58 + 58,
1114 .htotal = 1366 + 58 + 58 + 58,
1115 .vdisplay = 768,
1116 .vsync_start = 768 + 4,
1117 .vsync_end = 768 + 4 + 4,
1118 .vtotal = 768 + 4 + 4 + 4,
1119 .vrefresh = 60,
1120};
1121
1122static const struct panel_desc chunghwa_claa101wa01a = {
1123 .modes = &chunghwa_claa101wa01a_mode,
1124 .num_modes = 1,
1125 .bpc = 6,
1126 .size = {
1127 .width = 220,
1128 .height = 120,
1129 },
1130};
1131
1132static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1133 .clock = 69300,
1134 .hdisplay = 1366,
1135 .hsync_start = 1366 + 48,
1136 .hsync_end = 1366 + 48 + 32,
1137 .htotal = 1366 + 48 + 32 + 20,
1138 .vdisplay = 768,
1139 .vsync_start = 768 + 16,
1140 .vsync_end = 768 + 16 + 8,
1141 .vtotal = 768 + 16 + 8 + 16,
1142 .vrefresh = 60,
1143};
1144
1145static const struct panel_desc chunghwa_claa101wb01 = {
1146 .modes = &chunghwa_claa101wb01_mode,
1147 .num_modes = 1,
1148 .bpc = 6,
1149 .size = {
1150 .width = 223,
1151 .height = 125,
1152 },
1153};
1154
1155static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1156 .clock = 33260,
1157 .hdisplay = 800,
1158 .hsync_start = 800 + 40,
1159 .hsync_end = 800 + 40 + 128,
1160 .htotal = 800 + 40 + 128 + 88,
1161 .vdisplay = 480,
1162 .vsync_start = 480 + 10,
1163 .vsync_end = 480 + 10 + 2,
1164 .vtotal = 480 + 10 + 2 + 33,
1165 .vrefresh = 60,
1166 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1167};
1168
1169static const struct panel_desc dataimage_scf0700c48ggu18 = {
1170 .modes = &dataimage_scf0700c48ggu18_mode,
1171 .num_modes = 1,
1172 .bpc = 8,
1173 .size = {
1174 .width = 152,
1175 .height = 91,
1176 },
1177 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1178 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1179};
1180
1181static const struct display_timing dlc_dlc0700yzg_1_timing = {
1182 .pixelclock = { 45000000, 51200000, 57000000 },
1183 .hactive = { 1024, 1024, 1024 },
1184 .hfront_porch = { 100, 106, 113 },
1185 .hback_porch = { 100, 106, 113 },
1186 .hsync_len = { 100, 108, 114 },
1187 .vactive = { 600, 600, 600 },
1188 .vfront_porch = { 8, 11, 15 },
1189 .vback_porch = { 8, 11, 15 },
1190 .vsync_len = { 9, 13, 15 },
1191 .flags = DISPLAY_FLAGS_DE_HIGH,
1192};
1193
1194static const struct panel_desc dlc_dlc0700yzg_1 = {
1195 .timings = &dlc_dlc0700yzg_1_timing,
1196 .num_timings = 1,
1197 .bpc = 6,
1198 .size = {
1199 .width = 154,
1200 .height = 86,
1201 },
1202 .delay = {
1203 .prepare = 30,
1204 .enable = 200,
1205 .disable = 200,
1206 },
1207 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1208};
1209
1210static const struct display_timing dlc_dlc1010gig_timing = {
1211 .pixelclock = { 68900000, 71100000, 73400000 },
1212 .hactive = { 1280, 1280, 1280 },
1213 .hfront_porch = { 43, 53, 63 },
1214 .hback_porch = { 43, 53, 63 },
1215 .hsync_len = { 44, 54, 64 },
1216 .vactive = { 800, 800, 800 },
1217 .vfront_porch = { 5, 8, 11 },
1218 .vback_porch = { 5, 8, 11 },
1219 .vsync_len = { 5, 7, 11 },
1220 .flags = DISPLAY_FLAGS_DE_HIGH,
1221};
1222
1223static const struct panel_desc dlc_dlc1010gig = {
1224 .timings = &dlc_dlc1010gig_timing,
1225 .num_timings = 1,
1226 .bpc = 8,
1227 .size = {
1228 .width = 216,
1229 .height = 135,
1230 },
1231 .delay = {
1232 .prepare = 60,
1233 .enable = 150,
1234 .disable = 100,
1235 .unprepare = 60,
1236 },
1237 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1238};
1239
1240static const struct drm_display_mode edt_et035012dm6_mode = {
1241 .clock = 6500,
1242 .hdisplay = 320,
1243 .hsync_start = 320 + 20,
1244 .hsync_end = 320 + 20 + 30,
1245 .htotal = 320 + 20 + 68,
1246 .vdisplay = 240,
1247 .vsync_start = 240 + 4,
1248 .vsync_end = 240 + 4 + 4,
1249 .vtotal = 240 + 4 + 4 + 14,
1250 .vrefresh = 60,
1251 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1252};
1253
1254static const struct panel_desc edt_et035012dm6 = {
1255 .modes = &edt_et035012dm6_mode,
1256 .num_modes = 1,
1257 .bpc = 8,
1258 .size = {
1259 .width = 70,
1260 .height = 52,
1261 },
1262 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1263 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1264};
1265
1266static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1267 .clock = 9000,
1268 .hdisplay = 480,
1269 .hsync_start = 480 + 2,
1270 .hsync_end = 480 + 2 + 41,
1271 .htotal = 480 + 2 + 41 + 2,
1272 .vdisplay = 272,
1273 .vsync_start = 272 + 2,
1274 .vsync_end = 272 + 2 + 10,
1275 .vtotal = 272 + 2 + 10 + 2,
1276 .vrefresh = 60,
1277 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1278};
1279
1280static const struct panel_desc edt_etm0430g0dh6 = {
1281 .modes = &edt_etm0430g0dh6_mode,
1282 .num_modes = 1,
1283 .bpc = 6,
1284 .size = {
1285 .width = 95,
1286 .height = 54,
1287 },
1288};
1289
1290static const struct drm_display_mode edt_et057090dhu_mode = {
1291 .clock = 25175,
1292 .hdisplay = 640,
1293 .hsync_start = 640 + 16,
1294 .hsync_end = 640 + 16 + 30,
1295 .htotal = 640 + 16 + 30 + 114,
1296 .vdisplay = 480,
1297 .vsync_start = 480 + 10,
1298 .vsync_end = 480 + 10 + 3,
1299 .vtotal = 480 + 10 + 3 + 32,
1300 .vrefresh = 60,
1301 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1302};
1303
1304static const struct panel_desc edt_et057090dhu = {
1305 .modes = &edt_et057090dhu_mode,
1306 .num_modes = 1,
1307 .bpc = 6,
1308 .size = {
1309 .width = 115,
1310 .height = 86,
1311 },
1312 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1313 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1314};
1315
1316static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1317 .clock = 33260,
1318 .hdisplay = 800,
1319 .hsync_start = 800 + 40,
1320 .hsync_end = 800 + 40 + 128,
1321 .htotal = 800 + 40 + 128 + 88,
1322 .vdisplay = 480,
1323 .vsync_start = 480 + 10,
1324 .vsync_end = 480 + 10 + 2,
1325 .vtotal = 480 + 10 + 2 + 33,
1326 .vrefresh = 60,
1327 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1328};
1329
1330static const struct panel_desc edt_etm0700g0dh6 = {
1331 .modes = &edt_etm0700g0dh6_mode,
1332 .num_modes = 1,
1333 .bpc = 6,
1334 .size = {
1335 .width = 152,
1336 .height = 91,
1337 },
1338 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1339 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1340};
1341
1342static const struct panel_desc edt_etm0700g0bdh6 = {
1343 .modes = &edt_etm0700g0dh6_mode,
1344 .num_modes = 1,
1345 .bpc = 6,
1346 .size = {
1347 .width = 152,
1348 .height = 91,
1349 },
1350 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1351 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1352};
1353
1354static const struct display_timing evervision_vgg804821_timing = {
1355 .pixelclock = { 27600000, 33300000, 50000000 },
1356 .hactive = { 800, 800, 800 },
1357 .hfront_porch = { 40, 66, 70 },
1358 .hback_porch = { 40, 67, 70 },
1359 .hsync_len = { 40, 67, 70 },
1360 .vactive = { 480, 480, 480 },
1361 .vfront_porch = { 6, 10, 10 },
1362 .vback_porch = { 7, 11, 11 },
1363 .vsync_len = { 7, 11, 11 },
1364 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1365 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1366 DISPLAY_FLAGS_SYNC_NEGEDGE,
1367};
1368
1369static const struct panel_desc evervision_vgg804821 = {
1370 .timings = &evervision_vgg804821_timing,
1371 .num_timings = 1,
1372 .bpc = 8,
1373 .size = {
1374 .width = 108,
1375 .height = 64,
1376 },
1377 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1378 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1379};
1380
1381static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1382 .clock = 32260,
1383 .hdisplay = 800,
1384 .hsync_start = 800 + 168,
1385 .hsync_end = 800 + 168 + 64,
1386 .htotal = 800 + 168 + 64 + 88,
1387 .vdisplay = 480,
1388 .vsync_start = 480 + 37,
1389 .vsync_end = 480 + 37 + 2,
1390 .vtotal = 480 + 37 + 2 + 8,
1391 .vrefresh = 60,
1392};
1393
1394static const struct panel_desc foxlink_fl500wvr00_a0t = {
1395 .modes = &foxlink_fl500wvr00_a0t_mode,
1396 .num_modes = 1,
1397 .bpc = 8,
1398 .size = {
1399 .width = 108,
1400 .height = 65,
1401 },
1402 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1403};
1404
1405static const struct drm_display_mode friendlyarm_hd702e_mode = {
1406 .clock = 67185,
1407 .hdisplay = 800,
1408 .hsync_start = 800 + 20,
1409 .hsync_end = 800 + 20 + 24,
1410 .htotal = 800 + 20 + 24 + 20,
1411 .vdisplay = 1280,
1412 .vsync_start = 1280 + 4,
1413 .vsync_end = 1280 + 4 + 8,
1414 .vtotal = 1280 + 4 + 8 + 4,
1415 .vrefresh = 60,
1416 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1417};
1418
1419static const struct panel_desc friendlyarm_hd702e = {
1420 .modes = &friendlyarm_hd702e_mode,
1421 .num_modes = 1,
1422 .size = {
1423 .width = 94,
1424 .height = 151,
1425 },
1426};
1427
1428static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1429 .clock = 9000,
1430 .hdisplay = 480,
1431 .hsync_start = 480 + 5,
1432 .hsync_end = 480 + 5 + 1,
1433 .htotal = 480 + 5 + 1 + 40,
1434 .vdisplay = 272,
1435 .vsync_start = 272 + 8,
1436 .vsync_end = 272 + 8 + 1,
1437 .vtotal = 272 + 8 + 1 + 8,
1438 .vrefresh = 60,
1439};
1440
1441static const struct panel_desc giantplus_gpg482739qs5 = {
1442 .modes = &giantplus_gpg482739qs5_mode,
1443 .num_modes = 1,
1444 .bpc = 8,
1445 .size = {
1446 .width = 95,
1447 .height = 54,
1448 },
1449 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1450};
1451
1452static const struct display_timing giantplus_gpm940b0_timing = {
1453 .pixelclock = { 13500000, 27000000, 27500000 },
1454 .hactive = { 320, 320, 320 },
1455 .hfront_porch = { 14, 686, 718 },
1456 .hback_porch = { 50, 70, 255 },
1457 .hsync_len = { 1, 1, 1 },
1458 .vactive = { 240, 240, 240 },
1459 .vfront_porch = { 1, 1, 179 },
1460 .vback_porch = { 1, 21, 31 },
1461 .vsync_len = { 1, 1, 6 },
1462 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1463};
1464
1465static const struct panel_desc giantplus_gpm940b0 = {
1466 .timings = &giantplus_gpm940b0_timing,
1467 .num_timings = 1,
1468 .bpc = 8,
1469 .size = {
1470 .width = 60,
1471 .height = 45,
1472 },
1473 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
1474 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1475};
1476
1477static const struct display_timing hannstar_hsd070pww1_timing = {
1478 .pixelclock = { 64300000, 71100000, 82000000 },
1479 .hactive = { 1280, 1280, 1280 },
1480 .hfront_porch = { 1, 1, 10 },
1481 .hback_porch = { 1, 1, 10 },
1482 /*
1483 * According to the data sheet, the minimum horizontal blanking interval
1484 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1485 * minimum working horizontal blanking interval to be 60 clocks.
1486 */
1487 .hsync_len = { 58, 158, 661 },
1488 .vactive = { 800, 800, 800 },
1489 .vfront_porch = { 1, 1, 10 },
1490 .vback_porch = { 1, 1, 10 },
1491 .vsync_len = { 1, 21, 203 },
1492 .flags = DISPLAY_FLAGS_DE_HIGH,
1493};
1494
1495static const struct panel_desc hannstar_hsd070pww1 = {
1496 .timings = &hannstar_hsd070pww1_timing,
1497 .num_timings = 1,
1498 .bpc = 6,
1499 .size = {
1500 .width = 151,
1501 .height = 94,
1502 },
1503 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1504};
1505
1506static const struct display_timing hannstar_hsd100pxn1_timing = {
1507 .pixelclock = { 55000000, 65000000, 75000000 },
1508 .hactive = { 1024, 1024, 1024 },
1509 .hfront_porch = { 40, 40, 40 },
1510 .hback_porch = { 220, 220, 220 },
1511 .hsync_len = { 20, 60, 100 },
1512 .vactive = { 768, 768, 768 },
1513 .vfront_porch = { 7, 7, 7 },
1514 .vback_porch = { 21, 21, 21 },
1515 .vsync_len = { 10, 10, 10 },
1516 .flags = DISPLAY_FLAGS_DE_HIGH,
1517};
1518
1519static const struct panel_desc hannstar_hsd100pxn1 = {
1520 .timings = &hannstar_hsd100pxn1_timing,
1521 .num_timings = 1,
1522 .bpc = 6,
1523 .size = {
1524 .width = 203,
1525 .height = 152,
1526 },
1527 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1528};
1529
1530static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1531 .clock = 33333,
1532 .hdisplay = 800,
1533 .hsync_start = 800 + 85,
1534 .hsync_end = 800 + 85 + 86,
1535 .htotal = 800 + 85 + 86 + 85,
1536 .vdisplay = 480,
1537 .vsync_start = 480 + 16,
1538 .vsync_end = 480 + 16 + 13,
1539 .vtotal = 480 + 16 + 13 + 16,
1540 .vrefresh = 60,
1541};
1542
1543static const struct panel_desc hitachi_tx23d38vm0caa = {
1544 .modes = &hitachi_tx23d38vm0caa_mode,
1545 .num_modes = 1,
1546 .bpc = 6,
1547 .size = {
1548 .width = 195,
1549 .height = 117,
1550 },
1551 .delay = {
1552 .enable = 160,
1553 .disable = 160,
1554 },
1555};
1556
1557static const struct drm_display_mode innolux_at043tn24_mode = {
1558 .clock = 9000,
1559 .hdisplay = 480,
1560 .hsync_start = 480 + 2,
1561 .hsync_end = 480 + 2 + 41,
1562 .htotal = 480 + 2 + 41 + 2,
1563 .vdisplay = 272,
1564 .vsync_start = 272 + 2,
1565 .vsync_end = 272 + 2 + 10,
1566 .vtotal = 272 + 2 + 10 + 2,
1567 .vrefresh = 60,
1568 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1569};
1570
1571static const struct panel_desc innolux_at043tn24 = {
1572 .modes = &innolux_at043tn24_mode,
1573 .num_modes = 1,
1574 .bpc = 8,
1575 .size = {
1576 .width = 95,
1577 .height = 54,
1578 },
1579 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1580 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1581};
1582
1583static const struct drm_display_mode innolux_at070tn92_mode = {
1584 .clock = 33333,
1585 .hdisplay = 800,
1586 .hsync_start = 800 + 210,
1587 .hsync_end = 800 + 210 + 20,
1588 .htotal = 800 + 210 + 20 + 46,
1589 .vdisplay = 480,
1590 .vsync_start = 480 + 22,
1591 .vsync_end = 480 + 22 + 10,
1592 .vtotal = 480 + 22 + 23 + 10,
1593 .vrefresh = 60,
1594};
1595
1596static const struct panel_desc innolux_at070tn92 = {
1597 .modes = &innolux_at070tn92_mode,
1598 .num_modes = 1,
1599 .size = {
1600 .width = 154,
1601 .height = 86,
1602 },
1603 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1604};
1605
1606static const struct display_timing innolux_g070y2_l01_timing = {
1607 .pixelclock = { 28000000, 29500000, 32000000 },
1608 .hactive = { 800, 800, 800 },
1609 .hfront_porch = { 61, 91, 141 },
1610 .hback_porch = { 60, 90, 140 },
1611 .hsync_len = { 12, 12, 12 },
1612 .vactive = { 480, 480, 480 },
1613 .vfront_porch = { 4, 9, 30 },
1614 .vback_porch = { 4, 8, 28 },
1615 .vsync_len = { 2, 2, 2 },
1616 .flags = DISPLAY_FLAGS_DE_HIGH,
1617};
1618
1619static const struct panel_desc innolux_g070y2_l01 = {
1620 .timings = &innolux_g070y2_l01_timing,
1621 .num_timings = 1,
1622 .bpc = 6,
1623 .size = {
1624 .width = 152,
1625 .height = 91,
1626 },
1627 .delay = {
1628 .prepare = 10,
1629 .enable = 100,
1630 .disable = 100,
1631 .unprepare = 800,
1632 },
1633 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1634};
1635
1636static const struct display_timing innolux_g101ice_l01_timing = {
1637 .pixelclock = { 60400000, 71100000, 74700000 },
1638 .hactive = { 1280, 1280, 1280 },
1639 .hfront_porch = { 41, 80, 100 },
1640 .hback_porch = { 40, 79, 99 },
1641 .hsync_len = { 1, 1, 1 },
1642 .vactive = { 800, 800, 800 },
1643 .vfront_porch = { 5, 11, 14 },
1644 .vback_porch = { 4, 11, 14 },
1645 .vsync_len = { 1, 1, 1 },
1646 .flags = DISPLAY_FLAGS_DE_HIGH,
1647};
1648
1649static const struct panel_desc innolux_g101ice_l01 = {
1650 .timings = &innolux_g101ice_l01_timing,
1651 .num_timings = 1,
1652 .bpc = 8,
1653 .size = {
1654 .width = 217,
1655 .height = 135,
1656 },
1657 .delay = {
1658 .enable = 200,
1659 .disable = 200,
1660 },
1661 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1662};
1663
1664static const struct display_timing innolux_g121i1_l01_timing = {
1665 .pixelclock = { 67450000, 71000000, 74550000 },
1666 .hactive = { 1280, 1280, 1280 },
1667 .hfront_porch = { 40, 80, 160 },
1668 .hback_porch = { 39, 79, 159 },
1669 .hsync_len = { 1, 1, 1 },
1670 .vactive = { 800, 800, 800 },
1671 .vfront_porch = { 5, 11, 100 },
1672 .vback_porch = { 4, 11, 99 },
1673 .vsync_len = { 1, 1, 1 },
1674};
1675
1676static const struct panel_desc innolux_g121i1_l01 = {
1677 .timings = &innolux_g121i1_l01_timing,
1678 .num_timings = 1,
1679 .bpc = 6,
1680 .size = {
1681 .width = 261,
1682 .height = 163,
1683 },
1684 .delay = {
1685 .enable = 200,
1686 .disable = 20,
1687 },
1688 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1689};
1690
1691static const struct drm_display_mode innolux_g121x1_l03_mode = {
1692 .clock = 65000,
1693 .hdisplay = 1024,
1694 .hsync_start = 1024 + 0,
1695 .hsync_end = 1024 + 1,
1696 .htotal = 1024 + 0 + 1 + 320,
1697 .vdisplay = 768,
1698 .vsync_start = 768 + 38,
1699 .vsync_end = 768 + 38 + 1,
1700 .vtotal = 768 + 38 + 1 + 0,
1701 .vrefresh = 60,
1702 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1703};
1704
1705static const struct panel_desc innolux_g121x1_l03 = {
1706 .modes = &innolux_g121x1_l03_mode,
1707 .num_modes = 1,
1708 .bpc = 6,
1709 .size = {
1710 .width = 246,
1711 .height = 185,
1712 },
1713 .delay = {
1714 .enable = 200,
1715 .unprepare = 200,
1716 .disable = 400,
1717 },
1718};
1719
1720/*
1721 * Datasheet specifies that at 60 Hz refresh rate:
1722 * - total horizontal time: { 1506, 1592, 1716 }
1723 * - total vertical time: { 788, 800, 868 }
1724 *
1725 * ...but doesn't go into exactly how that should be split into a front
1726 * porch, back porch, or sync length. For now we'll leave a single setting
1727 * here which allows a bit of tweaking of the pixel clock at the expense of
1728 * refresh rate.
1729 */
1730static const struct display_timing innolux_n116bge_timing = {
1731 .pixelclock = { 72600000, 76420000, 80240000 },
1732 .hactive = { 1366, 1366, 1366 },
1733 .hfront_porch = { 136, 136, 136 },
1734 .hback_porch = { 60, 60, 60 },
1735 .hsync_len = { 30, 30, 30 },
1736 .vactive = { 768, 768, 768 },
1737 .vfront_porch = { 8, 8, 8 },
1738 .vback_porch = { 12, 12, 12 },
1739 .vsync_len = { 12, 12, 12 },
1740 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
1741};
1742
1743static const struct panel_desc innolux_n116bge = {
1744 .timings = &innolux_n116bge_timing,
1745 .num_timings = 1,
1746 .bpc = 6,
1747 .size = {
1748 .width = 256,
1749 .height = 144,
1750 },
1751};
1752
1753static const struct drm_display_mode innolux_n156bge_l21_mode = {
1754 .clock = 69300,
1755 .hdisplay = 1366,
1756 .hsync_start = 1366 + 16,
1757 .hsync_end = 1366 + 16 + 34,
1758 .htotal = 1366 + 16 + 34 + 50,
1759 .vdisplay = 768,
1760 .vsync_start = 768 + 2,
1761 .vsync_end = 768 + 2 + 6,
1762 .vtotal = 768 + 2 + 6 + 12,
1763 .vrefresh = 60,
1764};
1765
1766static const struct panel_desc innolux_n156bge_l21 = {
1767 .modes = &innolux_n156bge_l21_mode,
1768 .num_modes = 1,
1769 .bpc = 6,
1770 .size = {
1771 .width = 344,
1772 .height = 193,
1773 },
1774};
1775
1776static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
1777 .clock = 206016,
1778 .hdisplay = 2160,
1779 .hsync_start = 2160 + 48,
1780 .hsync_end = 2160 + 48 + 32,
1781 .htotal = 2160 + 48 + 32 + 80,
1782 .vdisplay = 1440,
1783 .vsync_start = 1440 + 3,
1784 .vsync_end = 1440 + 3 + 10,
1785 .vtotal = 1440 + 3 + 10 + 27,
1786 .vrefresh = 60,
1787 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
1788};
1789
1790static const struct panel_desc innolux_p120zdg_bf1 = {
1791 .modes = &innolux_p120zdg_bf1_mode,
1792 .num_modes = 1,
1793 .bpc = 8,
1794 .size = {
1795 .width = 254,
1796 .height = 169,
1797 },
1798 .delay = {
1799 .hpd_absent_delay = 200,
1800 .unprepare = 500,
1801 },
1802};
1803
1804static const struct drm_display_mode innolux_zj070na_01p_mode = {
1805 .clock = 51501,
1806 .hdisplay = 1024,
1807 .hsync_start = 1024 + 128,
1808 .hsync_end = 1024 + 128 + 64,
1809 .htotal = 1024 + 128 + 64 + 128,
1810 .vdisplay = 600,
1811 .vsync_start = 600 + 16,
1812 .vsync_end = 600 + 16 + 4,
1813 .vtotal = 600 + 16 + 4 + 16,
1814 .vrefresh = 60,
1815};
1816
1817static const struct panel_desc innolux_zj070na_01p = {
1818 .modes = &innolux_zj070na_01p_mode,
1819 .num_modes = 1,
1820 .bpc = 6,
1821 .size = {
1822 .width = 154,
1823 .height = 90,
1824 },
1825};
1826
1827static const struct display_timing koe_tx14d24vm1bpa_timing = {
1828 .pixelclock = { 5580000, 5850000, 6200000 },
1829 .hactive = { 320, 320, 320 },
1830 .hfront_porch = { 30, 30, 30 },
1831 .hback_porch = { 30, 30, 30 },
1832 .hsync_len = { 1, 5, 17 },
1833 .vactive = { 240, 240, 240 },
1834 .vfront_porch = { 6, 6, 6 },
1835 .vback_porch = { 5, 5, 5 },
1836 .vsync_len = { 1, 2, 11 },
1837 .flags = DISPLAY_FLAGS_DE_HIGH,
1838};
1839
1840static const struct panel_desc koe_tx14d24vm1bpa = {
1841 .timings = &koe_tx14d24vm1bpa_timing,
1842 .num_timings = 1,
1843 .bpc = 6,
1844 .size = {
1845 .width = 115,
1846 .height = 86,
1847 },
1848};
1849
1850static const struct display_timing koe_tx31d200vm0baa_timing = {
1851 .pixelclock = { 39600000, 43200000, 48000000 },
1852 .hactive = { 1280, 1280, 1280 },
1853 .hfront_porch = { 16, 36, 56 },
1854 .hback_porch = { 16, 36, 56 },
1855 .hsync_len = { 8, 8, 8 },
1856 .vactive = { 480, 480, 480 },
1857 .vfront_porch = { 6, 21, 33 },
1858 .vback_porch = { 6, 21, 33 },
1859 .vsync_len = { 8, 8, 8 },
1860 .flags = DISPLAY_FLAGS_DE_HIGH,
1861};
1862
1863static const struct panel_desc koe_tx31d200vm0baa = {
1864 .timings = &koe_tx31d200vm0baa_timing,
1865 .num_timings = 1,
1866 .bpc = 6,
1867 .size = {
1868 .width = 292,
1869 .height = 109,
1870 },
1871 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1872};
1873
1874static const struct display_timing kyo_tcg121xglp_timing = {
1875 .pixelclock = { 52000000, 65000000, 71000000 },
1876 .hactive = { 1024, 1024, 1024 },
1877 .hfront_porch = { 2, 2, 2 },
1878 .hback_porch = { 2, 2, 2 },
1879 .hsync_len = { 86, 124, 244 },
1880 .vactive = { 768, 768, 768 },
1881 .vfront_porch = { 2, 2, 2 },
1882 .vback_porch = { 2, 2, 2 },
1883 .vsync_len = { 6, 34, 73 },
1884 .flags = DISPLAY_FLAGS_DE_HIGH,
1885};
1886
1887static const struct panel_desc kyo_tcg121xglp = {
1888 .timings = &kyo_tcg121xglp_timing,
1889 .num_timings = 1,
1890 .bpc = 8,
1891 .size = {
1892 .width = 246,
1893 .height = 184,
1894 },
1895 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1896};
1897
1898static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
1899 .clock = 7000,
1900 .hdisplay = 320,
1901 .hsync_start = 320 + 20,
1902 .hsync_end = 320 + 20 + 30,
1903 .htotal = 320 + 20 + 30 + 38,
1904 .vdisplay = 240,
1905 .vsync_start = 240 + 4,
1906 .vsync_end = 240 + 4 + 3,
1907 .vtotal = 240 + 4 + 3 + 15,
1908 .vrefresh = 60,
1909};
1910
1911static const struct panel_desc lemaker_bl035_rgb_002 = {
1912 .modes = &lemaker_bl035_rgb_002_mode,
1913 .num_modes = 1,
1914 .size = {
1915 .width = 70,
1916 .height = 52,
1917 },
1918 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1919 .bus_flags = DRM_BUS_FLAG_DE_LOW,
1920};
1921
1922static const struct drm_display_mode lg_lb070wv8_mode = {
1923 .clock = 33246,
1924 .hdisplay = 800,
1925 .hsync_start = 800 + 88,
1926 .hsync_end = 800 + 88 + 80,
1927 .htotal = 800 + 88 + 80 + 88,
1928 .vdisplay = 480,
1929 .vsync_start = 480 + 10,
1930 .vsync_end = 480 + 10 + 25,
1931 .vtotal = 480 + 10 + 25 + 10,
1932 .vrefresh = 60,
1933};
1934
1935static const struct panel_desc lg_lb070wv8 = {
1936 .modes = &lg_lb070wv8_mode,
1937 .num_modes = 1,
1938 .bpc = 16,
1939 .size = {
1940 .width = 151,
1941 .height = 91,
1942 },
1943 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1944};
1945
1946static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1947 .clock = 200000,
1948 .hdisplay = 1536,
1949 .hsync_start = 1536 + 12,
1950 .hsync_end = 1536 + 12 + 16,
1951 .htotal = 1536 + 12 + 16 + 48,
1952 .vdisplay = 2048,
1953 .vsync_start = 2048 + 8,
1954 .vsync_end = 2048 + 8 + 4,
1955 .vtotal = 2048 + 8 + 4 + 8,
1956 .vrefresh = 60,
1957 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1958};
1959
1960static const struct panel_desc lg_lp079qx1_sp0v = {
1961 .modes = &lg_lp079qx1_sp0v_mode,
1962 .num_modes = 1,
1963 .size = {
1964 .width = 129,
1965 .height = 171,
1966 },
1967};
1968
1969static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1970 .clock = 205210,
1971 .hdisplay = 2048,
1972 .hsync_start = 2048 + 150,
1973 .hsync_end = 2048 + 150 + 5,
1974 .htotal = 2048 + 150 + 5 + 5,
1975 .vdisplay = 1536,
1976 .vsync_start = 1536 + 3,
1977 .vsync_end = 1536 + 3 + 1,
1978 .vtotal = 1536 + 3 + 1 + 9,
1979 .vrefresh = 60,
1980};
1981
1982static const struct panel_desc lg_lp097qx1_spa1 = {
1983 .modes = &lg_lp097qx1_spa1_mode,
1984 .num_modes = 1,
1985 .size = {
1986 .width = 208,
1987 .height = 147,
1988 },
1989};
1990
1991static const struct drm_display_mode lg_lp120up1_mode = {
1992 .clock = 162300,
1993 .hdisplay = 1920,
1994 .hsync_start = 1920 + 40,
1995 .hsync_end = 1920 + 40 + 40,
1996 .htotal = 1920 + 40 + 40+ 80,
1997 .vdisplay = 1280,
1998 .vsync_start = 1280 + 4,
1999 .vsync_end = 1280 + 4 + 4,
2000 .vtotal = 1280 + 4 + 4 + 12,
2001 .vrefresh = 60,
2002};
2003
2004static const struct panel_desc lg_lp120up1 = {
2005 .modes = &lg_lp120up1_mode,
2006 .num_modes = 1,
2007 .bpc = 8,
2008 .size = {
2009 .width = 267,
2010 .height = 183,
2011 },
2012};
2013
2014static const struct drm_display_mode lg_lp129qe_mode = {
2015 .clock = 285250,
2016 .hdisplay = 2560,
2017 .hsync_start = 2560 + 48,
2018 .hsync_end = 2560 + 48 + 32,
2019 .htotal = 2560 + 48 + 32 + 80,
2020 .vdisplay = 1700,
2021 .vsync_start = 1700 + 3,
2022 .vsync_end = 1700 + 3 + 10,
2023 .vtotal = 1700 + 3 + 10 + 36,
2024 .vrefresh = 60,
2025};
2026
2027static const struct panel_desc lg_lp129qe = {
2028 .modes = &lg_lp129qe_mode,
2029 .num_modes = 1,
2030 .bpc = 8,
2031 .size = {
2032 .width = 272,
2033 .height = 181,
2034 },
2035};
2036
2037static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2038 .clock = 30400,
2039 .hdisplay = 800,
2040 .hsync_start = 800 + 0,
2041 .hsync_end = 800 + 1,
2042 .htotal = 800 + 0 + 1 + 160,
2043 .vdisplay = 480,
2044 .vsync_start = 480 + 0,
2045 .vsync_end = 480 + 48 + 1,
2046 .vtotal = 480 + 48 + 1 + 0,
2047 .vrefresh = 60,
2048 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2049};
2050
2051static const struct panel_desc mitsubishi_aa070mc01 = {
2052 .modes = &mitsubishi_aa070mc01_mode,
2053 .num_modes = 1,
2054 .bpc = 8,
2055 .size = {
2056 .width = 152,
2057 .height = 91,
2058 },
2059
2060 .delay = {
2061 .enable = 200,
2062 .unprepare = 200,
2063 .disable = 400,
2064 },
2065 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2066 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2067};
2068
2069static const struct display_timing nec_nl12880bc20_05_timing = {
2070 .pixelclock = { 67000000, 71000000, 75000000 },
2071 .hactive = { 1280, 1280, 1280 },
2072 .hfront_porch = { 2, 30, 30 },
2073 .hback_porch = { 6, 100, 100 },
2074 .hsync_len = { 2, 30, 30 },
2075 .vactive = { 800, 800, 800 },
2076 .vfront_porch = { 5, 5, 5 },
2077 .vback_porch = { 11, 11, 11 },
2078 .vsync_len = { 7, 7, 7 },
2079};
2080
2081static const struct panel_desc nec_nl12880bc20_05 = {
2082 .timings = &nec_nl12880bc20_05_timing,
2083 .num_timings = 1,
2084 .bpc = 8,
2085 .size = {
2086 .width = 261,
2087 .height = 163,
2088 },
2089 .delay = {
2090 .enable = 50,
2091 .disable = 50,
2092 },
2093 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2094};
2095
2096static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2097 .clock = 10870,
2098 .hdisplay = 480,
2099 .hsync_start = 480 + 2,
2100 .hsync_end = 480 + 2 + 41,
2101 .htotal = 480 + 2 + 41 + 2,
2102 .vdisplay = 272,
2103 .vsync_start = 272 + 2,
2104 .vsync_end = 272 + 2 + 4,
2105 .vtotal = 272 + 2 + 4 + 2,
2106 .vrefresh = 74,
2107 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2108};
2109
2110static const struct panel_desc nec_nl4827hc19_05b = {
2111 .modes = &nec_nl4827hc19_05b_mode,
2112 .num_modes = 1,
2113 .bpc = 8,
2114 .size = {
2115 .width = 95,
2116 .height = 54,
2117 },
2118 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2119 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2120};
2121
2122static const struct drm_display_mode netron_dy_e231732_mode = {
2123 .clock = 66000,
2124 .hdisplay = 1024,
2125 .hsync_start = 1024 + 160,
2126 .hsync_end = 1024 + 160 + 70,
2127 .htotal = 1024 + 160 + 70 + 90,
2128 .vdisplay = 600,
2129 .vsync_start = 600 + 127,
2130 .vsync_end = 600 + 127 + 20,
2131 .vtotal = 600 + 127 + 20 + 3,
2132 .vrefresh = 60,
2133};
2134
2135static const struct panel_desc netron_dy_e231732 = {
2136 .modes = &netron_dy_e231732_mode,
2137 .num_modes = 1,
2138 .size = {
2139 .width = 154,
2140 .height = 87,
2141 },
2142 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2143};
2144
2145static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2146 .clock = 9000,
2147 .hdisplay = 480,
2148 .hsync_start = 480 + 2,
2149 .hsync_end = 480 + 2 + 41,
2150 .htotal = 480 + 2 + 41 + 2,
2151 .vdisplay = 272,
2152 .vsync_start = 272 + 2,
2153 .vsync_end = 272 + 2 + 10,
2154 .vtotal = 272 + 2 + 10 + 2,
2155 .vrefresh = 60,
2156 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2157};
2158
2159static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
2160 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
2161 .num_modes = 1,
2162 .bpc = 8,
2163 .size = {
2164 .width = 95,
2165 .height = 54,
2166 },
2167 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2168 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2169 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2170};
2171
2172static const struct display_timing nlt_nl192108ac18_02d_timing = {
2173 .pixelclock = { 130000000, 148350000, 163000000 },
2174 .hactive = { 1920, 1920, 1920 },
2175 .hfront_porch = { 80, 100, 100 },
2176 .hback_porch = { 100, 120, 120 },
2177 .hsync_len = { 50, 60, 60 },
2178 .vactive = { 1080, 1080, 1080 },
2179 .vfront_porch = { 12, 30, 30 },
2180 .vback_porch = { 4, 10, 10 },
2181 .vsync_len = { 4, 5, 5 },
2182};
2183
2184static const struct panel_desc nlt_nl192108ac18_02d = {
2185 .timings = &nlt_nl192108ac18_02d_timing,
2186 .num_timings = 1,
2187 .bpc = 8,
2188 .size = {
2189 .width = 344,
2190 .height = 194,
2191 },
2192 .delay = {
2193 .unprepare = 500,
2194 },
2195 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2196};
2197
2198static const struct drm_display_mode nvd_9128_mode = {
2199 .clock = 29500,
2200 .hdisplay = 800,
2201 .hsync_start = 800 + 130,
2202 .hsync_end = 800 + 130 + 98,
2203 .htotal = 800 + 0 + 130 + 98,
2204 .vdisplay = 480,
2205 .vsync_start = 480 + 10,
2206 .vsync_end = 480 + 10 + 50,
2207 .vtotal = 480 + 0 + 10 + 50,
2208};
2209
2210static const struct panel_desc nvd_9128 = {
2211 .modes = &nvd_9128_mode,
2212 .num_modes = 1,
2213 .bpc = 8,
2214 .size = {
2215 .width = 156,
2216 .height = 88,
2217 },
2218 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2219};
2220
2221static const struct display_timing okaya_rs800480t_7x0gp_timing = {
2222 .pixelclock = { 30000000, 30000000, 40000000 },
2223 .hactive = { 800, 800, 800 },
2224 .hfront_porch = { 40, 40, 40 },
2225 .hback_porch = { 40, 40, 40 },
2226 .hsync_len = { 1, 48, 48 },
2227 .vactive = { 480, 480, 480 },
2228 .vfront_porch = { 13, 13, 13 },
2229 .vback_porch = { 29, 29, 29 },
2230 .vsync_len = { 3, 3, 3 },
2231 .flags = DISPLAY_FLAGS_DE_HIGH,
2232};
2233
2234static const struct panel_desc okaya_rs800480t_7x0gp = {
2235 .timings = &okaya_rs800480t_7x0gp_timing,
2236 .num_timings = 1,
2237 .bpc = 6,
2238 .size = {
2239 .width = 154,
2240 .height = 87,
2241 },
2242 .delay = {
2243 .prepare = 41,
2244 .enable = 50,
2245 .unprepare = 41,
2246 .disable = 50,
2247 },
2248 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2249};
2250
2251static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
2252 .clock = 9000,
2253 .hdisplay = 480,
2254 .hsync_start = 480 + 5,
2255 .hsync_end = 480 + 5 + 30,
2256 .htotal = 480 + 5 + 30 + 10,
2257 .vdisplay = 272,
2258 .vsync_start = 272 + 8,
2259 .vsync_end = 272 + 8 + 5,
2260 .vtotal = 272 + 8 + 5 + 3,
2261 .vrefresh = 60,
2262};
2263
2264static const struct panel_desc olimex_lcd_olinuxino_43ts = {
2265 .modes = &olimex_lcd_olinuxino_43ts_mode,
2266 .num_modes = 1,
2267 .size = {
2268 .width = 95,
2269 .height = 54,
2270 },
2271 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2272};
2273
2274/*
2275 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
2276 * pixel clocks, but this is the timing that was being used in the Adafruit
2277 * installation instructions.
2278 */
2279static const struct drm_display_mode ontat_yx700wv03_mode = {
2280 .clock = 29500,
2281 .hdisplay = 800,
2282 .hsync_start = 824,
2283 .hsync_end = 896,
2284 .htotal = 992,
2285 .vdisplay = 480,
2286 .vsync_start = 483,
2287 .vsync_end = 493,
2288 .vtotal = 500,
2289 .vrefresh = 60,
2290 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2291};
2292
2293/*
2294 * Specification at:
2295 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
2296 */
2297static const struct panel_desc ontat_yx700wv03 = {
2298 .modes = &ontat_yx700wv03_mode,
2299 .num_modes = 1,
2300 .bpc = 8,
2301 .size = {
2302 .width = 154,
2303 .height = 83,
2304 },
2305 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2306};
2307
2308static const struct drm_display_mode ortustech_com37h3m_mode = {
2309 .clock = 22153,
2310 .hdisplay = 480,
2311 .hsync_start = 480 + 8,
2312 .hsync_end = 480 + 8 + 10,
2313 .htotal = 480 + 8 + 10 + 10,
2314 .vdisplay = 640,
2315 .vsync_start = 640 + 4,
2316 .vsync_end = 640 + 4 + 3,
2317 .vtotal = 640 + 4 + 3 + 4,
2318 .vrefresh = 60,
2319 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2320};
2321
2322static const struct panel_desc ortustech_com37h3m = {
2323 .modes = &ortustech_com37h3m_mode,
2324 .num_modes = 1,
2325 .bpc = 8,
2326 .size = {
2327 .width = 56, /* 56.16mm */
2328 .height = 75, /* 74.88mm */
2329 },
2330 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2331 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
2332 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2333};
2334
2335static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
2336 .clock = 25000,
2337 .hdisplay = 480,
2338 .hsync_start = 480 + 10,
2339 .hsync_end = 480 + 10 + 10,
2340 .htotal = 480 + 10 + 10 + 15,
2341 .vdisplay = 800,
2342 .vsync_start = 800 + 3,
2343 .vsync_end = 800 + 3 + 3,
2344 .vtotal = 800 + 3 + 3 + 3,
2345 .vrefresh = 60,
2346};
2347
2348static const struct panel_desc ortustech_com43h4m85ulc = {
2349 .modes = &ortustech_com43h4m85ulc_mode,
2350 .num_modes = 1,
2351 .bpc = 8,
2352 .size = {
2353 .width = 56,
2354 .height = 93,
2355 },
2356 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2357 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2358};
2359
2360static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
2361 .clock = 33000,
2362 .hdisplay = 800,
2363 .hsync_start = 800 + 210,
2364 .hsync_end = 800 + 210 + 30,
2365 .htotal = 800 + 210 + 30 + 16,
2366 .vdisplay = 480,
2367 .vsync_start = 480 + 22,
2368 .vsync_end = 480 + 22 + 13,
2369 .vtotal = 480 + 22 + 13 + 10,
2370 .vrefresh = 60,
2371 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2372};
2373
2374static const struct panel_desc osddisplays_osd070t1718_19ts = {
2375 .modes = &osddisplays_osd070t1718_19ts_mode,
2376 .num_modes = 1,
2377 .bpc = 8,
2378 .size = {
2379 .width = 152,
2380 .height = 91,
2381 },
2382 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2383 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2384};
2385
2386static const struct drm_display_mode pda_91_00156_a0_mode = {
2387 .clock = 33300,
2388 .hdisplay = 800,
2389 .hsync_start = 800 + 1,
2390 .hsync_end = 800 + 1 + 64,
2391 .htotal = 800 + 1 + 64 + 64,
2392 .vdisplay = 480,
2393 .vsync_start = 480 + 1,
2394 .vsync_end = 480 + 1 + 23,
2395 .vtotal = 480 + 1 + 23 + 22,
2396 .vrefresh = 60,
2397};
2398
2399static const struct panel_desc pda_91_00156_a0 = {
2400 .modes = &pda_91_00156_a0_mode,
2401 .num_modes = 1,
2402 .size = {
2403 .width = 152,
2404 .height = 91,
2405 },
2406 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2407};
2408
2409
2410static const struct drm_display_mode qd43003c0_40_mode = {
2411 .clock = 9000,
2412 .hdisplay = 480,
2413 .hsync_start = 480 + 8,
2414 .hsync_end = 480 + 8 + 4,
2415 .htotal = 480 + 8 + 4 + 39,
2416 .vdisplay = 272,
2417 .vsync_start = 272 + 4,
2418 .vsync_end = 272 + 4 + 10,
2419 .vtotal = 272 + 4 + 10 + 2,
2420 .vrefresh = 60,
2421};
2422
2423static const struct panel_desc qd43003c0_40 = {
2424 .modes = &qd43003c0_40_mode,
2425 .num_modes = 1,
2426 .bpc = 8,
2427 .size = {
2428 .width = 95,
2429 .height = 53,
2430 },
2431 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2432};
2433
2434static const struct display_timing rocktech_rk070er9427_timing = {
2435 .pixelclock = { 26400000, 33300000, 46800000 },
2436 .hactive = { 800, 800, 800 },
2437 .hfront_porch = { 16, 210, 354 },
2438 .hback_porch = { 46, 46, 46 },
2439 .hsync_len = { 1, 1, 1 },
2440 .vactive = { 480, 480, 480 },
2441 .vfront_porch = { 7, 22, 147 },
2442 .vback_porch = { 23, 23, 23 },
2443 .vsync_len = { 1, 1, 1 },
2444 .flags = DISPLAY_FLAGS_DE_HIGH,
2445};
2446
2447static const struct panel_desc rocktech_rk070er9427 = {
2448 .timings = &rocktech_rk070er9427_timing,
2449 .num_timings = 1,
2450 .bpc = 6,
2451 .size = {
2452 .width = 154,
2453 .height = 86,
2454 },
2455 .delay = {
2456 .prepare = 41,
2457 .enable = 50,
2458 .unprepare = 41,
2459 .disable = 50,
2460 },
2461 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2462};
2463
2464static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
2465 .clock = 271560,
2466 .hdisplay = 2560,
2467 .hsync_start = 2560 + 48,
2468 .hsync_end = 2560 + 48 + 32,
2469 .htotal = 2560 + 48 + 32 + 80,
2470 .vdisplay = 1600,
2471 .vsync_start = 1600 + 2,
2472 .vsync_end = 1600 + 2 + 5,
2473 .vtotal = 1600 + 2 + 5 + 57,
2474 .vrefresh = 60,
2475};
2476
2477static const struct panel_desc samsung_lsn122dl01_c01 = {
2478 .modes = &samsung_lsn122dl01_c01_mode,
2479 .num_modes = 1,
2480 .size = {
2481 .width = 263,
2482 .height = 164,
2483 },
2484};
2485
2486static const struct drm_display_mode samsung_ltn101nt05_mode = {
2487 .clock = 54030,
2488 .hdisplay = 1024,
2489 .hsync_start = 1024 + 24,
2490 .hsync_end = 1024 + 24 + 136,
2491 .htotal = 1024 + 24 + 136 + 160,
2492 .vdisplay = 600,
2493 .vsync_start = 600 + 3,
2494 .vsync_end = 600 + 3 + 6,
2495 .vtotal = 600 + 3 + 6 + 61,
2496 .vrefresh = 60,
2497};
2498
2499static const struct panel_desc samsung_ltn101nt05 = {
2500 .modes = &samsung_ltn101nt05_mode,
2501 .num_modes = 1,
2502 .bpc = 6,
2503 .size = {
2504 .width = 223,
2505 .height = 125,
2506 },
2507};
2508
2509static const struct drm_display_mode samsung_ltn140at29_301_mode = {
2510 .clock = 76300,
2511 .hdisplay = 1366,
2512 .hsync_start = 1366 + 64,
2513 .hsync_end = 1366 + 64 + 48,
2514 .htotal = 1366 + 64 + 48 + 128,
2515 .vdisplay = 768,
2516 .vsync_start = 768 + 2,
2517 .vsync_end = 768 + 2 + 5,
2518 .vtotal = 768 + 2 + 5 + 17,
2519 .vrefresh = 60,
2520};
2521
2522static const struct panel_desc samsung_ltn140at29_301 = {
2523 .modes = &samsung_ltn140at29_301_mode,
2524 .num_modes = 1,
2525 .bpc = 6,
2526 .size = {
2527 .width = 320,
2528 .height = 187,
2529 },
2530};
2531
2532static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
2533 .clock = 168480,
2534 .hdisplay = 1920,
2535 .hsync_start = 1920 + 48,
2536 .hsync_end = 1920 + 48 + 32,
2537 .htotal = 1920 + 48 + 32 + 80,
2538 .vdisplay = 1280,
2539 .vsync_start = 1280 + 3,
2540 .vsync_end = 1280 + 3 + 10,
2541 .vtotal = 1280 + 3 + 10 + 57,
2542 .vrefresh = 60,
2543 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2544};
2545
2546static const struct panel_desc sharp_ld_d5116z01b = {
2547 .modes = &sharp_ld_d5116z01b_mode,
2548 .num_modes = 1,
2549 .bpc = 8,
2550 .size = {
2551 .width = 260,
2552 .height = 120,
2553 },
2554 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2555 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2556};
2557
2558static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
2559 .clock = 33260,
2560 .hdisplay = 800,
2561 .hsync_start = 800 + 64,
2562 .hsync_end = 800 + 64 + 128,
2563 .htotal = 800 + 64 + 128 + 64,
2564 .vdisplay = 480,
2565 .vsync_start = 480 + 8,
2566 .vsync_end = 480 + 8 + 2,
2567 .vtotal = 480 + 8 + 2 + 35,
2568 .vrefresh = 60,
2569 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
2570};
2571
2572static const struct panel_desc sharp_lq070y3dg3b = {
2573 .modes = &sharp_lq070y3dg3b_mode,
2574 .num_modes = 1,
2575 .bpc = 8,
2576 .size = {
2577 .width = 152, /* 152.4mm */
2578 .height = 91, /* 91.4mm */
2579 },
2580 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2581 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
2582 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2583};
2584
2585static const struct drm_display_mode sharp_lq035q7db03_mode = {
2586 .clock = 5500,
2587 .hdisplay = 240,
2588 .hsync_start = 240 + 16,
2589 .hsync_end = 240 + 16 + 7,
2590 .htotal = 240 + 16 + 7 + 5,
2591 .vdisplay = 320,
2592 .vsync_start = 320 + 9,
2593 .vsync_end = 320 + 9 + 1,
2594 .vtotal = 320 + 9 + 1 + 7,
2595 .vrefresh = 60,
2596};
2597
2598static const struct panel_desc sharp_lq035q7db03 = {
2599 .modes = &sharp_lq035q7db03_mode,
2600 .num_modes = 1,
2601 .bpc = 6,
2602 .size = {
2603 .width = 54,
2604 .height = 72,
2605 },
2606 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2607};
2608
2609static const struct display_timing sharp_lq101k1ly04_timing = {
2610 .pixelclock = { 60000000, 65000000, 80000000 },
2611 .hactive = { 1280, 1280, 1280 },
2612 .hfront_porch = { 20, 20, 20 },
2613 .hback_porch = { 20, 20, 20 },
2614 .hsync_len = { 10, 10, 10 },
2615 .vactive = { 800, 800, 800 },
2616 .vfront_porch = { 4, 4, 4 },
2617 .vback_porch = { 4, 4, 4 },
2618 .vsync_len = { 4, 4, 4 },
2619 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
2620};
2621
2622static const struct panel_desc sharp_lq101k1ly04 = {
2623 .timings = &sharp_lq101k1ly04_timing,
2624 .num_timings = 1,
2625 .bpc = 8,
2626 .size = {
2627 .width = 217,
2628 .height = 136,
2629 },
2630 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
2631};
2632
2633static const struct display_timing sharp_lq123p1jx31_timing = {
2634 .pixelclock = { 252750000, 252750000, 266604720 },
2635 .hactive = { 2400, 2400, 2400 },
2636 .hfront_porch = { 48, 48, 48 },
2637 .hback_porch = { 80, 80, 84 },
2638 .hsync_len = { 32, 32, 32 },
2639 .vactive = { 1600, 1600, 1600 },
2640 .vfront_porch = { 3, 3, 3 },
2641 .vback_porch = { 33, 33, 120 },
2642 .vsync_len = { 10, 10, 10 },
2643 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
2644};
2645
2646static const struct panel_desc sharp_lq123p1jx31 = {
2647 .timings = &sharp_lq123p1jx31_timing,
2648 .num_timings = 1,
2649 .bpc = 8,
2650 .size = {
2651 .width = 259,
2652 .height = 173,
2653 },
2654 .delay = {
2655 .prepare = 110,
2656 .enable = 50,
2657 .unprepare = 550,
2658 },
2659};
2660
2661static const struct drm_display_mode sharp_lq150x1lg11_mode = {
2662 .clock = 71100,
2663 .hdisplay = 1024,
2664 .hsync_start = 1024 + 168,
2665 .hsync_end = 1024 + 168 + 64,
2666 .htotal = 1024 + 168 + 64 + 88,
2667 .vdisplay = 768,
2668 .vsync_start = 768 + 37,
2669 .vsync_end = 768 + 37 + 2,
2670 .vtotal = 768 + 37 + 2 + 8,
2671 .vrefresh = 60,
2672};
2673
2674static const struct panel_desc sharp_lq150x1lg11 = {
2675 .modes = &sharp_lq150x1lg11_mode,
2676 .num_modes = 1,
2677 .bpc = 6,
2678 .size = {
2679 .width = 304,
2680 .height = 228,
2681 },
2682 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
2683};
2684
2685static const struct display_timing sharp_ls020b1dd01d_timing = {
2686 .pixelclock = { 2000000, 4200000, 5000000 },
2687 .hactive = { 240, 240, 240 },
2688 .hfront_porch = { 66, 66, 66 },
2689 .hback_porch = { 1, 1, 1 },
2690 .hsync_len = { 1, 1, 1 },
2691 .vactive = { 160, 160, 160 },
2692 .vfront_porch = { 52, 52, 52 },
2693 .vback_porch = { 6, 6, 6 },
2694 .vsync_len = { 10, 10, 10 },
2695 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW,
2696};
2697
2698static const struct panel_desc sharp_ls020b1dd01d = {
2699 .timings = &sharp_ls020b1dd01d_timing,
2700 .num_timings = 1,
2701 .bpc = 6,
2702 .size = {
2703 .width = 42,
2704 .height = 28,
2705 },
2706 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
2707 .bus_flags = DRM_BUS_FLAG_DE_HIGH
2708 | DRM_BUS_FLAG_PIXDATA_NEGEDGE
2709 | DRM_BUS_FLAG_SHARP_SIGNALS,
2710};
2711
2712static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
2713 .clock = 33300,
2714 .hdisplay = 800,
2715 .hsync_start = 800 + 1,
2716 .hsync_end = 800 + 1 + 64,
2717 .htotal = 800 + 1 + 64 + 64,
2718 .vdisplay = 480,
2719 .vsync_start = 480 + 1,
2720 .vsync_end = 480 + 1 + 23,
2721 .vtotal = 480 + 1 + 23 + 22,
2722 .vrefresh = 60,
2723};
2724
2725static const struct panel_desc shelly_sca07010_bfn_lnn = {
2726 .modes = &shelly_sca07010_bfn_lnn_mode,
2727 .num_modes = 1,
2728 .size = {
2729 .width = 152,
2730 .height = 91,
2731 },
2732 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2733};
2734
2735static const struct drm_display_mode starry_kr122ea0sra_mode = {
2736 .clock = 147000,
2737 .hdisplay = 1920,
2738 .hsync_start = 1920 + 16,
2739 .hsync_end = 1920 + 16 + 16,
2740 .htotal = 1920 + 16 + 16 + 32,
2741 .vdisplay = 1200,
2742 .vsync_start = 1200 + 15,
2743 .vsync_end = 1200 + 15 + 2,
2744 .vtotal = 1200 + 15 + 2 + 18,
2745 .vrefresh = 60,
2746 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2747};
2748
2749static const struct panel_desc starry_kr122ea0sra = {
2750 .modes = &starry_kr122ea0sra_mode,
2751 .num_modes = 1,
2752 .size = {
2753 .width = 263,
2754 .height = 164,
2755 },
2756 .delay = {
2757 .prepare = 10 + 200,
2758 .enable = 50,
2759 .unprepare = 10 + 500,
2760 },
2761};
2762
2763static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
2764 .clock = 30000,
2765 .hdisplay = 800,
2766 .hsync_start = 800 + 39,
2767 .hsync_end = 800 + 39 + 47,
2768 .htotal = 800 + 39 + 47 + 39,
2769 .vdisplay = 480,
2770 .vsync_start = 480 + 13,
2771 .vsync_end = 480 + 13 + 2,
2772 .vtotal = 480 + 13 + 2 + 29,
2773 .vrefresh = 62,
2774};
2775
2776static const struct panel_desc tfc_s9700rtwv43tr_01b = {
2777 .modes = &tfc_s9700rtwv43tr_01b_mode,
2778 .num_modes = 1,
2779 .bpc = 8,
2780 .size = {
2781 .width = 155,
2782 .height = 90,
2783 },
2784 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2785 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
2786};
2787
2788static const struct display_timing tianma_tm070jdhg30_timing = {
2789 .pixelclock = { 62600000, 68200000, 78100000 },
2790 .hactive = { 1280, 1280, 1280 },
2791 .hfront_porch = { 15, 64, 159 },
2792 .hback_porch = { 5, 5, 5 },
2793 .hsync_len = { 1, 1, 256 },
2794 .vactive = { 800, 800, 800 },
2795 .vfront_porch = { 3, 40, 99 },
2796 .vback_porch = { 2, 2, 2 },
2797 .vsync_len = { 1, 1, 128 },
2798 .flags = DISPLAY_FLAGS_DE_HIGH,
2799};
2800
2801static const struct panel_desc tianma_tm070jdhg30 = {
2802 .timings = &tianma_tm070jdhg30_timing,
2803 .num_timings = 1,
2804 .bpc = 8,
2805 .size = {
2806 .width = 151,
2807 .height = 95,
2808 },
2809 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2810};
2811
2812static const struct display_timing tianma_tm070rvhg71_timing = {
2813 .pixelclock = { 27700000, 29200000, 39600000 },
2814 .hactive = { 800, 800, 800 },
2815 .hfront_porch = { 12, 40, 212 },
2816 .hback_porch = { 88, 88, 88 },
2817 .hsync_len = { 1, 1, 40 },
2818 .vactive = { 480, 480, 480 },
2819 .vfront_porch = { 1, 13, 88 },
2820 .vback_porch = { 32, 32, 32 },
2821 .vsync_len = { 1, 1, 3 },
2822 .flags = DISPLAY_FLAGS_DE_HIGH,
2823};
2824
2825static const struct panel_desc tianma_tm070rvhg71 = {
2826 .timings = &tianma_tm070rvhg71_timing,
2827 .num_timings = 1,
2828 .bpc = 8,
2829 .size = {
2830 .width = 154,
2831 .height = 86,
2832 },
2833 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2834};
2835
2836static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
2837 {
2838 .clock = 10000,
2839 .hdisplay = 320,
2840 .hsync_start = 320 + 50,
2841 .hsync_end = 320 + 50 + 6,
2842 .htotal = 320 + 50 + 6 + 38,
2843 .vdisplay = 240,
2844 .vsync_start = 240 + 3,
2845 .vsync_end = 240 + 3 + 1,
2846 .vtotal = 240 + 3 + 1 + 17,
2847 .vrefresh = 60,
2848 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2849 },
2850};
2851
2852static const struct panel_desc ti_nspire_cx_lcd_panel = {
2853 .modes = ti_nspire_cx_lcd_mode,
2854 .num_modes = 1,
2855 .bpc = 8,
2856 .size = {
2857 .width = 65,
2858 .height = 49,
2859 },
2860 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2861 .bus_flags = DRM_BUS_FLAG_PIXDATA_NEGEDGE,
2862};
2863
2864static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
2865 {
2866 .clock = 10000,
2867 .hdisplay = 320,
2868 .hsync_start = 320 + 6,
2869 .hsync_end = 320 + 6 + 6,
2870 .htotal = 320 + 6 + 6 + 6,
2871 .vdisplay = 240,
2872 .vsync_start = 240 + 0,
2873 .vsync_end = 240 + 0 + 1,
2874 .vtotal = 240 + 0 + 1 + 0,
2875 .vrefresh = 60,
2876 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2877 },
2878};
2879
2880static const struct panel_desc ti_nspire_classic_lcd_panel = {
2881 .modes = ti_nspire_classic_lcd_mode,
2882 .num_modes = 1,
2883 /* The grayscale panel has 8 bit for the color .. Y (black) */
2884 .bpc = 8,
2885 .size = {
2886 .width = 71,
2887 .height = 53,
2888 },
2889 /* This is the grayscale bus format */
2890 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
2891 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
2892};
2893
2894static const struct drm_display_mode toshiba_lt089ac29000_mode = {
2895 .clock = 79500,
2896 .hdisplay = 1280,
2897 .hsync_start = 1280 + 192,
2898 .hsync_end = 1280 + 192 + 128,
2899 .htotal = 1280 + 192 + 128 + 64,
2900 .vdisplay = 768,
2901 .vsync_start = 768 + 20,
2902 .vsync_end = 768 + 20 + 7,
2903 .vtotal = 768 + 20 + 7 + 3,
2904 .vrefresh = 60,
2905};
2906
2907static const struct panel_desc toshiba_lt089ac29000 = {
2908 .modes = &toshiba_lt089ac29000_mode,
2909 .num_modes = 1,
2910 .size = {
2911 .width = 194,
2912 .height = 116,
2913 },
2914 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2915 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2916};
2917
2918static const struct drm_display_mode tpk_f07a_0102_mode = {
2919 .clock = 33260,
2920 .hdisplay = 800,
2921 .hsync_start = 800 + 40,
2922 .hsync_end = 800 + 40 + 128,
2923 .htotal = 800 + 40 + 128 + 88,
2924 .vdisplay = 480,
2925 .vsync_start = 480 + 10,
2926 .vsync_end = 480 + 10 + 2,
2927 .vtotal = 480 + 10 + 2 + 33,
2928 .vrefresh = 60,
2929};
2930
2931static const struct panel_desc tpk_f07a_0102 = {
2932 .modes = &tpk_f07a_0102_mode,
2933 .num_modes = 1,
2934 .size = {
2935 .width = 152,
2936 .height = 91,
2937 },
2938 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2939};
2940
2941static const struct drm_display_mode tpk_f10a_0102_mode = {
2942 .clock = 45000,
2943 .hdisplay = 1024,
2944 .hsync_start = 1024 + 176,
2945 .hsync_end = 1024 + 176 + 5,
2946 .htotal = 1024 + 176 + 5 + 88,
2947 .vdisplay = 600,
2948 .vsync_start = 600 + 20,
2949 .vsync_end = 600 + 20 + 5,
2950 .vtotal = 600 + 20 + 5 + 25,
2951 .vrefresh = 60,
2952};
2953
2954static const struct panel_desc tpk_f10a_0102 = {
2955 .modes = &tpk_f10a_0102_mode,
2956 .num_modes = 1,
2957 .size = {
2958 .width = 223,
2959 .height = 125,
2960 },
2961};
2962
2963static const struct display_timing urt_umsh_8596md_timing = {
2964 .pixelclock = { 33260000, 33260000, 33260000 },
2965 .hactive = { 800, 800, 800 },
2966 .hfront_porch = { 41, 41, 41 },
2967 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
2968 .hsync_len = { 71, 128, 128 },
2969 .vactive = { 480, 480, 480 },
2970 .vfront_porch = { 10, 10, 10 },
2971 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
2972 .vsync_len = { 2, 2, 2 },
2973 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
2974 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2975};
2976
2977static const struct panel_desc urt_umsh_8596md_lvds = {
2978 .timings = &urt_umsh_8596md_timing,
2979 .num_timings = 1,
2980 .bpc = 6,
2981 .size = {
2982 .width = 152,
2983 .height = 91,
2984 },
2985 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2986};
2987
2988static const struct panel_desc urt_umsh_8596md_parallel = {
2989 .timings = &urt_umsh_8596md_timing,
2990 .num_timings = 1,
2991 .bpc = 6,
2992 .size = {
2993 .width = 152,
2994 .height = 91,
2995 },
2996 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2997};
2998
2999static const struct drm_display_mode vl050_8048nt_c01_mode = {
3000 .clock = 33333,
3001 .hdisplay = 800,
3002 .hsync_start = 800 + 210,
3003 .hsync_end = 800 + 210 + 20,
3004 .htotal = 800 + 210 + 20 + 46,
3005 .vdisplay = 480,
3006 .vsync_start = 480 + 22,
3007 .vsync_end = 480 + 22 + 10,
3008 .vtotal = 480 + 22 + 10 + 23,
3009 .vrefresh = 60,
3010 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3011};
3012
3013static const struct panel_desc vl050_8048nt_c01 = {
3014 .modes = &vl050_8048nt_c01_mode,
3015 .num_modes = 1,
3016 .bpc = 8,
3017 .size = {
3018 .width = 120,
3019 .height = 76,
3020 },
3021 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3022 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
3023};
3024
3025static const struct drm_display_mode winstar_wf35ltiacd_mode = {
3026 .clock = 6410,
3027 .hdisplay = 320,
3028 .hsync_start = 320 + 20,
3029 .hsync_end = 320 + 20 + 30,
3030 .htotal = 320 + 20 + 30 + 38,
3031 .vdisplay = 240,
3032 .vsync_start = 240 + 4,
3033 .vsync_end = 240 + 4 + 3,
3034 .vtotal = 240 + 4 + 3 + 15,
3035 .vrefresh = 60,
3036 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3037};
3038
3039static const struct panel_desc winstar_wf35ltiacd = {
3040 .modes = &winstar_wf35ltiacd_mode,
3041 .num_modes = 1,
3042 .bpc = 8,
3043 .size = {
3044 .width = 70,
3045 .height = 53,
3046 },
3047 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3048};
3049
3050static const struct drm_display_mode arm_rtsm_mode[] = {
3051 {
3052 .clock = 65000,
3053 .hdisplay = 1024,
3054 .hsync_start = 1024 + 24,
3055 .hsync_end = 1024 + 24 + 136,
3056 .htotal = 1024 + 24 + 136 + 160,
3057 .vdisplay = 768,
3058 .vsync_start = 768 + 3,
3059 .vsync_end = 768 + 3 + 6,
3060 .vtotal = 768 + 3 + 6 + 29,
3061 .vrefresh = 60,
3062 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3063 },
3064};
3065
3066static const struct panel_desc arm_rtsm = {
3067 .modes = arm_rtsm_mode,
3068 .num_modes = 1,
3069 .bpc = 8,
3070 .size = {
3071 .width = 400,
3072 .height = 300,
3073 },
3074 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3075};
3076
3077static const struct of_device_id platform_of_match[] = {
3078 {
3079 .compatible = "ampire,am-480272h3tmqw-t01h",
3080 .data = &ire_am_480272h3tmqw_t01h,
3081 }, {
3082 .compatible = "ampire,am800480r3tmqwa1h",
3083 .data = &ire_am800480r3tmqwa1h,
3084 }, {
3085 .compatible = "arm,rtsm-display",
3086 .data = &arm_rtsm,
3087 }, {
3088 .compatible = "armadeus,st0700-adapt",
3089 .data = &armadeus_st0700_adapt,
3090 }, {
3091 .compatible = "auo,b101aw03",
3092 .data = &auo_b101aw03,
3093 }, {
3094 .compatible = "auo,b101ean01",
3095 .data = &auo_b101ean01,
3096 }, {
3097 .compatible = "auo,b101xtn01",
3098 .data = &auo_b101xtn01,
3099 }, {
3100 .compatible = "auo,b116xw03",
3101 .data = &auo_b116xw03,
3102 }, {
3103 .compatible = "auo,b133htn01",
3104 .data = &auo_b133htn01,
3105 }, {
3106 .compatible = "auo,b133xtn01",
3107 .data = &auo_b133xtn01,
3108 }, {
3109 .compatible = "auo,g070vvn01",
3110 .data = &auo_g070vvn01,
3111 }, {
3112 .compatible = "auo,g101evn010",
3113 .data = &auo_g101evn010,
3114 }, {
3115 .compatible = "auo,g104sn02",
3116 .data = &auo_g104sn02,
3117 }, {
3118 .compatible = "auo,g133han01",
3119 .data = &auo_g133han01,
3120 }, {
3121 .compatible = "auo,g185han01",
3122 .data = &auo_g185han01,
3123 }, {
3124 .compatible = "auo,p320hvn03",
3125 .data = &auo_p320hvn03,
3126 }, {
3127 .compatible = "auo,t215hvn01",
3128 .data = &auo_t215hvn01,
3129 }, {
3130 .compatible = "avic,tm070ddh03",
3131 .data = &avic_tm070ddh03,
3132 }, {
3133 .compatible = "bananapi,s070wv20-ct16",
3134 .data = &bananapi_s070wv20_ct16,
3135 }, {
3136 .compatible = "boe,hv070wsa-100",
3137 .data = &boe_hv070wsa
3138 }, {
3139 .compatible = "boe,nv101wxmn51",
3140 .data = &boe_nv101wxmn51,
3141 }, {
3142 .compatible = "cdtech,s043wq26h-ct7",
3143 .data = &cdtech_s043wq26h_ct7,
3144 }, {
3145 .compatible = "cdtech,s070wv95-ct16",
3146 .data = &cdtech_s070wv95_ct16,
3147 }, {
3148 .compatible = "chunghwa,claa070wp03xg",
3149 .data = &chunghwa_claa070wp03xg,
3150 }, {
3151 .compatible = "chunghwa,claa101wa01a",
3152 .data = &chunghwa_claa101wa01a
3153 }, {
3154 .compatible = "chunghwa,claa101wb01",
3155 .data = &chunghwa_claa101wb01
3156 }, {
3157 .compatible = "dataimage,scf0700c48ggu18",
3158 .data = &dataimage_scf0700c48ggu18,
3159 }, {
3160 .compatible = "dlc,dlc0700yzg-1",
3161 .data = &dlc_dlc0700yzg_1,
3162 }, {
3163 .compatible = "dlc,dlc1010gig",
3164 .data = &dlc_dlc1010gig,
3165 }, {
3166 .compatible = "edt,et035012dm6",
3167 .data = &edt_et035012dm6,
3168 }, {
3169 .compatible = "edt,etm0430g0dh6",
3170 .data = &edt_etm0430g0dh6,
3171 }, {
3172 .compatible = "edt,et057090dhu",
3173 .data = &edt_et057090dhu,
3174 }, {
3175 .compatible = "edt,et070080dh6",
3176 .data = &edt_etm0700g0dh6,
3177 }, {
3178 .compatible = "edt,etm0700g0dh6",
3179 .data = &edt_etm0700g0dh6,
3180 }, {
3181 .compatible = "edt,etm0700g0bdh6",
3182 .data = &edt_etm0700g0bdh6,
3183 }, {
3184 .compatible = "edt,etm0700g0edh6",
3185 .data = &edt_etm0700g0bdh6,
3186 }, {
3187 .compatible = "evervision,vgg804821",
3188 .data = &evervision_vgg804821,
3189 }, {
3190 .compatible = "foxlink,fl500wvr00-a0t",
3191 .data = &foxlink_fl500wvr00_a0t,
3192 }, {
3193 .compatible = "friendlyarm,hd702e",
3194 .data = &friendlyarm_hd702e,
3195 }, {
3196 .compatible = "giantplus,gpg482739qs5",
3197 .data = &giantplus_gpg482739qs5
3198 }, {
3199 .compatible = "giantplus,gpm940b0",
3200 .data = &giantplus_gpm940b0,
3201 }, {
3202 .compatible = "hannstar,hsd070pww1",
3203 .data = &hannstar_hsd070pww1,
3204 }, {
3205 .compatible = "hannstar,hsd100pxn1",
3206 .data = &hannstar_hsd100pxn1,
3207 }, {
3208 .compatible = "hit,tx23d38vm0caa",
3209 .data = &hitachi_tx23d38vm0caa
3210 }, {
3211 .compatible = "innolux,at043tn24",
3212 .data = &innolux_at043tn24,
3213 }, {
3214 .compatible = "innolux,at070tn92",
3215 .data = &innolux_at070tn92,
3216 }, {
3217 .compatible = "innolux,g070y2-l01",
3218 .data = &innolux_g070y2_l01,
3219 }, {
3220 .compatible = "innolux,g101ice-l01",
3221 .data = &innolux_g101ice_l01
3222 }, {
3223 .compatible = "innolux,g121i1-l01",
3224 .data = &innolux_g121i1_l01
3225 }, {
3226 .compatible = "innolux,g121x1-l03",
3227 .data = &innolux_g121x1_l03,
3228 }, {
3229 .compatible = "innolux,n116bge",
3230 .data = &innolux_n116bge,
3231 }, {
3232 .compatible = "innolux,n156bge-l21",
3233 .data = &innolux_n156bge_l21,
3234 }, {
3235 .compatible = "innolux,p120zdg-bf1",
3236 .data = &innolux_p120zdg_bf1,
3237 }, {
3238 .compatible = "innolux,zj070na-01p",
3239 .data = &innolux_zj070na_01p,
3240 }, {
3241 .compatible = "koe,tx14d24vm1bpa",
3242 .data = &koe_tx14d24vm1bpa,
3243 }, {
3244 .compatible = "koe,tx31d200vm0baa",
3245 .data = &koe_tx31d200vm0baa,
3246 }, {
3247 .compatible = "kyo,tcg121xglp",
3248 .data = &kyo_tcg121xglp,
3249 }, {
3250 .compatible = "lemaker,bl035-rgb-002",
3251 .data = &lemaker_bl035_rgb_002,
3252 }, {
3253 .compatible = "lg,lb070wv8",
3254 .data = &lg_lb070wv8,
3255 }, {
3256 .compatible = "lg,lp079qx1-sp0v",
3257 .data = &lg_lp079qx1_sp0v,
3258 }, {
3259 .compatible = "lg,lp097qx1-spa1",
3260 .data = &lg_lp097qx1_spa1,
3261 }, {
3262 .compatible = "lg,lp120up1",
3263 .data = &lg_lp120up1,
3264 }, {
3265 .compatible = "lg,lp129qe",
3266 .data = &lg_lp129qe,
3267 }, {
3268 .compatible = "mitsubishi,aa070mc01-ca1",
3269 .data = &mitsubishi_aa070mc01,
3270 }, {
3271 .compatible = "nec,nl12880bc20-05",
3272 .data = &nec_nl12880bc20_05,
3273 }, {
3274 .compatible = "nec,nl4827hc19-05b",
3275 .data = &nec_nl4827hc19_05b,
3276 }, {
3277 .compatible = "netron-dy,e231732",
3278 .data = &netron_dy_e231732,
3279 }, {
3280 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
3281 .data = &newhaven_nhd_43_480272ef_atxl,
3282 }, {
3283 .compatible = "nlt,nl192108ac18-02d",
3284 .data = &nlt_nl192108ac18_02d,
3285 }, {
3286 .compatible = "nvd,9128",
3287 .data = &nvd_9128,
3288 }, {
3289 .compatible = "okaya,rs800480t-7x0gp",
3290 .data = &okaya_rs800480t_7x0gp,
3291 }, {
3292 .compatible = "olimex,lcd-olinuxino-43-ts",
3293 .data = &olimex_lcd_olinuxino_43ts,
3294 }, {
3295 .compatible = "ontat,yx700wv03",
3296 .data = &ontat_yx700wv03,
3297 }, {
3298 .compatible = "ortustech,com37h3m05dtc",
3299 .data = &ortustech_com37h3m,
3300 }, {
3301 .compatible = "ortustech,com37h3m99dtc",
3302 .data = &ortustech_com37h3m,
3303 }, {
3304 .compatible = "ortustech,com43h4m85ulc",
3305 .data = &ortustech_com43h4m85ulc,
3306 }, {
3307 .compatible = "osddisplays,osd070t1718-19ts",
3308 .data = &osddisplays_osd070t1718_19ts,
3309 }, {
3310 .compatible = "pda,91-00156-a0",
3311 .data = &pda_91_00156_a0,
3312 }, {
3313 .compatible = "qiaodian,qd43003c0-40",
3314 .data = &qd43003c0_40,
3315 }, {
3316 .compatible = "rocktech,rk070er9427",
3317 .data = &rocktech_rk070er9427,
3318 }, {
3319 .compatible = "samsung,lsn122dl01-c01",
3320 .data = &samsung_lsn122dl01_c01,
3321 }, {
3322 .compatible = "samsung,ltn101nt05",
3323 .data = &samsung_ltn101nt05,
3324 }, {
3325 .compatible = "samsung,ltn140at29-301",
3326 .data = &samsung_ltn140at29_301,
3327 }, {
3328 .compatible = "sharp,ld-d5116z01b",
3329 .data = &sharp_ld_d5116z01b,
3330 }, {
3331 .compatible = "sharp,lq035q7db03",
3332 .data = &sharp_lq035q7db03,
3333 }, {
3334 .compatible = "sharp,lq070y3dg3b",
3335 .data = &sharp_lq070y3dg3b,
3336 }, {
3337 .compatible = "sharp,lq101k1ly04",
3338 .data = &sharp_lq101k1ly04,
3339 }, {
3340 .compatible = "sharp,lq123p1jx31",
3341 .data = &sharp_lq123p1jx31,
3342 }, {
3343 .compatible = "sharp,lq150x1lg11",
3344 .data = &sharp_lq150x1lg11,
3345 }, {
3346 .compatible = "sharp,ls020b1dd01d",
3347 .data = &sharp_ls020b1dd01d,
3348 }, {
3349 .compatible = "shelly,sca07010-bfn-lnn",
3350 .data = &shelly_sca07010_bfn_lnn,
3351 }, {
3352 .compatible = "starry,kr122ea0sra",
3353 .data = &starry_kr122ea0sra,
3354 }, {
3355 .compatible = "tfc,s9700rtwv43tr-01b",
3356 .data = &tfc_s9700rtwv43tr_01b,
3357 }, {
3358 .compatible = "tianma,tm070jdhg30",
3359 .data = &tianma_tm070jdhg30,
3360 }, {
3361 .compatible = "tianma,tm070rvhg71",
3362 .data = &tianma_tm070rvhg71,
3363 }, {
3364 .compatible = "ti,nspire-cx-lcd-panel",
3365 .data = &ti_nspire_cx_lcd_panel,
3366 }, {
3367 .compatible = "ti,nspire-classic-lcd-panel",
3368 .data = &ti_nspire_classic_lcd_panel,
3369 }, {
3370 .compatible = "toshiba,lt089ac29000",
3371 .data = &toshiba_lt089ac29000,
3372 }, {
3373 .compatible = "tpk,f07a-0102",
3374 .data = &tpk_f07a_0102,
3375 }, {
3376 .compatible = "tpk,f10a-0102",
3377 .data = &tpk_f10a_0102,
3378 }, {
3379 .compatible = "urt,umsh-8596md-t",
3380 .data = &urt_umsh_8596md_parallel,
3381 }, {
3382 .compatible = "urt,umsh-8596md-1t",
3383 .data = &urt_umsh_8596md_parallel,
3384 }, {
3385 .compatible = "urt,umsh-8596md-7t",
3386 .data = &urt_umsh_8596md_parallel,
3387 }, {
3388 .compatible = "urt,umsh-8596md-11t",
3389 .data = &urt_umsh_8596md_lvds,
3390 }, {
3391 .compatible = "urt,umsh-8596md-19t",
3392 .data = &urt_umsh_8596md_lvds,
3393 }, {
3394 .compatible = "urt,umsh-8596md-20t",
3395 .data = &urt_umsh_8596md_parallel,
3396 }, {
3397 .compatible = "vxt,vl050-8048nt-c01",
3398 .data = &vl050_8048nt_c01,
3399 }, {
3400 .compatible = "winstar,wf35ltiacd",
3401 .data = &winstar_wf35ltiacd,
3402 }, {
3403 /* sentinel */
3404 }
3405};
3406MODULE_DEVICE_TABLE(of, platform_of_match);
3407
3408static int panel_simple_platform_probe(struct platform_device *pdev)
3409{
3410 const struct of_device_id *id;
3411
3412 id = of_match_node(platform_of_match, pdev->dev.of_node);
3413 if (!id)
3414 return -ENODEV;
3415
3416 return panel_simple_probe(&pdev->dev, id->data);
3417}
3418
3419static int panel_simple_platform_remove(struct platform_device *pdev)
3420{
3421 return panel_simple_remove(&pdev->dev);
3422}
3423
3424static void panel_simple_platform_shutdown(struct platform_device *pdev)
3425{
3426 panel_simple_shutdown(&pdev->dev);
3427}
3428
3429static struct platform_driver panel_simple_platform_driver = {
3430 .driver = {
3431 .name = "panel-simple",
3432 .of_match_table = platform_of_match,
3433 },
3434 .probe = panel_simple_platform_probe,
3435 .remove = panel_simple_platform_remove,
3436 .shutdown = panel_simple_platform_shutdown,
3437};
3438
3439struct panel_desc_dsi {
3440 struct panel_desc desc;
3441
3442 unsigned long flags;
3443 enum mipi_dsi_pixel_format format;
3444 unsigned int lanes;
3445};
3446
3447static const struct drm_display_mode auo_b080uan01_mode = {
3448 .clock = 154500,
3449 .hdisplay = 1200,
3450 .hsync_start = 1200 + 62,
3451 .hsync_end = 1200 + 62 + 4,
3452 .htotal = 1200 + 62 + 4 + 62,
3453 .vdisplay = 1920,
3454 .vsync_start = 1920 + 9,
3455 .vsync_end = 1920 + 9 + 2,
3456 .vtotal = 1920 + 9 + 2 + 8,
3457 .vrefresh = 60,
3458};
3459
3460static const struct panel_desc_dsi auo_b080uan01 = {
3461 .desc = {
3462 .modes = &auo_b080uan01_mode,
3463 .num_modes = 1,
3464 .bpc = 8,
3465 .size = {
3466 .width = 108,
3467 .height = 272,
3468 },
3469 },
3470 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
3471 .format = MIPI_DSI_FMT_RGB888,
3472 .lanes = 4,
3473};
3474
3475static const struct drm_display_mode boe_tv080wum_nl0_mode = {
3476 .clock = 160000,
3477 .hdisplay = 1200,
3478 .hsync_start = 1200 + 120,
3479 .hsync_end = 1200 + 120 + 20,
3480 .htotal = 1200 + 120 + 20 + 21,
3481 .vdisplay = 1920,
3482 .vsync_start = 1920 + 21,
3483 .vsync_end = 1920 + 21 + 3,
3484 .vtotal = 1920 + 21 + 3 + 18,
3485 .vrefresh = 60,
3486 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3487};
3488
3489static const struct panel_desc_dsi boe_tv080wum_nl0 = {
3490 .desc = {
3491 .modes = &boe_tv080wum_nl0_mode,
3492 .num_modes = 1,
3493 .size = {
3494 .width = 107,
3495 .height = 172,
3496 },
3497 },
3498 .flags = MIPI_DSI_MODE_VIDEO |
3499 MIPI_DSI_MODE_VIDEO_BURST |
3500 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
3501 .format = MIPI_DSI_FMT_RGB888,
3502 .lanes = 4,
3503};
3504
3505static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
3506 .clock = 71000,
3507 .hdisplay = 800,
3508 .hsync_start = 800 + 32,
3509 .hsync_end = 800 + 32 + 1,
3510 .htotal = 800 + 32 + 1 + 57,
3511 .vdisplay = 1280,
3512 .vsync_start = 1280 + 28,
3513 .vsync_end = 1280 + 28 + 1,
3514 .vtotal = 1280 + 28 + 1 + 14,
3515 .vrefresh = 60,
3516};
3517
3518static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
3519 .desc = {
3520 .modes = &lg_ld070wx3_sl01_mode,
3521 .num_modes = 1,
3522 .bpc = 8,
3523 .size = {
3524 .width = 94,
3525 .height = 151,
3526 },
3527 },
3528 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
3529 .format = MIPI_DSI_FMT_RGB888,
3530 .lanes = 4,
3531};
3532
3533static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
3534 .clock = 67000,
3535 .hdisplay = 720,
3536 .hsync_start = 720 + 12,
3537 .hsync_end = 720 + 12 + 4,
3538 .htotal = 720 + 12 + 4 + 112,
3539 .vdisplay = 1280,
3540 .vsync_start = 1280 + 8,
3541 .vsync_end = 1280 + 8 + 4,
3542 .vtotal = 1280 + 8 + 4 + 12,
3543 .vrefresh = 60,
3544};
3545
3546static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
3547 .desc = {
3548 .modes = &lg_lh500wx1_sd03_mode,
3549 .num_modes = 1,
3550 .bpc = 8,
3551 .size = {
3552 .width = 62,
3553 .height = 110,
3554 },
3555 },
3556 .flags = MIPI_DSI_MODE_VIDEO,
3557 .format = MIPI_DSI_FMT_RGB888,
3558 .lanes = 4,
3559};
3560
3561static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
3562 .clock = 157200,
3563 .hdisplay = 1920,
3564 .hsync_start = 1920 + 154,
3565 .hsync_end = 1920 + 154 + 16,
3566 .htotal = 1920 + 154 + 16 + 32,
3567 .vdisplay = 1200,
3568 .vsync_start = 1200 + 17,
3569 .vsync_end = 1200 + 17 + 2,
3570 .vtotal = 1200 + 17 + 2 + 16,
3571 .vrefresh = 60,
3572};
3573
3574static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
3575 .desc = {
3576 .modes = &panasonic_vvx10f004b00_mode,
3577 .num_modes = 1,
3578 .bpc = 8,
3579 .size = {
3580 .width = 217,
3581 .height = 136,
3582 },
3583 },
3584 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
3585 MIPI_DSI_CLOCK_NON_CONTINUOUS,
3586 .format = MIPI_DSI_FMT_RGB888,
3587 .lanes = 4,
3588};
3589
3590static const struct drm_display_mode lg_acx467akm_7_mode = {
3591 .clock = 150000,
3592 .hdisplay = 1080,
3593 .hsync_start = 1080 + 2,
3594 .hsync_end = 1080 + 2 + 2,
3595 .htotal = 1080 + 2 + 2 + 2,
3596 .vdisplay = 1920,
3597 .vsync_start = 1920 + 2,
3598 .vsync_end = 1920 + 2 + 2,
3599 .vtotal = 1920 + 2 + 2 + 2,
3600 .vrefresh = 60,
3601};
3602
3603static const struct panel_desc_dsi lg_acx467akm_7 = {
3604 .desc = {
3605 .modes = &lg_acx467akm_7_mode,
3606 .num_modes = 1,
3607 .bpc = 8,
3608 .size = {
3609 .width = 62,
3610 .height = 110,
3611 },
3612 },
3613 .flags = 0,
3614 .format = MIPI_DSI_FMT_RGB888,
3615 .lanes = 4,
3616};
3617
3618static const struct drm_display_mode osd101t2045_53ts_mode = {
3619 .clock = 154500,
3620 .hdisplay = 1920,
3621 .hsync_start = 1920 + 112,
3622 .hsync_end = 1920 + 112 + 16,
3623 .htotal = 1920 + 112 + 16 + 32,
3624 .vdisplay = 1200,
3625 .vsync_start = 1200 + 16,
3626 .vsync_end = 1200 + 16 + 2,
3627 .vtotal = 1200 + 16 + 2 + 16,
3628 .vrefresh = 60,
3629 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3630};
3631
3632static const struct panel_desc_dsi osd101t2045_53ts = {
3633 .desc = {
3634 .modes = &osd101t2045_53ts_mode,
3635 .num_modes = 1,
3636 .bpc = 8,
3637 .size = {
3638 .width = 217,
3639 .height = 136,
3640 },
3641 },
3642 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
3643 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
3644 MIPI_DSI_MODE_EOT_PACKET,
3645 .format = MIPI_DSI_FMT_RGB888,
3646 .lanes = 4,
3647};
3648
3649static const struct of_device_id dsi_of_match[] = {
3650 {
3651 .compatible = "auo,b080uan01",
3652 .data = &auo_b080uan01
3653 }, {
3654 .compatible = "boe,tv080wum-nl0",
3655 .data = &boe_tv080wum_nl0
3656 }, {
3657 .compatible = "lg,ld070wx3-sl01",
3658 .data = &lg_ld070wx3_sl01
3659 }, {
3660 .compatible = "lg,lh500wx1-sd03",
3661 .data = &lg_lh500wx1_sd03
3662 }, {
3663 .compatible = "panasonic,vvx10f004b00",
3664 .data = &panasonic_vvx10f004b00
3665 }, {
3666 .compatible = "lg,acx467akm-7",
3667 .data = &lg_acx467akm_7
3668 }, {
3669 .compatible = "osddisplays,osd101t2045-53ts",
3670 .data = &osd101t2045_53ts
3671 }, {
3672 /* sentinel */
3673 }
3674};
3675MODULE_DEVICE_TABLE(of, dsi_of_match);
3676
3677static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
3678{
3679 const struct panel_desc_dsi *desc;
3680 const struct of_device_id *id;
3681 int err;
3682
3683 id = of_match_node(dsi_of_match, dsi->dev.of_node);
3684 if (!id)
3685 return -ENODEV;
3686
3687 desc = id->data;
3688
3689 err = panel_simple_probe(&dsi->dev, &desc->desc);
3690 if (err < 0)
3691 return err;
3692
3693 dsi->mode_flags = desc->flags;
3694 dsi->format = desc->format;
3695 dsi->lanes = desc->lanes;
3696
3697 err = mipi_dsi_attach(dsi);
3698 if (err) {
3699 struct panel_simple *panel = dev_get_drvdata(&dsi->dev);
3700
3701 drm_panel_remove(&panel->base);
3702 }
3703
3704 return err;
3705}
3706
3707static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
3708{
3709 int err;
3710
3711 err = mipi_dsi_detach(dsi);
3712 if (err < 0)
3713 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
3714
3715 return panel_simple_remove(&dsi->dev);
3716}
3717
3718static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
3719{
3720 panel_simple_shutdown(&dsi->dev);
3721}
3722
3723static struct mipi_dsi_driver panel_simple_dsi_driver = {
3724 .driver = {
3725 .name = "panel-simple-dsi",
3726 .of_match_table = dsi_of_match,
3727 },
3728 .probe = panel_simple_dsi_probe,
3729 .remove = panel_simple_dsi_remove,
3730 .shutdown = panel_simple_dsi_shutdown,
3731};
3732
3733static int __init panel_simple_init(void)
3734{
3735 int err;
3736
3737 err = platform_driver_register(&panel_simple_platform_driver);
3738 if (err < 0)
3739 return err;
3740
3741 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
3742 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
3743 if (err < 0)
3744 return err;
3745 }
3746
3747 return 0;
3748}
3749module_init(panel_simple_init);
3750
3751static void __exit panel_simple_exit(void)
3752{
3753 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
3754 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
3755
3756 platform_driver_unregister(&panel_simple_platform_driver);
3757}
3758module_exit(panel_simple_exit);
3759
3760MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
3761MODULE_DESCRIPTION("DRM Driver for Simple Panels");
3762MODULE_LICENSE("GPL and additional rights");
1/*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/delay.h>
25#include <linux/gpio/consumer.h>
26#include <linux/i2c.h>
27#include <linux/media-bus-format.h>
28#include <linux/module.h>
29#include <linux/of_platform.h>
30#include <linux/platform_device.h>
31#include <linux/pm_runtime.h>
32#include <linux/regulator/consumer.h>
33
34#include <video/display_timing.h>
35#include <video/of_display_timing.h>
36#include <video/videomode.h>
37
38#include <drm/drm_crtc.h>
39#include <drm/drm_device.h>
40#include <drm/drm_edid.h>
41#include <drm/drm_mipi_dsi.h>
42#include <drm/drm_panel.h>
43#include <drm/drm_of.h>
44
45/**
46 * struct panel_desc - Describes a simple panel.
47 */
48struct panel_desc {
49 /**
50 * @modes: Pointer to array of fixed modes appropriate for this panel.
51 *
52 * If only one mode then this can just be the address of the mode.
53 * NOTE: cannot be used with "timings" and also if this is specified
54 * then you cannot override the mode in the device tree.
55 */
56 const struct drm_display_mode *modes;
57
58 /** @num_modes: Number of elements in modes array. */
59 unsigned int num_modes;
60
61 /**
62 * @timings: Pointer to array of display timings
63 *
64 * NOTE: cannot be used with "modes" and also these will be used to
65 * validate a device tree override if one is present.
66 */
67 const struct display_timing *timings;
68
69 /** @num_timings: Number of elements in timings array. */
70 unsigned int num_timings;
71
72 /** @bpc: Bits per color. */
73 unsigned int bpc;
74
75 /** @size: Structure containing the physical size of this panel. */
76 struct {
77 /**
78 * @size.width: Width (in mm) of the active display area.
79 */
80 unsigned int width;
81
82 /**
83 * @size.height: Height (in mm) of the active display area.
84 */
85 unsigned int height;
86 } size;
87
88 /** @delay: Structure containing various delay values for this panel. */
89 struct {
90 /**
91 * @delay.prepare: Time for the panel to become ready.
92 *
93 * The time (in milliseconds) that it takes for the panel to
94 * become ready and start receiving video data
95 */
96 unsigned int prepare;
97
98 /**
99 * @delay.enable: Time for the panel to display a valid frame.
100 *
101 * The time (in milliseconds) that it takes for the panel to
102 * display the first valid frame after starting to receive
103 * video data.
104 */
105 unsigned int enable;
106
107 /**
108 * @delay.disable: Time for the panel to turn the display off.
109 *
110 * The time (in milliseconds) that it takes for the panel to
111 * turn the display off (no content is visible).
112 */
113 unsigned int disable;
114
115 /**
116 * @delay.unprepare: Time to power down completely.
117 *
118 * The time (in milliseconds) that it takes for the panel
119 * to power itself down completely.
120 *
121 * This time is used to prevent a future "prepare" from
122 * starting until at least this many milliseconds has passed.
123 * If at prepare time less time has passed since unprepare
124 * finished, the driver waits for the remaining time.
125 */
126 unsigned int unprepare;
127 } delay;
128
129 /** @bus_format: See MEDIA_BUS_FMT_... defines. */
130 u32 bus_format;
131
132 /** @bus_flags: See DRM_BUS_FLAG_... defines. */
133 u32 bus_flags;
134
135 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */
136 int connector_type;
137};
138
139struct panel_simple {
140 struct drm_panel base;
141 bool enabled;
142
143 bool prepared;
144
145 ktime_t unprepared_time;
146
147 const struct panel_desc *desc;
148
149 struct regulator *supply;
150 struct i2c_adapter *ddc;
151
152 struct gpio_desc *enable_gpio;
153
154 struct edid *edid;
155
156 struct drm_display_mode override_mode;
157
158 enum drm_panel_orientation orientation;
159};
160
161static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
162{
163 return container_of(panel, struct panel_simple, base);
164}
165
166static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
167 struct drm_connector *connector)
168{
169 struct drm_display_mode *mode;
170 unsigned int i, num = 0;
171
172 for (i = 0; i < panel->desc->num_timings; i++) {
173 const struct display_timing *dt = &panel->desc->timings[i];
174 struct videomode vm;
175
176 videomode_from_timing(dt, &vm);
177 mode = drm_mode_create(connector->dev);
178 if (!mode) {
179 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
180 dt->hactive.typ, dt->vactive.typ);
181 continue;
182 }
183
184 drm_display_mode_from_videomode(&vm, mode);
185
186 mode->type |= DRM_MODE_TYPE_DRIVER;
187
188 if (panel->desc->num_timings == 1)
189 mode->type |= DRM_MODE_TYPE_PREFERRED;
190
191 drm_mode_probed_add(connector, mode);
192 num++;
193 }
194
195 return num;
196}
197
198static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
199 struct drm_connector *connector)
200{
201 struct drm_display_mode *mode;
202 unsigned int i, num = 0;
203
204 for (i = 0; i < panel->desc->num_modes; i++) {
205 const struct drm_display_mode *m = &panel->desc->modes[i];
206
207 mode = drm_mode_duplicate(connector->dev, m);
208 if (!mode) {
209 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
210 m->hdisplay, m->vdisplay,
211 drm_mode_vrefresh(m));
212 continue;
213 }
214
215 mode->type |= DRM_MODE_TYPE_DRIVER;
216
217 if (panel->desc->num_modes == 1)
218 mode->type |= DRM_MODE_TYPE_PREFERRED;
219
220 drm_mode_set_name(mode);
221
222 drm_mode_probed_add(connector, mode);
223 num++;
224 }
225
226 return num;
227}
228
229static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
230 struct drm_connector *connector)
231{
232 struct drm_display_mode *mode;
233 bool has_override = panel->override_mode.type;
234 unsigned int num = 0;
235
236 if (!panel->desc)
237 return 0;
238
239 if (has_override) {
240 mode = drm_mode_duplicate(connector->dev,
241 &panel->override_mode);
242 if (mode) {
243 drm_mode_probed_add(connector, mode);
244 num = 1;
245 } else {
246 dev_err(panel->base.dev, "failed to add override mode\n");
247 }
248 }
249
250 /* Only add timings if override was not there or failed to validate */
251 if (num == 0 && panel->desc->num_timings)
252 num = panel_simple_get_timings_modes(panel, connector);
253
254 /*
255 * Only add fixed modes if timings/override added no mode.
256 *
257 * We should only ever have either the display timings specified
258 * or a fixed mode. Anything else is rather bogus.
259 */
260 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
261 if (num == 0)
262 num = panel_simple_get_display_modes(panel, connector);
263
264 connector->display_info.bpc = panel->desc->bpc;
265 connector->display_info.width_mm = panel->desc->size.width;
266 connector->display_info.height_mm = panel->desc->size.height;
267 if (panel->desc->bus_format)
268 drm_display_info_set_bus_formats(&connector->display_info,
269 &panel->desc->bus_format, 1);
270 connector->display_info.bus_flags = panel->desc->bus_flags;
271
272 return num;
273}
274
275static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms)
276{
277 ktime_t now_ktime, min_ktime;
278
279 if (!min_ms)
280 return;
281
282 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms));
283 now_ktime = ktime_get_boottime();
284
285 if (ktime_before(now_ktime, min_ktime))
286 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1);
287}
288
289static int panel_simple_disable(struct drm_panel *panel)
290{
291 struct panel_simple *p = to_panel_simple(panel);
292
293 if (!p->enabled)
294 return 0;
295
296 if (p->desc->delay.disable)
297 msleep(p->desc->delay.disable);
298
299 p->enabled = false;
300
301 return 0;
302}
303
304static int panel_simple_suspend(struct device *dev)
305{
306 struct panel_simple *p = dev_get_drvdata(dev);
307
308 gpiod_set_value_cansleep(p->enable_gpio, 0);
309 regulator_disable(p->supply);
310 p->unprepared_time = ktime_get_boottime();
311
312 kfree(p->edid);
313 p->edid = NULL;
314
315 return 0;
316}
317
318static int panel_simple_unprepare(struct drm_panel *panel)
319{
320 struct panel_simple *p = to_panel_simple(panel);
321 int ret;
322
323 /* Unpreparing when already unprepared is a no-op */
324 if (!p->prepared)
325 return 0;
326
327 pm_runtime_mark_last_busy(panel->dev);
328 ret = pm_runtime_put_autosuspend(panel->dev);
329 if (ret < 0)
330 return ret;
331 p->prepared = false;
332
333 return 0;
334}
335
336static int panel_simple_resume(struct device *dev)
337{
338 struct panel_simple *p = dev_get_drvdata(dev);
339 int err;
340
341 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare);
342
343 err = regulator_enable(p->supply);
344 if (err < 0) {
345 dev_err(dev, "failed to enable supply: %d\n", err);
346 return err;
347 }
348
349 gpiod_set_value_cansleep(p->enable_gpio, 1);
350
351 if (p->desc->delay.prepare)
352 msleep(p->desc->delay.prepare);
353
354 return 0;
355}
356
357static int panel_simple_prepare(struct drm_panel *panel)
358{
359 struct panel_simple *p = to_panel_simple(panel);
360 int ret;
361
362 /* Preparing when already prepared is a no-op */
363 if (p->prepared)
364 return 0;
365
366 ret = pm_runtime_get_sync(panel->dev);
367 if (ret < 0) {
368 pm_runtime_put_autosuspend(panel->dev);
369 return ret;
370 }
371
372 p->prepared = true;
373
374 return 0;
375}
376
377static int panel_simple_enable(struct drm_panel *panel)
378{
379 struct panel_simple *p = to_panel_simple(panel);
380
381 if (p->enabled)
382 return 0;
383
384 if (p->desc->delay.enable)
385 msleep(p->desc->delay.enable);
386
387 p->enabled = true;
388
389 return 0;
390}
391
392static int panel_simple_get_modes(struct drm_panel *panel,
393 struct drm_connector *connector)
394{
395 struct panel_simple *p = to_panel_simple(panel);
396 int num = 0;
397
398 /* probe EDID if a DDC bus is available */
399 if (p->ddc) {
400 pm_runtime_get_sync(panel->dev);
401
402 if (!p->edid)
403 p->edid = drm_get_edid(connector, p->ddc);
404
405 if (p->edid)
406 num += drm_add_edid_modes(connector, p->edid);
407
408 pm_runtime_mark_last_busy(panel->dev);
409 pm_runtime_put_autosuspend(panel->dev);
410 }
411
412 /* add hard-coded panel modes */
413 num += panel_simple_get_non_edid_modes(p, connector);
414
415 /*
416 * TODO: Remove once all drm drivers call
417 * drm_connector_set_orientation_from_panel()
418 */
419 drm_connector_set_panel_orientation(connector, p->orientation);
420
421 return num;
422}
423
424static int panel_simple_get_timings(struct drm_panel *panel,
425 unsigned int num_timings,
426 struct display_timing *timings)
427{
428 struct panel_simple *p = to_panel_simple(panel);
429 unsigned int i;
430
431 if (p->desc->num_timings < num_timings)
432 num_timings = p->desc->num_timings;
433
434 if (timings)
435 for (i = 0; i < num_timings; i++)
436 timings[i] = p->desc->timings[i];
437
438 return p->desc->num_timings;
439}
440
441static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel)
442{
443 struct panel_simple *p = to_panel_simple(panel);
444
445 return p->orientation;
446}
447
448static const struct drm_panel_funcs panel_simple_funcs = {
449 .disable = panel_simple_disable,
450 .unprepare = panel_simple_unprepare,
451 .prepare = panel_simple_prepare,
452 .enable = panel_simple_enable,
453 .get_modes = panel_simple_get_modes,
454 .get_orientation = panel_simple_get_orientation,
455 .get_timings = panel_simple_get_timings,
456};
457
458static struct panel_desc panel_dpi;
459
460static int panel_dpi_probe(struct device *dev,
461 struct panel_simple *panel)
462{
463 struct display_timing *timing;
464 const struct device_node *np;
465 struct panel_desc *desc;
466 unsigned int bus_flags;
467 struct videomode vm;
468 int ret;
469
470 np = dev->of_node;
471 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
472 if (!desc)
473 return -ENOMEM;
474
475 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
476 if (!timing)
477 return -ENOMEM;
478
479 ret = of_get_display_timing(np, "panel-timing", timing);
480 if (ret < 0) {
481 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
482 np);
483 return ret;
484 }
485
486 desc->timings = timing;
487 desc->num_timings = 1;
488
489 of_property_read_u32(np, "width-mm", &desc->size.width);
490 of_property_read_u32(np, "height-mm", &desc->size.height);
491
492 /* Extract bus_flags from display_timing */
493 bus_flags = 0;
494 vm.flags = timing->flags;
495 drm_bus_flags_from_videomode(&vm, &bus_flags);
496 desc->bus_flags = bus_flags;
497
498 /* We do not know the connector for the DT node, so guess it */
499 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
500
501 panel->desc = desc;
502
503 return 0;
504}
505
506#define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
507 (to_check->field.typ >= bounds->field.min && \
508 to_check->field.typ <= bounds->field.max)
509static void panel_simple_parse_panel_timing_node(struct device *dev,
510 struct panel_simple *panel,
511 const struct display_timing *ot)
512{
513 const struct panel_desc *desc = panel->desc;
514 struct videomode vm;
515 unsigned int i;
516
517 if (WARN_ON(desc->num_modes)) {
518 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
519 return;
520 }
521 if (WARN_ON(!desc->num_timings)) {
522 dev_err(dev, "Reject override mode: no timings specified\n");
523 return;
524 }
525
526 for (i = 0; i < panel->desc->num_timings; i++) {
527 const struct display_timing *dt = &panel->desc->timings[i];
528
529 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
530 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
531 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
532 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
533 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
534 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
535 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
536 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
537 continue;
538
539 if (ot->flags != dt->flags)
540 continue;
541
542 videomode_from_timing(ot, &vm);
543 drm_display_mode_from_videomode(&vm, &panel->override_mode);
544 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
545 DRM_MODE_TYPE_PREFERRED;
546 break;
547 }
548
549 if (WARN_ON(!panel->override_mode.type))
550 dev_err(dev, "Reject override mode: No display_timing found\n");
551}
552
553static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev,
554 struct panel_simple *panel)
555{
556 int ret, bpc;
557
558 ret = drm_of_lvds_get_data_mapping(dev->of_node);
559 if (ret < 0) {
560 if (ret == -EINVAL)
561 dev_warn(dev, "Ignore invalid data-mapping property\n");
562
563 /*
564 * Ignore non-existing or malformatted property, fallback to
565 * default data-mapping, and return 0.
566 */
567 return 0;
568 }
569
570 switch (ret) {
571 default:
572 WARN_ON(1);
573 fallthrough;
574 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
575 fallthrough;
576 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
577 bpc = 8;
578 break;
579 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
580 bpc = 6;
581 }
582
583 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) {
584 struct panel_desc *override_desc;
585
586 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL);
587 if (!override_desc)
588 return -ENOMEM;
589
590 override_desc->bus_format = ret;
591 override_desc->bpc = bpc;
592 panel->desc = override_desc;
593 }
594
595 return 0;
596}
597
598static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
599{
600 struct panel_simple *panel;
601 struct display_timing dt;
602 struct device_node *ddc;
603 int connector_type;
604 u32 bus_flags;
605 int err;
606
607 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
608 if (!panel)
609 return -ENOMEM;
610
611 panel->enabled = false;
612 panel->desc = desc;
613
614 panel->supply = devm_regulator_get(dev, "power");
615 if (IS_ERR(panel->supply))
616 return PTR_ERR(panel->supply);
617
618 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
619 GPIOD_OUT_LOW);
620 if (IS_ERR(panel->enable_gpio))
621 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio),
622 "failed to request GPIO\n");
623
624 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
625 if (err) {
626 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
627 return err;
628 }
629
630 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
631 if (ddc) {
632 panel->ddc = of_find_i2c_adapter_by_node(ddc);
633 of_node_put(ddc);
634
635 if (!panel->ddc)
636 return -EPROBE_DEFER;
637 }
638
639 if (desc == &panel_dpi) {
640 /* Handle the generic panel-dpi binding */
641 err = panel_dpi_probe(dev, panel);
642 if (err)
643 goto free_ddc;
644 desc = panel->desc;
645 } else {
646 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
647 panel_simple_parse_panel_timing_node(dev, panel, &dt);
648 }
649
650 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) {
651 /* Optional data-mapping property for overriding bus format */
652 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel);
653 if (err)
654 goto free_ddc;
655 }
656
657 connector_type = desc->connector_type;
658 /* Catch common mistakes for panels. */
659 switch (connector_type) {
660 case 0:
661 dev_warn(dev, "Specify missing connector_type\n");
662 connector_type = DRM_MODE_CONNECTOR_DPI;
663 break;
664 case DRM_MODE_CONNECTOR_LVDS:
665 WARN_ON(desc->bus_flags &
666 ~(DRM_BUS_FLAG_DE_LOW |
667 DRM_BUS_FLAG_DE_HIGH |
668 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
669 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
670 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
671 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
672 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
673 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
674 desc->bpc != 6);
675 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
676 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
677 desc->bpc != 8);
678 break;
679 case DRM_MODE_CONNECTOR_eDP:
680 dev_warn(dev, "eDP panels moved to panel-edp\n");
681 err = -EINVAL;
682 goto free_ddc;
683 case DRM_MODE_CONNECTOR_DSI:
684 if (desc->bpc != 6 && desc->bpc != 8)
685 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
686 break;
687 case DRM_MODE_CONNECTOR_DPI:
688 bus_flags = DRM_BUS_FLAG_DE_LOW |
689 DRM_BUS_FLAG_DE_HIGH |
690 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
691 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
692 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
693 DRM_BUS_FLAG_DATA_LSB_TO_MSB |
694 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
695 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
696 if (desc->bus_flags & ~bus_flags)
697 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
698 if (!(desc->bus_flags & bus_flags))
699 dev_warn(dev, "Specify missing bus_flags\n");
700 if (desc->bus_format == 0)
701 dev_warn(dev, "Specify missing bus_format\n");
702 if (desc->bpc != 6 && desc->bpc != 8)
703 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
704 break;
705 default:
706 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
707 connector_type = DRM_MODE_CONNECTOR_DPI;
708 break;
709 }
710
711 dev_set_drvdata(dev, panel);
712
713 /*
714 * We use runtime PM for prepare / unprepare since those power the panel
715 * on and off and those can be very slow operations. This is important
716 * to optimize powering the panel on briefly to read the EDID before
717 * fully enabling the panel.
718 */
719 pm_runtime_enable(dev);
720 pm_runtime_set_autosuspend_delay(dev, 1000);
721 pm_runtime_use_autosuspend(dev);
722
723 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
724
725 err = drm_panel_of_backlight(&panel->base);
726 if (err) {
727 dev_err_probe(dev, err, "Could not find backlight\n");
728 goto disable_pm_runtime;
729 }
730
731 drm_panel_add(&panel->base);
732
733 return 0;
734
735disable_pm_runtime:
736 pm_runtime_dont_use_autosuspend(dev);
737 pm_runtime_disable(dev);
738free_ddc:
739 if (panel->ddc)
740 put_device(&panel->ddc->dev);
741
742 return err;
743}
744
745static void panel_simple_remove(struct device *dev)
746{
747 struct panel_simple *panel = dev_get_drvdata(dev);
748
749 drm_panel_remove(&panel->base);
750 drm_panel_disable(&panel->base);
751 drm_panel_unprepare(&panel->base);
752
753 pm_runtime_dont_use_autosuspend(dev);
754 pm_runtime_disable(dev);
755 if (panel->ddc)
756 put_device(&panel->ddc->dev);
757}
758
759static void panel_simple_shutdown(struct device *dev)
760{
761 struct panel_simple *panel = dev_get_drvdata(dev);
762
763 drm_panel_disable(&panel->base);
764 drm_panel_unprepare(&panel->base);
765}
766
767static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
768 .clock = 71100,
769 .hdisplay = 1280,
770 .hsync_start = 1280 + 40,
771 .hsync_end = 1280 + 40 + 80,
772 .htotal = 1280 + 40 + 80 + 40,
773 .vdisplay = 800,
774 .vsync_start = 800 + 3,
775 .vsync_end = 800 + 3 + 10,
776 .vtotal = 800 + 3 + 10 + 10,
777 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
778};
779
780static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
781 .modes = &ire_am_1280800n3tzqw_t00h_mode,
782 .num_modes = 1,
783 .bpc = 8,
784 .size = {
785 .width = 217,
786 .height = 136,
787 },
788 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
789 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
790 .connector_type = DRM_MODE_CONNECTOR_LVDS,
791};
792
793static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
794 .clock = 9000,
795 .hdisplay = 480,
796 .hsync_start = 480 + 2,
797 .hsync_end = 480 + 2 + 41,
798 .htotal = 480 + 2 + 41 + 2,
799 .vdisplay = 272,
800 .vsync_start = 272 + 2,
801 .vsync_end = 272 + 2 + 10,
802 .vtotal = 272 + 2 + 10 + 2,
803 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
804};
805
806static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
807 .modes = &ire_am_480272h3tmqw_t01h_mode,
808 .num_modes = 1,
809 .bpc = 8,
810 .size = {
811 .width = 99,
812 .height = 58,
813 },
814 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
815};
816
817static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
818 .clock = 33333,
819 .hdisplay = 800,
820 .hsync_start = 800 + 0,
821 .hsync_end = 800 + 0 + 255,
822 .htotal = 800 + 0 + 255 + 0,
823 .vdisplay = 480,
824 .vsync_start = 480 + 2,
825 .vsync_end = 480 + 2 + 45,
826 .vtotal = 480 + 2 + 45 + 0,
827 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
828};
829
830static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = {
831 .pixelclock = { 29930000, 33260000, 36590000 },
832 .hactive = { 800, 800, 800 },
833 .hfront_porch = { 1, 40, 168 },
834 .hback_porch = { 88, 88, 88 },
835 .hsync_len = { 1, 128, 128 },
836 .vactive = { 480, 480, 480 },
837 .vfront_porch = { 1, 35, 37 },
838 .vback_porch = { 8, 8, 8 },
839 .vsync_len = { 1, 2, 2 },
840 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
841 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
842 DISPLAY_FLAGS_SYNC_POSEDGE,
843};
844
845static const struct panel_desc ampire_am_800480l1tmqw_t00h = {
846 .timings = &ire_am_800480l1tmqw_t00h_timing,
847 .num_timings = 1,
848 .bpc = 8,
849 .size = {
850 .width = 111,
851 .height = 67,
852 },
853 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
854 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
855 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
856 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
857 .connector_type = DRM_MODE_CONNECTOR_DPI,
858};
859
860static const struct panel_desc ampire_am800480r3tmqwa1h = {
861 .modes = &ire_am800480r3tmqwa1h_mode,
862 .num_modes = 1,
863 .bpc = 6,
864 .size = {
865 .width = 152,
866 .height = 91,
867 },
868 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
869};
870
871static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = {
872 .pixelclock = { 34500000, 39600000, 50400000 },
873 .hactive = { 800, 800, 800 },
874 .hfront_porch = { 12, 112, 312 },
875 .hback_porch = { 87, 87, 48 },
876 .hsync_len = { 1, 1, 40 },
877 .vactive = { 600, 600, 600 },
878 .vfront_porch = { 1, 21, 61 },
879 .vback_porch = { 38, 38, 19 },
880 .vsync_len = { 1, 1, 20 },
881 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
882 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
883 DISPLAY_FLAGS_SYNC_POSEDGE,
884};
885
886static const struct panel_desc ampire_am800600p5tmqwtb8h = {
887 .timings = &ire_am800600p5tmqw_tb8h_timing,
888 .num_timings = 1,
889 .bpc = 6,
890 .size = {
891 .width = 162,
892 .height = 122,
893 },
894 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
895 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
896 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
897 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
898 .connector_type = DRM_MODE_CONNECTOR_DPI,
899};
900
901static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
902 .pixelclock = { 26400000, 33300000, 46800000 },
903 .hactive = { 800, 800, 800 },
904 .hfront_porch = { 16, 210, 354 },
905 .hback_porch = { 45, 36, 6 },
906 .hsync_len = { 1, 10, 40 },
907 .vactive = { 480, 480, 480 },
908 .vfront_porch = { 7, 22, 147 },
909 .vback_porch = { 22, 13, 3 },
910 .vsync_len = { 1, 10, 20 },
911 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
912 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
913};
914
915static const struct panel_desc armadeus_st0700_adapt = {
916 .timings = &santek_st0700i5y_rbslw_f_timing,
917 .num_timings = 1,
918 .bpc = 6,
919 .size = {
920 .width = 154,
921 .height = 86,
922 },
923 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
924 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
925};
926
927static const struct drm_display_mode auo_b101aw03_mode = {
928 .clock = 51450,
929 .hdisplay = 1024,
930 .hsync_start = 1024 + 156,
931 .hsync_end = 1024 + 156 + 8,
932 .htotal = 1024 + 156 + 8 + 156,
933 .vdisplay = 600,
934 .vsync_start = 600 + 16,
935 .vsync_end = 600 + 16 + 6,
936 .vtotal = 600 + 16 + 6 + 16,
937};
938
939static const struct panel_desc auo_b101aw03 = {
940 .modes = &auo_b101aw03_mode,
941 .num_modes = 1,
942 .bpc = 6,
943 .size = {
944 .width = 223,
945 .height = 125,
946 },
947 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
948 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
949 .connector_type = DRM_MODE_CONNECTOR_LVDS,
950};
951
952static const struct drm_display_mode auo_b101xtn01_mode = {
953 .clock = 72000,
954 .hdisplay = 1366,
955 .hsync_start = 1366 + 20,
956 .hsync_end = 1366 + 20 + 70,
957 .htotal = 1366 + 20 + 70,
958 .vdisplay = 768,
959 .vsync_start = 768 + 14,
960 .vsync_end = 768 + 14 + 42,
961 .vtotal = 768 + 14 + 42,
962 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
963};
964
965static const struct panel_desc auo_b101xtn01 = {
966 .modes = &auo_b101xtn01_mode,
967 .num_modes = 1,
968 .bpc = 6,
969 .size = {
970 .width = 223,
971 .height = 125,
972 },
973};
974
975static const struct drm_display_mode auo_b116xw03_mode = {
976 .clock = 70589,
977 .hdisplay = 1366,
978 .hsync_start = 1366 + 40,
979 .hsync_end = 1366 + 40 + 40,
980 .htotal = 1366 + 40 + 40 + 32,
981 .vdisplay = 768,
982 .vsync_start = 768 + 10,
983 .vsync_end = 768 + 10 + 12,
984 .vtotal = 768 + 10 + 12 + 6,
985 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
986};
987
988static const struct panel_desc auo_b116xw03 = {
989 .modes = &auo_b116xw03_mode,
990 .num_modes = 1,
991 .bpc = 6,
992 .size = {
993 .width = 256,
994 .height = 144,
995 },
996 .delay = {
997 .prepare = 1,
998 .enable = 200,
999 .disable = 200,
1000 .unprepare = 500,
1001 },
1002 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1003 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1004 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1005};
1006
1007static const struct display_timing auo_g070vvn01_timings = {
1008 .pixelclock = { 33300000, 34209000, 45000000 },
1009 .hactive = { 800, 800, 800 },
1010 .hfront_porch = { 20, 40, 200 },
1011 .hback_porch = { 87, 40, 1 },
1012 .hsync_len = { 1, 48, 87 },
1013 .vactive = { 480, 480, 480 },
1014 .vfront_porch = { 5, 13, 200 },
1015 .vback_porch = { 31, 31, 29 },
1016 .vsync_len = { 1, 1, 3 },
1017};
1018
1019static const struct panel_desc auo_g070vvn01 = {
1020 .timings = &auo_g070vvn01_timings,
1021 .num_timings = 1,
1022 .bpc = 8,
1023 .size = {
1024 .width = 152,
1025 .height = 91,
1026 },
1027 .delay = {
1028 .prepare = 200,
1029 .enable = 50,
1030 .disable = 50,
1031 .unprepare = 1000,
1032 },
1033};
1034
1035static const struct drm_display_mode auo_g101evn010_mode = {
1036 .clock = 68930,
1037 .hdisplay = 1280,
1038 .hsync_start = 1280 + 82,
1039 .hsync_end = 1280 + 82 + 2,
1040 .htotal = 1280 + 82 + 2 + 84,
1041 .vdisplay = 800,
1042 .vsync_start = 800 + 8,
1043 .vsync_end = 800 + 8 + 2,
1044 .vtotal = 800 + 8 + 2 + 6,
1045};
1046
1047static const struct panel_desc auo_g101evn010 = {
1048 .modes = &auo_g101evn010_mode,
1049 .num_modes = 1,
1050 .bpc = 6,
1051 .size = {
1052 .width = 216,
1053 .height = 135,
1054 },
1055 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1056 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1057};
1058
1059static const struct drm_display_mode auo_g104sn02_mode = {
1060 .clock = 40000,
1061 .hdisplay = 800,
1062 .hsync_start = 800 + 40,
1063 .hsync_end = 800 + 40 + 216,
1064 .htotal = 800 + 40 + 216 + 128,
1065 .vdisplay = 600,
1066 .vsync_start = 600 + 10,
1067 .vsync_end = 600 + 10 + 35,
1068 .vtotal = 600 + 10 + 35 + 2,
1069};
1070
1071static const struct panel_desc auo_g104sn02 = {
1072 .modes = &auo_g104sn02_mode,
1073 .num_modes = 1,
1074 .bpc = 8,
1075 .size = {
1076 .width = 211,
1077 .height = 158,
1078 },
1079 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1080 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1081};
1082
1083static const struct display_timing auo_g121ean01_timing = {
1084 .pixelclock = { 60000000, 74400000, 90000000 },
1085 .hactive = { 1280, 1280, 1280 },
1086 .hfront_porch = { 20, 50, 100 },
1087 .hback_porch = { 20, 50, 100 },
1088 .hsync_len = { 30, 100, 200 },
1089 .vactive = { 800, 800, 800 },
1090 .vfront_porch = { 2, 10, 25 },
1091 .vback_porch = { 2, 10, 25 },
1092 .vsync_len = { 4, 18, 50 },
1093};
1094
1095static const struct panel_desc auo_g121ean01 = {
1096 .timings = &auo_g121ean01_timing,
1097 .num_timings = 1,
1098 .bpc = 8,
1099 .size = {
1100 .width = 261,
1101 .height = 163,
1102 },
1103 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1104 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1105};
1106
1107static const struct display_timing auo_g133han01_timings = {
1108 .pixelclock = { 134000000, 141200000, 149000000 },
1109 .hactive = { 1920, 1920, 1920 },
1110 .hfront_porch = { 39, 58, 77 },
1111 .hback_porch = { 59, 88, 117 },
1112 .hsync_len = { 28, 42, 56 },
1113 .vactive = { 1080, 1080, 1080 },
1114 .vfront_porch = { 3, 8, 11 },
1115 .vback_porch = { 5, 14, 19 },
1116 .vsync_len = { 4, 14, 19 },
1117};
1118
1119static const struct panel_desc auo_g133han01 = {
1120 .timings = &auo_g133han01_timings,
1121 .num_timings = 1,
1122 .bpc = 8,
1123 .size = {
1124 .width = 293,
1125 .height = 165,
1126 },
1127 .delay = {
1128 .prepare = 200,
1129 .enable = 50,
1130 .disable = 50,
1131 .unprepare = 1000,
1132 },
1133 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1134 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1135};
1136
1137static const struct display_timing auo_g156han04_timings = {
1138 .pixelclock = { 137000000, 141000000, 146000000 },
1139 .hactive = { 1920, 1920, 1920 },
1140 .hfront_porch = { 60, 60, 60 },
1141 .hback_porch = { 90, 92, 111 },
1142 .hsync_len = { 32, 32, 32 },
1143 .vactive = { 1080, 1080, 1080 },
1144 .vfront_porch = { 12, 12, 12 },
1145 .vback_porch = { 24, 36, 56 },
1146 .vsync_len = { 8, 8, 8 },
1147};
1148
1149static const struct panel_desc auo_g156han04 = {
1150 .timings = &auo_g156han04_timings,
1151 .num_timings = 1,
1152 .bpc = 8,
1153 .size = {
1154 .width = 344,
1155 .height = 194,
1156 },
1157 .delay = {
1158 .prepare = 50, /* T2 */
1159 .enable = 200, /* T3 */
1160 .disable = 110, /* T10 */
1161 .unprepare = 1000, /* T13 */
1162 },
1163 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1164 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1165 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1166};
1167
1168static const struct drm_display_mode auo_g156xtn01_mode = {
1169 .clock = 76000,
1170 .hdisplay = 1366,
1171 .hsync_start = 1366 + 33,
1172 .hsync_end = 1366 + 33 + 67,
1173 .htotal = 1560,
1174 .vdisplay = 768,
1175 .vsync_start = 768 + 4,
1176 .vsync_end = 768 + 4 + 4,
1177 .vtotal = 806,
1178};
1179
1180static const struct panel_desc auo_g156xtn01 = {
1181 .modes = &auo_g156xtn01_mode,
1182 .num_modes = 1,
1183 .bpc = 8,
1184 .size = {
1185 .width = 344,
1186 .height = 194,
1187 },
1188 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1189 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1190};
1191
1192static const struct display_timing auo_g185han01_timings = {
1193 .pixelclock = { 120000000, 144000000, 175000000 },
1194 .hactive = { 1920, 1920, 1920 },
1195 .hfront_porch = { 36, 120, 148 },
1196 .hback_porch = { 24, 88, 108 },
1197 .hsync_len = { 20, 48, 64 },
1198 .vactive = { 1080, 1080, 1080 },
1199 .vfront_porch = { 6, 10, 40 },
1200 .vback_porch = { 2, 5, 20 },
1201 .vsync_len = { 2, 5, 20 },
1202};
1203
1204static const struct panel_desc auo_g185han01 = {
1205 .timings = &auo_g185han01_timings,
1206 .num_timings = 1,
1207 .bpc = 8,
1208 .size = {
1209 .width = 409,
1210 .height = 230,
1211 },
1212 .delay = {
1213 .prepare = 50,
1214 .enable = 200,
1215 .disable = 110,
1216 .unprepare = 1000,
1217 },
1218 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1219 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1220};
1221
1222static const struct display_timing auo_g190ean01_timings = {
1223 .pixelclock = { 90000000, 108000000, 135000000 },
1224 .hactive = { 1280, 1280, 1280 },
1225 .hfront_porch = { 126, 184, 1266 },
1226 .hback_porch = { 84, 122, 844 },
1227 .hsync_len = { 70, 102, 704 },
1228 .vactive = { 1024, 1024, 1024 },
1229 .vfront_porch = { 4, 26, 76 },
1230 .vback_porch = { 2, 8, 25 },
1231 .vsync_len = { 2, 8, 25 },
1232};
1233
1234static const struct panel_desc auo_g190ean01 = {
1235 .timings = &auo_g190ean01_timings,
1236 .num_timings = 1,
1237 .bpc = 8,
1238 .size = {
1239 .width = 376,
1240 .height = 301,
1241 },
1242 .delay = {
1243 .prepare = 50,
1244 .enable = 200,
1245 .disable = 110,
1246 .unprepare = 1000,
1247 },
1248 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1249 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1250};
1251
1252static const struct display_timing auo_p320hvn03_timings = {
1253 .pixelclock = { 106000000, 148500000, 164000000 },
1254 .hactive = { 1920, 1920, 1920 },
1255 .hfront_porch = { 25, 50, 130 },
1256 .hback_porch = { 25, 50, 130 },
1257 .hsync_len = { 20, 40, 105 },
1258 .vactive = { 1080, 1080, 1080 },
1259 .vfront_porch = { 8, 17, 150 },
1260 .vback_porch = { 8, 17, 150 },
1261 .vsync_len = { 4, 11, 100 },
1262};
1263
1264static const struct panel_desc auo_p320hvn03 = {
1265 .timings = &auo_p320hvn03_timings,
1266 .num_timings = 1,
1267 .bpc = 8,
1268 .size = {
1269 .width = 698,
1270 .height = 393,
1271 },
1272 .delay = {
1273 .prepare = 1,
1274 .enable = 450,
1275 .unprepare = 500,
1276 },
1277 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1278 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1279};
1280
1281static const struct drm_display_mode auo_t215hvn01_mode = {
1282 .clock = 148800,
1283 .hdisplay = 1920,
1284 .hsync_start = 1920 + 88,
1285 .hsync_end = 1920 + 88 + 44,
1286 .htotal = 1920 + 88 + 44 + 148,
1287 .vdisplay = 1080,
1288 .vsync_start = 1080 + 4,
1289 .vsync_end = 1080 + 4 + 5,
1290 .vtotal = 1080 + 4 + 5 + 36,
1291};
1292
1293static const struct panel_desc auo_t215hvn01 = {
1294 .modes = &auo_t215hvn01_mode,
1295 .num_modes = 1,
1296 .bpc = 8,
1297 .size = {
1298 .width = 430,
1299 .height = 270,
1300 },
1301 .delay = {
1302 .disable = 5,
1303 .unprepare = 1000,
1304 },
1305 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1306 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1307};
1308
1309static const struct drm_display_mode avic_tm070ddh03_mode = {
1310 .clock = 51200,
1311 .hdisplay = 1024,
1312 .hsync_start = 1024 + 160,
1313 .hsync_end = 1024 + 160 + 4,
1314 .htotal = 1024 + 160 + 4 + 156,
1315 .vdisplay = 600,
1316 .vsync_start = 600 + 17,
1317 .vsync_end = 600 + 17 + 1,
1318 .vtotal = 600 + 17 + 1 + 17,
1319};
1320
1321static const struct panel_desc avic_tm070ddh03 = {
1322 .modes = &avic_tm070ddh03_mode,
1323 .num_modes = 1,
1324 .bpc = 8,
1325 .size = {
1326 .width = 154,
1327 .height = 90,
1328 },
1329 .delay = {
1330 .prepare = 20,
1331 .enable = 200,
1332 .disable = 200,
1333 },
1334};
1335
1336static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1337 .clock = 30000,
1338 .hdisplay = 800,
1339 .hsync_start = 800 + 40,
1340 .hsync_end = 800 + 40 + 48,
1341 .htotal = 800 + 40 + 48 + 40,
1342 .vdisplay = 480,
1343 .vsync_start = 480 + 13,
1344 .vsync_end = 480 + 13 + 3,
1345 .vtotal = 480 + 13 + 3 + 29,
1346};
1347
1348static const struct panel_desc bananapi_s070wv20_ct16 = {
1349 .modes = &bananapi_s070wv20_ct16_mode,
1350 .num_modes = 1,
1351 .bpc = 6,
1352 .size = {
1353 .width = 154,
1354 .height = 86,
1355 },
1356};
1357
1358static const struct drm_display_mode boe_bp101wx1_100_mode = {
1359 .clock = 78945,
1360 .hdisplay = 1280,
1361 .hsync_start = 1280 + 0,
1362 .hsync_end = 1280 + 0 + 2,
1363 .htotal = 1280 + 62 + 0 + 2,
1364 .vdisplay = 800,
1365 .vsync_start = 800 + 8,
1366 .vsync_end = 800 + 8 + 2,
1367 .vtotal = 800 + 6 + 8 + 2,
1368};
1369
1370static const struct panel_desc boe_bp101wx1_100 = {
1371 .modes = &boe_bp101wx1_100_mode,
1372 .num_modes = 1,
1373 .bpc = 8,
1374 .size = {
1375 .width = 217,
1376 .height = 136,
1377 },
1378 .delay = {
1379 .enable = 50,
1380 .disable = 50,
1381 },
1382 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1383 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1384 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1385};
1386
1387static const struct display_timing boe_ev121wxm_n10_1850_timing = {
1388 .pixelclock = { 69922000, 71000000, 72293000 },
1389 .hactive = { 1280, 1280, 1280 },
1390 .hfront_porch = { 48, 48, 48 },
1391 .hback_porch = { 80, 80, 80 },
1392 .hsync_len = { 32, 32, 32 },
1393 .vactive = { 800, 800, 800 },
1394 .vfront_porch = { 3, 3, 3 },
1395 .vback_porch = { 14, 14, 14 },
1396 .vsync_len = { 6, 6, 6 },
1397};
1398
1399static const struct panel_desc boe_ev121wxm_n10_1850 = {
1400 .timings = &boe_ev121wxm_n10_1850_timing,
1401 .num_timings = 1,
1402 .bpc = 8,
1403 .size = {
1404 .width = 261,
1405 .height = 163,
1406 },
1407 .delay = {
1408 .prepare = 9,
1409 .enable = 300,
1410 .unprepare = 300,
1411 .disable = 560,
1412 },
1413 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1414 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1415 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1416};
1417
1418static const struct drm_display_mode boe_hv070wsa_mode = {
1419 .clock = 42105,
1420 .hdisplay = 1024,
1421 .hsync_start = 1024 + 30,
1422 .hsync_end = 1024 + 30 + 30,
1423 .htotal = 1024 + 30 + 30 + 30,
1424 .vdisplay = 600,
1425 .vsync_start = 600 + 10,
1426 .vsync_end = 600 + 10 + 10,
1427 .vtotal = 600 + 10 + 10 + 10,
1428};
1429
1430static const struct panel_desc boe_hv070wsa = {
1431 .modes = &boe_hv070wsa_mode,
1432 .num_modes = 1,
1433 .bpc = 8,
1434 .size = {
1435 .width = 154,
1436 .height = 90,
1437 },
1438 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1439 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1440 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1441};
1442
1443static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1444 .clock = 9000,
1445 .hdisplay = 480,
1446 .hsync_start = 480 + 5,
1447 .hsync_end = 480 + 5 + 5,
1448 .htotal = 480 + 5 + 5 + 40,
1449 .vdisplay = 272,
1450 .vsync_start = 272 + 8,
1451 .vsync_end = 272 + 8 + 8,
1452 .vtotal = 272 + 8 + 8 + 8,
1453 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1454};
1455
1456static const struct panel_desc cdtech_s043wq26h_ct7 = {
1457 .modes = &cdtech_s043wq26h_ct7_mode,
1458 .num_modes = 1,
1459 .bpc = 8,
1460 .size = {
1461 .width = 95,
1462 .height = 54,
1463 },
1464 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1465};
1466
1467/* S070PWS19HP-FC21 2017/04/22 */
1468static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1469 .clock = 51200,
1470 .hdisplay = 1024,
1471 .hsync_start = 1024 + 160,
1472 .hsync_end = 1024 + 160 + 20,
1473 .htotal = 1024 + 160 + 20 + 140,
1474 .vdisplay = 600,
1475 .vsync_start = 600 + 12,
1476 .vsync_end = 600 + 12 + 3,
1477 .vtotal = 600 + 12 + 3 + 20,
1478 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1479};
1480
1481static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1482 .modes = &cdtech_s070pws19hp_fc21_mode,
1483 .num_modes = 1,
1484 .bpc = 6,
1485 .size = {
1486 .width = 154,
1487 .height = 86,
1488 },
1489 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1490 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1491 .connector_type = DRM_MODE_CONNECTOR_DPI,
1492};
1493
1494/* S070SWV29HG-DC44 2017/09/21 */
1495static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1496 .clock = 33300,
1497 .hdisplay = 800,
1498 .hsync_start = 800 + 210,
1499 .hsync_end = 800 + 210 + 2,
1500 .htotal = 800 + 210 + 2 + 44,
1501 .vdisplay = 480,
1502 .vsync_start = 480 + 22,
1503 .vsync_end = 480 + 22 + 2,
1504 .vtotal = 480 + 22 + 2 + 21,
1505 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1506};
1507
1508static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1509 .modes = &cdtech_s070swv29hg_dc44_mode,
1510 .num_modes = 1,
1511 .bpc = 6,
1512 .size = {
1513 .width = 154,
1514 .height = 86,
1515 },
1516 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1517 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1518 .connector_type = DRM_MODE_CONNECTOR_DPI,
1519};
1520
1521static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1522 .clock = 35000,
1523 .hdisplay = 800,
1524 .hsync_start = 800 + 40,
1525 .hsync_end = 800 + 40 + 40,
1526 .htotal = 800 + 40 + 40 + 48,
1527 .vdisplay = 480,
1528 .vsync_start = 480 + 29,
1529 .vsync_end = 480 + 29 + 13,
1530 .vtotal = 480 + 29 + 13 + 3,
1531 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1532};
1533
1534static const struct panel_desc cdtech_s070wv95_ct16 = {
1535 .modes = &cdtech_s070wv95_ct16_mode,
1536 .num_modes = 1,
1537 .bpc = 8,
1538 .size = {
1539 .width = 154,
1540 .height = 85,
1541 },
1542};
1543
1544static const struct display_timing chefree_ch101olhlwh_002_timing = {
1545 .pixelclock = { 68900000, 71100000, 73400000 },
1546 .hactive = { 1280, 1280, 1280 },
1547 .hfront_porch = { 65, 80, 95 },
1548 .hback_porch = { 64, 79, 94 },
1549 .hsync_len = { 1, 1, 1 },
1550 .vactive = { 800, 800, 800 },
1551 .vfront_porch = { 7, 11, 14 },
1552 .vback_porch = { 7, 11, 14 },
1553 .vsync_len = { 1, 1, 1 },
1554 .flags = DISPLAY_FLAGS_DE_HIGH,
1555};
1556
1557static const struct panel_desc chefree_ch101olhlwh_002 = {
1558 .timings = &chefree_ch101olhlwh_002_timing,
1559 .num_timings = 1,
1560 .bpc = 8,
1561 .size = {
1562 .width = 217,
1563 .height = 135,
1564 },
1565 .delay = {
1566 .enable = 200,
1567 .disable = 200,
1568 },
1569 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1570 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1571 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1572};
1573
1574static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1575 .clock = 66770,
1576 .hdisplay = 800,
1577 .hsync_start = 800 + 49,
1578 .hsync_end = 800 + 49 + 33,
1579 .htotal = 800 + 49 + 33 + 17,
1580 .vdisplay = 1280,
1581 .vsync_start = 1280 + 1,
1582 .vsync_end = 1280 + 1 + 7,
1583 .vtotal = 1280 + 1 + 7 + 15,
1584 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1585};
1586
1587static const struct panel_desc chunghwa_claa070wp03xg = {
1588 .modes = &chunghwa_claa070wp03xg_mode,
1589 .num_modes = 1,
1590 .bpc = 6,
1591 .size = {
1592 .width = 94,
1593 .height = 150,
1594 },
1595 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1596 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1597 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1598};
1599
1600static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1601 .clock = 72070,
1602 .hdisplay = 1366,
1603 .hsync_start = 1366 + 58,
1604 .hsync_end = 1366 + 58 + 58,
1605 .htotal = 1366 + 58 + 58 + 58,
1606 .vdisplay = 768,
1607 .vsync_start = 768 + 4,
1608 .vsync_end = 768 + 4 + 4,
1609 .vtotal = 768 + 4 + 4 + 4,
1610};
1611
1612static const struct panel_desc chunghwa_claa101wa01a = {
1613 .modes = &chunghwa_claa101wa01a_mode,
1614 .num_modes = 1,
1615 .bpc = 6,
1616 .size = {
1617 .width = 220,
1618 .height = 120,
1619 },
1620 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1621 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1622 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1623};
1624
1625static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1626 .clock = 69300,
1627 .hdisplay = 1366,
1628 .hsync_start = 1366 + 48,
1629 .hsync_end = 1366 + 48 + 32,
1630 .htotal = 1366 + 48 + 32 + 20,
1631 .vdisplay = 768,
1632 .vsync_start = 768 + 16,
1633 .vsync_end = 768 + 16 + 8,
1634 .vtotal = 768 + 16 + 8 + 16,
1635};
1636
1637static const struct panel_desc chunghwa_claa101wb01 = {
1638 .modes = &chunghwa_claa101wb01_mode,
1639 .num_modes = 1,
1640 .bpc = 6,
1641 .size = {
1642 .width = 223,
1643 .height = 125,
1644 },
1645 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1646 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1647 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1648};
1649
1650static const struct display_timing dataimage_fg040346dsswbg04_timing = {
1651 .pixelclock = { 5000000, 9000000, 12000000 },
1652 .hactive = { 480, 480, 480 },
1653 .hfront_porch = { 12, 12, 12 },
1654 .hback_porch = { 12, 12, 12 },
1655 .hsync_len = { 21, 21, 21 },
1656 .vactive = { 272, 272, 272 },
1657 .vfront_porch = { 4, 4, 4 },
1658 .vback_porch = { 4, 4, 4 },
1659 .vsync_len = { 8, 8, 8 },
1660};
1661
1662static const struct panel_desc dataimage_fg040346dsswbg04 = {
1663 .timings = &dataimage_fg040346dsswbg04_timing,
1664 .num_timings = 1,
1665 .bpc = 8,
1666 .size = {
1667 .width = 95,
1668 .height = 54,
1669 },
1670 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1671 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1672 .connector_type = DRM_MODE_CONNECTOR_DPI,
1673};
1674
1675static const struct display_timing dataimage_fg1001l0dsswmg01_timing = {
1676 .pixelclock = { 68900000, 71110000, 73400000 },
1677 .hactive = { 1280, 1280, 1280 },
1678 .vactive = { 800, 800, 800 },
1679 .hback_porch = { 100, 100, 100 },
1680 .hfront_porch = { 100, 100, 100 },
1681 .vback_porch = { 5, 5, 5 },
1682 .vfront_porch = { 5, 5, 5 },
1683 .hsync_len = { 24, 24, 24 },
1684 .vsync_len = { 3, 3, 3 },
1685 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
1686 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1687};
1688
1689static const struct panel_desc dataimage_fg1001l0dsswmg01 = {
1690 .timings = &dataimage_fg1001l0dsswmg01_timing,
1691 .num_timings = 1,
1692 .bpc = 8,
1693 .size = {
1694 .width = 217,
1695 .height = 136,
1696 },
1697};
1698
1699static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1700 .clock = 33260,
1701 .hdisplay = 800,
1702 .hsync_start = 800 + 40,
1703 .hsync_end = 800 + 40 + 128,
1704 .htotal = 800 + 40 + 128 + 88,
1705 .vdisplay = 480,
1706 .vsync_start = 480 + 10,
1707 .vsync_end = 480 + 10 + 2,
1708 .vtotal = 480 + 10 + 2 + 33,
1709 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1710};
1711
1712static const struct panel_desc dataimage_scf0700c48ggu18 = {
1713 .modes = &dataimage_scf0700c48ggu18_mode,
1714 .num_modes = 1,
1715 .bpc = 8,
1716 .size = {
1717 .width = 152,
1718 .height = 91,
1719 },
1720 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1721 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1722};
1723
1724static const struct display_timing dlc_dlc0700yzg_1_timing = {
1725 .pixelclock = { 45000000, 51200000, 57000000 },
1726 .hactive = { 1024, 1024, 1024 },
1727 .hfront_porch = { 100, 106, 113 },
1728 .hback_porch = { 100, 106, 113 },
1729 .hsync_len = { 100, 108, 114 },
1730 .vactive = { 600, 600, 600 },
1731 .vfront_porch = { 8, 11, 15 },
1732 .vback_porch = { 8, 11, 15 },
1733 .vsync_len = { 9, 13, 15 },
1734 .flags = DISPLAY_FLAGS_DE_HIGH,
1735};
1736
1737static const struct panel_desc dlc_dlc0700yzg_1 = {
1738 .timings = &dlc_dlc0700yzg_1_timing,
1739 .num_timings = 1,
1740 .bpc = 6,
1741 .size = {
1742 .width = 154,
1743 .height = 86,
1744 },
1745 .delay = {
1746 .prepare = 30,
1747 .enable = 200,
1748 .disable = 200,
1749 },
1750 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1751 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1752};
1753
1754static const struct display_timing dlc_dlc1010gig_timing = {
1755 .pixelclock = { 68900000, 71100000, 73400000 },
1756 .hactive = { 1280, 1280, 1280 },
1757 .hfront_porch = { 43, 53, 63 },
1758 .hback_porch = { 43, 53, 63 },
1759 .hsync_len = { 44, 54, 64 },
1760 .vactive = { 800, 800, 800 },
1761 .vfront_porch = { 5, 8, 11 },
1762 .vback_porch = { 5, 8, 11 },
1763 .vsync_len = { 5, 7, 11 },
1764 .flags = DISPLAY_FLAGS_DE_HIGH,
1765};
1766
1767static const struct panel_desc dlc_dlc1010gig = {
1768 .timings = &dlc_dlc1010gig_timing,
1769 .num_timings = 1,
1770 .bpc = 8,
1771 .size = {
1772 .width = 216,
1773 .height = 135,
1774 },
1775 .delay = {
1776 .prepare = 60,
1777 .enable = 150,
1778 .disable = 100,
1779 .unprepare = 60,
1780 },
1781 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1782 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1783};
1784
1785static const struct drm_display_mode edt_et035012dm6_mode = {
1786 .clock = 6500,
1787 .hdisplay = 320,
1788 .hsync_start = 320 + 20,
1789 .hsync_end = 320 + 20 + 30,
1790 .htotal = 320 + 20 + 68,
1791 .vdisplay = 240,
1792 .vsync_start = 240 + 4,
1793 .vsync_end = 240 + 4 + 4,
1794 .vtotal = 240 + 4 + 4 + 14,
1795 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1796};
1797
1798static const struct panel_desc edt_et035012dm6 = {
1799 .modes = &edt_et035012dm6_mode,
1800 .num_modes = 1,
1801 .bpc = 8,
1802 .size = {
1803 .width = 70,
1804 .height = 52,
1805 },
1806 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1807 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1808};
1809
1810static const struct drm_display_mode edt_etm0350g0dh6_mode = {
1811 .clock = 6520,
1812 .hdisplay = 320,
1813 .hsync_start = 320 + 20,
1814 .hsync_end = 320 + 20 + 68,
1815 .htotal = 320 + 20 + 68,
1816 .vdisplay = 240,
1817 .vsync_start = 240 + 4,
1818 .vsync_end = 240 + 4 + 18,
1819 .vtotal = 240 + 4 + 18,
1820 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1821};
1822
1823static const struct panel_desc edt_etm0350g0dh6 = {
1824 .modes = &edt_etm0350g0dh6_mode,
1825 .num_modes = 1,
1826 .bpc = 6,
1827 .size = {
1828 .width = 70,
1829 .height = 53,
1830 },
1831 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1832 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1833 .connector_type = DRM_MODE_CONNECTOR_DPI,
1834};
1835
1836static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1837 .clock = 10870,
1838 .hdisplay = 480,
1839 .hsync_start = 480 + 8,
1840 .hsync_end = 480 + 8 + 4,
1841 .htotal = 480 + 8 + 4 + 41,
1842
1843 /*
1844 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1845 * fb_align
1846 */
1847
1848 .vdisplay = 288,
1849 .vsync_start = 288 + 2,
1850 .vsync_end = 288 + 2 + 4,
1851 .vtotal = 288 + 2 + 4 + 10,
1852};
1853
1854static const struct panel_desc edt_etm043080dh6gp = {
1855 .modes = &edt_etm043080dh6gp_mode,
1856 .num_modes = 1,
1857 .bpc = 8,
1858 .size = {
1859 .width = 100,
1860 .height = 65,
1861 },
1862 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1863 .connector_type = DRM_MODE_CONNECTOR_DPI,
1864};
1865
1866static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1867 .clock = 9000,
1868 .hdisplay = 480,
1869 .hsync_start = 480 + 2,
1870 .hsync_end = 480 + 2 + 41,
1871 .htotal = 480 + 2 + 41 + 2,
1872 .vdisplay = 272,
1873 .vsync_start = 272 + 2,
1874 .vsync_end = 272 + 2 + 10,
1875 .vtotal = 272 + 2 + 10 + 2,
1876 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1877};
1878
1879static const struct panel_desc edt_etm0430g0dh6 = {
1880 .modes = &edt_etm0430g0dh6_mode,
1881 .num_modes = 1,
1882 .bpc = 6,
1883 .size = {
1884 .width = 95,
1885 .height = 54,
1886 },
1887 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1888 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1889 .connector_type = DRM_MODE_CONNECTOR_DPI,
1890};
1891
1892static const struct drm_display_mode edt_et057090dhu_mode = {
1893 .clock = 25175,
1894 .hdisplay = 640,
1895 .hsync_start = 640 + 16,
1896 .hsync_end = 640 + 16 + 30,
1897 .htotal = 640 + 16 + 30 + 114,
1898 .vdisplay = 480,
1899 .vsync_start = 480 + 10,
1900 .vsync_end = 480 + 10 + 3,
1901 .vtotal = 480 + 10 + 3 + 32,
1902 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1903};
1904
1905static const struct panel_desc edt_et057090dhu = {
1906 .modes = &edt_et057090dhu_mode,
1907 .num_modes = 1,
1908 .bpc = 6,
1909 .size = {
1910 .width = 115,
1911 .height = 86,
1912 },
1913 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1914 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1915 .connector_type = DRM_MODE_CONNECTOR_DPI,
1916};
1917
1918static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1919 .clock = 33260,
1920 .hdisplay = 800,
1921 .hsync_start = 800 + 40,
1922 .hsync_end = 800 + 40 + 128,
1923 .htotal = 800 + 40 + 128 + 88,
1924 .vdisplay = 480,
1925 .vsync_start = 480 + 10,
1926 .vsync_end = 480 + 10 + 2,
1927 .vtotal = 480 + 10 + 2 + 33,
1928 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1929};
1930
1931static const struct panel_desc edt_etm0700g0dh6 = {
1932 .modes = &edt_etm0700g0dh6_mode,
1933 .num_modes = 1,
1934 .bpc = 6,
1935 .size = {
1936 .width = 152,
1937 .height = 91,
1938 },
1939 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1940 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1941 .connector_type = DRM_MODE_CONNECTOR_DPI,
1942};
1943
1944static const struct panel_desc edt_etm0700g0bdh6 = {
1945 .modes = &edt_etm0700g0dh6_mode,
1946 .num_modes = 1,
1947 .bpc = 6,
1948 .size = {
1949 .width = 152,
1950 .height = 91,
1951 },
1952 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1953 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1954 .connector_type = DRM_MODE_CONNECTOR_DPI,
1955};
1956
1957static const struct display_timing edt_etml0700y5dha_timing = {
1958 .pixelclock = { 40800000, 51200000, 67200000 },
1959 .hactive = { 1024, 1024, 1024 },
1960 .hfront_porch = { 30, 106, 125 },
1961 .hback_porch = { 30, 106, 125 },
1962 .hsync_len = { 30, 108, 126 },
1963 .vactive = { 600, 600, 600 },
1964 .vfront_porch = { 3, 12, 67},
1965 .vback_porch = { 3, 12, 67 },
1966 .vsync_len = { 4, 11, 66 },
1967 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
1968 DISPLAY_FLAGS_DE_HIGH,
1969};
1970
1971static const struct panel_desc edt_etml0700y5dha = {
1972 .timings = &edt_etml0700y5dha_timing,
1973 .num_timings = 1,
1974 .bpc = 8,
1975 .size = {
1976 .width = 155,
1977 .height = 86,
1978 },
1979 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1980 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1981};
1982
1983static const struct drm_display_mode edt_etmv570g2dhu_mode = {
1984 .clock = 25175,
1985 .hdisplay = 640,
1986 .hsync_start = 640,
1987 .hsync_end = 640 + 16,
1988 .htotal = 640 + 16 + 30 + 114,
1989 .vdisplay = 480,
1990 .vsync_start = 480 + 10,
1991 .vsync_end = 480 + 10 + 3,
1992 .vtotal = 480 + 10 + 3 + 35,
1993 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC,
1994};
1995
1996static const struct panel_desc edt_etmv570g2dhu = {
1997 .modes = &edt_etmv570g2dhu_mode,
1998 .num_modes = 1,
1999 .bpc = 6,
2000 .size = {
2001 .width = 115,
2002 .height = 86,
2003 },
2004 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2005 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
2006 .connector_type = DRM_MODE_CONNECTOR_DPI,
2007};
2008
2009static const struct display_timing eink_vb3300_kca_timing = {
2010 .pixelclock = { 40000000, 40000000, 40000000 },
2011 .hactive = { 334, 334, 334 },
2012 .hfront_porch = { 1, 1, 1 },
2013 .hback_porch = { 1, 1, 1 },
2014 .hsync_len = { 1, 1, 1 },
2015 .vactive = { 1405, 1405, 1405 },
2016 .vfront_porch = { 1, 1, 1 },
2017 .vback_porch = { 1, 1, 1 },
2018 .vsync_len = { 1, 1, 1 },
2019 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2020 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
2021};
2022
2023static const struct panel_desc eink_vb3300_kca = {
2024 .timings = &eink_vb3300_kca_timing,
2025 .num_timings = 1,
2026 .bpc = 6,
2027 .size = {
2028 .width = 157,
2029 .height = 209,
2030 },
2031 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2032 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2033 .connector_type = DRM_MODE_CONNECTOR_DPI,
2034};
2035
2036static const struct display_timing evervision_vgg644804_timing = {
2037 .pixelclock = { 25175000, 25175000, 25175000 },
2038 .hactive = { 640, 640, 640 },
2039 .hfront_porch = { 16, 16, 16 },
2040 .hback_porch = { 82, 114, 170 },
2041 .hsync_len = { 5, 30, 30 },
2042 .vactive = { 480, 480, 480 },
2043 .vfront_porch = { 10, 10, 10 },
2044 .vback_porch = { 30, 32, 34 },
2045 .vsync_len = { 1, 3, 5 },
2046 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2047 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2048 DISPLAY_FLAGS_SYNC_POSEDGE,
2049};
2050
2051static const struct panel_desc evervision_vgg644804 = {
2052 .timings = &evervision_vgg644804_timing,
2053 .num_timings = 1,
2054 .bpc = 8,
2055 .size = {
2056 .width = 115,
2057 .height = 86,
2058 },
2059 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2060 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2061};
2062
2063static const struct display_timing evervision_vgg804821_timing = {
2064 .pixelclock = { 27600000, 33300000, 50000000 },
2065 .hactive = { 800, 800, 800 },
2066 .hfront_porch = { 40, 66, 70 },
2067 .hback_porch = { 40, 67, 70 },
2068 .hsync_len = { 40, 67, 70 },
2069 .vactive = { 480, 480, 480 },
2070 .vfront_porch = { 6, 10, 10 },
2071 .vback_porch = { 7, 11, 11 },
2072 .vsync_len = { 7, 11, 11 },
2073 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
2074 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
2075 DISPLAY_FLAGS_SYNC_NEGEDGE,
2076};
2077
2078static const struct panel_desc evervision_vgg804821 = {
2079 .timings = &evervision_vgg804821_timing,
2080 .num_timings = 1,
2081 .bpc = 8,
2082 .size = {
2083 .width = 108,
2084 .height = 64,
2085 },
2086 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2087 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2088};
2089
2090static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
2091 .clock = 32260,
2092 .hdisplay = 800,
2093 .hsync_start = 800 + 168,
2094 .hsync_end = 800 + 168 + 64,
2095 .htotal = 800 + 168 + 64 + 88,
2096 .vdisplay = 480,
2097 .vsync_start = 480 + 37,
2098 .vsync_end = 480 + 37 + 2,
2099 .vtotal = 480 + 37 + 2 + 8,
2100};
2101
2102static const struct panel_desc foxlink_fl500wvr00_a0t = {
2103 .modes = &foxlink_fl500wvr00_a0t_mode,
2104 .num_modes = 1,
2105 .bpc = 8,
2106 .size = {
2107 .width = 108,
2108 .height = 65,
2109 },
2110 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2111};
2112
2113static const struct drm_display_mode frida_frd350h54004_modes[] = {
2114 { /* 60 Hz */
2115 .clock = 6000,
2116 .hdisplay = 320,
2117 .hsync_start = 320 + 44,
2118 .hsync_end = 320 + 44 + 16,
2119 .htotal = 320 + 44 + 16 + 20,
2120 .vdisplay = 240,
2121 .vsync_start = 240 + 2,
2122 .vsync_end = 240 + 2 + 6,
2123 .vtotal = 240 + 2 + 6 + 2,
2124 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2125 },
2126 { /* 50 Hz */
2127 .clock = 5400,
2128 .hdisplay = 320,
2129 .hsync_start = 320 + 56,
2130 .hsync_end = 320 + 56 + 16,
2131 .htotal = 320 + 56 + 16 + 40,
2132 .vdisplay = 240,
2133 .vsync_start = 240 + 2,
2134 .vsync_end = 240 + 2 + 6,
2135 .vtotal = 240 + 2 + 6 + 2,
2136 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2137 },
2138};
2139
2140static const struct panel_desc frida_frd350h54004 = {
2141 .modes = frida_frd350h54004_modes,
2142 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
2143 .bpc = 8,
2144 .size = {
2145 .width = 77,
2146 .height = 64,
2147 },
2148 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2149 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2150 .connector_type = DRM_MODE_CONNECTOR_DPI,
2151};
2152
2153static const struct drm_display_mode friendlyarm_hd702e_mode = {
2154 .clock = 67185,
2155 .hdisplay = 800,
2156 .hsync_start = 800 + 20,
2157 .hsync_end = 800 + 20 + 24,
2158 .htotal = 800 + 20 + 24 + 20,
2159 .vdisplay = 1280,
2160 .vsync_start = 1280 + 4,
2161 .vsync_end = 1280 + 4 + 8,
2162 .vtotal = 1280 + 4 + 8 + 4,
2163 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2164};
2165
2166static const struct panel_desc friendlyarm_hd702e = {
2167 .modes = &friendlyarm_hd702e_mode,
2168 .num_modes = 1,
2169 .size = {
2170 .width = 94,
2171 .height = 151,
2172 },
2173};
2174
2175static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
2176 .clock = 9000,
2177 .hdisplay = 480,
2178 .hsync_start = 480 + 5,
2179 .hsync_end = 480 + 5 + 1,
2180 .htotal = 480 + 5 + 1 + 40,
2181 .vdisplay = 272,
2182 .vsync_start = 272 + 8,
2183 .vsync_end = 272 + 8 + 1,
2184 .vtotal = 272 + 8 + 1 + 8,
2185};
2186
2187static const struct panel_desc giantplus_gpg482739qs5 = {
2188 .modes = &giantplus_gpg482739qs5_mode,
2189 .num_modes = 1,
2190 .bpc = 8,
2191 .size = {
2192 .width = 95,
2193 .height = 54,
2194 },
2195 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2196};
2197
2198static const struct display_timing giantplus_gpm940b0_timing = {
2199 .pixelclock = { 13500000, 27000000, 27500000 },
2200 .hactive = { 320, 320, 320 },
2201 .hfront_porch = { 14, 686, 718 },
2202 .hback_porch = { 50, 70, 255 },
2203 .hsync_len = { 1, 1, 1 },
2204 .vactive = { 240, 240, 240 },
2205 .vfront_porch = { 1, 1, 179 },
2206 .vback_porch = { 1, 21, 31 },
2207 .vsync_len = { 1, 1, 6 },
2208 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2209};
2210
2211static const struct panel_desc giantplus_gpm940b0 = {
2212 .timings = &giantplus_gpm940b0_timing,
2213 .num_timings = 1,
2214 .bpc = 8,
2215 .size = {
2216 .width = 60,
2217 .height = 45,
2218 },
2219 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
2220 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2221};
2222
2223static const struct display_timing hannstar_hsd070pww1_timing = {
2224 .pixelclock = { 64300000, 71100000, 82000000 },
2225 .hactive = { 1280, 1280, 1280 },
2226 .hfront_porch = { 1, 1, 10 },
2227 .hback_porch = { 1, 1, 10 },
2228 /*
2229 * According to the data sheet, the minimum horizontal blanking interval
2230 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
2231 * minimum working horizontal blanking interval to be 60 clocks.
2232 */
2233 .hsync_len = { 58, 158, 661 },
2234 .vactive = { 800, 800, 800 },
2235 .vfront_porch = { 1, 1, 10 },
2236 .vback_porch = { 1, 1, 10 },
2237 .vsync_len = { 1, 21, 203 },
2238 .flags = DISPLAY_FLAGS_DE_HIGH,
2239};
2240
2241static const struct panel_desc hannstar_hsd070pww1 = {
2242 .timings = &hannstar_hsd070pww1_timing,
2243 .num_timings = 1,
2244 .bpc = 6,
2245 .size = {
2246 .width = 151,
2247 .height = 94,
2248 },
2249 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2250 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2251};
2252
2253static const struct display_timing hannstar_hsd100pxn1_timing = {
2254 .pixelclock = { 55000000, 65000000, 75000000 },
2255 .hactive = { 1024, 1024, 1024 },
2256 .hfront_porch = { 40, 40, 40 },
2257 .hback_porch = { 220, 220, 220 },
2258 .hsync_len = { 20, 60, 100 },
2259 .vactive = { 768, 768, 768 },
2260 .vfront_porch = { 7, 7, 7 },
2261 .vback_porch = { 21, 21, 21 },
2262 .vsync_len = { 10, 10, 10 },
2263 .flags = DISPLAY_FLAGS_DE_HIGH,
2264};
2265
2266static const struct panel_desc hannstar_hsd100pxn1 = {
2267 .timings = &hannstar_hsd100pxn1_timing,
2268 .num_timings = 1,
2269 .bpc = 6,
2270 .size = {
2271 .width = 203,
2272 .height = 152,
2273 },
2274 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2275 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2276};
2277
2278static const struct display_timing hannstar_hsd101pww2_timing = {
2279 .pixelclock = { 64300000, 71100000, 82000000 },
2280 .hactive = { 1280, 1280, 1280 },
2281 .hfront_porch = { 1, 1, 10 },
2282 .hback_porch = { 1, 1, 10 },
2283 .hsync_len = { 58, 158, 661 },
2284 .vactive = { 800, 800, 800 },
2285 .vfront_porch = { 1, 1, 10 },
2286 .vback_porch = { 1, 1, 10 },
2287 .vsync_len = { 1, 21, 203 },
2288 .flags = DISPLAY_FLAGS_DE_HIGH,
2289};
2290
2291static const struct panel_desc hannstar_hsd101pww2 = {
2292 .timings = &hannstar_hsd101pww2_timing,
2293 .num_timings = 1,
2294 .bpc = 8,
2295 .size = {
2296 .width = 217,
2297 .height = 136,
2298 },
2299 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2300 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2301};
2302
2303static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2304 .clock = 33333,
2305 .hdisplay = 800,
2306 .hsync_start = 800 + 85,
2307 .hsync_end = 800 + 85 + 86,
2308 .htotal = 800 + 85 + 86 + 85,
2309 .vdisplay = 480,
2310 .vsync_start = 480 + 16,
2311 .vsync_end = 480 + 16 + 13,
2312 .vtotal = 480 + 16 + 13 + 16,
2313};
2314
2315static const struct panel_desc hitachi_tx23d38vm0caa = {
2316 .modes = &hitachi_tx23d38vm0caa_mode,
2317 .num_modes = 1,
2318 .bpc = 6,
2319 .size = {
2320 .width = 195,
2321 .height = 117,
2322 },
2323 .delay = {
2324 .enable = 160,
2325 .disable = 160,
2326 },
2327};
2328
2329static const struct drm_display_mode innolux_at043tn24_mode = {
2330 .clock = 9000,
2331 .hdisplay = 480,
2332 .hsync_start = 480 + 2,
2333 .hsync_end = 480 + 2 + 41,
2334 .htotal = 480 + 2 + 41 + 2,
2335 .vdisplay = 272,
2336 .vsync_start = 272 + 2,
2337 .vsync_end = 272 + 2 + 10,
2338 .vtotal = 272 + 2 + 10 + 2,
2339 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2340};
2341
2342static const struct panel_desc innolux_at043tn24 = {
2343 .modes = &innolux_at043tn24_mode,
2344 .num_modes = 1,
2345 .bpc = 8,
2346 .size = {
2347 .width = 95,
2348 .height = 54,
2349 },
2350 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2351 .connector_type = DRM_MODE_CONNECTOR_DPI,
2352 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2353};
2354
2355static const struct drm_display_mode innolux_at070tn92_mode = {
2356 .clock = 33333,
2357 .hdisplay = 800,
2358 .hsync_start = 800 + 210,
2359 .hsync_end = 800 + 210 + 20,
2360 .htotal = 800 + 210 + 20 + 46,
2361 .vdisplay = 480,
2362 .vsync_start = 480 + 22,
2363 .vsync_end = 480 + 22 + 10,
2364 .vtotal = 480 + 22 + 23 + 10,
2365};
2366
2367static const struct panel_desc innolux_at070tn92 = {
2368 .modes = &innolux_at070tn92_mode,
2369 .num_modes = 1,
2370 .size = {
2371 .width = 154,
2372 .height = 86,
2373 },
2374 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2375};
2376
2377static const struct display_timing innolux_g070ace_l01_timing = {
2378 .pixelclock = { 25200000, 35000000, 35700000 },
2379 .hactive = { 800, 800, 800 },
2380 .hfront_porch = { 30, 32, 87 },
2381 .hback_porch = { 30, 32, 87 },
2382 .hsync_len = { 1, 1, 1 },
2383 .vactive = { 480, 480, 480 },
2384 .vfront_porch = { 3, 3, 3 },
2385 .vback_porch = { 13, 13, 13 },
2386 .vsync_len = { 1, 1, 4 },
2387 .flags = DISPLAY_FLAGS_DE_HIGH,
2388};
2389
2390static const struct panel_desc innolux_g070ace_l01 = {
2391 .timings = &innolux_g070ace_l01_timing,
2392 .num_timings = 1,
2393 .bpc = 8,
2394 .size = {
2395 .width = 152,
2396 .height = 91,
2397 },
2398 .delay = {
2399 .prepare = 10,
2400 .enable = 50,
2401 .disable = 50,
2402 .unprepare = 500,
2403 },
2404 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2405 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2406 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2407};
2408
2409static const struct display_timing innolux_g070y2_l01_timing = {
2410 .pixelclock = { 28000000, 29500000, 32000000 },
2411 .hactive = { 800, 800, 800 },
2412 .hfront_porch = { 61, 91, 141 },
2413 .hback_porch = { 60, 90, 140 },
2414 .hsync_len = { 12, 12, 12 },
2415 .vactive = { 480, 480, 480 },
2416 .vfront_porch = { 4, 9, 30 },
2417 .vback_porch = { 4, 8, 28 },
2418 .vsync_len = { 2, 2, 2 },
2419 .flags = DISPLAY_FLAGS_DE_HIGH,
2420};
2421
2422static const struct panel_desc innolux_g070y2_l01 = {
2423 .timings = &innolux_g070y2_l01_timing,
2424 .num_timings = 1,
2425 .bpc = 8,
2426 .size = {
2427 .width = 152,
2428 .height = 91,
2429 },
2430 .delay = {
2431 .prepare = 10,
2432 .enable = 100,
2433 .disable = 100,
2434 .unprepare = 800,
2435 },
2436 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2437 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2438 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2439};
2440
2441static const struct drm_display_mode innolux_g070y2_t02_mode = {
2442 .clock = 33333,
2443 .hdisplay = 800,
2444 .hsync_start = 800 + 210,
2445 .hsync_end = 800 + 210 + 20,
2446 .htotal = 800 + 210 + 20 + 46,
2447 .vdisplay = 480,
2448 .vsync_start = 480 + 22,
2449 .vsync_end = 480 + 22 + 10,
2450 .vtotal = 480 + 22 + 23 + 10,
2451};
2452
2453static const struct panel_desc innolux_g070y2_t02 = {
2454 .modes = &innolux_g070y2_t02_mode,
2455 .num_modes = 1,
2456 .bpc = 8,
2457 .size = {
2458 .width = 152,
2459 .height = 92,
2460 },
2461 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2462 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2463 .connector_type = DRM_MODE_CONNECTOR_DPI,
2464};
2465
2466static const struct display_timing innolux_g101ice_l01_timing = {
2467 .pixelclock = { 60400000, 71100000, 74700000 },
2468 .hactive = { 1280, 1280, 1280 },
2469 .hfront_porch = { 30, 60, 70 },
2470 .hback_porch = { 30, 60, 70 },
2471 .hsync_len = { 22, 40, 60 },
2472 .vactive = { 800, 800, 800 },
2473 .vfront_porch = { 3, 8, 14 },
2474 .vback_porch = { 3, 8, 14 },
2475 .vsync_len = { 4, 7, 12 },
2476 .flags = DISPLAY_FLAGS_DE_HIGH,
2477};
2478
2479static const struct panel_desc innolux_g101ice_l01 = {
2480 .timings = &innolux_g101ice_l01_timing,
2481 .num_timings = 1,
2482 .bpc = 8,
2483 .size = {
2484 .width = 217,
2485 .height = 135,
2486 },
2487 .delay = {
2488 .enable = 200,
2489 .disable = 200,
2490 },
2491 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2492 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2493 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2494};
2495
2496static const struct display_timing innolux_g121i1_l01_timing = {
2497 .pixelclock = { 67450000, 71000000, 74550000 },
2498 .hactive = { 1280, 1280, 1280 },
2499 .hfront_porch = { 40, 80, 160 },
2500 .hback_porch = { 39, 79, 159 },
2501 .hsync_len = { 1, 1, 1 },
2502 .vactive = { 800, 800, 800 },
2503 .vfront_porch = { 5, 11, 100 },
2504 .vback_porch = { 4, 11, 99 },
2505 .vsync_len = { 1, 1, 1 },
2506};
2507
2508static const struct panel_desc innolux_g121i1_l01 = {
2509 .timings = &innolux_g121i1_l01_timing,
2510 .num_timings = 1,
2511 .bpc = 6,
2512 .size = {
2513 .width = 261,
2514 .height = 163,
2515 },
2516 .delay = {
2517 .enable = 200,
2518 .disable = 20,
2519 },
2520 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2521 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2522};
2523
2524static const struct drm_display_mode innolux_g121x1_l03_mode = {
2525 .clock = 65000,
2526 .hdisplay = 1024,
2527 .hsync_start = 1024 + 0,
2528 .hsync_end = 1024 + 1,
2529 .htotal = 1024 + 0 + 1 + 320,
2530 .vdisplay = 768,
2531 .vsync_start = 768 + 38,
2532 .vsync_end = 768 + 38 + 1,
2533 .vtotal = 768 + 38 + 1 + 0,
2534 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2535};
2536
2537static const struct panel_desc innolux_g121x1_l03 = {
2538 .modes = &innolux_g121x1_l03_mode,
2539 .num_modes = 1,
2540 .bpc = 6,
2541 .size = {
2542 .width = 246,
2543 .height = 185,
2544 },
2545 .delay = {
2546 .enable = 200,
2547 .unprepare = 200,
2548 .disable = 400,
2549 },
2550};
2551
2552static const struct display_timing innolux_g156hce_l01_timings = {
2553 .pixelclock = { 120000000, 141860000, 150000000 },
2554 .hactive = { 1920, 1920, 1920 },
2555 .hfront_porch = { 80, 90, 100 },
2556 .hback_porch = { 80, 90, 100 },
2557 .hsync_len = { 20, 30, 30 },
2558 .vactive = { 1080, 1080, 1080 },
2559 .vfront_porch = { 3, 10, 20 },
2560 .vback_porch = { 3, 10, 20 },
2561 .vsync_len = { 4, 10, 10 },
2562};
2563
2564static const struct panel_desc innolux_g156hce_l01 = {
2565 .timings = &innolux_g156hce_l01_timings,
2566 .num_timings = 1,
2567 .bpc = 8,
2568 .size = {
2569 .width = 344,
2570 .height = 194,
2571 },
2572 .delay = {
2573 .prepare = 1, /* T1+T2 */
2574 .enable = 450, /* T5 */
2575 .disable = 200, /* T6 */
2576 .unprepare = 10, /* T3+T7 */
2577 },
2578 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2579 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2580 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2581};
2582
2583static const struct drm_display_mode innolux_n156bge_l21_mode = {
2584 .clock = 69300,
2585 .hdisplay = 1366,
2586 .hsync_start = 1366 + 16,
2587 .hsync_end = 1366 + 16 + 34,
2588 .htotal = 1366 + 16 + 34 + 50,
2589 .vdisplay = 768,
2590 .vsync_start = 768 + 2,
2591 .vsync_end = 768 + 2 + 6,
2592 .vtotal = 768 + 2 + 6 + 12,
2593};
2594
2595static const struct panel_desc innolux_n156bge_l21 = {
2596 .modes = &innolux_n156bge_l21_mode,
2597 .num_modes = 1,
2598 .bpc = 6,
2599 .size = {
2600 .width = 344,
2601 .height = 193,
2602 },
2603 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2604 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2605 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2606};
2607
2608static const struct drm_display_mode innolux_zj070na_01p_mode = {
2609 .clock = 51501,
2610 .hdisplay = 1024,
2611 .hsync_start = 1024 + 128,
2612 .hsync_end = 1024 + 128 + 64,
2613 .htotal = 1024 + 128 + 64 + 128,
2614 .vdisplay = 600,
2615 .vsync_start = 600 + 16,
2616 .vsync_end = 600 + 16 + 4,
2617 .vtotal = 600 + 16 + 4 + 16,
2618};
2619
2620static const struct panel_desc innolux_zj070na_01p = {
2621 .modes = &innolux_zj070na_01p_mode,
2622 .num_modes = 1,
2623 .bpc = 6,
2624 .size = {
2625 .width = 154,
2626 .height = 90,
2627 },
2628};
2629
2630static const struct display_timing koe_tx14d24vm1bpa_timing = {
2631 .pixelclock = { 5580000, 5850000, 6200000 },
2632 .hactive = { 320, 320, 320 },
2633 .hfront_porch = { 30, 30, 30 },
2634 .hback_porch = { 30, 30, 30 },
2635 .hsync_len = { 1, 5, 17 },
2636 .vactive = { 240, 240, 240 },
2637 .vfront_porch = { 6, 6, 6 },
2638 .vback_porch = { 5, 5, 5 },
2639 .vsync_len = { 1, 2, 11 },
2640 .flags = DISPLAY_FLAGS_DE_HIGH,
2641};
2642
2643static const struct panel_desc koe_tx14d24vm1bpa = {
2644 .timings = &koe_tx14d24vm1bpa_timing,
2645 .num_timings = 1,
2646 .bpc = 6,
2647 .size = {
2648 .width = 115,
2649 .height = 86,
2650 },
2651};
2652
2653static const struct display_timing koe_tx26d202vm0bwa_timing = {
2654 .pixelclock = { 151820000, 156720000, 159780000 },
2655 .hactive = { 1920, 1920, 1920 },
2656 .hfront_porch = { 105, 130, 142 },
2657 .hback_porch = { 45, 70, 82 },
2658 .hsync_len = { 30, 30, 30 },
2659 .vactive = { 1200, 1200, 1200},
2660 .vfront_porch = { 3, 5, 10 },
2661 .vback_porch = { 2, 5, 10 },
2662 .vsync_len = { 5, 5, 5 },
2663};
2664
2665static const struct panel_desc koe_tx26d202vm0bwa = {
2666 .timings = &koe_tx26d202vm0bwa_timing,
2667 .num_timings = 1,
2668 .bpc = 8,
2669 .size = {
2670 .width = 217,
2671 .height = 136,
2672 },
2673 .delay = {
2674 .prepare = 1000,
2675 .enable = 1000,
2676 .unprepare = 1000,
2677 .disable = 1000,
2678 },
2679 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2680 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2681 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2682};
2683
2684static const struct display_timing koe_tx31d200vm0baa_timing = {
2685 .pixelclock = { 39600000, 43200000, 48000000 },
2686 .hactive = { 1280, 1280, 1280 },
2687 .hfront_porch = { 16, 36, 56 },
2688 .hback_porch = { 16, 36, 56 },
2689 .hsync_len = { 8, 8, 8 },
2690 .vactive = { 480, 480, 480 },
2691 .vfront_porch = { 6, 21, 33 },
2692 .vback_porch = { 6, 21, 33 },
2693 .vsync_len = { 8, 8, 8 },
2694 .flags = DISPLAY_FLAGS_DE_HIGH,
2695};
2696
2697static const struct panel_desc koe_tx31d200vm0baa = {
2698 .timings = &koe_tx31d200vm0baa_timing,
2699 .num_timings = 1,
2700 .bpc = 6,
2701 .size = {
2702 .width = 292,
2703 .height = 109,
2704 },
2705 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2706 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2707};
2708
2709static const struct display_timing kyo_tcg121xglp_timing = {
2710 .pixelclock = { 52000000, 65000000, 71000000 },
2711 .hactive = { 1024, 1024, 1024 },
2712 .hfront_porch = { 2, 2, 2 },
2713 .hback_porch = { 2, 2, 2 },
2714 .hsync_len = { 86, 124, 244 },
2715 .vactive = { 768, 768, 768 },
2716 .vfront_porch = { 2, 2, 2 },
2717 .vback_porch = { 2, 2, 2 },
2718 .vsync_len = { 6, 34, 73 },
2719 .flags = DISPLAY_FLAGS_DE_HIGH,
2720};
2721
2722static const struct panel_desc kyo_tcg121xglp = {
2723 .timings = &kyo_tcg121xglp_timing,
2724 .num_timings = 1,
2725 .bpc = 8,
2726 .size = {
2727 .width = 246,
2728 .height = 184,
2729 },
2730 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2731 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2732};
2733
2734static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2735 .clock = 7000,
2736 .hdisplay = 320,
2737 .hsync_start = 320 + 20,
2738 .hsync_end = 320 + 20 + 30,
2739 .htotal = 320 + 20 + 30 + 38,
2740 .vdisplay = 240,
2741 .vsync_start = 240 + 4,
2742 .vsync_end = 240 + 4 + 3,
2743 .vtotal = 240 + 4 + 3 + 15,
2744};
2745
2746static const struct panel_desc lemaker_bl035_rgb_002 = {
2747 .modes = &lemaker_bl035_rgb_002_mode,
2748 .num_modes = 1,
2749 .size = {
2750 .width = 70,
2751 .height = 52,
2752 },
2753 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2754 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2755};
2756
2757static const struct drm_display_mode lg_lb070wv8_mode = {
2758 .clock = 33246,
2759 .hdisplay = 800,
2760 .hsync_start = 800 + 88,
2761 .hsync_end = 800 + 88 + 80,
2762 .htotal = 800 + 88 + 80 + 88,
2763 .vdisplay = 480,
2764 .vsync_start = 480 + 10,
2765 .vsync_end = 480 + 10 + 25,
2766 .vtotal = 480 + 10 + 25 + 10,
2767};
2768
2769static const struct panel_desc lg_lb070wv8 = {
2770 .modes = &lg_lb070wv8_mode,
2771 .num_modes = 1,
2772 .bpc = 8,
2773 .size = {
2774 .width = 151,
2775 .height = 91,
2776 },
2777 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2778 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2779};
2780
2781static const struct display_timing logictechno_lt161010_2nh_timing = {
2782 .pixelclock = { 26400000, 33300000, 46800000 },
2783 .hactive = { 800, 800, 800 },
2784 .hfront_porch = { 16, 210, 354 },
2785 .hback_porch = { 46, 46, 46 },
2786 .hsync_len = { 1, 20, 40 },
2787 .vactive = { 480, 480, 480 },
2788 .vfront_porch = { 7, 22, 147 },
2789 .vback_porch = { 23, 23, 23 },
2790 .vsync_len = { 1, 10, 20 },
2791 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2792 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2793 DISPLAY_FLAGS_SYNC_POSEDGE,
2794};
2795
2796static const struct panel_desc logictechno_lt161010_2nh = {
2797 .timings = &logictechno_lt161010_2nh_timing,
2798 .num_timings = 1,
2799 .bpc = 6,
2800 .size = {
2801 .width = 154,
2802 .height = 86,
2803 },
2804 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2805 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2806 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2807 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2808 .connector_type = DRM_MODE_CONNECTOR_DPI,
2809};
2810
2811static const struct display_timing logictechno_lt170410_2whc_timing = {
2812 .pixelclock = { 68900000, 71100000, 73400000 },
2813 .hactive = { 1280, 1280, 1280 },
2814 .hfront_porch = { 23, 60, 71 },
2815 .hback_porch = { 23, 60, 71 },
2816 .hsync_len = { 15, 40, 47 },
2817 .vactive = { 800, 800, 800 },
2818 .vfront_porch = { 5, 7, 10 },
2819 .vback_porch = { 5, 7, 10 },
2820 .vsync_len = { 6, 9, 12 },
2821 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2822 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2823 DISPLAY_FLAGS_SYNC_POSEDGE,
2824};
2825
2826static const struct panel_desc logictechno_lt170410_2whc = {
2827 .timings = &logictechno_lt170410_2whc_timing,
2828 .num_timings = 1,
2829 .bpc = 8,
2830 .size = {
2831 .width = 217,
2832 .height = 136,
2833 },
2834 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2835 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2836 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2837};
2838
2839static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = {
2840 .clock = 33000,
2841 .hdisplay = 800,
2842 .hsync_start = 800 + 112,
2843 .hsync_end = 800 + 112 + 3,
2844 .htotal = 800 + 112 + 3 + 85,
2845 .vdisplay = 480,
2846 .vsync_start = 480 + 38,
2847 .vsync_end = 480 + 38 + 3,
2848 .vtotal = 480 + 38 + 3 + 29,
2849 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2850};
2851
2852static const struct panel_desc logictechno_lttd800480070_l2rt = {
2853 .modes = &logictechno_lttd800480070_l2rt_mode,
2854 .num_modes = 1,
2855 .bpc = 8,
2856 .size = {
2857 .width = 154,
2858 .height = 86,
2859 },
2860 .delay = {
2861 .prepare = 45,
2862 .enable = 100,
2863 .disable = 100,
2864 .unprepare = 45
2865 },
2866 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2867 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2868 .connector_type = DRM_MODE_CONNECTOR_DPI,
2869};
2870
2871static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = {
2872 .clock = 33000,
2873 .hdisplay = 800,
2874 .hsync_start = 800 + 154,
2875 .hsync_end = 800 + 154 + 3,
2876 .htotal = 800 + 154 + 3 + 43,
2877 .vdisplay = 480,
2878 .vsync_start = 480 + 47,
2879 .vsync_end = 480 + 47 + 3,
2880 .vtotal = 480 + 47 + 3 + 20,
2881 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2882};
2883
2884static const struct panel_desc logictechno_lttd800480070_l6wh_rt = {
2885 .modes = &logictechno_lttd800480070_l6wh_rt_mode,
2886 .num_modes = 1,
2887 .bpc = 8,
2888 .size = {
2889 .width = 154,
2890 .height = 86,
2891 },
2892 .delay = {
2893 .prepare = 45,
2894 .enable = 100,
2895 .disable = 100,
2896 .unprepare = 45
2897 },
2898 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2899 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2900 .connector_type = DRM_MODE_CONNECTOR_DPI,
2901};
2902
2903static const struct drm_display_mode logicpd_type_28_mode = {
2904 .clock = 9107,
2905 .hdisplay = 480,
2906 .hsync_start = 480 + 3,
2907 .hsync_end = 480 + 3 + 42,
2908 .htotal = 480 + 3 + 42 + 2,
2909
2910 .vdisplay = 272,
2911 .vsync_start = 272 + 2,
2912 .vsync_end = 272 + 2 + 11,
2913 .vtotal = 272 + 2 + 11 + 3,
2914 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2915};
2916
2917static const struct panel_desc logicpd_type_28 = {
2918 .modes = &logicpd_type_28_mode,
2919 .num_modes = 1,
2920 .bpc = 8,
2921 .size = {
2922 .width = 105,
2923 .height = 67,
2924 },
2925 .delay = {
2926 .prepare = 200,
2927 .enable = 200,
2928 .unprepare = 200,
2929 .disable = 200,
2930 },
2931 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2932 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2933 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2934 .connector_type = DRM_MODE_CONNECTOR_DPI,
2935};
2936
2937static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2938 .clock = 30400,
2939 .hdisplay = 800,
2940 .hsync_start = 800 + 0,
2941 .hsync_end = 800 + 1,
2942 .htotal = 800 + 0 + 1 + 160,
2943 .vdisplay = 480,
2944 .vsync_start = 480 + 0,
2945 .vsync_end = 480 + 48 + 1,
2946 .vtotal = 480 + 48 + 1 + 0,
2947 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2948};
2949
2950static const struct panel_desc mitsubishi_aa070mc01 = {
2951 .modes = &mitsubishi_aa070mc01_mode,
2952 .num_modes = 1,
2953 .bpc = 8,
2954 .size = {
2955 .width = 152,
2956 .height = 91,
2957 },
2958
2959 .delay = {
2960 .enable = 200,
2961 .unprepare = 200,
2962 .disable = 400,
2963 },
2964 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2965 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2966 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2967};
2968
2969static const struct drm_display_mode mitsubishi_aa084xe01_mode = {
2970 .clock = 56234,
2971 .hdisplay = 1024,
2972 .hsync_start = 1024 + 24,
2973 .hsync_end = 1024 + 24 + 63,
2974 .htotal = 1024 + 24 + 63 + 1,
2975 .vdisplay = 768,
2976 .vsync_start = 768 + 3,
2977 .vsync_end = 768 + 3 + 6,
2978 .vtotal = 768 + 3 + 6 + 1,
2979 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2980};
2981
2982static const struct panel_desc mitsubishi_aa084xe01 = {
2983 .modes = &mitsubishi_aa084xe01_mode,
2984 .num_modes = 1,
2985 .bpc = 8,
2986 .size = {
2987 .width = 1024,
2988 .height = 768,
2989 },
2990 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
2991 .connector_type = DRM_MODE_CONNECTOR_DPI,
2992 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2993};
2994
2995static const struct display_timing multi_inno_mi0700s4t_6_timing = {
2996 .pixelclock = { 29000000, 33000000, 38000000 },
2997 .hactive = { 800, 800, 800 },
2998 .hfront_porch = { 180, 210, 240 },
2999 .hback_porch = { 16, 16, 16 },
3000 .hsync_len = { 30, 30, 30 },
3001 .vactive = { 480, 480, 480 },
3002 .vfront_porch = { 12, 22, 32 },
3003 .vback_porch = { 10, 10, 10 },
3004 .vsync_len = { 13, 13, 13 },
3005 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3006 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3007 DISPLAY_FLAGS_SYNC_POSEDGE,
3008};
3009
3010static const struct panel_desc multi_inno_mi0700s4t_6 = {
3011 .timings = &multi_inno_mi0700s4t_6_timing,
3012 .num_timings = 1,
3013 .bpc = 8,
3014 .size = {
3015 .width = 154,
3016 .height = 86,
3017 },
3018 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3019 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3020 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3021 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3022 .connector_type = DRM_MODE_CONNECTOR_DPI,
3023};
3024
3025static const struct display_timing multi_inno_mi0800ft_9_timing = {
3026 .pixelclock = { 32000000, 40000000, 50000000 },
3027 .hactive = { 800, 800, 800 },
3028 .hfront_porch = { 16, 210, 354 },
3029 .hback_porch = { 6, 26, 45 },
3030 .hsync_len = { 1, 20, 40 },
3031 .vactive = { 600, 600, 600 },
3032 .vfront_porch = { 1, 12, 77 },
3033 .vback_porch = { 3, 13, 22 },
3034 .vsync_len = { 1, 10, 20 },
3035 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3036 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3037 DISPLAY_FLAGS_SYNC_POSEDGE,
3038};
3039
3040static const struct panel_desc multi_inno_mi0800ft_9 = {
3041 .timings = &multi_inno_mi0800ft_9_timing,
3042 .num_timings = 1,
3043 .bpc = 8,
3044 .size = {
3045 .width = 162,
3046 .height = 122,
3047 },
3048 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3049 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3050 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3051 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3052 .connector_type = DRM_MODE_CONNECTOR_DPI,
3053};
3054
3055static const struct display_timing multi_inno_mi1010ait_1cp_timing = {
3056 .pixelclock = { 68900000, 70000000, 73400000 },
3057 .hactive = { 1280, 1280, 1280 },
3058 .hfront_porch = { 30, 60, 71 },
3059 .hback_porch = { 30, 60, 71 },
3060 .hsync_len = { 10, 10, 48 },
3061 .vactive = { 800, 800, 800 },
3062 .vfront_porch = { 5, 10, 10 },
3063 .vback_porch = { 5, 10, 10 },
3064 .vsync_len = { 5, 6, 13 },
3065 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3066 DISPLAY_FLAGS_DE_HIGH,
3067};
3068
3069static const struct panel_desc multi_inno_mi1010ait_1cp = {
3070 .timings = &multi_inno_mi1010ait_1cp_timing,
3071 .num_timings = 1,
3072 .bpc = 8,
3073 .size = {
3074 .width = 217,
3075 .height = 136,
3076 },
3077 .delay = {
3078 .enable = 50,
3079 .disable = 50,
3080 },
3081 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3082 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3083 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3084};
3085
3086static const struct display_timing nec_nl12880bc20_05_timing = {
3087 .pixelclock = { 67000000, 71000000, 75000000 },
3088 .hactive = { 1280, 1280, 1280 },
3089 .hfront_porch = { 2, 30, 30 },
3090 .hback_porch = { 6, 100, 100 },
3091 .hsync_len = { 2, 30, 30 },
3092 .vactive = { 800, 800, 800 },
3093 .vfront_porch = { 5, 5, 5 },
3094 .vback_porch = { 11, 11, 11 },
3095 .vsync_len = { 7, 7, 7 },
3096};
3097
3098static const struct panel_desc nec_nl12880bc20_05 = {
3099 .timings = &nec_nl12880bc20_05_timing,
3100 .num_timings = 1,
3101 .bpc = 8,
3102 .size = {
3103 .width = 261,
3104 .height = 163,
3105 },
3106 .delay = {
3107 .enable = 50,
3108 .disable = 50,
3109 },
3110 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3111 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3112};
3113
3114static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
3115 .clock = 10870,
3116 .hdisplay = 480,
3117 .hsync_start = 480 + 2,
3118 .hsync_end = 480 + 2 + 41,
3119 .htotal = 480 + 2 + 41 + 2,
3120 .vdisplay = 272,
3121 .vsync_start = 272 + 2,
3122 .vsync_end = 272 + 2 + 4,
3123 .vtotal = 272 + 2 + 4 + 2,
3124 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3125};
3126
3127static const struct panel_desc nec_nl4827hc19_05b = {
3128 .modes = &nec_nl4827hc19_05b_mode,
3129 .num_modes = 1,
3130 .bpc = 8,
3131 .size = {
3132 .width = 95,
3133 .height = 54,
3134 },
3135 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3136 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3137};
3138
3139static const struct drm_display_mode netron_dy_e231732_mode = {
3140 .clock = 66000,
3141 .hdisplay = 1024,
3142 .hsync_start = 1024 + 160,
3143 .hsync_end = 1024 + 160 + 70,
3144 .htotal = 1024 + 160 + 70 + 90,
3145 .vdisplay = 600,
3146 .vsync_start = 600 + 127,
3147 .vsync_end = 600 + 127 + 20,
3148 .vtotal = 600 + 127 + 20 + 3,
3149};
3150
3151static const struct panel_desc netron_dy_e231732 = {
3152 .modes = &netron_dy_e231732_mode,
3153 .num_modes = 1,
3154 .size = {
3155 .width = 154,
3156 .height = 87,
3157 },
3158 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3159};
3160
3161static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
3162 .clock = 9000,
3163 .hdisplay = 480,
3164 .hsync_start = 480 + 2,
3165 .hsync_end = 480 + 2 + 41,
3166 .htotal = 480 + 2 + 41 + 2,
3167 .vdisplay = 272,
3168 .vsync_start = 272 + 2,
3169 .vsync_end = 272 + 2 + 10,
3170 .vtotal = 272 + 2 + 10 + 2,
3171 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3172};
3173
3174static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
3175 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
3176 .num_modes = 1,
3177 .bpc = 8,
3178 .size = {
3179 .width = 95,
3180 .height = 54,
3181 },
3182 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3183 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3184 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3185 .connector_type = DRM_MODE_CONNECTOR_DPI,
3186};
3187
3188static const struct display_timing nlt_nl192108ac18_02d_timing = {
3189 .pixelclock = { 130000000, 148350000, 163000000 },
3190 .hactive = { 1920, 1920, 1920 },
3191 .hfront_porch = { 80, 100, 100 },
3192 .hback_porch = { 100, 120, 120 },
3193 .hsync_len = { 50, 60, 60 },
3194 .vactive = { 1080, 1080, 1080 },
3195 .vfront_porch = { 12, 30, 30 },
3196 .vback_porch = { 4, 10, 10 },
3197 .vsync_len = { 4, 5, 5 },
3198};
3199
3200static const struct panel_desc nlt_nl192108ac18_02d = {
3201 .timings = &nlt_nl192108ac18_02d_timing,
3202 .num_timings = 1,
3203 .bpc = 8,
3204 .size = {
3205 .width = 344,
3206 .height = 194,
3207 },
3208 .delay = {
3209 .unprepare = 500,
3210 },
3211 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3212 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3213};
3214
3215static const struct drm_display_mode nvd_9128_mode = {
3216 .clock = 29500,
3217 .hdisplay = 800,
3218 .hsync_start = 800 + 130,
3219 .hsync_end = 800 + 130 + 98,
3220 .htotal = 800 + 0 + 130 + 98,
3221 .vdisplay = 480,
3222 .vsync_start = 480 + 10,
3223 .vsync_end = 480 + 10 + 50,
3224 .vtotal = 480 + 0 + 10 + 50,
3225};
3226
3227static const struct panel_desc nvd_9128 = {
3228 .modes = &nvd_9128_mode,
3229 .num_modes = 1,
3230 .bpc = 8,
3231 .size = {
3232 .width = 156,
3233 .height = 88,
3234 },
3235 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3236 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3237};
3238
3239static const struct display_timing okaya_rs800480t_7x0gp_timing = {
3240 .pixelclock = { 30000000, 30000000, 40000000 },
3241 .hactive = { 800, 800, 800 },
3242 .hfront_porch = { 40, 40, 40 },
3243 .hback_porch = { 40, 40, 40 },
3244 .hsync_len = { 1, 48, 48 },
3245 .vactive = { 480, 480, 480 },
3246 .vfront_porch = { 13, 13, 13 },
3247 .vback_porch = { 29, 29, 29 },
3248 .vsync_len = { 3, 3, 3 },
3249 .flags = DISPLAY_FLAGS_DE_HIGH,
3250};
3251
3252static const struct panel_desc okaya_rs800480t_7x0gp = {
3253 .timings = &okaya_rs800480t_7x0gp_timing,
3254 .num_timings = 1,
3255 .bpc = 6,
3256 .size = {
3257 .width = 154,
3258 .height = 87,
3259 },
3260 .delay = {
3261 .prepare = 41,
3262 .enable = 50,
3263 .unprepare = 41,
3264 .disable = 50,
3265 },
3266 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3267};
3268
3269static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
3270 .clock = 9000,
3271 .hdisplay = 480,
3272 .hsync_start = 480 + 5,
3273 .hsync_end = 480 + 5 + 30,
3274 .htotal = 480 + 5 + 30 + 10,
3275 .vdisplay = 272,
3276 .vsync_start = 272 + 8,
3277 .vsync_end = 272 + 8 + 5,
3278 .vtotal = 272 + 8 + 5 + 3,
3279};
3280
3281static const struct panel_desc olimex_lcd_olinuxino_43ts = {
3282 .modes = &olimex_lcd_olinuxino_43ts_mode,
3283 .num_modes = 1,
3284 .size = {
3285 .width = 95,
3286 .height = 54,
3287 },
3288 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3289};
3290
3291/*
3292 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
3293 * pixel clocks, but this is the timing that was being used in the Adafruit
3294 * installation instructions.
3295 */
3296static const struct drm_display_mode ontat_yx700wv03_mode = {
3297 .clock = 29500,
3298 .hdisplay = 800,
3299 .hsync_start = 824,
3300 .hsync_end = 896,
3301 .htotal = 992,
3302 .vdisplay = 480,
3303 .vsync_start = 483,
3304 .vsync_end = 493,
3305 .vtotal = 500,
3306 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3307};
3308
3309/*
3310 * Specification at:
3311 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
3312 */
3313static const struct panel_desc ontat_yx700wv03 = {
3314 .modes = &ontat_yx700wv03_mode,
3315 .num_modes = 1,
3316 .bpc = 8,
3317 .size = {
3318 .width = 154,
3319 .height = 83,
3320 },
3321 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3322};
3323
3324static const struct drm_display_mode ortustech_com37h3m_mode = {
3325 .clock = 22230,
3326 .hdisplay = 480,
3327 .hsync_start = 480 + 40,
3328 .hsync_end = 480 + 40 + 10,
3329 .htotal = 480 + 40 + 10 + 40,
3330 .vdisplay = 640,
3331 .vsync_start = 640 + 4,
3332 .vsync_end = 640 + 4 + 2,
3333 .vtotal = 640 + 4 + 2 + 4,
3334 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3335};
3336
3337static const struct panel_desc ortustech_com37h3m = {
3338 .modes = &ortustech_com37h3m_mode,
3339 .num_modes = 1,
3340 .bpc = 8,
3341 .size = {
3342 .width = 56, /* 56.16mm */
3343 .height = 75, /* 74.88mm */
3344 },
3345 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3346 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3347 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3348};
3349
3350static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
3351 .clock = 25000,
3352 .hdisplay = 480,
3353 .hsync_start = 480 + 10,
3354 .hsync_end = 480 + 10 + 10,
3355 .htotal = 480 + 10 + 10 + 15,
3356 .vdisplay = 800,
3357 .vsync_start = 800 + 3,
3358 .vsync_end = 800 + 3 + 3,
3359 .vtotal = 800 + 3 + 3 + 3,
3360};
3361
3362static const struct panel_desc ortustech_com43h4m85ulc = {
3363 .modes = &ortustech_com43h4m85ulc_mode,
3364 .num_modes = 1,
3365 .bpc = 6,
3366 .size = {
3367 .width = 56,
3368 .height = 93,
3369 },
3370 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3371 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3372 .connector_type = DRM_MODE_CONNECTOR_DPI,
3373};
3374
3375static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
3376 .clock = 33000,
3377 .hdisplay = 800,
3378 .hsync_start = 800 + 210,
3379 .hsync_end = 800 + 210 + 30,
3380 .htotal = 800 + 210 + 30 + 16,
3381 .vdisplay = 480,
3382 .vsync_start = 480 + 22,
3383 .vsync_end = 480 + 22 + 13,
3384 .vtotal = 480 + 22 + 13 + 10,
3385 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3386};
3387
3388static const struct panel_desc osddisplays_osd070t1718_19ts = {
3389 .modes = &osddisplays_osd070t1718_19ts_mode,
3390 .num_modes = 1,
3391 .bpc = 8,
3392 .size = {
3393 .width = 152,
3394 .height = 91,
3395 },
3396 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3397 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3398 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3399 .connector_type = DRM_MODE_CONNECTOR_DPI,
3400};
3401
3402static const struct drm_display_mode pda_91_00156_a0_mode = {
3403 .clock = 33300,
3404 .hdisplay = 800,
3405 .hsync_start = 800 + 1,
3406 .hsync_end = 800 + 1 + 64,
3407 .htotal = 800 + 1 + 64 + 64,
3408 .vdisplay = 480,
3409 .vsync_start = 480 + 1,
3410 .vsync_end = 480 + 1 + 23,
3411 .vtotal = 480 + 1 + 23 + 22,
3412};
3413
3414static const struct panel_desc pda_91_00156_a0 = {
3415 .modes = &pda_91_00156_a0_mode,
3416 .num_modes = 1,
3417 .size = {
3418 .width = 152,
3419 .height = 91,
3420 },
3421 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3422};
3423
3424static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3425 .clock = 24750,
3426 .hdisplay = 800,
3427 .hsync_start = 800 + 54,
3428 .hsync_end = 800 + 54 + 2,
3429 .htotal = 800 + 54 + 2 + 44,
3430 .vdisplay = 480,
3431 .vsync_start = 480 + 49,
3432 .vsync_end = 480 + 49 + 2,
3433 .vtotal = 480 + 49 + 2 + 22,
3434 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3435};
3436
3437static const struct panel_desc powertip_ph800480t013_idf02 = {
3438 .modes = &powertip_ph800480t013_idf02_mode,
3439 .num_modes = 1,
3440 .bpc = 8,
3441 .size = {
3442 .width = 152,
3443 .height = 91,
3444 },
3445 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3446 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3447 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3448 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3449 .connector_type = DRM_MODE_CONNECTOR_DPI,
3450};
3451
3452static const struct drm_display_mode qd43003c0_40_mode = {
3453 .clock = 9000,
3454 .hdisplay = 480,
3455 .hsync_start = 480 + 8,
3456 .hsync_end = 480 + 8 + 4,
3457 .htotal = 480 + 8 + 4 + 39,
3458 .vdisplay = 272,
3459 .vsync_start = 272 + 4,
3460 .vsync_end = 272 + 4 + 10,
3461 .vtotal = 272 + 4 + 10 + 2,
3462};
3463
3464static const struct panel_desc qd43003c0_40 = {
3465 .modes = &qd43003c0_40_mode,
3466 .num_modes = 1,
3467 .bpc = 8,
3468 .size = {
3469 .width = 95,
3470 .height = 53,
3471 },
3472 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3473};
3474
3475static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = {
3476 { /* 60 Hz */
3477 .clock = 10800,
3478 .hdisplay = 480,
3479 .hsync_start = 480 + 77,
3480 .hsync_end = 480 + 77 + 41,
3481 .htotal = 480 + 77 + 41 + 2,
3482 .vdisplay = 272,
3483 .vsync_start = 272 + 16,
3484 .vsync_end = 272 + 16 + 10,
3485 .vtotal = 272 + 16 + 10 + 2,
3486 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3487 },
3488 { /* 50 Hz */
3489 .clock = 10800,
3490 .hdisplay = 480,
3491 .hsync_start = 480 + 17,
3492 .hsync_end = 480 + 17 + 41,
3493 .htotal = 480 + 17 + 41 + 2,
3494 .vdisplay = 272,
3495 .vsync_start = 272 + 116,
3496 .vsync_end = 272 + 116 + 10,
3497 .vtotal = 272 + 116 + 10 + 2,
3498 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3499 },
3500};
3501
3502static const struct panel_desc qishenglong_gopher2b_lcd = {
3503 .modes = qishenglong_gopher2b_lcd_modes,
3504 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes),
3505 .bpc = 8,
3506 .size = {
3507 .width = 95,
3508 .height = 54,
3509 },
3510 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3511 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3512 .connector_type = DRM_MODE_CONNECTOR_DPI,
3513};
3514
3515static const struct display_timing rocktech_rk043fn48h_timing = {
3516 .pixelclock = { 6000000, 9000000, 12000000 },
3517 .hactive = { 480, 480, 480 },
3518 .hback_porch = { 8, 43, 43 },
3519 .hfront_porch = { 2, 8, 8 },
3520 .hsync_len = { 1, 1, 1 },
3521 .vactive = { 272, 272, 272 },
3522 .vback_porch = { 2, 12, 12 },
3523 .vfront_porch = { 1, 4, 4 },
3524 .vsync_len = { 1, 10, 10 },
3525 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW |
3526 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
3527};
3528
3529static const struct panel_desc rocktech_rk043fn48h = {
3530 .timings = &rocktech_rk043fn48h_timing,
3531 .num_timings = 1,
3532 .bpc = 8,
3533 .size = {
3534 .width = 95,
3535 .height = 54,
3536 },
3537 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3538 .connector_type = DRM_MODE_CONNECTOR_DPI,
3539};
3540
3541static const struct display_timing rocktech_rk070er9427_timing = {
3542 .pixelclock = { 26400000, 33300000, 46800000 },
3543 .hactive = { 800, 800, 800 },
3544 .hfront_porch = { 16, 210, 354 },
3545 .hback_porch = { 46, 46, 46 },
3546 .hsync_len = { 1, 1, 1 },
3547 .vactive = { 480, 480, 480 },
3548 .vfront_porch = { 7, 22, 147 },
3549 .vback_porch = { 23, 23, 23 },
3550 .vsync_len = { 1, 1, 1 },
3551 .flags = DISPLAY_FLAGS_DE_HIGH,
3552};
3553
3554static const struct panel_desc rocktech_rk070er9427 = {
3555 .timings = &rocktech_rk070er9427_timing,
3556 .num_timings = 1,
3557 .bpc = 6,
3558 .size = {
3559 .width = 154,
3560 .height = 86,
3561 },
3562 .delay = {
3563 .prepare = 41,
3564 .enable = 50,
3565 .unprepare = 41,
3566 .disable = 50,
3567 },
3568 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3569};
3570
3571static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3572 .clock = 71100,
3573 .hdisplay = 1280,
3574 .hsync_start = 1280 + 48,
3575 .hsync_end = 1280 + 48 + 32,
3576 .htotal = 1280 + 48 + 32 + 80,
3577 .vdisplay = 800,
3578 .vsync_start = 800 + 2,
3579 .vsync_end = 800 + 2 + 5,
3580 .vtotal = 800 + 2 + 5 + 16,
3581};
3582
3583static const struct panel_desc rocktech_rk101ii01d_ct = {
3584 .modes = &rocktech_rk101ii01d_ct_mode,
3585 .bpc = 8,
3586 .num_modes = 1,
3587 .size = {
3588 .width = 217,
3589 .height = 136,
3590 },
3591 .delay = {
3592 .prepare = 50,
3593 .disable = 50,
3594 },
3595 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3596 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3597 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3598};
3599
3600static const struct display_timing samsung_ltl101al01_timing = {
3601 .pixelclock = { 66663000, 66663000, 66663000 },
3602 .hactive = { 1280, 1280, 1280 },
3603 .hfront_porch = { 18, 18, 18 },
3604 .hback_porch = { 36, 36, 36 },
3605 .hsync_len = { 16, 16, 16 },
3606 .vactive = { 800, 800, 800 },
3607 .vfront_porch = { 4, 4, 4 },
3608 .vback_porch = { 16, 16, 16 },
3609 .vsync_len = { 3, 3, 3 },
3610 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3611};
3612
3613static const struct panel_desc samsung_ltl101al01 = {
3614 .timings = &samsung_ltl101al01_timing,
3615 .num_timings = 1,
3616 .bpc = 8,
3617 .size = {
3618 .width = 217,
3619 .height = 135,
3620 },
3621 .delay = {
3622 .prepare = 40,
3623 .enable = 300,
3624 .disable = 200,
3625 .unprepare = 600,
3626 },
3627 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3628 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3629};
3630
3631static const struct drm_display_mode samsung_ltn101nt05_mode = {
3632 .clock = 54030,
3633 .hdisplay = 1024,
3634 .hsync_start = 1024 + 24,
3635 .hsync_end = 1024 + 24 + 136,
3636 .htotal = 1024 + 24 + 136 + 160,
3637 .vdisplay = 600,
3638 .vsync_start = 600 + 3,
3639 .vsync_end = 600 + 3 + 6,
3640 .vtotal = 600 + 3 + 6 + 61,
3641};
3642
3643static const struct panel_desc samsung_ltn101nt05 = {
3644 .modes = &samsung_ltn101nt05_mode,
3645 .num_modes = 1,
3646 .bpc = 6,
3647 .size = {
3648 .width = 223,
3649 .height = 125,
3650 },
3651 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3652 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3653 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3654};
3655
3656static const struct display_timing satoz_sat050at40h12r2_timing = {
3657 .pixelclock = {33300000, 33300000, 50000000},
3658 .hactive = {800, 800, 800},
3659 .hfront_porch = {16, 210, 354},
3660 .hback_porch = {46, 46, 46},
3661 .hsync_len = {1, 1, 40},
3662 .vactive = {480, 480, 480},
3663 .vfront_porch = {7, 22, 147},
3664 .vback_porch = {23, 23, 23},
3665 .vsync_len = {1, 1, 20},
3666};
3667
3668static const struct panel_desc satoz_sat050at40h12r2 = {
3669 .timings = &satoz_sat050at40h12r2_timing,
3670 .num_timings = 1,
3671 .bpc = 8,
3672 .size = {
3673 .width = 108,
3674 .height = 65,
3675 },
3676 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3677 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3678};
3679
3680static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3681 .clock = 33260,
3682 .hdisplay = 800,
3683 .hsync_start = 800 + 64,
3684 .hsync_end = 800 + 64 + 128,
3685 .htotal = 800 + 64 + 128 + 64,
3686 .vdisplay = 480,
3687 .vsync_start = 480 + 8,
3688 .vsync_end = 480 + 8 + 2,
3689 .vtotal = 480 + 8 + 2 + 35,
3690 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3691};
3692
3693static const struct panel_desc sharp_lq070y3dg3b = {
3694 .modes = &sharp_lq070y3dg3b_mode,
3695 .num_modes = 1,
3696 .bpc = 8,
3697 .size = {
3698 .width = 152, /* 152.4mm */
3699 .height = 91, /* 91.4mm */
3700 },
3701 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3702 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3703 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3704};
3705
3706static const struct drm_display_mode sharp_lq035q7db03_mode = {
3707 .clock = 5500,
3708 .hdisplay = 240,
3709 .hsync_start = 240 + 16,
3710 .hsync_end = 240 + 16 + 7,
3711 .htotal = 240 + 16 + 7 + 5,
3712 .vdisplay = 320,
3713 .vsync_start = 320 + 9,
3714 .vsync_end = 320 + 9 + 1,
3715 .vtotal = 320 + 9 + 1 + 7,
3716};
3717
3718static const struct panel_desc sharp_lq035q7db03 = {
3719 .modes = &sharp_lq035q7db03_mode,
3720 .num_modes = 1,
3721 .bpc = 6,
3722 .size = {
3723 .width = 54,
3724 .height = 72,
3725 },
3726 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3727};
3728
3729static const struct display_timing sharp_lq101k1ly04_timing = {
3730 .pixelclock = { 60000000, 65000000, 80000000 },
3731 .hactive = { 1280, 1280, 1280 },
3732 .hfront_porch = { 20, 20, 20 },
3733 .hback_porch = { 20, 20, 20 },
3734 .hsync_len = { 10, 10, 10 },
3735 .vactive = { 800, 800, 800 },
3736 .vfront_porch = { 4, 4, 4 },
3737 .vback_porch = { 4, 4, 4 },
3738 .vsync_len = { 4, 4, 4 },
3739 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3740};
3741
3742static const struct panel_desc sharp_lq101k1ly04 = {
3743 .timings = &sharp_lq101k1ly04_timing,
3744 .num_timings = 1,
3745 .bpc = 8,
3746 .size = {
3747 .width = 217,
3748 .height = 136,
3749 },
3750 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3751 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3752};
3753
3754static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
3755 { /* 50 Hz */
3756 .clock = 3000,
3757 .hdisplay = 240,
3758 .hsync_start = 240 + 58,
3759 .hsync_end = 240 + 58 + 1,
3760 .htotal = 240 + 58 + 1 + 1,
3761 .vdisplay = 160,
3762 .vsync_start = 160 + 24,
3763 .vsync_end = 160 + 24 + 10,
3764 .vtotal = 160 + 24 + 10 + 6,
3765 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3766 },
3767 { /* 60 Hz */
3768 .clock = 3000,
3769 .hdisplay = 240,
3770 .hsync_start = 240 + 8,
3771 .hsync_end = 240 + 8 + 1,
3772 .htotal = 240 + 8 + 1 + 1,
3773 .vdisplay = 160,
3774 .vsync_start = 160 + 24,
3775 .vsync_end = 160 + 24 + 10,
3776 .vtotal = 160 + 24 + 10 + 6,
3777 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3778 },
3779};
3780
3781static const struct panel_desc sharp_ls020b1dd01d = {
3782 .modes = sharp_ls020b1dd01d_modes,
3783 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
3784 .bpc = 6,
3785 .size = {
3786 .width = 42,
3787 .height = 28,
3788 },
3789 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3790 .bus_flags = DRM_BUS_FLAG_DE_HIGH
3791 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
3792 | DRM_BUS_FLAG_SHARP_SIGNALS,
3793};
3794
3795static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3796 .clock = 33300,
3797 .hdisplay = 800,
3798 .hsync_start = 800 + 1,
3799 .hsync_end = 800 + 1 + 64,
3800 .htotal = 800 + 1 + 64 + 64,
3801 .vdisplay = 480,
3802 .vsync_start = 480 + 1,
3803 .vsync_end = 480 + 1 + 23,
3804 .vtotal = 480 + 1 + 23 + 22,
3805};
3806
3807static const struct panel_desc shelly_sca07010_bfn_lnn = {
3808 .modes = &shelly_sca07010_bfn_lnn_mode,
3809 .num_modes = 1,
3810 .size = {
3811 .width = 152,
3812 .height = 91,
3813 },
3814 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3815};
3816
3817static const struct drm_display_mode starry_kr070pe2t_mode = {
3818 .clock = 33000,
3819 .hdisplay = 800,
3820 .hsync_start = 800 + 209,
3821 .hsync_end = 800 + 209 + 1,
3822 .htotal = 800 + 209 + 1 + 45,
3823 .vdisplay = 480,
3824 .vsync_start = 480 + 22,
3825 .vsync_end = 480 + 22 + 1,
3826 .vtotal = 480 + 22 + 1 + 22,
3827};
3828
3829static const struct panel_desc starry_kr070pe2t = {
3830 .modes = &starry_kr070pe2t_mode,
3831 .num_modes = 1,
3832 .bpc = 8,
3833 .size = {
3834 .width = 152,
3835 .height = 86,
3836 },
3837 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3838 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
3839 .connector_type = DRM_MODE_CONNECTOR_DPI,
3840};
3841
3842static const struct display_timing startek_kd070wvfpa_mode = {
3843 .pixelclock = { 25200000, 27200000, 30500000 },
3844 .hactive = { 800, 800, 800 },
3845 .hfront_porch = { 19, 44, 115 },
3846 .hback_porch = { 5, 16, 101 },
3847 .hsync_len = { 1, 2, 100 },
3848 .vactive = { 480, 480, 480 },
3849 .vfront_porch = { 5, 43, 67 },
3850 .vback_porch = { 5, 5, 67 },
3851 .vsync_len = { 1, 2, 66 },
3852 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3853 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3854 DISPLAY_FLAGS_SYNC_POSEDGE,
3855};
3856
3857static const struct panel_desc startek_kd070wvfpa = {
3858 .timings = &startek_kd070wvfpa_mode,
3859 .num_timings = 1,
3860 .bpc = 8,
3861 .size = {
3862 .width = 152,
3863 .height = 91,
3864 },
3865 .delay = {
3866 .prepare = 20,
3867 .enable = 200,
3868 .disable = 200,
3869 },
3870 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3871 .connector_type = DRM_MODE_CONNECTOR_DPI,
3872 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3873 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3874 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3875};
3876
3877static const struct display_timing tsd_tst043015cmhx_timing = {
3878 .pixelclock = { 5000000, 9000000, 12000000 },
3879 .hactive = { 480, 480, 480 },
3880 .hfront_porch = { 4, 5, 65 },
3881 .hback_porch = { 36, 40, 255 },
3882 .hsync_len = { 1, 1, 1 },
3883 .vactive = { 272, 272, 272 },
3884 .vfront_porch = { 2, 8, 97 },
3885 .vback_porch = { 3, 8, 31 },
3886 .vsync_len = { 1, 1, 1 },
3887
3888 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3889 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
3890};
3891
3892static const struct panel_desc tsd_tst043015cmhx = {
3893 .timings = &tsd_tst043015cmhx_timing,
3894 .num_timings = 1,
3895 .bpc = 8,
3896 .size = {
3897 .width = 105,
3898 .height = 67,
3899 },
3900 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3901 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3902};
3903
3904static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
3905 .clock = 30000,
3906 .hdisplay = 800,
3907 .hsync_start = 800 + 39,
3908 .hsync_end = 800 + 39 + 47,
3909 .htotal = 800 + 39 + 47 + 39,
3910 .vdisplay = 480,
3911 .vsync_start = 480 + 13,
3912 .vsync_end = 480 + 13 + 2,
3913 .vtotal = 480 + 13 + 2 + 29,
3914};
3915
3916static const struct panel_desc tfc_s9700rtwv43tr_01b = {
3917 .modes = &tfc_s9700rtwv43tr_01b_mode,
3918 .num_modes = 1,
3919 .bpc = 8,
3920 .size = {
3921 .width = 155,
3922 .height = 90,
3923 },
3924 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3925 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3926};
3927
3928static const struct display_timing tianma_tm070jdhg30_timing = {
3929 .pixelclock = { 62600000, 68200000, 78100000 },
3930 .hactive = { 1280, 1280, 1280 },
3931 .hfront_porch = { 15, 64, 159 },
3932 .hback_porch = { 5, 5, 5 },
3933 .hsync_len = { 1, 1, 256 },
3934 .vactive = { 800, 800, 800 },
3935 .vfront_porch = { 3, 40, 99 },
3936 .vback_porch = { 2, 2, 2 },
3937 .vsync_len = { 1, 1, 128 },
3938 .flags = DISPLAY_FLAGS_DE_HIGH,
3939};
3940
3941static const struct panel_desc tianma_tm070jdhg30 = {
3942 .timings = &tianma_tm070jdhg30_timing,
3943 .num_timings = 1,
3944 .bpc = 8,
3945 .size = {
3946 .width = 151,
3947 .height = 95,
3948 },
3949 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3950 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3951 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3952};
3953
3954static const struct panel_desc tianma_tm070jvhg33 = {
3955 .timings = &tianma_tm070jdhg30_timing,
3956 .num_timings = 1,
3957 .bpc = 8,
3958 .size = {
3959 .width = 150,
3960 .height = 94,
3961 },
3962 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3963 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3964 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3965};
3966
3967static const struct display_timing tianma_tm070rvhg71_timing = {
3968 .pixelclock = { 27700000, 29200000, 39600000 },
3969 .hactive = { 800, 800, 800 },
3970 .hfront_porch = { 12, 40, 212 },
3971 .hback_porch = { 88, 88, 88 },
3972 .hsync_len = { 1, 1, 40 },
3973 .vactive = { 480, 480, 480 },
3974 .vfront_porch = { 1, 13, 88 },
3975 .vback_porch = { 32, 32, 32 },
3976 .vsync_len = { 1, 1, 3 },
3977 .flags = DISPLAY_FLAGS_DE_HIGH,
3978};
3979
3980static const struct panel_desc tianma_tm070rvhg71 = {
3981 .timings = &tianma_tm070rvhg71_timing,
3982 .num_timings = 1,
3983 .bpc = 8,
3984 .size = {
3985 .width = 154,
3986 .height = 86,
3987 },
3988 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3989 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3990};
3991
3992static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
3993 {
3994 .clock = 10000,
3995 .hdisplay = 320,
3996 .hsync_start = 320 + 50,
3997 .hsync_end = 320 + 50 + 6,
3998 .htotal = 320 + 50 + 6 + 38,
3999 .vdisplay = 240,
4000 .vsync_start = 240 + 3,
4001 .vsync_end = 240 + 3 + 1,
4002 .vtotal = 240 + 3 + 1 + 17,
4003 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4004 },
4005};
4006
4007static const struct panel_desc ti_nspire_cx_lcd_panel = {
4008 .modes = ti_nspire_cx_lcd_mode,
4009 .num_modes = 1,
4010 .bpc = 8,
4011 .size = {
4012 .width = 65,
4013 .height = 49,
4014 },
4015 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4016 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
4017};
4018
4019static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
4020 {
4021 .clock = 10000,
4022 .hdisplay = 320,
4023 .hsync_start = 320 + 6,
4024 .hsync_end = 320 + 6 + 6,
4025 .htotal = 320 + 6 + 6 + 6,
4026 .vdisplay = 240,
4027 .vsync_start = 240 + 0,
4028 .vsync_end = 240 + 0 + 1,
4029 .vtotal = 240 + 0 + 1 + 0,
4030 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4031 },
4032};
4033
4034static const struct panel_desc ti_nspire_classic_lcd_panel = {
4035 .modes = ti_nspire_classic_lcd_mode,
4036 .num_modes = 1,
4037 /* The grayscale panel has 8 bit for the color .. Y (black) */
4038 .bpc = 8,
4039 .size = {
4040 .width = 71,
4041 .height = 53,
4042 },
4043 /* This is the grayscale bus format */
4044 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
4045 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4046};
4047
4048static const struct drm_display_mode toshiba_lt089ac29000_mode = {
4049 .clock = 79500,
4050 .hdisplay = 1280,
4051 .hsync_start = 1280 + 192,
4052 .hsync_end = 1280 + 192 + 128,
4053 .htotal = 1280 + 192 + 128 + 64,
4054 .vdisplay = 768,
4055 .vsync_start = 768 + 20,
4056 .vsync_end = 768 + 20 + 7,
4057 .vtotal = 768 + 20 + 7 + 3,
4058};
4059
4060static const struct panel_desc toshiba_lt089ac29000 = {
4061 .modes = &toshiba_lt089ac29000_mode,
4062 .num_modes = 1,
4063 .size = {
4064 .width = 194,
4065 .height = 116,
4066 },
4067 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
4068 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4069 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4070};
4071
4072static const struct drm_display_mode tpk_f07a_0102_mode = {
4073 .clock = 33260,
4074 .hdisplay = 800,
4075 .hsync_start = 800 + 40,
4076 .hsync_end = 800 + 40 + 128,
4077 .htotal = 800 + 40 + 128 + 88,
4078 .vdisplay = 480,
4079 .vsync_start = 480 + 10,
4080 .vsync_end = 480 + 10 + 2,
4081 .vtotal = 480 + 10 + 2 + 33,
4082};
4083
4084static const struct panel_desc tpk_f07a_0102 = {
4085 .modes = &tpk_f07a_0102_mode,
4086 .num_modes = 1,
4087 .size = {
4088 .width = 152,
4089 .height = 91,
4090 },
4091 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
4092};
4093
4094static const struct drm_display_mode tpk_f10a_0102_mode = {
4095 .clock = 45000,
4096 .hdisplay = 1024,
4097 .hsync_start = 1024 + 176,
4098 .hsync_end = 1024 + 176 + 5,
4099 .htotal = 1024 + 176 + 5 + 88,
4100 .vdisplay = 600,
4101 .vsync_start = 600 + 20,
4102 .vsync_end = 600 + 20 + 5,
4103 .vtotal = 600 + 20 + 5 + 25,
4104};
4105
4106static const struct panel_desc tpk_f10a_0102 = {
4107 .modes = &tpk_f10a_0102_mode,
4108 .num_modes = 1,
4109 .size = {
4110 .width = 223,
4111 .height = 125,
4112 },
4113};
4114
4115static const struct display_timing urt_umsh_8596md_timing = {
4116 .pixelclock = { 33260000, 33260000, 33260000 },
4117 .hactive = { 800, 800, 800 },
4118 .hfront_porch = { 41, 41, 41 },
4119 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
4120 .hsync_len = { 71, 128, 128 },
4121 .vactive = { 480, 480, 480 },
4122 .vfront_porch = { 10, 10, 10 },
4123 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
4124 .vsync_len = { 2, 2, 2 },
4125 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
4126 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
4127};
4128
4129static const struct panel_desc urt_umsh_8596md_lvds = {
4130 .timings = &urt_umsh_8596md_timing,
4131 .num_timings = 1,
4132 .bpc = 6,
4133 .size = {
4134 .width = 152,
4135 .height = 91,
4136 },
4137 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
4138 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4139};
4140
4141static const struct panel_desc urt_umsh_8596md_parallel = {
4142 .timings = &urt_umsh_8596md_timing,
4143 .num_timings = 1,
4144 .bpc = 6,
4145 .size = {
4146 .width = 152,
4147 .height = 91,
4148 },
4149 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
4150};
4151
4152static const struct drm_display_mode vivax_tpc9150_panel_mode = {
4153 .clock = 60000,
4154 .hdisplay = 1024,
4155 .hsync_start = 1024 + 160,
4156 .hsync_end = 1024 + 160 + 100,
4157 .htotal = 1024 + 160 + 100 + 60,
4158 .vdisplay = 600,
4159 .vsync_start = 600 + 12,
4160 .vsync_end = 600 + 12 + 10,
4161 .vtotal = 600 + 12 + 10 + 13,
4162};
4163
4164static const struct panel_desc vivax_tpc9150_panel = {
4165 .modes = &vivax_tpc9150_panel_mode,
4166 .num_modes = 1,
4167 .bpc = 6,
4168 .size = {
4169 .width = 200,
4170 .height = 115,
4171 },
4172 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
4173 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4174 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4175};
4176
4177static const struct drm_display_mode vl050_8048nt_c01_mode = {
4178 .clock = 33333,
4179 .hdisplay = 800,
4180 .hsync_start = 800 + 210,
4181 .hsync_end = 800 + 210 + 20,
4182 .htotal = 800 + 210 + 20 + 46,
4183 .vdisplay = 480,
4184 .vsync_start = 480 + 22,
4185 .vsync_end = 480 + 22 + 10,
4186 .vtotal = 480 + 22 + 10 + 23,
4187 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4188};
4189
4190static const struct panel_desc vl050_8048nt_c01 = {
4191 .modes = &vl050_8048nt_c01_mode,
4192 .num_modes = 1,
4193 .bpc = 8,
4194 .size = {
4195 .width = 120,
4196 .height = 76,
4197 },
4198 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4199 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4200};
4201
4202static const struct drm_display_mode winstar_wf35ltiacd_mode = {
4203 .clock = 6410,
4204 .hdisplay = 320,
4205 .hsync_start = 320 + 20,
4206 .hsync_end = 320 + 20 + 30,
4207 .htotal = 320 + 20 + 30 + 38,
4208 .vdisplay = 240,
4209 .vsync_start = 240 + 4,
4210 .vsync_end = 240 + 4 + 3,
4211 .vtotal = 240 + 4 + 3 + 15,
4212 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4213};
4214
4215static const struct panel_desc winstar_wf35ltiacd = {
4216 .modes = &winstar_wf35ltiacd_mode,
4217 .num_modes = 1,
4218 .bpc = 8,
4219 .size = {
4220 .width = 70,
4221 .height = 53,
4222 },
4223 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4224};
4225
4226static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = {
4227 .clock = 51200,
4228 .hdisplay = 1024,
4229 .hsync_start = 1024 + 100,
4230 .hsync_end = 1024 + 100 + 100,
4231 .htotal = 1024 + 100 + 100 + 120,
4232 .vdisplay = 600,
4233 .vsync_start = 600 + 10,
4234 .vsync_end = 600 + 10 + 10,
4235 .vtotal = 600 + 10 + 10 + 15,
4236 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4237};
4238
4239static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = {
4240 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode,
4241 .num_modes = 1,
4242 .bpc = 8,
4243 .size = {
4244 .width = 154,
4245 .height = 90,
4246 },
4247 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4248 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4249 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4250};
4251
4252static const struct drm_display_mode arm_rtsm_mode[] = {
4253 {
4254 .clock = 65000,
4255 .hdisplay = 1024,
4256 .hsync_start = 1024 + 24,
4257 .hsync_end = 1024 + 24 + 136,
4258 .htotal = 1024 + 24 + 136 + 160,
4259 .vdisplay = 768,
4260 .vsync_start = 768 + 3,
4261 .vsync_end = 768 + 3 + 6,
4262 .vtotal = 768 + 3 + 6 + 29,
4263 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4264 },
4265};
4266
4267static const struct panel_desc arm_rtsm = {
4268 .modes = arm_rtsm_mode,
4269 .num_modes = 1,
4270 .bpc = 8,
4271 .size = {
4272 .width = 400,
4273 .height = 300,
4274 },
4275 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4276};
4277
4278static const struct of_device_id platform_of_match[] = {
4279 {
4280 .compatible = "ampire,am-1280800n3tzqw-t00h",
4281 .data = &ire_am_1280800n3tzqw_t00h,
4282 }, {
4283 .compatible = "ampire,am-480272h3tmqw-t01h",
4284 .data = &ire_am_480272h3tmqw_t01h,
4285 }, {
4286 .compatible = "ampire,am-800480l1tmqw-t00h",
4287 .data = &ire_am_800480l1tmqw_t00h,
4288 }, {
4289 .compatible = "ampire,am800480r3tmqwa1h",
4290 .data = &ire_am800480r3tmqwa1h,
4291 }, {
4292 .compatible = "ampire,am800600p5tmqw-tb8h",
4293 .data = &ire_am800600p5tmqwtb8h,
4294 }, {
4295 .compatible = "arm,rtsm-display",
4296 .data = &arm_rtsm,
4297 }, {
4298 .compatible = "armadeus,st0700-adapt",
4299 .data = &armadeus_st0700_adapt,
4300 }, {
4301 .compatible = "auo,b101aw03",
4302 .data = &auo_b101aw03,
4303 }, {
4304 .compatible = "auo,b101xtn01",
4305 .data = &auo_b101xtn01,
4306 }, {
4307 .compatible = "auo,b116xw03",
4308 .data = &auo_b116xw03,
4309 }, {
4310 .compatible = "auo,g070vvn01",
4311 .data = &auo_g070vvn01,
4312 }, {
4313 .compatible = "auo,g101evn010",
4314 .data = &auo_g101evn010,
4315 }, {
4316 .compatible = "auo,g104sn02",
4317 .data = &auo_g104sn02,
4318 }, {
4319 .compatible = "auo,g121ean01",
4320 .data = &auo_g121ean01,
4321 }, {
4322 .compatible = "auo,g133han01",
4323 .data = &auo_g133han01,
4324 }, {
4325 .compatible = "auo,g156han04",
4326 .data = &auo_g156han04,
4327 }, {
4328 .compatible = "auo,g156xtn01",
4329 .data = &auo_g156xtn01,
4330 }, {
4331 .compatible = "auo,g185han01",
4332 .data = &auo_g185han01,
4333 }, {
4334 .compatible = "auo,g190ean01",
4335 .data = &auo_g190ean01,
4336 }, {
4337 .compatible = "auo,p320hvn03",
4338 .data = &auo_p320hvn03,
4339 }, {
4340 .compatible = "auo,t215hvn01",
4341 .data = &auo_t215hvn01,
4342 }, {
4343 .compatible = "avic,tm070ddh03",
4344 .data = &avic_tm070ddh03,
4345 }, {
4346 .compatible = "bananapi,s070wv20-ct16",
4347 .data = &bananapi_s070wv20_ct16,
4348 }, {
4349 .compatible = "boe,bp101wx1-100",
4350 .data = &boe_bp101wx1_100,
4351 }, {
4352 .compatible = "boe,ev121wxm-n10-1850",
4353 .data = &boe_ev121wxm_n10_1850,
4354 }, {
4355 .compatible = "boe,hv070wsa-100",
4356 .data = &boe_hv070wsa
4357 }, {
4358 .compatible = "cdtech,s043wq26h-ct7",
4359 .data = &cdtech_s043wq26h_ct7,
4360 }, {
4361 .compatible = "cdtech,s070pws19hp-fc21",
4362 .data = &cdtech_s070pws19hp_fc21,
4363 }, {
4364 .compatible = "cdtech,s070swv29hg-dc44",
4365 .data = &cdtech_s070swv29hg_dc44,
4366 }, {
4367 .compatible = "cdtech,s070wv95-ct16",
4368 .data = &cdtech_s070wv95_ct16,
4369 }, {
4370 .compatible = "chefree,ch101olhlwh-002",
4371 .data = &chefree_ch101olhlwh_002,
4372 }, {
4373 .compatible = "chunghwa,claa070wp03xg",
4374 .data = &chunghwa_claa070wp03xg,
4375 }, {
4376 .compatible = "chunghwa,claa101wa01a",
4377 .data = &chunghwa_claa101wa01a
4378 }, {
4379 .compatible = "chunghwa,claa101wb01",
4380 .data = &chunghwa_claa101wb01
4381 }, {
4382 .compatible = "dataimage,fg040346dsswbg04",
4383 .data = &dataimage_fg040346dsswbg04,
4384 }, {
4385 .compatible = "dataimage,fg1001l0dsswmg01",
4386 .data = &dataimage_fg1001l0dsswmg01,
4387 }, {
4388 .compatible = "dataimage,scf0700c48ggu18",
4389 .data = &dataimage_scf0700c48ggu18,
4390 }, {
4391 .compatible = "dlc,dlc0700yzg-1",
4392 .data = &dlc_dlc0700yzg_1,
4393 }, {
4394 .compatible = "dlc,dlc1010gig",
4395 .data = &dlc_dlc1010gig,
4396 }, {
4397 .compatible = "edt,et035012dm6",
4398 .data = &edt_et035012dm6,
4399 }, {
4400 .compatible = "edt,etm0350g0dh6",
4401 .data = &edt_etm0350g0dh6,
4402 }, {
4403 .compatible = "edt,etm043080dh6gp",
4404 .data = &edt_etm043080dh6gp,
4405 }, {
4406 .compatible = "edt,etm0430g0dh6",
4407 .data = &edt_etm0430g0dh6,
4408 }, {
4409 .compatible = "edt,et057090dhu",
4410 .data = &edt_et057090dhu,
4411 }, {
4412 .compatible = "edt,et070080dh6",
4413 .data = &edt_etm0700g0dh6,
4414 }, {
4415 .compatible = "edt,etm0700g0dh6",
4416 .data = &edt_etm0700g0dh6,
4417 }, {
4418 .compatible = "edt,etm0700g0bdh6",
4419 .data = &edt_etm0700g0bdh6,
4420 }, {
4421 .compatible = "edt,etm0700g0edh6",
4422 .data = &edt_etm0700g0bdh6,
4423 }, {
4424 .compatible = "edt,etml0700y5dha",
4425 .data = &edt_etml0700y5dha,
4426 }, {
4427 .compatible = "edt,etmv570g2dhu",
4428 .data = &edt_etmv570g2dhu,
4429 }, {
4430 .compatible = "eink,vb3300-kca",
4431 .data = &eink_vb3300_kca,
4432 }, {
4433 .compatible = "evervision,vgg644804",
4434 .data = &evervision_vgg644804,
4435 }, {
4436 .compatible = "evervision,vgg804821",
4437 .data = &evervision_vgg804821,
4438 }, {
4439 .compatible = "foxlink,fl500wvr00-a0t",
4440 .data = &foxlink_fl500wvr00_a0t,
4441 }, {
4442 .compatible = "frida,frd350h54004",
4443 .data = &frida_frd350h54004,
4444 }, {
4445 .compatible = "friendlyarm,hd702e",
4446 .data = &friendlyarm_hd702e,
4447 }, {
4448 .compatible = "giantplus,gpg482739qs5",
4449 .data = &giantplus_gpg482739qs5
4450 }, {
4451 .compatible = "giantplus,gpm940b0",
4452 .data = &giantplus_gpm940b0,
4453 }, {
4454 .compatible = "hannstar,hsd070pww1",
4455 .data = &hannstar_hsd070pww1,
4456 }, {
4457 .compatible = "hannstar,hsd100pxn1",
4458 .data = &hannstar_hsd100pxn1,
4459 }, {
4460 .compatible = "hannstar,hsd101pww2",
4461 .data = &hannstar_hsd101pww2,
4462 }, {
4463 .compatible = "hit,tx23d38vm0caa",
4464 .data = &hitachi_tx23d38vm0caa
4465 }, {
4466 .compatible = "innolux,at043tn24",
4467 .data = &innolux_at043tn24,
4468 }, {
4469 .compatible = "innolux,at070tn92",
4470 .data = &innolux_at070tn92,
4471 }, {
4472 .compatible = "innolux,g070ace-l01",
4473 .data = &innolux_g070ace_l01,
4474 }, {
4475 .compatible = "innolux,g070y2-l01",
4476 .data = &innolux_g070y2_l01,
4477 }, {
4478 .compatible = "innolux,g070y2-t02",
4479 .data = &innolux_g070y2_t02,
4480 }, {
4481 .compatible = "innolux,g101ice-l01",
4482 .data = &innolux_g101ice_l01
4483 }, {
4484 .compatible = "innolux,g121i1-l01",
4485 .data = &innolux_g121i1_l01
4486 }, {
4487 .compatible = "innolux,g121x1-l03",
4488 .data = &innolux_g121x1_l03,
4489 }, {
4490 .compatible = "innolux,g156hce-l01",
4491 .data = &innolux_g156hce_l01,
4492 }, {
4493 .compatible = "innolux,n156bge-l21",
4494 .data = &innolux_n156bge_l21,
4495 }, {
4496 .compatible = "innolux,zj070na-01p",
4497 .data = &innolux_zj070na_01p,
4498 }, {
4499 .compatible = "koe,tx14d24vm1bpa",
4500 .data = &koe_tx14d24vm1bpa,
4501 }, {
4502 .compatible = "koe,tx26d202vm0bwa",
4503 .data = &koe_tx26d202vm0bwa,
4504 }, {
4505 .compatible = "koe,tx31d200vm0baa",
4506 .data = &koe_tx31d200vm0baa,
4507 }, {
4508 .compatible = "kyo,tcg121xglp",
4509 .data = &kyo_tcg121xglp,
4510 }, {
4511 .compatible = "lemaker,bl035-rgb-002",
4512 .data = &lemaker_bl035_rgb_002,
4513 }, {
4514 .compatible = "lg,lb070wv8",
4515 .data = &lg_lb070wv8,
4516 }, {
4517 .compatible = "logicpd,type28",
4518 .data = &logicpd_type_28,
4519 }, {
4520 .compatible = "logictechno,lt161010-2nhc",
4521 .data = &logictechno_lt161010_2nh,
4522 }, {
4523 .compatible = "logictechno,lt161010-2nhr",
4524 .data = &logictechno_lt161010_2nh,
4525 }, {
4526 .compatible = "logictechno,lt170410-2whc",
4527 .data = &logictechno_lt170410_2whc,
4528 }, {
4529 .compatible = "logictechno,lttd800480070-l2rt",
4530 .data = &logictechno_lttd800480070_l2rt,
4531 }, {
4532 .compatible = "logictechno,lttd800480070-l6wh-rt",
4533 .data = &logictechno_lttd800480070_l6wh_rt,
4534 }, {
4535 .compatible = "mitsubishi,aa070mc01-ca1",
4536 .data = &mitsubishi_aa070mc01,
4537 }, {
4538 .compatible = "mitsubishi,aa084xe01",
4539 .data = &mitsubishi_aa084xe01,
4540 }, {
4541 .compatible = "multi-inno,mi0700s4t-6",
4542 .data = &multi_inno_mi0700s4t_6,
4543 }, {
4544 .compatible = "multi-inno,mi0800ft-9",
4545 .data = &multi_inno_mi0800ft_9,
4546 }, {
4547 .compatible = "multi-inno,mi1010ait-1cp",
4548 .data = &multi_inno_mi1010ait_1cp,
4549 }, {
4550 .compatible = "nec,nl12880bc20-05",
4551 .data = &nec_nl12880bc20_05,
4552 }, {
4553 .compatible = "nec,nl4827hc19-05b",
4554 .data = &nec_nl4827hc19_05b,
4555 }, {
4556 .compatible = "netron-dy,e231732",
4557 .data = &netron_dy_e231732,
4558 }, {
4559 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
4560 .data = &newhaven_nhd_43_480272ef_atxl,
4561 }, {
4562 .compatible = "nlt,nl192108ac18-02d",
4563 .data = &nlt_nl192108ac18_02d,
4564 }, {
4565 .compatible = "nvd,9128",
4566 .data = &nvd_9128,
4567 }, {
4568 .compatible = "okaya,rs800480t-7x0gp",
4569 .data = &okaya_rs800480t_7x0gp,
4570 }, {
4571 .compatible = "olimex,lcd-olinuxino-43-ts",
4572 .data = &olimex_lcd_olinuxino_43ts,
4573 }, {
4574 .compatible = "ontat,yx700wv03",
4575 .data = &ontat_yx700wv03,
4576 }, {
4577 .compatible = "ortustech,com37h3m05dtc",
4578 .data = &ortustech_com37h3m,
4579 }, {
4580 .compatible = "ortustech,com37h3m99dtc",
4581 .data = &ortustech_com37h3m,
4582 }, {
4583 .compatible = "ortustech,com43h4m85ulc",
4584 .data = &ortustech_com43h4m85ulc,
4585 }, {
4586 .compatible = "osddisplays,osd070t1718-19ts",
4587 .data = &osddisplays_osd070t1718_19ts,
4588 }, {
4589 .compatible = "pda,91-00156-a0",
4590 .data = &pda_91_00156_a0,
4591 }, {
4592 .compatible = "powertip,ph800480t013-idf02",
4593 .data = &powertip_ph800480t013_idf02,
4594 }, {
4595 .compatible = "qiaodian,qd43003c0-40",
4596 .data = &qd43003c0_40,
4597 }, {
4598 .compatible = "qishenglong,gopher2b-lcd",
4599 .data = &qishenglong_gopher2b_lcd,
4600 }, {
4601 .compatible = "rocktech,rk043fn48h",
4602 .data = &rocktech_rk043fn48h,
4603 }, {
4604 .compatible = "rocktech,rk070er9427",
4605 .data = &rocktech_rk070er9427,
4606 }, {
4607 .compatible = "rocktech,rk101ii01d-ct",
4608 .data = &rocktech_rk101ii01d_ct,
4609 }, {
4610 .compatible = "samsung,ltl101al01",
4611 .data = &samsung_ltl101al01,
4612 }, {
4613 .compatible = "samsung,ltn101nt05",
4614 .data = &samsung_ltn101nt05,
4615 }, {
4616 .compatible = "satoz,sat050at40h12r2",
4617 .data = &satoz_sat050at40h12r2,
4618 }, {
4619 .compatible = "sharp,lq035q7db03",
4620 .data = &sharp_lq035q7db03,
4621 }, {
4622 .compatible = "sharp,lq070y3dg3b",
4623 .data = &sharp_lq070y3dg3b,
4624 }, {
4625 .compatible = "sharp,lq101k1ly04",
4626 .data = &sharp_lq101k1ly04,
4627 }, {
4628 .compatible = "sharp,ls020b1dd01d",
4629 .data = &sharp_ls020b1dd01d,
4630 }, {
4631 .compatible = "shelly,sca07010-bfn-lnn",
4632 .data = &shelly_sca07010_bfn_lnn,
4633 }, {
4634 .compatible = "starry,kr070pe2t",
4635 .data = &starry_kr070pe2t,
4636 }, {
4637 .compatible = "startek,kd070wvfpa",
4638 .data = &startek_kd070wvfpa,
4639 }, {
4640 .compatible = "team-source-display,tst043015cmhx",
4641 .data = &tsd_tst043015cmhx,
4642 }, {
4643 .compatible = "tfc,s9700rtwv43tr-01b",
4644 .data = &tfc_s9700rtwv43tr_01b,
4645 }, {
4646 .compatible = "tianma,tm070jdhg30",
4647 .data = &tianma_tm070jdhg30,
4648 }, {
4649 .compatible = "tianma,tm070jvhg33",
4650 .data = &tianma_tm070jvhg33,
4651 }, {
4652 .compatible = "tianma,tm070rvhg71",
4653 .data = &tianma_tm070rvhg71,
4654 }, {
4655 .compatible = "ti,nspire-cx-lcd-panel",
4656 .data = &ti_nspire_cx_lcd_panel,
4657 }, {
4658 .compatible = "ti,nspire-classic-lcd-panel",
4659 .data = &ti_nspire_classic_lcd_panel,
4660 }, {
4661 .compatible = "toshiba,lt089ac29000",
4662 .data = &toshiba_lt089ac29000,
4663 }, {
4664 .compatible = "tpk,f07a-0102",
4665 .data = &tpk_f07a_0102,
4666 }, {
4667 .compatible = "tpk,f10a-0102",
4668 .data = &tpk_f10a_0102,
4669 }, {
4670 .compatible = "urt,umsh-8596md-t",
4671 .data = &urt_umsh_8596md_parallel,
4672 }, {
4673 .compatible = "urt,umsh-8596md-1t",
4674 .data = &urt_umsh_8596md_parallel,
4675 }, {
4676 .compatible = "urt,umsh-8596md-7t",
4677 .data = &urt_umsh_8596md_parallel,
4678 }, {
4679 .compatible = "urt,umsh-8596md-11t",
4680 .data = &urt_umsh_8596md_lvds,
4681 }, {
4682 .compatible = "urt,umsh-8596md-19t",
4683 .data = &urt_umsh_8596md_lvds,
4684 }, {
4685 .compatible = "urt,umsh-8596md-20t",
4686 .data = &urt_umsh_8596md_parallel,
4687 }, {
4688 .compatible = "vivax,tpc9150-panel",
4689 .data = &vivax_tpc9150_panel,
4690 }, {
4691 .compatible = "vxt,vl050-8048nt-c01",
4692 .data = &vl050_8048nt_c01,
4693 }, {
4694 .compatible = "winstar,wf35ltiacd",
4695 .data = &winstar_wf35ltiacd,
4696 }, {
4697 .compatible = "yes-optoelectronics,ytc700tlag-05-201c",
4698 .data = &yes_optoelectronics_ytc700tlag_05_201c,
4699 }, {
4700 /* Must be the last entry */
4701 .compatible = "panel-dpi",
4702 .data = &panel_dpi,
4703 }, {
4704 /* sentinel */
4705 }
4706};
4707MODULE_DEVICE_TABLE(of, platform_of_match);
4708
4709static int panel_simple_platform_probe(struct platform_device *pdev)
4710{
4711 const struct panel_desc *desc;
4712
4713 desc = of_device_get_match_data(&pdev->dev);
4714 if (!desc)
4715 return -ENODEV;
4716
4717 return panel_simple_probe(&pdev->dev, desc);
4718}
4719
4720static void panel_simple_platform_remove(struct platform_device *pdev)
4721{
4722 panel_simple_remove(&pdev->dev);
4723}
4724
4725static void panel_simple_platform_shutdown(struct platform_device *pdev)
4726{
4727 panel_simple_shutdown(&pdev->dev);
4728}
4729
4730static const struct dev_pm_ops panel_simple_pm_ops = {
4731 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL)
4732 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
4733 pm_runtime_force_resume)
4734};
4735
4736static struct platform_driver panel_simple_platform_driver = {
4737 .driver = {
4738 .name = "panel-simple",
4739 .of_match_table = platform_of_match,
4740 .pm = &panel_simple_pm_ops,
4741 },
4742 .probe = panel_simple_platform_probe,
4743 .remove_new = panel_simple_platform_remove,
4744 .shutdown = panel_simple_platform_shutdown,
4745};
4746
4747struct panel_desc_dsi {
4748 struct panel_desc desc;
4749
4750 unsigned long flags;
4751 enum mipi_dsi_pixel_format format;
4752 unsigned int lanes;
4753};
4754
4755static const struct drm_display_mode auo_b080uan01_mode = {
4756 .clock = 154500,
4757 .hdisplay = 1200,
4758 .hsync_start = 1200 + 62,
4759 .hsync_end = 1200 + 62 + 4,
4760 .htotal = 1200 + 62 + 4 + 62,
4761 .vdisplay = 1920,
4762 .vsync_start = 1920 + 9,
4763 .vsync_end = 1920 + 9 + 2,
4764 .vtotal = 1920 + 9 + 2 + 8,
4765};
4766
4767static const struct panel_desc_dsi auo_b080uan01 = {
4768 .desc = {
4769 .modes = &auo_b080uan01_mode,
4770 .num_modes = 1,
4771 .bpc = 8,
4772 .size = {
4773 .width = 108,
4774 .height = 272,
4775 },
4776 .connector_type = DRM_MODE_CONNECTOR_DSI,
4777 },
4778 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4779 .format = MIPI_DSI_FMT_RGB888,
4780 .lanes = 4,
4781};
4782
4783static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4784 .clock = 160000,
4785 .hdisplay = 1200,
4786 .hsync_start = 1200 + 120,
4787 .hsync_end = 1200 + 120 + 20,
4788 .htotal = 1200 + 120 + 20 + 21,
4789 .vdisplay = 1920,
4790 .vsync_start = 1920 + 21,
4791 .vsync_end = 1920 + 21 + 3,
4792 .vtotal = 1920 + 21 + 3 + 18,
4793 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4794};
4795
4796static const struct panel_desc_dsi boe_tv080wum_nl0 = {
4797 .desc = {
4798 .modes = &boe_tv080wum_nl0_mode,
4799 .num_modes = 1,
4800 .size = {
4801 .width = 107,
4802 .height = 172,
4803 },
4804 .connector_type = DRM_MODE_CONNECTOR_DSI,
4805 },
4806 .flags = MIPI_DSI_MODE_VIDEO |
4807 MIPI_DSI_MODE_VIDEO_BURST |
4808 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
4809 .format = MIPI_DSI_FMT_RGB888,
4810 .lanes = 4,
4811};
4812
4813static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
4814 .clock = 71000,
4815 .hdisplay = 800,
4816 .hsync_start = 800 + 32,
4817 .hsync_end = 800 + 32 + 1,
4818 .htotal = 800 + 32 + 1 + 57,
4819 .vdisplay = 1280,
4820 .vsync_start = 1280 + 28,
4821 .vsync_end = 1280 + 28 + 1,
4822 .vtotal = 1280 + 28 + 1 + 14,
4823};
4824
4825static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
4826 .desc = {
4827 .modes = &lg_ld070wx3_sl01_mode,
4828 .num_modes = 1,
4829 .bpc = 8,
4830 .size = {
4831 .width = 94,
4832 .height = 151,
4833 },
4834 .connector_type = DRM_MODE_CONNECTOR_DSI,
4835 },
4836 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4837 .format = MIPI_DSI_FMT_RGB888,
4838 .lanes = 4,
4839};
4840
4841static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
4842 .clock = 67000,
4843 .hdisplay = 720,
4844 .hsync_start = 720 + 12,
4845 .hsync_end = 720 + 12 + 4,
4846 .htotal = 720 + 12 + 4 + 112,
4847 .vdisplay = 1280,
4848 .vsync_start = 1280 + 8,
4849 .vsync_end = 1280 + 8 + 4,
4850 .vtotal = 1280 + 8 + 4 + 12,
4851};
4852
4853static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
4854 .desc = {
4855 .modes = &lg_lh500wx1_sd03_mode,
4856 .num_modes = 1,
4857 .bpc = 8,
4858 .size = {
4859 .width = 62,
4860 .height = 110,
4861 },
4862 .connector_type = DRM_MODE_CONNECTOR_DSI,
4863 },
4864 .flags = MIPI_DSI_MODE_VIDEO,
4865 .format = MIPI_DSI_FMT_RGB888,
4866 .lanes = 4,
4867};
4868
4869static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
4870 .clock = 157200,
4871 .hdisplay = 1920,
4872 .hsync_start = 1920 + 154,
4873 .hsync_end = 1920 + 154 + 16,
4874 .htotal = 1920 + 154 + 16 + 32,
4875 .vdisplay = 1200,
4876 .vsync_start = 1200 + 17,
4877 .vsync_end = 1200 + 17 + 2,
4878 .vtotal = 1200 + 17 + 2 + 16,
4879};
4880
4881static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
4882 .desc = {
4883 .modes = &panasonic_vvx10f004b00_mode,
4884 .num_modes = 1,
4885 .bpc = 8,
4886 .size = {
4887 .width = 217,
4888 .height = 136,
4889 },
4890 .connector_type = DRM_MODE_CONNECTOR_DSI,
4891 },
4892 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4893 MIPI_DSI_CLOCK_NON_CONTINUOUS,
4894 .format = MIPI_DSI_FMT_RGB888,
4895 .lanes = 4,
4896};
4897
4898static const struct drm_display_mode lg_acx467akm_7_mode = {
4899 .clock = 150000,
4900 .hdisplay = 1080,
4901 .hsync_start = 1080 + 2,
4902 .hsync_end = 1080 + 2 + 2,
4903 .htotal = 1080 + 2 + 2 + 2,
4904 .vdisplay = 1920,
4905 .vsync_start = 1920 + 2,
4906 .vsync_end = 1920 + 2 + 2,
4907 .vtotal = 1920 + 2 + 2 + 2,
4908};
4909
4910static const struct panel_desc_dsi lg_acx467akm_7 = {
4911 .desc = {
4912 .modes = &lg_acx467akm_7_mode,
4913 .num_modes = 1,
4914 .bpc = 8,
4915 .size = {
4916 .width = 62,
4917 .height = 110,
4918 },
4919 .connector_type = DRM_MODE_CONNECTOR_DSI,
4920 },
4921 .flags = 0,
4922 .format = MIPI_DSI_FMT_RGB888,
4923 .lanes = 4,
4924};
4925
4926static const struct drm_display_mode osd101t2045_53ts_mode = {
4927 .clock = 154500,
4928 .hdisplay = 1920,
4929 .hsync_start = 1920 + 112,
4930 .hsync_end = 1920 + 112 + 16,
4931 .htotal = 1920 + 112 + 16 + 32,
4932 .vdisplay = 1200,
4933 .vsync_start = 1200 + 16,
4934 .vsync_end = 1200 + 16 + 2,
4935 .vtotal = 1200 + 16 + 2 + 16,
4936 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4937};
4938
4939static const struct panel_desc_dsi osd101t2045_53ts = {
4940 .desc = {
4941 .modes = &osd101t2045_53ts_mode,
4942 .num_modes = 1,
4943 .bpc = 8,
4944 .size = {
4945 .width = 217,
4946 .height = 136,
4947 },
4948 .connector_type = DRM_MODE_CONNECTOR_DSI,
4949 },
4950 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
4951 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4952 MIPI_DSI_MODE_NO_EOT_PACKET,
4953 .format = MIPI_DSI_FMT_RGB888,
4954 .lanes = 4,
4955};
4956
4957static const struct of_device_id dsi_of_match[] = {
4958 {
4959 .compatible = "auo,b080uan01",
4960 .data = &auo_b080uan01
4961 }, {
4962 .compatible = "boe,tv080wum-nl0",
4963 .data = &boe_tv080wum_nl0
4964 }, {
4965 .compatible = "lg,ld070wx3-sl01",
4966 .data = &lg_ld070wx3_sl01
4967 }, {
4968 .compatible = "lg,lh500wx1-sd03",
4969 .data = &lg_lh500wx1_sd03
4970 }, {
4971 .compatible = "panasonic,vvx10f004b00",
4972 .data = &panasonic_vvx10f004b00
4973 }, {
4974 .compatible = "lg,acx467akm-7",
4975 .data = &lg_acx467akm_7
4976 }, {
4977 .compatible = "osddisplays,osd101t2045-53ts",
4978 .data = &osd101t2045_53ts
4979 }, {
4980 /* sentinel */
4981 }
4982};
4983MODULE_DEVICE_TABLE(of, dsi_of_match);
4984
4985static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
4986{
4987 const struct panel_desc_dsi *desc;
4988 int err;
4989
4990 desc = of_device_get_match_data(&dsi->dev);
4991 if (!desc)
4992 return -ENODEV;
4993
4994 err = panel_simple_probe(&dsi->dev, &desc->desc);
4995 if (err < 0)
4996 return err;
4997
4998 dsi->mode_flags = desc->flags;
4999 dsi->format = desc->format;
5000 dsi->lanes = desc->lanes;
5001
5002 err = mipi_dsi_attach(dsi);
5003 if (err) {
5004 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi);
5005
5006 drm_panel_remove(&panel->base);
5007 }
5008
5009 return err;
5010}
5011
5012static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
5013{
5014 int err;
5015
5016 err = mipi_dsi_detach(dsi);
5017 if (err < 0)
5018 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
5019
5020 panel_simple_remove(&dsi->dev);
5021}
5022
5023static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
5024{
5025 panel_simple_shutdown(&dsi->dev);
5026}
5027
5028static struct mipi_dsi_driver panel_simple_dsi_driver = {
5029 .driver = {
5030 .name = "panel-simple-dsi",
5031 .of_match_table = dsi_of_match,
5032 .pm = &panel_simple_pm_ops,
5033 },
5034 .probe = panel_simple_dsi_probe,
5035 .remove = panel_simple_dsi_remove,
5036 .shutdown = panel_simple_dsi_shutdown,
5037};
5038
5039static int __init panel_simple_init(void)
5040{
5041 int err;
5042
5043 err = platform_driver_register(&panel_simple_platform_driver);
5044 if (err < 0)
5045 return err;
5046
5047 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
5048 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
5049 if (err < 0)
5050 goto err_did_platform_register;
5051 }
5052
5053 return 0;
5054
5055err_did_platform_register:
5056 platform_driver_unregister(&panel_simple_platform_driver);
5057
5058 return err;
5059}
5060module_init(panel_simple_init);
5061
5062static void __exit panel_simple_exit(void)
5063{
5064 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
5065 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
5066
5067 platform_driver_unregister(&panel_simple_platform_driver);
5068}
5069module_exit(panel_simple_exit);
5070
5071MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
5072MODULE_DESCRIPTION("DRM Driver for Simple Panels");
5073MODULE_LICENSE("GPL and additional rights");