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1/*
2 * SPDX-License-Identifier: MIT
3 *
4 * Copyright � 2008-2018 Intel Corporation
5 */
6
7#ifndef _I915_GPU_ERROR_H_
8#define _I915_GPU_ERROR_H_
9
10#include <linux/atomic.h>
11#include <linux/kref.h>
12#include <linux/ktime.h>
13#include <linux/sched.h>
14
15#include <drm/drm_mm.h>
16
17#include "gt/intel_engine.h"
18#include "gt/uc/intel_uc_fw.h"
19
20#include "intel_device_info.h"
21
22#include "i915_gem.h"
23#include "i915_gem_gtt.h"
24#include "i915_params.h"
25#include "i915_scheduler.h"
26
27struct drm_i915_private;
28struct intel_overlay_error_state;
29struct intel_display_error_state;
30
31struct i915_gpu_state {
32 struct kref ref;
33 ktime_t time;
34 ktime_t boottime;
35 ktime_t uptime;
36 unsigned long capture;
37 unsigned long epoch;
38
39 struct drm_i915_private *i915;
40
41 char error_msg[128];
42 bool simulated;
43 bool awake;
44 bool wakelock;
45 bool suspended;
46 int iommu;
47 u32 reset_count;
48 u32 suspend_count;
49 struct intel_device_info device_info;
50 struct intel_runtime_info runtime_info;
51 struct intel_driver_caps driver_caps;
52 struct i915_params params;
53
54 struct i915_error_uc {
55 struct intel_uc_fw guc_fw;
56 struct intel_uc_fw huc_fw;
57 struct drm_i915_error_object *guc_log;
58 } uc;
59
60 /* Generic register state */
61 u32 eir;
62 u32 pgtbl_er;
63 u32 ier;
64 u32 gtier[6], ngtier;
65 u32 ccid;
66 u32 derrmr;
67 u32 forcewake;
68 u32 error; /* gen6+ */
69 u32 err_int; /* gen7 */
70 u32 fault_data0; /* gen8, gen9 */
71 u32 fault_data1; /* gen8, gen9 */
72 u32 done_reg;
73 u32 gac_eco;
74 u32 gam_ecochk;
75 u32 gab_ctl;
76 u32 gfx_mode;
77
78 u32 nfence;
79 u64 fence[I915_MAX_NUM_FENCES];
80 struct intel_overlay_error_state *overlay;
81 struct intel_display_error_state *display;
82
83 struct drm_i915_error_engine {
84 const struct intel_engine_cs *engine;
85
86 /* Software tracked state */
87 bool idle;
88 unsigned long hangcheck_timestamp;
89 int num_requests;
90 u32 reset_count;
91
92 /* position of active request inside the ring */
93 u32 rq_head, rq_post, rq_tail;
94
95 /* our own tracking of ring head and tail */
96 u32 cpu_ring_head;
97 u32 cpu_ring_tail;
98
99 /* Register state */
100 u32 start;
101 u32 tail;
102 u32 head;
103 u32 ctl;
104 u32 mode;
105 u32 hws;
106 u32 ipeir;
107 u32 ipehr;
108 u32 bbstate;
109 u32 instpm;
110 u32 instps;
111 u64 bbaddr;
112 u64 acthd;
113 u32 fault_reg;
114 u64 faddr;
115 u32 rc_psmi; /* sleep state */
116 struct intel_instdone instdone;
117
118 struct drm_i915_error_context {
119 char comm[TASK_COMM_LEN];
120 pid_t pid;
121 u32 hw_id;
122 int active;
123 int guilty;
124 struct i915_sched_attr sched_attr;
125 } context;
126
127 struct drm_i915_error_object {
128 u64 gtt_offset;
129 u64 gtt_size;
130 int num_pages;
131 int page_count;
132 int unused;
133 u32 *pages[0];
134 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
135
136 struct drm_i915_error_object **user_bo;
137 long user_bo_count;
138
139 struct drm_i915_error_object *wa_ctx;
140 struct drm_i915_error_object *default_state;
141
142 struct drm_i915_error_request {
143 unsigned long flags;
144 long jiffies;
145 pid_t pid;
146 u32 context;
147 u32 seqno;
148 u32 start;
149 u32 head;
150 u32 tail;
151 struct i915_sched_attr sched_attr;
152 } *requests, execlist[EXECLIST_MAX_PORTS];
153 unsigned int num_ports;
154
155 struct {
156 u32 gfx_mode;
157 union {
158 u64 pdp[4];
159 u32 pp_dir_base;
160 };
161 } vm_info;
162
163 struct drm_i915_error_engine *next;
164 } *engine;
165
166 struct scatterlist *sgl, *fit;
167};
168
169struct i915_gpu_error {
170 /* For reset and error_state handling. */
171 spinlock_t lock;
172 /* Protected by the above dev->gpu_error.lock. */
173 struct i915_gpu_state *first_error;
174
175 atomic_t pending_fb_pin;
176
177 /** Number of times the device has been reset (global) */
178 atomic_t reset_count;
179
180 /** Number of times an engine has been reset */
181 atomic_t reset_engine_count[I915_NUM_ENGINES];
182};
183
184struct drm_i915_error_state_buf {
185 struct drm_i915_private *i915;
186 struct scatterlist *sgl, *cur, *end;
187
188 char *buf;
189 size_t bytes;
190 size_t size;
191 loff_t iter;
192
193 int err;
194};
195
196#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
197
198__printf(2, 3)
199void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
200
201struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
202void i915_capture_error_state(struct drm_i915_private *dev_priv,
203 intel_engine_mask_t engine_mask,
204 const char *error_msg);
205
206static inline struct i915_gpu_state *
207i915_gpu_state_get(struct i915_gpu_state *gpu)
208{
209 kref_get(&gpu->ref);
210 return gpu;
211}
212
213ssize_t i915_gpu_state_copy_to_buffer(struct i915_gpu_state *error,
214 char *buf, loff_t offset, size_t count);
215
216void __i915_gpu_state_free(struct kref *kref);
217static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
218{
219 if (gpu)
220 kref_put(&gpu->ref, __i915_gpu_state_free);
221}
222
223struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
224void i915_reset_error_state(struct drm_i915_private *i915);
225void i915_disable_error_state(struct drm_i915_private *i915, int err);
226
227#else
228
229static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
230 u32 engine_mask,
231 const char *error_msg)
232{
233}
234
235static inline struct i915_gpu_state *
236i915_first_error_state(struct drm_i915_private *i915)
237{
238 return ERR_PTR(-ENODEV);
239}
240
241static inline void i915_reset_error_state(struct drm_i915_private *i915)
242{
243}
244
245static inline void i915_disable_error_state(struct drm_i915_private *i915,
246 int err)
247{
248}
249
250#endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */
251
252#endif /* _I915_GPU_ERROR_H_ */
1/*
2 * SPDX-License-Identifier: MIT
3 *
4 * Copyright © 2008-2018 Intel Corporation
5 */
6
7#ifndef _I915_GPU_ERROR_H_
8#define _I915_GPU_ERROR_H_
9
10#include <linux/atomic.h>
11#include <linux/kref.h>
12#include <linux/ktime.h>
13#include <linux/sched.h>
14
15#include <drm/drm_mm.h>
16
17#include "display/intel_display_device.h"
18#include "display/intel_display_params.h"
19#include "gt/intel_engine.h"
20#include "gt/intel_engine_types.h"
21#include "gt/intel_gt_types.h"
22#include "gt/uc/intel_uc_fw.h"
23
24#include "intel_device_info.h"
25
26#include "i915_gem.h"
27#include "i915_gem_gtt.h"
28#include "i915_params.h"
29#include "i915_scheduler.h"
30
31struct drm_i915_private;
32struct i915_vma_compress;
33struct intel_engine_capture_vma;
34struct intel_overlay_error_state;
35
36struct i915_vma_coredump {
37 struct i915_vma_coredump *next;
38
39 char name[20];
40
41 u64 gtt_offset;
42 u64 gtt_size;
43 u32 gtt_page_sizes;
44
45 int unused;
46 struct list_head page_list;
47};
48
49struct i915_request_coredump {
50 unsigned long flags;
51 pid_t pid;
52 u32 context;
53 u32 seqno;
54 u32 head;
55 u32 tail;
56 struct i915_sched_attr sched_attr;
57};
58
59struct __guc_capture_parsed_output;
60
61struct intel_engine_coredump {
62 const struct intel_engine_cs *engine;
63
64 bool hung;
65 bool simulated;
66 u32 reset_count;
67
68 /* position of active request inside the ring */
69 u32 rq_head, rq_post, rq_tail;
70
71 /* Register state */
72 u32 ccid;
73 u32 start;
74 u32 tail;
75 u32 head;
76 u32 ctl;
77 u32 mode;
78 u32 hws;
79 u32 ipeir;
80 u32 ipehr;
81 u32 esr;
82 u32 bbstate;
83 u32 instpm;
84 u32 instps;
85 u64 bbaddr;
86 u64 acthd;
87 u32 fault_reg;
88 u64 faddr;
89 u32 rc_psmi; /* sleep state */
90 u32 nopid;
91 u32 excc;
92 u32 cmd_cctl;
93 u32 cscmdop;
94 u32 ctx_sr_ctl;
95 u32 dma_faddr_hi;
96 u32 dma_faddr_lo;
97 struct intel_instdone instdone;
98
99 /* GuC matched capture-lists info */
100 struct intel_guc_state_capture *guc_capture;
101 struct __guc_capture_parsed_output *guc_capture_node;
102
103 struct i915_gem_context_coredump {
104 char comm[TASK_COMM_LEN];
105
106 u64 total_runtime;
107 u64 avg_runtime;
108
109 pid_t pid;
110 int active;
111 int guilty;
112 struct i915_sched_attr sched_attr;
113 u32 hwsp_seqno;
114 } context;
115
116 struct i915_vma_coredump *vma;
117
118 struct i915_request_coredump execlist[EXECLIST_MAX_PORTS];
119 unsigned int num_ports;
120
121 struct {
122 u32 gfx_mode;
123 union {
124 u64 pdp[4];
125 u32 pp_dir_base;
126 };
127 } vm_info;
128
129 struct intel_engine_coredump *next;
130};
131
132struct intel_ctb_coredump {
133 u32 raw_head, head;
134 u32 raw_tail, tail;
135 u32 raw_status;
136 u32 desc_offset;
137 u32 cmds_offset;
138 u32 size;
139};
140
141struct intel_gt_coredump {
142 const struct intel_gt *_gt;
143 bool awake;
144 bool simulated;
145
146 struct intel_gt_info info;
147
148 /* Generic register state */
149 u32 eir;
150 u32 pgtbl_er;
151 u32 ier;
152 u32 gtier[6], ngtier;
153 u32 forcewake;
154 u32 error; /* gen6+ */
155 u32 err_int; /* gen7 */
156 u32 fault_data0; /* gen8, gen9 */
157 u32 fault_data1; /* gen8, gen9 */
158 u32 done_reg;
159 u32 gac_eco;
160 u32 gam_ecochk;
161 u32 gab_ctl;
162 u32 gfx_mode;
163 u32 gtt_cache;
164 u32 aux_err; /* gen12 */
165 u32 gam_done; /* gen12 */
166 u32 clock_frequency;
167 u32 clock_period_ns;
168
169 /* Display related */
170 u32 derrmr;
171 u32 sfc_done[I915_MAX_SFC]; /* gen12 */
172
173 u32 nfence;
174 u64 fence[I915_MAX_NUM_FENCES];
175
176 struct intel_engine_coredump *engine;
177
178 struct intel_uc_coredump {
179 struct intel_uc_fw guc_fw;
180 struct intel_uc_fw huc_fw;
181 struct guc_info {
182 struct intel_ctb_coredump ctb[2];
183 struct i915_vma_coredump *vma_ctb;
184 struct i915_vma_coredump *vma_log;
185 u32 timestamp;
186 u16 last_fence;
187 bool is_guc_capture;
188 } guc;
189 } *uc;
190
191 struct intel_gt_coredump *next;
192};
193
194struct i915_gpu_coredump {
195 struct kref ref;
196 ktime_t time;
197 ktime_t boottime;
198 ktime_t uptime;
199 unsigned long capture;
200
201 struct drm_i915_private *i915;
202
203 struct intel_gt_coredump *gt;
204
205 char error_msg[128];
206 bool simulated;
207 bool wakelock;
208 bool suspended;
209 int iommu;
210 u32 reset_count;
211 u32 suspend_count;
212
213 struct intel_device_info device_info;
214 struct intel_runtime_info runtime_info;
215 struct intel_display_device_info display_device_info;
216 struct intel_display_runtime_info display_runtime_info;
217 struct intel_driver_caps driver_caps;
218 struct i915_params params;
219 struct intel_display_params display_params;
220
221 struct intel_overlay_error_state *overlay;
222
223 struct scatterlist *sgl, *fit;
224};
225
226struct i915_gpu_error {
227 /* For reset and error_state handling. */
228 spinlock_t lock;
229 /* Protected by the above dev->gpu_error.lock. */
230 struct i915_gpu_coredump *first_error;
231
232 atomic_t pending_fb_pin;
233
234 /** Number of times the device has been reset (global) */
235 atomic_t reset_count;
236
237 /** Number of times an engine has been reset */
238 atomic_t reset_engine_count[MAX_ENGINE_CLASS];
239};
240
241struct drm_i915_error_state_buf {
242 struct drm_i915_private *i915;
243 struct scatterlist *sgl, *cur, *end;
244
245 char *buf;
246 size_t bytes;
247 size_t size;
248 loff_t iter;
249
250 int err;
251};
252
253static inline u32 i915_reset_count(struct i915_gpu_error *error)
254{
255 return atomic_read(&error->reset_count);
256}
257
258static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
259 const struct intel_engine_cs *engine)
260{
261 return atomic_read(&error->reset_engine_count[engine->class]);
262}
263
264static inline void
265i915_increase_reset_engine_count(struct i915_gpu_error *error,
266 const struct intel_engine_cs *engine)
267{
268 atomic_inc(&error->reset_engine_count[engine->class]);
269}
270
271#define CORE_DUMP_FLAG_NONE 0x0
272#define CORE_DUMP_FLAG_IS_GUC_CAPTURE BIT(0)
273
274#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) && IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
275void intel_klog_error_capture(struct intel_gt *gt,
276 intel_engine_mask_t engine_mask);
277#else
278static inline void intel_klog_error_capture(struct intel_gt *gt,
279 intel_engine_mask_t engine_mask)
280{
281}
282#endif
283
284#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
285
286__printf(2, 3)
287void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
288
289void i915_capture_error_state(struct intel_gt *gt,
290 intel_engine_mask_t engine_mask, u32 dump_flags);
291
292struct i915_gpu_coredump *
293i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp);
294
295struct intel_gt_coredump *
296intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags);
297
298struct intel_engine_coredump *
299intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags);
300
301struct intel_engine_capture_vma *
302intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
303 struct i915_request *rq,
304 gfp_t gfp);
305
306void intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
307 struct intel_engine_capture_vma *capture,
308 struct i915_vma_compress *compress);
309
310struct i915_vma_compress *
311i915_vma_capture_prepare(struct intel_gt_coredump *gt);
312
313void i915_vma_capture_finish(struct intel_gt_coredump *gt,
314 struct i915_vma_compress *compress);
315
316void i915_error_state_store(struct i915_gpu_coredump *error);
317
318static inline struct i915_gpu_coredump *
319i915_gpu_coredump_get(struct i915_gpu_coredump *gpu)
320{
321 kref_get(&gpu->ref);
322 return gpu;
323}
324
325ssize_t
326i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error,
327 char *buf, loff_t offset, size_t count);
328
329void __i915_gpu_coredump_free(struct kref *kref);
330static inline void i915_gpu_coredump_put(struct i915_gpu_coredump *gpu)
331{
332 if (gpu)
333 kref_put(&gpu->ref, __i915_gpu_coredump_free);
334}
335
336void i915_reset_error_state(struct drm_i915_private *i915);
337void i915_disable_error_state(struct drm_i915_private *i915, int err);
338
339void i915_gpu_error_debugfs_register(struct drm_i915_private *i915);
340void i915_gpu_error_sysfs_setup(struct drm_i915_private *i915);
341void i915_gpu_error_sysfs_teardown(struct drm_i915_private *i915);
342
343#else
344
345__printf(2, 3)
346static inline void
347i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
348{
349}
350
351static inline void
352i915_capture_error_state(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags)
353{
354}
355
356static inline struct i915_gpu_coredump *
357i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp)
358{
359 return NULL;
360}
361
362static inline struct intel_gt_coredump *
363intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags)
364{
365 return NULL;
366}
367
368static inline struct intel_engine_coredump *
369intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags)
370{
371 return NULL;
372}
373
374static inline struct intel_engine_capture_vma *
375intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
376 struct i915_request *rq,
377 gfp_t gfp)
378{
379 return NULL;
380}
381
382static inline void
383intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
384 struct intel_engine_capture_vma *capture,
385 struct i915_vma_compress *compress)
386{
387}
388
389static inline struct i915_vma_compress *
390i915_vma_capture_prepare(struct intel_gt_coredump *gt)
391{
392 return NULL;
393}
394
395static inline void
396i915_vma_capture_finish(struct intel_gt_coredump *gt,
397 struct i915_vma_compress *compress)
398{
399}
400
401static inline void
402i915_error_state_store(struct i915_gpu_coredump *error)
403{
404}
405
406static inline void i915_gpu_coredump_put(struct i915_gpu_coredump *gpu)
407{
408}
409
410static inline void i915_reset_error_state(struct drm_i915_private *i915)
411{
412}
413
414static inline void i915_disable_error_state(struct drm_i915_private *i915,
415 int err)
416{
417}
418
419static inline void i915_gpu_error_debugfs_register(struct drm_i915_private *i915)
420{
421}
422
423static inline void i915_gpu_error_sysfs_setup(struct drm_i915_private *i915)
424{
425}
426
427static inline void i915_gpu_error_sysfs_teardown(struct drm_i915_private *i915)
428{
429}
430
431#endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */
432
433#endif /* _I915_GPU_ERROR_H_ */