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1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Copyright 2015 Freescale Semiconductor, Inc.
4// Copyright 2016 Toradex AG
5
6#include "imx7s.dtsi"
7#include <dt-bindings/reset/imx7-reset.h>
8
9/ {
10 cpus {
11 cpu0: cpu@0 {
12 clock-frequency = <996000000>;
13 operating-points-v2 = <&cpu0_opp_table>;
14 #cooling-cells = <2>;
15 nvmem-cells = <&cpu_speed_grade>;
16 nvmem-cell-names = "speed_grade";
17 };
18
19 cpu1: cpu@1 {
20 compatible = "arm,cortex-a7";
21 device_type = "cpu";
22 reg = <1>;
23 clock-frequency = <996000000>;
24 operating-points-v2 = <&cpu0_opp_table>;
25 cpu-idle-states = <&cpu_sleep_wait>;
26 };
27 };
28
29 timer {
30 compatible = "arm,armv7-timer";
31 interrupt-parent = <&intc>;
32 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
33 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
34 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
35 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
36 };
37
38 cpu0_opp_table: opp-table {
39 compatible = "operating-points-v2";
40 opp-shared;
41
42 opp-792000000 {
43 opp-hz = /bits/ 64 <792000000>;
44 opp-microvolt = <1000000>;
45 clock-latency-ns = <150000>;
46 opp-supported-hw = <0xf>, <0xf>;
47 };
48
49 opp-996000000 {
50 opp-hz = /bits/ 64 <996000000>;
51 opp-microvolt = <1100000>;
52 clock-latency-ns = <150000>;
53 opp-supported-hw = <0xc>, <0xf>;
54 };
55
56 opp-1200000000 {
57 opp-hz = /bits/ 64 <1200000000>;
58 opp-microvolt = <1225000>;
59 clock-latency-ns = <150000>;
60 opp-supported-hw = <0x8>, <0xf>;
61 };
62 };
63
64 usbphynop2: usbphynop2 {
65 compatible = "usb-nop-xceiv";
66 clocks = <&clks IMX7D_USB_PHY2_CLK>;
67 clock-names = "main_clk";
68 #phy-cells = <0>;
69 };
70
71 soc {
72 etm@3007d000 {
73 compatible = "arm,coresight-etm3x", "arm,primecell";
74 reg = <0x3007d000 0x1000>;
75
76 /*
77 * System will hang if added nosmp in kernel command line
78 * without arm,primecell-periphid because amba bus try to
79 * read id and core1 power off at this time.
80 */
81 arm,primecell-periphid = <0xbb956>;
82 cpu = <&cpu1>;
83 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
84 clock-names = "apb_pclk";
85
86 out-ports {
87 port {
88 etm1_out_port: endpoint {
89 remote-endpoint = <&ca_funnel_in_port1>;
90 };
91 };
92 };
93 };
94
95 intc: interrupt-controller@31001000 {
96 compatible = "arm,cortex-a7-gic";
97 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
98 #interrupt-cells = <3>;
99 interrupt-controller;
100 interrupt-parent = <&intc>;
101 reg = <0x31001000 0x1000>,
102 <0x31002000 0x2000>,
103 <0x31004000 0x2000>,
104 <0x31006000 0x2000>;
105 };
106 };
107};
108
109&aips2 {
110 pcie_phy: pcie-phy@306d0000 {
111 compatible = "fsl,imx7d-pcie-phy";
112 reg = <0x306d0000 0x10000>;
113 status = "disabled";
114 };
115};
116
117&aips3 {
118 usbotg2: usb@30b20000 {
119 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
120 reg = <0x30b20000 0x200>;
121 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
122 clocks = <&clks IMX7D_USB_CTRL_CLK>;
123 fsl,usbphy = <&usbphynop2>;
124 fsl,usbmisc = <&usbmisc2 0>;
125 phy-clkgate-delay-us = <400>;
126 status = "disabled";
127 };
128
129 usbmisc2: usbmisc@30b20200 {
130 #index-cells = <1>;
131 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
132 reg = <0x30b20200 0x200>;
133 };
134
135 fec2: ethernet@30bf0000 {
136 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
137 reg = <0x30bf0000 0x10000>;
138 interrupt-names = "int0", "int1", "int2", "pps";
139 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
143 clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>,
144 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
145 <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
146 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
147 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
148 clock-names = "ipg", "ahb", "ptp",
149 "enet_clk_ref", "enet_out";
150 fsl,num-tx-queues = <3>;
151 fsl,num-rx-queues = <3>;
152 status = "disabled";
153 };
154
155 pcie: pcie@33800000 {
156 compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
157 reg = <0x33800000 0x4000>,
158 <0x4ff00000 0x80000>;
159 reg-names = "dbi", "config";
160 #address-cells = <3>;
161 #size-cells = <2>;
162 device_type = "pci";
163 bus-range = <0x00 0xff>;
164 ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O */
165 0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
166 num-lanes = <1>;
167 num-viewport = <4>;
168 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
169 interrupt-names = "msi";
170 #interrupt-cells = <1>;
171 interrupt-map-mask = <0 0 0 0x7>;
172 /*
173 * Reference manual lists pci irqs incorrectly
174 * Real hardware ordering is same as imx6: D+MSI, C, B, A
175 */
176 interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
177 <0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
178 <0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
179 <0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
180 clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
181 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
182 <&clks IMX7D_PCIE_PHY_ROOT_CLK>;
183 clock-names = "pcie", "pcie_bus", "pcie_phy";
184 assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
185 <&clks IMX7D_PCIE_PHY_ROOT_SRC>;
186 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
187 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
188
189 fsl,max-link-speed = <2>;
190 power-domains = <&pgc_pcie_phy>;
191 resets = <&src IMX7_RESET_PCIEPHY>,
192 <&src IMX7_RESET_PCIE_CTRL_APPS_EN>,
193 <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>;
194 reset-names = "pciephy", "apps", "turnoff";
195 fsl,imx7d-pcie-phy = <&pcie_phy>;
196 status = "disabled";
197 };
198};
199
200&ca_funnel_in_ports {
201 #address-cells = <1>;
202 #size-cells = <0>;
203
204 port@1 {
205 reg = <1>;
206 ca_funnel_in_port1: endpoint {
207 remote-endpoint = <&etm1_out_port>;
208 };
209 };
210};