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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright(C) 2015 Linaro Limited. All rights reserved.
4 * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
5 */
6
7#ifndef INCLUDE__UTIL_PERF_CS_ETM_H__
8#define INCLUDE__UTIL_PERF_CS_ETM_H__
9
10#include "util/event.h"
11#include <linux/bits.h>
12
13struct perf_session;
14
15/* Versionning header in case things need tro change in the future. That way
16 * decoding of old snapshot is still possible.
17 */
18enum {
19 /* Starting with 0x0 */
20 CS_HEADER_VERSION_0,
21 /* PMU->type (32 bit), total # of CPUs (32 bit) */
22 CS_PMU_TYPE_CPUS,
23 CS_ETM_SNAPSHOT,
24 CS_HEADER_VERSION_0_MAX,
25};
26
27/* Beginning of header common to both ETMv3 and V4 */
28enum {
29 CS_ETM_MAGIC,
30 CS_ETM_CPU,
31};
32
33/* ETMv3/PTM metadata */
34enum {
35 /* Dynamic, configurable parameters */
36 CS_ETM_ETMCR = CS_ETM_CPU + 1,
37 CS_ETM_ETMTRACEIDR,
38 /* RO, taken from sysFS */
39 CS_ETM_ETMCCER,
40 CS_ETM_ETMIDR,
41 CS_ETM_PRIV_MAX,
42};
43
44/* ETMv4 metadata */
45enum {
46 /* Dynamic, configurable parameters */
47 CS_ETMV4_TRCCONFIGR = CS_ETM_CPU + 1,
48 CS_ETMV4_TRCTRACEIDR,
49 /* RO, taken from sysFS */
50 CS_ETMV4_TRCIDR0,
51 CS_ETMV4_TRCIDR1,
52 CS_ETMV4_TRCIDR2,
53 CS_ETMV4_TRCIDR8,
54 CS_ETMV4_TRCAUTHSTATUS,
55 CS_ETMV4_PRIV_MAX,
56};
57
58/*
59 * ETMv3 exception encoding number:
60 * See Embedded Trace Macrocell spcification (ARM IHI 0014Q)
61 * table 7-12 Encoding of Exception[3:0] for non-ARMv7-M processors.
62 */
63enum {
64 CS_ETMV3_EXC_NONE = 0,
65 CS_ETMV3_EXC_DEBUG_HALT = 1,
66 CS_ETMV3_EXC_SMC = 2,
67 CS_ETMV3_EXC_HYP = 3,
68 CS_ETMV3_EXC_ASYNC_DATA_ABORT = 4,
69 CS_ETMV3_EXC_JAZELLE_THUMBEE = 5,
70 CS_ETMV3_EXC_PE_RESET = 8,
71 CS_ETMV3_EXC_UNDEFINED_INSTR = 9,
72 CS_ETMV3_EXC_SVC = 10,
73 CS_ETMV3_EXC_PREFETCH_ABORT = 11,
74 CS_ETMV3_EXC_DATA_FAULT = 12,
75 CS_ETMV3_EXC_GENERIC = 13,
76 CS_ETMV3_EXC_IRQ = 14,
77 CS_ETMV3_EXC_FIQ = 15,
78};
79
80/*
81 * ETMv4 exception encoding number:
82 * See ARM Embedded Trace Macrocell Architecture Specification (ARM IHI 0064D)
83 * table 6-12 Possible values for the TYPE field in an Exception instruction
84 * trace packet, for ARMv7-A/R and ARMv8-A/R PEs.
85 */
86enum {
87 CS_ETMV4_EXC_RESET = 0,
88 CS_ETMV4_EXC_DEBUG_HALT = 1,
89 CS_ETMV4_EXC_CALL = 2,
90 CS_ETMV4_EXC_TRAP = 3,
91 CS_ETMV4_EXC_SYSTEM_ERROR = 4,
92 CS_ETMV4_EXC_INST_DEBUG = 6,
93 CS_ETMV4_EXC_DATA_DEBUG = 7,
94 CS_ETMV4_EXC_ALIGNMENT = 10,
95 CS_ETMV4_EXC_INST_FAULT = 11,
96 CS_ETMV4_EXC_DATA_FAULT = 12,
97 CS_ETMV4_EXC_IRQ = 14,
98 CS_ETMV4_EXC_FIQ = 15,
99 CS_ETMV4_EXC_END = 31,
100};
101
102enum cs_etm_sample_type {
103 CS_ETM_EMPTY,
104 CS_ETM_RANGE,
105 CS_ETM_DISCONTINUITY,
106 CS_ETM_EXCEPTION,
107 CS_ETM_EXCEPTION_RET,
108};
109
110enum cs_etm_isa {
111 CS_ETM_ISA_UNKNOWN,
112 CS_ETM_ISA_A64,
113 CS_ETM_ISA_A32,
114 CS_ETM_ISA_T32,
115};
116
117/* RB tree for quick conversion between traceID and metadata pointers */
118struct intlist *traceid_list;
119
120struct cs_etm_queue;
121
122struct cs_etm_packet {
123 enum cs_etm_sample_type sample_type;
124 enum cs_etm_isa isa;
125 u64 start_addr;
126 u64 end_addr;
127 u32 instr_count;
128 u32 last_instr_type;
129 u32 last_instr_subtype;
130 u32 flags;
131 u32 exception_number;
132 u8 last_instr_cond;
133 u8 last_instr_taken_branch;
134 u8 last_instr_size;
135 u8 trace_chan_id;
136 int cpu;
137};
138
139#define CS_ETM_PACKET_MAX_BUFFER 1024
140
141/*
142 * When working with per-thread scenarios the process under trace can
143 * be scheduled on any CPU and as such, more than one traceID may be
144 * associated with the same process. Since a traceID of '0' is illegal
145 * as per the CoreSight architecture, use that specific value to
146 * identify the queue where all packets (with any traceID) are
147 * aggregated.
148 */
149#define CS_ETM_PER_THREAD_TRACEID 0
150
151struct cs_etm_packet_queue {
152 u32 packet_count;
153 u32 head;
154 u32 tail;
155 u32 instr_count;
156 u64 timestamp;
157 u64 next_timestamp;
158 struct cs_etm_packet packet_buffer[CS_ETM_PACKET_MAX_BUFFER];
159};
160
161#define KiB(x) ((x) * 1024)
162#define MiB(x) ((x) * 1024 * 1024)
163
164#define CS_ETM_INVAL_ADDR 0xdeadbeefdeadbeefUL
165
166#define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
167
168#define CS_ETM_HEADER_SIZE (CS_HEADER_VERSION_0_MAX * sizeof(u64))
169
170#define __perf_cs_etmv3_magic 0x3030303030303030ULL
171#define __perf_cs_etmv4_magic 0x4040404040404040ULL
172#define CS_ETMV3_PRIV_SIZE (CS_ETM_PRIV_MAX * sizeof(u64))
173#define CS_ETMV4_PRIV_SIZE (CS_ETMV4_PRIV_MAX * sizeof(u64))
174
175#ifdef HAVE_CSTRACE_SUPPORT
176int cs_etm__process_auxtrace_info(union perf_event *event,
177 struct perf_session *session);
178int cs_etm__get_cpu(u8 trace_chan_id, int *cpu);
179int cs_etm__etmq_set_tid(struct cs_etm_queue *etmq,
180 pid_t tid, u8 trace_chan_id);
181bool cs_etm__etmq_is_timeless(struct cs_etm_queue *etmq);
182void cs_etm__etmq_set_traceid_queue_timestamp(struct cs_etm_queue *etmq,
183 u8 trace_chan_id);
184struct cs_etm_packet_queue
185*cs_etm__etmq_get_packet_queue(struct cs_etm_queue *etmq, u8 trace_chan_id);
186#else
187static inline int
188cs_etm__process_auxtrace_info(union perf_event *event __maybe_unused,
189 struct perf_session *session __maybe_unused)
190{
191 return -1;
192}
193
194static inline int cs_etm__get_cpu(u8 trace_chan_id __maybe_unused,
195 int *cpu __maybe_unused)
196{
197 return -1;
198}
199
200static inline int cs_etm__etmq_set_tid(
201 struct cs_etm_queue *etmq __maybe_unused,
202 pid_t tid __maybe_unused,
203 u8 trace_chan_id __maybe_unused)
204{
205 return -1;
206}
207
208static inline bool cs_etm__etmq_is_timeless(
209 struct cs_etm_queue *etmq __maybe_unused)
210{
211 /* What else to return? */
212 return true;
213}
214
215static inline void cs_etm__etmq_set_traceid_queue_timestamp(
216 struct cs_etm_queue *etmq __maybe_unused,
217 u8 trace_chan_id __maybe_unused) {}
218
219static inline struct cs_etm_packet_queue *cs_etm__etmq_get_packet_queue(
220 struct cs_etm_queue *etmq __maybe_unused,
221 u8 trace_chan_id __maybe_unused)
222{
223 return NULL;
224}
225#endif
226
227#endif
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright(C) 2015 Linaro Limited. All rights reserved.
4 * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
5 */
6
7#ifndef INCLUDE__UTIL_PERF_CS_ETM_H__
8#define INCLUDE__UTIL_PERF_CS_ETM_H__
9
10#include "debug.h"
11#include "util/event.h"
12#include <linux/bits.h>
13
14struct perf_session;
15
16/*
17 * Versioning header in case things need to change in the future. That way
18 * decoding of old snapshot is still possible.
19 */
20enum {
21 /* Starting with 0x0 */
22 CS_HEADER_VERSION,
23 /* PMU->type (32 bit), total # of CPUs (32 bit) */
24 CS_PMU_TYPE_CPUS,
25 CS_ETM_SNAPSHOT,
26 CS_HEADER_VERSION_MAX,
27};
28
29/*
30 * Update the version for new format.
31 *
32 * New version 1 format adds a param count to the per cpu metadata.
33 * This allows easy adding of new metadata parameters.
34 * Requires that new params always added after current ones.
35 * Also allows client reader to handle file versions that are different by
36 * checking the number of params in the file vs the number expected.
37 */
38#define CS_HEADER_CURRENT_VERSION 1
39
40/* Beginning of header common to both ETMv3 and V4 */
41enum {
42 CS_ETM_MAGIC,
43 CS_ETM_CPU,
44 /* Number of trace config params in following ETM specific block */
45 CS_ETM_NR_TRC_PARAMS,
46 CS_ETM_COMMON_BLK_MAX_V1,
47};
48
49/* ETMv3/PTM metadata */
50enum {
51 /* Dynamic, configurable parameters */
52 CS_ETM_ETMCR = CS_ETM_COMMON_BLK_MAX_V1,
53 CS_ETM_ETMTRACEIDR,
54 /* RO, taken from sysFS */
55 CS_ETM_ETMCCER,
56 CS_ETM_ETMIDR,
57 CS_ETM_PRIV_MAX,
58};
59
60/* define fixed version 0 length - allow new format reader to read old files. */
61#define CS_ETM_NR_TRC_PARAMS_V0 (CS_ETM_ETMIDR - CS_ETM_ETMCR + 1)
62
63/* ETMv4 metadata */
64enum {
65 /* Dynamic, configurable parameters */
66 CS_ETMV4_TRCCONFIGR = CS_ETM_COMMON_BLK_MAX_V1,
67 CS_ETMV4_TRCTRACEIDR,
68 /* RO, taken from sysFS */
69 CS_ETMV4_TRCIDR0,
70 CS_ETMV4_TRCIDR1,
71 CS_ETMV4_TRCIDR2,
72 CS_ETMV4_TRCIDR8,
73 CS_ETMV4_TRCAUTHSTATUS,
74 CS_ETMV4_PRIV_MAX,
75};
76
77/* define fixed version 0 length - allow new format reader to read old files. */
78#define CS_ETMV4_NR_TRC_PARAMS_V0 (CS_ETMV4_TRCAUTHSTATUS - CS_ETMV4_TRCCONFIGR + 1)
79
80/*
81 * ETE metadata is ETMv4 plus TRCDEVARCH register and doesn't support header V0 since it was
82 * added in header V1
83 */
84enum {
85 CS_ETE_TRCDEVARCH = CS_ETMV4_PRIV_MAX,
86 CS_ETE_PRIV_MAX
87};
88
89/*
90 * ETMv3 exception encoding number:
91 * See Embedded Trace Macrocell specification (ARM IHI 0014Q)
92 * table 7-12 Encoding of Exception[3:0] for non-ARMv7-M processors.
93 */
94enum {
95 CS_ETMV3_EXC_NONE = 0,
96 CS_ETMV3_EXC_DEBUG_HALT = 1,
97 CS_ETMV3_EXC_SMC = 2,
98 CS_ETMV3_EXC_HYP = 3,
99 CS_ETMV3_EXC_ASYNC_DATA_ABORT = 4,
100 CS_ETMV3_EXC_JAZELLE_THUMBEE = 5,
101 CS_ETMV3_EXC_PE_RESET = 8,
102 CS_ETMV3_EXC_UNDEFINED_INSTR = 9,
103 CS_ETMV3_EXC_SVC = 10,
104 CS_ETMV3_EXC_PREFETCH_ABORT = 11,
105 CS_ETMV3_EXC_DATA_FAULT = 12,
106 CS_ETMV3_EXC_GENERIC = 13,
107 CS_ETMV3_EXC_IRQ = 14,
108 CS_ETMV3_EXC_FIQ = 15,
109};
110
111/*
112 * ETMv4 exception encoding number:
113 * See ARM Embedded Trace Macrocell Architecture Specification (ARM IHI 0064D)
114 * table 6-12 Possible values for the TYPE field in an Exception instruction
115 * trace packet, for ARMv7-A/R and ARMv8-A/R PEs.
116 */
117enum {
118 CS_ETMV4_EXC_RESET = 0,
119 CS_ETMV4_EXC_DEBUG_HALT = 1,
120 CS_ETMV4_EXC_CALL = 2,
121 CS_ETMV4_EXC_TRAP = 3,
122 CS_ETMV4_EXC_SYSTEM_ERROR = 4,
123 CS_ETMV4_EXC_INST_DEBUG = 6,
124 CS_ETMV4_EXC_DATA_DEBUG = 7,
125 CS_ETMV4_EXC_ALIGNMENT = 10,
126 CS_ETMV4_EXC_INST_FAULT = 11,
127 CS_ETMV4_EXC_DATA_FAULT = 12,
128 CS_ETMV4_EXC_IRQ = 14,
129 CS_ETMV4_EXC_FIQ = 15,
130 CS_ETMV4_EXC_END = 31,
131};
132
133enum cs_etm_sample_type {
134 CS_ETM_EMPTY,
135 CS_ETM_RANGE,
136 CS_ETM_DISCONTINUITY,
137 CS_ETM_EXCEPTION,
138 CS_ETM_EXCEPTION_RET,
139};
140
141enum cs_etm_isa {
142 CS_ETM_ISA_UNKNOWN,
143 CS_ETM_ISA_A64,
144 CS_ETM_ISA_A32,
145 CS_ETM_ISA_T32,
146};
147
148struct cs_etm_queue;
149
150struct cs_etm_packet {
151 enum cs_etm_sample_type sample_type;
152 enum cs_etm_isa isa;
153 u64 start_addr;
154 u64 end_addr;
155 u32 instr_count;
156 u32 last_instr_type;
157 u32 last_instr_subtype;
158 u32 flags;
159 u32 exception_number;
160 u8 last_instr_cond;
161 u8 last_instr_taken_branch;
162 u8 last_instr_size;
163 u8 trace_chan_id;
164 int cpu;
165};
166
167#define CS_ETM_PACKET_MAX_BUFFER 1024
168
169/*
170 * When working with per-thread scenarios the process under trace can
171 * be scheduled on any CPU and as such, more than one traceID may be
172 * associated with the same process. Since a traceID of '0' is illegal
173 * as per the CoreSight architecture, use that specific value to
174 * identify the queue where all packets (with any traceID) are
175 * aggregated.
176 */
177#define CS_ETM_PER_THREAD_TRACEID 0
178
179struct cs_etm_packet_queue {
180 u32 packet_count;
181 u32 head;
182 u32 tail;
183 u32 instr_count;
184 u64 cs_timestamp;
185 u64 next_cs_timestamp;
186 struct cs_etm_packet packet_buffer[CS_ETM_PACKET_MAX_BUFFER];
187};
188
189#define KiB(x) ((x) * 1024)
190#define MiB(x) ((x) * 1024 * 1024)
191
192#define CS_ETM_INVAL_ADDR 0xdeadbeefdeadbeefUL
193
194#define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
195
196#define CS_ETM_HEADER_SIZE (CS_HEADER_VERSION_MAX * sizeof(u64))
197
198#define __perf_cs_etmv3_magic 0x3030303030303030ULL
199#define __perf_cs_etmv4_magic 0x4040404040404040ULL
200#define __perf_cs_ete_magic 0x5050505050505050ULL
201#define CS_ETMV3_PRIV_SIZE (CS_ETM_PRIV_MAX * sizeof(u64))
202#define CS_ETMV4_PRIV_SIZE (CS_ETMV4_PRIV_MAX * sizeof(u64))
203#define CS_ETE_PRIV_SIZE (CS_ETE_PRIV_MAX * sizeof(u64))
204
205#define INFO_HEADER_SIZE (sizeof(((struct perf_record_auxtrace_info *)0)->type) + \
206 sizeof(((struct perf_record_auxtrace_info *)0)->reserved__))
207
208int cs_etm__process_auxtrace_info(union perf_event *event,
209 struct perf_session *session);
210
211#ifdef HAVE_CSTRACE_SUPPORT
212int cs_etm__get_cpu(u8 trace_chan_id, int *cpu);
213int cs_etm__get_pid_fmt(u8 trace_chan_id, u64 *pid_fmt);
214int cs_etm__etmq_set_tid(struct cs_etm_queue *etmq,
215 pid_t tid, u8 trace_chan_id);
216bool cs_etm__etmq_is_timeless(struct cs_etm_queue *etmq);
217void cs_etm__etmq_set_traceid_queue_timestamp(struct cs_etm_queue *etmq,
218 u8 trace_chan_id);
219struct cs_etm_packet_queue
220*cs_etm__etmq_get_packet_queue(struct cs_etm_queue *etmq, u8 trace_chan_id);
221int cs_etm__process_auxtrace_info_full(union perf_event *event __maybe_unused,
222 struct perf_session *session __maybe_unused);
223#else
224static inline int
225cs_etm__process_auxtrace_info_full(union perf_event *event __maybe_unused,
226 struct perf_session *session __maybe_unused)
227{
228 pr_err("\nCS ETM Trace: OpenCSD is not linked in, please recompile with CORESIGHT=1\n");
229 return -1;
230}
231#endif
232
233#endif