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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Based on meson_uart.c, by AMLOGIC, INC.
4 *
5 * Copyright (C) 2014 Carlo Caione <carlo@caione.org>
6 */
7
8#if defined(CONFIG_SERIAL_MESON_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
9#define SUPPORT_SYSRQ
10#endif
11
12#include <linux/clk.h>
13#include <linux/console.h>
14#include <linux/delay.h>
15#include <linux/init.h>
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/of.h>
20#include <linux/platform_device.h>
21#include <linux/serial.h>
22#include <linux/serial_core.h>
23#include <linux/tty.h>
24#include <linux/tty_flip.h>
25
26/* Register offsets */
27#define AML_UART_WFIFO 0x00
28#define AML_UART_RFIFO 0x04
29#define AML_UART_CONTROL 0x08
30#define AML_UART_STATUS 0x0c
31#define AML_UART_MISC 0x10
32#define AML_UART_REG5 0x14
33
34/* AML_UART_CONTROL bits */
35#define AML_UART_TX_EN BIT(12)
36#define AML_UART_RX_EN BIT(13)
37#define AML_UART_TWO_WIRE_EN BIT(15)
38#define AML_UART_STOP_BIT_LEN_MASK (0x03 << 16)
39#define AML_UART_STOP_BIT_1SB (0x00 << 16)
40#define AML_UART_STOP_BIT_2SB (0x01 << 16)
41#define AML_UART_PARITY_TYPE BIT(18)
42#define AML_UART_PARITY_EN BIT(19)
43#define AML_UART_TX_RST BIT(22)
44#define AML_UART_RX_RST BIT(23)
45#define AML_UART_CLEAR_ERR BIT(24)
46#define AML_UART_RX_INT_EN BIT(27)
47#define AML_UART_TX_INT_EN BIT(28)
48#define AML_UART_DATA_LEN_MASK (0x03 << 20)
49#define AML_UART_DATA_LEN_8BIT (0x00 << 20)
50#define AML_UART_DATA_LEN_7BIT (0x01 << 20)
51#define AML_UART_DATA_LEN_6BIT (0x02 << 20)
52#define AML_UART_DATA_LEN_5BIT (0x03 << 20)
53
54/* AML_UART_STATUS bits */
55#define AML_UART_PARITY_ERR BIT(16)
56#define AML_UART_FRAME_ERR BIT(17)
57#define AML_UART_TX_FIFO_WERR BIT(18)
58#define AML_UART_RX_EMPTY BIT(20)
59#define AML_UART_TX_FULL BIT(21)
60#define AML_UART_TX_EMPTY BIT(22)
61#define AML_UART_XMIT_BUSY BIT(25)
62#define AML_UART_ERR (AML_UART_PARITY_ERR | \
63 AML_UART_FRAME_ERR | \
64 AML_UART_TX_FIFO_WERR)
65
66/* AML_UART_MISC bits */
67#define AML_UART_XMIT_IRQ(c) (((c) & 0xff) << 8)
68#define AML_UART_RECV_IRQ(c) ((c) & 0xff)
69
70/* AML_UART_REG5 bits */
71#define AML_UART_BAUD_MASK 0x7fffff
72#define AML_UART_BAUD_USE BIT(23)
73#define AML_UART_BAUD_XTAL BIT(24)
74
75#define AML_UART_PORT_NUM 12
76#define AML_UART_PORT_OFFSET 6
77#define AML_UART_DEV_NAME "ttyAML"
78
79
80static struct uart_driver meson_uart_driver;
81
82static struct uart_port *meson_ports[AML_UART_PORT_NUM];
83
84static void meson_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
85{
86}
87
88static unsigned int meson_uart_get_mctrl(struct uart_port *port)
89{
90 return TIOCM_CTS;
91}
92
93static unsigned int meson_uart_tx_empty(struct uart_port *port)
94{
95 u32 val;
96
97 val = readl(port->membase + AML_UART_STATUS);
98 val &= (AML_UART_TX_EMPTY | AML_UART_XMIT_BUSY);
99 return (val == AML_UART_TX_EMPTY) ? TIOCSER_TEMT : 0;
100}
101
102static void meson_uart_stop_tx(struct uart_port *port)
103{
104 u32 val;
105
106 val = readl(port->membase + AML_UART_CONTROL);
107 val &= ~AML_UART_TX_INT_EN;
108 writel(val, port->membase + AML_UART_CONTROL);
109}
110
111static void meson_uart_stop_rx(struct uart_port *port)
112{
113 u32 val;
114
115 val = readl(port->membase + AML_UART_CONTROL);
116 val &= ~AML_UART_RX_EN;
117 writel(val, port->membase + AML_UART_CONTROL);
118}
119
120static void meson_uart_shutdown(struct uart_port *port)
121{
122 unsigned long flags;
123 u32 val;
124
125 free_irq(port->irq, port);
126
127 spin_lock_irqsave(&port->lock, flags);
128
129 val = readl(port->membase + AML_UART_CONTROL);
130 val &= ~AML_UART_RX_EN;
131 val &= ~(AML_UART_RX_INT_EN | AML_UART_TX_INT_EN);
132 writel(val, port->membase + AML_UART_CONTROL);
133
134 spin_unlock_irqrestore(&port->lock, flags);
135}
136
137static void meson_uart_start_tx(struct uart_port *port)
138{
139 struct circ_buf *xmit = &port->state->xmit;
140 unsigned int ch;
141 u32 val;
142
143 if (uart_tx_stopped(port)) {
144 meson_uart_stop_tx(port);
145 return;
146 }
147
148 while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) {
149 if (port->x_char) {
150 writel(port->x_char, port->membase + AML_UART_WFIFO);
151 port->icount.tx++;
152 port->x_char = 0;
153 continue;
154 }
155
156 if (uart_circ_empty(xmit))
157 break;
158
159 ch = xmit->buf[xmit->tail];
160 writel(ch, port->membase + AML_UART_WFIFO);
161 xmit->tail = (xmit->tail+1) & (SERIAL_XMIT_SIZE - 1);
162 port->icount.tx++;
163 }
164
165 if (!uart_circ_empty(xmit)) {
166 val = readl(port->membase + AML_UART_CONTROL);
167 val |= AML_UART_TX_INT_EN;
168 writel(val, port->membase + AML_UART_CONTROL);
169 }
170
171 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
172 uart_write_wakeup(port);
173}
174
175static void meson_receive_chars(struct uart_port *port)
176{
177 struct tty_port *tport = &port->state->port;
178 char flag;
179 u32 ostatus, status, ch, mode;
180
181 do {
182 flag = TTY_NORMAL;
183 port->icount.rx++;
184 ostatus = status = readl(port->membase + AML_UART_STATUS);
185
186 if (status & AML_UART_ERR) {
187 if (status & AML_UART_TX_FIFO_WERR)
188 port->icount.overrun++;
189 else if (status & AML_UART_FRAME_ERR)
190 port->icount.frame++;
191 else if (status & AML_UART_PARITY_ERR)
192 port->icount.frame++;
193
194 mode = readl(port->membase + AML_UART_CONTROL);
195 mode |= AML_UART_CLEAR_ERR;
196 writel(mode, port->membase + AML_UART_CONTROL);
197
198 /* It doesn't clear to 0 automatically */
199 mode &= ~AML_UART_CLEAR_ERR;
200 writel(mode, port->membase + AML_UART_CONTROL);
201
202 status &= port->read_status_mask;
203 if (status & AML_UART_FRAME_ERR)
204 flag = TTY_FRAME;
205 else if (status & AML_UART_PARITY_ERR)
206 flag = TTY_PARITY;
207 }
208
209 ch = readl(port->membase + AML_UART_RFIFO);
210 ch &= 0xff;
211
212 if ((ostatus & AML_UART_FRAME_ERR) && (ch == 0)) {
213 port->icount.brk++;
214 flag = TTY_BREAK;
215 if (uart_handle_break(port))
216 continue;
217 }
218
219 if (uart_handle_sysrq_char(port, ch))
220 continue;
221
222 if ((status & port->ignore_status_mask) == 0)
223 tty_insert_flip_char(tport, ch, flag);
224
225 if (status & AML_UART_TX_FIFO_WERR)
226 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
227
228 } while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY));
229
230 spin_unlock(&port->lock);
231 tty_flip_buffer_push(tport);
232 spin_lock(&port->lock);
233}
234
235static irqreturn_t meson_uart_interrupt(int irq, void *dev_id)
236{
237 struct uart_port *port = (struct uart_port *)dev_id;
238
239 spin_lock(&port->lock);
240
241 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY))
242 meson_receive_chars(port);
243
244 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) {
245 if (readl(port->membase + AML_UART_CONTROL) & AML_UART_TX_INT_EN)
246 meson_uart_start_tx(port);
247 }
248
249 spin_unlock(&port->lock);
250
251 return IRQ_HANDLED;
252}
253
254static const char *meson_uart_type(struct uart_port *port)
255{
256 return (port->type == PORT_MESON) ? "meson_uart" : NULL;
257}
258
259static void meson_uart_reset(struct uart_port *port)
260{
261 u32 val;
262
263 val = readl(port->membase + AML_UART_CONTROL);
264 val |= (AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLEAR_ERR);
265 writel(val, port->membase + AML_UART_CONTROL);
266
267 val &= ~(AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLEAR_ERR);
268 writel(val, port->membase + AML_UART_CONTROL);
269}
270
271static int meson_uart_startup(struct uart_port *port)
272{
273 u32 val;
274 int ret = 0;
275
276 val = readl(port->membase + AML_UART_CONTROL);
277 val |= AML_UART_CLEAR_ERR;
278 writel(val, port->membase + AML_UART_CONTROL);
279 val &= ~AML_UART_CLEAR_ERR;
280 writel(val, port->membase + AML_UART_CONTROL);
281
282 val |= (AML_UART_RX_EN | AML_UART_TX_EN);
283 writel(val, port->membase + AML_UART_CONTROL);
284
285 val |= (AML_UART_RX_INT_EN | AML_UART_TX_INT_EN);
286 writel(val, port->membase + AML_UART_CONTROL);
287
288 val = (AML_UART_RECV_IRQ(1) | AML_UART_XMIT_IRQ(port->fifosize / 2));
289 writel(val, port->membase + AML_UART_MISC);
290
291 ret = request_irq(port->irq, meson_uart_interrupt, 0,
292 port->name, port);
293
294 return ret;
295}
296
297static void meson_uart_change_speed(struct uart_port *port, unsigned long baud)
298{
299 u32 val;
300
301 while (!meson_uart_tx_empty(port))
302 cpu_relax();
303
304 if (port->uartclk == 24000000) {
305 val = ((port->uartclk / 3) / baud) - 1;
306 val |= AML_UART_BAUD_XTAL;
307 } else {
308 val = ((port->uartclk * 10 / (baud * 4) + 5) / 10) - 1;
309 }
310 val |= AML_UART_BAUD_USE;
311 writel(val, port->membase + AML_UART_REG5);
312}
313
314static void meson_uart_set_termios(struct uart_port *port,
315 struct ktermios *termios,
316 struct ktermios *old)
317{
318 unsigned int cflags, iflags, baud;
319 unsigned long flags;
320 u32 val;
321
322 spin_lock_irqsave(&port->lock, flags);
323
324 cflags = termios->c_cflag;
325 iflags = termios->c_iflag;
326
327 val = readl(port->membase + AML_UART_CONTROL);
328
329 val &= ~AML_UART_DATA_LEN_MASK;
330 switch (cflags & CSIZE) {
331 case CS8:
332 val |= AML_UART_DATA_LEN_8BIT;
333 break;
334 case CS7:
335 val |= AML_UART_DATA_LEN_7BIT;
336 break;
337 case CS6:
338 val |= AML_UART_DATA_LEN_6BIT;
339 break;
340 case CS5:
341 val |= AML_UART_DATA_LEN_5BIT;
342 break;
343 }
344
345 if (cflags & PARENB)
346 val |= AML_UART_PARITY_EN;
347 else
348 val &= ~AML_UART_PARITY_EN;
349
350 if (cflags & PARODD)
351 val |= AML_UART_PARITY_TYPE;
352 else
353 val &= ~AML_UART_PARITY_TYPE;
354
355 val &= ~AML_UART_STOP_BIT_LEN_MASK;
356 if (cflags & CSTOPB)
357 val |= AML_UART_STOP_BIT_2SB;
358 else
359 val |= AML_UART_STOP_BIT_1SB;
360
361 if (cflags & CRTSCTS)
362 val &= ~AML_UART_TWO_WIRE_EN;
363 else
364 val |= AML_UART_TWO_WIRE_EN;
365
366 writel(val, port->membase + AML_UART_CONTROL);
367
368 baud = uart_get_baud_rate(port, termios, old, 50, 4000000);
369 meson_uart_change_speed(port, baud);
370
371 port->read_status_mask = AML_UART_TX_FIFO_WERR;
372 if (iflags & INPCK)
373 port->read_status_mask |= AML_UART_PARITY_ERR |
374 AML_UART_FRAME_ERR;
375
376 port->ignore_status_mask = 0;
377 if (iflags & IGNPAR)
378 port->ignore_status_mask |= AML_UART_PARITY_ERR |
379 AML_UART_FRAME_ERR;
380
381 uart_update_timeout(port, termios->c_cflag, baud);
382 spin_unlock_irqrestore(&port->lock, flags);
383}
384
385static int meson_uart_verify_port(struct uart_port *port,
386 struct serial_struct *ser)
387{
388 int ret = 0;
389
390 if (port->type != PORT_MESON)
391 ret = -EINVAL;
392 if (port->irq != ser->irq)
393 ret = -EINVAL;
394 if (ser->baud_base < 9600)
395 ret = -EINVAL;
396 return ret;
397}
398
399static void meson_uart_release_port(struct uart_port *port)
400{
401 devm_iounmap(port->dev, port->membase);
402 port->membase = NULL;
403 devm_release_mem_region(port->dev, port->mapbase, port->mapsize);
404}
405
406static int meson_uart_request_port(struct uart_port *port)
407{
408 if (!devm_request_mem_region(port->dev, port->mapbase, port->mapsize,
409 dev_name(port->dev))) {
410 dev_err(port->dev, "Memory region busy\n");
411 return -EBUSY;
412 }
413
414 port->membase = devm_ioremap_nocache(port->dev, port->mapbase,
415 port->mapsize);
416 if (!port->membase)
417 return -ENOMEM;
418
419 return 0;
420}
421
422static void meson_uart_config_port(struct uart_port *port, int flags)
423{
424 if (flags & UART_CONFIG_TYPE) {
425 port->type = PORT_MESON;
426 meson_uart_request_port(port);
427 }
428}
429
430static const struct uart_ops meson_uart_ops = {
431 .set_mctrl = meson_uart_set_mctrl,
432 .get_mctrl = meson_uart_get_mctrl,
433 .tx_empty = meson_uart_tx_empty,
434 .start_tx = meson_uart_start_tx,
435 .stop_tx = meson_uart_stop_tx,
436 .stop_rx = meson_uart_stop_rx,
437 .startup = meson_uart_startup,
438 .shutdown = meson_uart_shutdown,
439 .set_termios = meson_uart_set_termios,
440 .type = meson_uart_type,
441 .config_port = meson_uart_config_port,
442 .request_port = meson_uart_request_port,
443 .release_port = meson_uart_release_port,
444 .verify_port = meson_uart_verify_port,
445};
446
447#ifdef CONFIG_SERIAL_MESON_CONSOLE
448static void meson_uart_enable_tx_engine(struct uart_port *port)
449{
450 u32 val;
451
452 val = readl(port->membase + AML_UART_CONTROL);
453 val |= AML_UART_TX_EN;
454 writel(val, port->membase + AML_UART_CONTROL);
455}
456
457static void meson_console_putchar(struct uart_port *port, int ch)
458{
459 if (!port->membase)
460 return;
461
462 while (readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)
463 cpu_relax();
464 writel(ch, port->membase + AML_UART_WFIFO);
465}
466
467static void meson_serial_port_write(struct uart_port *port, const char *s,
468 u_int count)
469{
470 unsigned long flags;
471 int locked;
472 u32 val, tmp;
473
474 local_irq_save(flags);
475 if (port->sysrq) {
476 locked = 0;
477 } else if (oops_in_progress) {
478 locked = spin_trylock(&port->lock);
479 } else {
480 spin_lock(&port->lock);
481 locked = 1;
482 }
483
484 val = readl(port->membase + AML_UART_CONTROL);
485 tmp = val & ~(AML_UART_TX_INT_EN | AML_UART_RX_INT_EN);
486 writel(tmp, port->membase + AML_UART_CONTROL);
487
488 uart_console_write(port, s, count, meson_console_putchar);
489 writel(val, port->membase + AML_UART_CONTROL);
490
491 if (locked)
492 spin_unlock(&port->lock);
493 local_irq_restore(flags);
494}
495
496static void meson_serial_console_write(struct console *co, const char *s,
497 u_int count)
498{
499 struct uart_port *port;
500
501 port = meson_ports[co->index];
502 if (!port)
503 return;
504
505 meson_serial_port_write(port, s, count);
506}
507
508static int meson_serial_console_setup(struct console *co, char *options)
509{
510 struct uart_port *port;
511 int baud = 115200;
512 int bits = 8;
513 int parity = 'n';
514 int flow = 'n';
515
516 if (co->index < 0 || co->index >= AML_UART_PORT_NUM)
517 return -EINVAL;
518
519 port = meson_ports[co->index];
520 if (!port || !port->membase)
521 return -ENODEV;
522
523 meson_uart_enable_tx_engine(port);
524
525 if (options)
526 uart_parse_options(options, &baud, &parity, &bits, &flow);
527
528 return uart_set_options(port, co, baud, parity, bits, flow);
529}
530
531static struct console meson_serial_console = {
532 .name = AML_UART_DEV_NAME,
533 .write = meson_serial_console_write,
534 .device = uart_console_device,
535 .setup = meson_serial_console_setup,
536 .flags = CON_PRINTBUFFER,
537 .index = -1,
538 .data = &meson_uart_driver,
539};
540
541static int __init meson_serial_console_init(void)
542{
543 register_console(&meson_serial_console);
544 return 0;
545}
546console_initcall(meson_serial_console_init);
547
548static void meson_serial_early_console_write(struct console *co,
549 const char *s,
550 u_int count)
551{
552 struct earlycon_device *dev = co->data;
553
554 meson_serial_port_write(&dev->port, s, count);
555}
556
557static int __init
558meson_serial_early_console_setup(struct earlycon_device *device, const char *opt)
559{
560 if (!device->port.membase)
561 return -ENODEV;
562
563 meson_uart_enable_tx_engine(&device->port);
564 device->con->write = meson_serial_early_console_write;
565 return 0;
566}
567/* Legacy bindings, should be removed when no more used */
568OF_EARLYCON_DECLARE(meson, "amlogic,meson-uart",
569 meson_serial_early_console_setup);
570/* Stable bindings */
571OF_EARLYCON_DECLARE(meson, "amlogic,meson-ao-uart",
572 meson_serial_early_console_setup);
573
574#define MESON_SERIAL_CONSOLE (&meson_serial_console)
575#else
576#define MESON_SERIAL_CONSOLE NULL
577#endif
578
579static struct uart_driver meson_uart_driver = {
580 .owner = THIS_MODULE,
581 .driver_name = "meson_uart",
582 .dev_name = AML_UART_DEV_NAME,
583 .nr = AML_UART_PORT_NUM,
584 .cons = MESON_SERIAL_CONSOLE,
585};
586
587static inline struct clk *meson_uart_probe_clock(struct device *dev,
588 const char *id)
589{
590 struct clk *clk = NULL;
591 int ret;
592
593 clk = devm_clk_get(dev, id);
594 if (IS_ERR(clk))
595 return clk;
596
597 ret = clk_prepare_enable(clk);
598 if (ret) {
599 dev_err(dev, "couldn't enable clk\n");
600 return ERR_PTR(ret);
601 }
602
603 devm_add_action_or_reset(dev,
604 (void(*)(void *))clk_disable_unprepare,
605 clk);
606
607 return clk;
608}
609
610/*
611 * This function gets clocks in the legacy non-stable DT bindings.
612 * This code will be remove once all the platforms switch to the
613 * new DT bindings.
614 */
615static int meson_uart_probe_clocks_legacy(struct platform_device *pdev,
616 struct uart_port *port)
617{
618 struct clk *clk = NULL;
619
620 clk = meson_uart_probe_clock(&pdev->dev, NULL);
621 if (IS_ERR(clk))
622 return PTR_ERR(clk);
623
624 port->uartclk = clk_get_rate(clk);
625
626 return 0;
627}
628
629static int meson_uart_probe_clocks(struct platform_device *pdev,
630 struct uart_port *port)
631{
632 struct clk *clk_xtal = NULL;
633 struct clk *clk_pclk = NULL;
634 struct clk *clk_baud = NULL;
635
636 clk_pclk = meson_uart_probe_clock(&pdev->dev, "pclk");
637 if (IS_ERR(clk_pclk))
638 return PTR_ERR(clk_pclk);
639
640 clk_xtal = meson_uart_probe_clock(&pdev->dev, "xtal");
641 if (IS_ERR(clk_xtal))
642 return PTR_ERR(clk_xtal);
643
644 clk_baud = meson_uart_probe_clock(&pdev->dev, "baud");
645 if (IS_ERR(clk_baud))
646 return PTR_ERR(clk_baud);
647
648 port->uartclk = clk_get_rate(clk_baud);
649
650 return 0;
651}
652
653static int meson_uart_probe(struct platform_device *pdev)
654{
655 struct resource *res_mem, *res_irq;
656 struct uart_port *port;
657 int ret = 0;
658 int id = -1;
659
660 if (pdev->dev.of_node)
661 pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
662
663 if (pdev->id < 0) {
664 for (id = AML_UART_PORT_OFFSET; id < AML_UART_PORT_NUM; id++) {
665 if (!meson_ports[id]) {
666 pdev->id = id;
667 break;
668 }
669 }
670 }
671
672 if (pdev->id < 0 || pdev->id >= AML_UART_PORT_NUM)
673 return -EINVAL;
674
675 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
676 if (!res_mem)
677 return -ENODEV;
678
679 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
680 if (!res_irq)
681 return -ENODEV;
682
683 if (meson_ports[pdev->id]) {
684 dev_err(&pdev->dev, "port %d already allocated\n", pdev->id);
685 return -EBUSY;
686 }
687
688 port = devm_kzalloc(&pdev->dev, sizeof(struct uart_port), GFP_KERNEL);
689 if (!port)
690 return -ENOMEM;
691
692 /* Use legacy way until all platforms switch to new bindings */
693 if (of_device_is_compatible(pdev->dev.of_node, "amlogic,meson-uart"))
694 ret = meson_uart_probe_clocks_legacy(pdev, port);
695 else
696 ret = meson_uart_probe_clocks(pdev, port);
697
698 if (ret)
699 return ret;
700
701 port->iotype = UPIO_MEM;
702 port->mapbase = res_mem->start;
703 port->mapsize = resource_size(res_mem);
704 port->irq = res_irq->start;
705 port->flags = UPF_BOOT_AUTOCONF | UPF_LOW_LATENCY;
706 port->dev = &pdev->dev;
707 port->line = pdev->id;
708 port->type = PORT_MESON;
709 port->x_char = 0;
710 port->ops = &meson_uart_ops;
711 port->fifosize = 64;
712
713 meson_ports[pdev->id] = port;
714 platform_set_drvdata(pdev, port);
715
716 /* reset port before registering (and possibly registering console) */
717 if (meson_uart_request_port(port) >= 0) {
718 meson_uart_reset(port);
719 meson_uart_release_port(port);
720 }
721
722 ret = uart_add_one_port(&meson_uart_driver, port);
723 if (ret)
724 meson_ports[pdev->id] = NULL;
725
726 return ret;
727}
728
729static int meson_uart_remove(struct platform_device *pdev)
730{
731 struct uart_port *port;
732
733 port = platform_get_drvdata(pdev);
734 uart_remove_one_port(&meson_uart_driver, port);
735 meson_ports[pdev->id] = NULL;
736
737 return 0;
738}
739
740static const struct of_device_id meson_uart_dt_match[] = {
741 /* Legacy bindings, should be removed when no more used */
742 { .compatible = "amlogic,meson-uart" },
743 /* Stable bindings */
744 { .compatible = "amlogic,meson6-uart" },
745 { .compatible = "amlogic,meson8-uart" },
746 { .compatible = "amlogic,meson8b-uart" },
747 { .compatible = "amlogic,meson-gx-uart" },
748 { /* sentinel */ },
749};
750MODULE_DEVICE_TABLE(of, meson_uart_dt_match);
751
752static struct platform_driver meson_uart_platform_driver = {
753 .probe = meson_uart_probe,
754 .remove = meson_uart_remove,
755 .driver = {
756 .name = "meson_uart",
757 .of_match_table = meson_uart_dt_match,
758 },
759};
760
761static int __init meson_uart_init(void)
762{
763 int ret;
764
765 ret = uart_register_driver(&meson_uart_driver);
766 if (ret)
767 return ret;
768
769 ret = platform_driver_register(&meson_uart_platform_driver);
770 if (ret)
771 uart_unregister_driver(&meson_uart_driver);
772
773 return ret;
774}
775
776static void __exit meson_uart_exit(void)
777{
778 platform_driver_unregister(&meson_uart_platform_driver);
779 uart_unregister_driver(&meson_uart_driver);
780}
781
782module_init(meson_uart_init);
783module_exit(meson_uart_exit);
784
785MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
786MODULE_DESCRIPTION("Amlogic Meson serial port driver");
787MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Based on meson_uart.c, by AMLOGIC, INC.
4 *
5 * Copyright (C) 2014 Carlo Caione <carlo@caione.org>
6 */
7
8#include <linux/clk.h>
9#include <linux/console.h>
10#include <linux/delay.h>
11#include <linux/init.h>
12#include <linux/io.h>
13#include <linux/iopoll.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/of.h>
17#include <linux/platform_device.h>
18#include <linux/serial.h>
19#include <linux/serial_core.h>
20#include <linux/tty.h>
21#include <linux/tty_flip.h>
22
23/* Register offsets */
24#define AML_UART_WFIFO 0x00
25#define AML_UART_RFIFO 0x04
26#define AML_UART_CONTROL 0x08
27#define AML_UART_STATUS 0x0c
28#define AML_UART_MISC 0x10
29#define AML_UART_REG5 0x14
30
31/* AML_UART_CONTROL bits */
32#define AML_UART_TX_EN BIT(12)
33#define AML_UART_RX_EN BIT(13)
34#define AML_UART_TWO_WIRE_EN BIT(15)
35#define AML_UART_STOP_BIT_LEN_MASK (0x03 << 16)
36#define AML_UART_STOP_BIT_1SB (0x00 << 16)
37#define AML_UART_STOP_BIT_2SB (0x01 << 16)
38#define AML_UART_PARITY_TYPE BIT(18)
39#define AML_UART_PARITY_EN BIT(19)
40#define AML_UART_TX_RST BIT(22)
41#define AML_UART_RX_RST BIT(23)
42#define AML_UART_CLEAR_ERR BIT(24)
43#define AML_UART_RX_INT_EN BIT(27)
44#define AML_UART_TX_INT_EN BIT(28)
45#define AML_UART_DATA_LEN_MASK (0x03 << 20)
46#define AML_UART_DATA_LEN_8BIT (0x00 << 20)
47#define AML_UART_DATA_LEN_7BIT (0x01 << 20)
48#define AML_UART_DATA_LEN_6BIT (0x02 << 20)
49#define AML_UART_DATA_LEN_5BIT (0x03 << 20)
50
51/* AML_UART_STATUS bits */
52#define AML_UART_PARITY_ERR BIT(16)
53#define AML_UART_FRAME_ERR BIT(17)
54#define AML_UART_TX_FIFO_WERR BIT(18)
55#define AML_UART_RX_EMPTY BIT(20)
56#define AML_UART_TX_FULL BIT(21)
57#define AML_UART_TX_EMPTY BIT(22)
58#define AML_UART_XMIT_BUSY BIT(25)
59#define AML_UART_ERR (AML_UART_PARITY_ERR | \
60 AML_UART_FRAME_ERR | \
61 AML_UART_TX_FIFO_WERR)
62
63/* AML_UART_MISC bits */
64#define AML_UART_XMIT_IRQ(c) (((c) & 0xff) << 8)
65#define AML_UART_RECV_IRQ(c) ((c) & 0xff)
66
67/* AML_UART_REG5 bits */
68#define AML_UART_BAUD_MASK 0x7fffff
69#define AML_UART_BAUD_USE BIT(23)
70#define AML_UART_BAUD_XTAL BIT(24)
71#define AML_UART_BAUD_XTAL_DIV2 BIT(27)
72
73#define AML_UART_PORT_NUM 12
74#define AML_UART_PORT_OFFSET 6
75#define AML_UART_DEV_NAME "ttyAML"
76
77#define AML_UART_POLL_USEC 5
78#define AML_UART_TIMEOUT_USEC 10000
79
80static struct uart_driver meson_uart_driver;
81
82static struct uart_port *meson_ports[AML_UART_PORT_NUM];
83
84struct meson_uart_data {
85 bool has_xtal_div2;
86};
87
88static void meson_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
89{
90}
91
92static unsigned int meson_uart_get_mctrl(struct uart_port *port)
93{
94 return TIOCM_CTS;
95}
96
97static unsigned int meson_uart_tx_empty(struct uart_port *port)
98{
99 u32 val;
100
101 val = readl(port->membase + AML_UART_STATUS);
102 val &= (AML_UART_TX_EMPTY | AML_UART_XMIT_BUSY);
103 return (val == AML_UART_TX_EMPTY) ? TIOCSER_TEMT : 0;
104}
105
106static void meson_uart_stop_tx(struct uart_port *port)
107{
108 u32 val;
109
110 val = readl(port->membase + AML_UART_CONTROL);
111 val &= ~AML_UART_TX_INT_EN;
112 writel(val, port->membase + AML_UART_CONTROL);
113}
114
115static void meson_uart_stop_rx(struct uart_port *port)
116{
117 u32 val;
118
119 val = readl(port->membase + AML_UART_CONTROL);
120 val &= ~AML_UART_RX_EN;
121 writel(val, port->membase + AML_UART_CONTROL);
122}
123
124static void meson_uart_shutdown(struct uart_port *port)
125{
126 unsigned long flags;
127 u32 val;
128
129 free_irq(port->irq, port);
130
131 spin_lock_irqsave(&port->lock, flags);
132
133 val = readl(port->membase + AML_UART_CONTROL);
134 val &= ~AML_UART_RX_EN;
135 val &= ~(AML_UART_RX_INT_EN | AML_UART_TX_INT_EN);
136 writel(val, port->membase + AML_UART_CONTROL);
137
138 spin_unlock_irqrestore(&port->lock, flags);
139}
140
141static void meson_uart_start_tx(struct uart_port *port)
142{
143 struct circ_buf *xmit = &port->state->xmit;
144 unsigned int ch;
145 u32 val;
146
147 if (uart_tx_stopped(port)) {
148 meson_uart_stop_tx(port);
149 return;
150 }
151
152 while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) {
153 if (port->x_char) {
154 writel(port->x_char, port->membase + AML_UART_WFIFO);
155 port->icount.tx++;
156 port->x_char = 0;
157 continue;
158 }
159
160 if (uart_circ_empty(xmit))
161 break;
162
163 ch = xmit->buf[xmit->tail];
164 writel(ch, port->membase + AML_UART_WFIFO);
165 uart_xmit_advance(port, 1);
166 }
167
168 if (!uart_circ_empty(xmit)) {
169 val = readl(port->membase + AML_UART_CONTROL);
170 val |= AML_UART_TX_INT_EN;
171 writel(val, port->membase + AML_UART_CONTROL);
172 }
173
174 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
175 uart_write_wakeup(port);
176}
177
178static void meson_receive_chars(struct uart_port *port)
179{
180 struct tty_port *tport = &port->state->port;
181 char flag;
182 u32 ostatus, status, ch, mode;
183
184 do {
185 flag = TTY_NORMAL;
186 port->icount.rx++;
187 ostatus = status = readl(port->membase + AML_UART_STATUS);
188
189 if (status & AML_UART_ERR) {
190 if (status & AML_UART_TX_FIFO_WERR)
191 port->icount.overrun++;
192 else if (status & AML_UART_FRAME_ERR)
193 port->icount.frame++;
194 else if (status & AML_UART_PARITY_ERR)
195 port->icount.frame++;
196
197 mode = readl(port->membase + AML_UART_CONTROL);
198 mode |= AML_UART_CLEAR_ERR;
199 writel(mode, port->membase + AML_UART_CONTROL);
200
201 /* It doesn't clear to 0 automatically */
202 mode &= ~AML_UART_CLEAR_ERR;
203 writel(mode, port->membase + AML_UART_CONTROL);
204
205 status &= port->read_status_mask;
206 if (status & AML_UART_FRAME_ERR)
207 flag = TTY_FRAME;
208 else if (status & AML_UART_PARITY_ERR)
209 flag = TTY_PARITY;
210 }
211
212 ch = readl(port->membase + AML_UART_RFIFO);
213 ch &= 0xff;
214
215 if ((ostatus & AML_UART_FRAME_ERR) && (ch == 0)) {
216 port->icount.brk++;
217 flag = TTY_BREAK;
218 if (uart_handle_break(port))
219 continue;
220 }
221
222 if (uart_handle_sysrq_char(port, ch))
223 continue;
224
225 if ((status & port->ignore_status_mask) == 0)
226 tty_insert_flip_char(tport, ch, flag);
227
228 if (status & AML_UART_TX_FIFO_WERR)
229 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
230
231 } while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY));
232
233 tty_flip_buffer_push(tport);
234}
235
236static irqreturn_t meson_uart_interrupt(int irq, void *dev_id)
237{
238 struct uart_port *port = (struct uart_port *)dev_id;
239
240 spin_lock(&port->lock);
241
242 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY))
243 meson_receive_chars(port);
244
245 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) {
246 if (readl(port->membase + AML_UART_CONTROL) & AML_UART_TX_INT_EN)
247 meson_uart_start_tx(port);
248 }
249
250 spin_unlock(&port->lock);
251
252 return IRQ_HANDLED;
253}
254
255static const char *meson_uart_type(struct uart_port *port)
256{
257 return (port->type == PORT_MESON) ? "meson_uart" : NULL;
258}
259
260/*
261 * This function is called only from probe() using a temporary io mapping
262 * in order to perform a reset before setting up the device. Since the
263 * temporarily mapped region was successfully requested, there can be no
264 * console on this port at this time. Hence it is not necessary for this
265 * function to acquire the port->lock. (Since there is no console on this
266 * port at this time, the port->lock is not initialized yet.)
267 */
268static void meson_uart_reset(struct uart_port *port)
269{
270 u32 val;
271
272 val = readl(port->membase + AML_UART_CONTROL);
273 val |= (AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLEAR_ERR);
274 writel(val, port->membase + AML_UART_CONTROL);
275
276 val &= ~(AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLEAR_ERR);
277 writel(val, port->membase + AML_UART_CONTROL);
278}
279
280static int meson_uart_startup(struct uart_port *port)
281{
282 unsigned long flags;
283 u32 val;
284 int ret = 0;
285
286 spin_lock_irqsave(&port->lock, flags);
287
288 val = readl(port->membase + AML_UART_CONTROL);
289 val |= AML_UART_CLEAR_ERR;
290 writel(val, port->membase + AML_UART_CONTROL);
291 val &= ~AML_UART_CLEAR_ERR;
292 writel(val, port->membase + AML_UART_CONTROL);
293
294 val |= (AML_UART_RX_EN | AML_UART_TX_EN);
295 writel(val, port->membase + AML_UART_CONTROL);
296
297 val |= (AML_UART_RX_INT_EN | AML_UART_TX_INT_EN);
298 writel(val, port->membase + AML_UART_CONTROL);
299
300 val = (AML_UART_RECV_IRQ(1) | AML_UART_XMIT_IRQ(port->fifosize / 2));
301 writel(val, port->membase + AML_UART_MISC);
302
303 spin_unlock_irqrestore(&port->lock, flags);
304
305 ret = request_irq(port->irq, meson_uart_interrupt, 0,
306 port->name, port);
307
308 return ret;
309}
310
311static void meson_uart_change_speed(struct uart_port *port, unsigned long baud)
312{
313 const struct meson_uart_data *private_data = port->private_data;
314 u32 val = 0;
315
316 while (!meson_uart_tx_empty(port))
317 cpu_relax();
318
319 if (port->uartclk == 24000000) {
320 unsigned int xtal_div = 3;
321
322 if (private_data && private_data->has_xtal_div2) {
323 xtal_div = 2;
324 val |= AML_UART_BAUD_XTAL_DIV2;
325 }
326 val |= DIV_ROUND_CLOSEST(port->uartclk / xtal_div, baud) - 1;
327 val |= AML_UART_BAUD_XTAL;
328 } else {
329 val = DIV_ROUND_CLOSEST(port->uartclk / 4, baud) - 1;
330 }
331 val |= AML_UART_BAUD_USE;
332 writel(val, port->membase + AML_UART_REG5);
333}
334
335static void meson_uart_set_termios(struct uart_port *port,
336 struct ktermios *termios,
337 const struct ktermios *old)
338{
339 unsigned int cflags, iflags, baud;
340 unsigned long flags;
341 u32 val;
342
343 spin_lock_irqsave(&port->lock, flags);
344
345 cflags = termios->c_cflag;
346 iflags = termios->c_iflag;
347
348 val = readl(port->membase + AML_UART_CONTROL);
349
350 val &= ~AML_UART_DATA_LEN_MASK;
351 switch (cflags & CSIZE) {
352 case CS8:
353 val |= AML_UART_DATA_LEN_8BIT;
354 break;
355 case CS7:
356 val |= AML_UART_DATA_LEN_7BIT;
357 break;
358 case CS6:
359 val |= AML_UART_DATA_LEN_6BIT;
360 break;
361 case CS5:
362 val |= AML_UART_DATA_LEN_5BIT;
363 break;
364 }
365
366 if (cflags & PARENB)
367 val |= AML_UART_PARITY_EN;
368 else
369 val &= ~AML_UART_PARITY_EN;
370
371 if (cflags & PARODD)
372 val |= AML_UART_PARITY_TYPE;
373 else
374 val &= ~AML_UART_PARITY_TYPE;
375
376 val &= ~AML_UART_STOP_BIT_LEN_MASK;
377 if (cflags & CSTOPB)
378 val |= AML_UART_STOP_BIT_2SB;
379 else
380 val |= AML_UART_STOP_BIT_1SB;
381
382 if (cflags & CRTSCTS)
383 val &= ~AML_UART_TWO_WIRE_EN;
384 else
385 val |= AML_UART_TWO_WIRE_EN;
386
387 writel(val, port->membase + AML_UART_CONTROL);
388
389 baud = uart_get_baud_rate(port, termios, old, 50, 4000000);
390 meson_uart_change_speed(port, baud);
391
392 port->read_status_mask = AML_UART_TX_FIFO_WERR;
393 if (iflags & INPCK)
394 port->read_status_mask |= AML_UART_PARITY_ERR |
395 AML_UART_FRAME_ERR;
396
397 port->ignore_status_mask = 0;
398 if (iflags & IGNPAR)
399 port->ignore_status_mask |= AML_UART_PARITY_ERR |
400 AML_UART_FRAME_ERR;
401
402 uart_update_timeout(port, termios->c_cflag, baud);
403 spin_unlock_irqrestore(&port->lock, flags);
404}
405
406static int meson_uart_verify_port(struct uart_port *port,
407 struct serial_struct *ser)
408{
409 int ret = 0;
410
411 if (port->type != PORT_MESON)
412 ret = -EINVAL;
413 if (port->irq != ser->irq)
414 ret = -EINVAL;
415 if (ser->baud_base < 9600)
416 ret = -EINVAL;
417 return ret;
418}
419
420static void meson_uart_release_port(struct uart_port *port)
421{
422 devm_iounmap(port->dev, port->membase);
423 port->membase = NULL;
424 devm_release_mem_region(port->dev, port->mapbase, port->mapsize);
425}
426
427static int meson_uart_request_port(struct uart_port *port)
428{
429 if (!devm_request_mem_region(port->dev, port->mapbase, port->mapsize,
430 dev_name(port->dev))) {
431 dev_err(port->dev, "Memory region busy\n");
432 return -EBUSY;
433 }
434
435 port->membase = devm_ioremap(port->dev, port->mapbase,
436 port->mapsize);
437 if (!port->membase)
438 return -ENOMEM;
439
440 return 0;
441}
442
443static void meson_uart_config_port(struct uart_port *port, int flags)
444{
445 if (flags & UART_CONFIG_TYPE) {
446 port->type = PORT_MESON;
447 meson_uart_request_port(port);
448 }
449}
450
451#ifdef CONFIG_CONSOLE_POLL
452/*
453 * Console polling routines for writing and reading from the uart while
454 * in an interrupt or debug context (i.e. kgdb).
455 */
456
457static int meson_uart_poll_get_char(struct uart_port *port)
458{
459 u32 c;
460 unsigned long flags;
461
462 spin_lock_irqsave(&port->lock, flags);
463
464 if (readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY)
465 c = NO_POLL_CHAR;
466 else
467 c = readl(port->membase + AML_UART_RFIFO);
468
469 spin_unlock_irqrestore(&port->lock, flags);
470
471 return c;
472}
473
474static void meson_uart_poll_put_char(struct uart_port *port, unsigned char c)
475{
476 unsigned long flags;
477 u32 reg;
478 int ret;
479
480 spin_lock_irqsave(&port->lock, flags);
481
482 /* Wait until FIFO is empty or timeout */
483 ret = readl_poll_timeout_atomic(port->membase + AML_UART_STATUS, reg,
484 reg & AML_UART_TX_EMPTY,
485 AML_UART_POLL_USEC,
486 AML_UART_TIMEOUT_USEC);
487 if (ret == -ETIMEDOUT) {
488 dev_err(port->dev, "Timeout waiting for UART TX EMPTY\n");
489 goto out;
490 }
491
492 /* Write the character */
493 writel(c, port->membase + AML_UART_WFIFO);
494
495 /* Wait until FIFO is empty or timeout */
496 ret = readl_poll_timeout_atomic(port->membase + AML_UART_STATUS, reg,
497 reg & AML_UART_TX_EMPTY,
498 AML_UART_POLL_USEC,
499 AML_UART_TIMEOUT_USEC);
500 if (ret == -ETIMEDOUT)
501 dev_err(port->dev, "Timeout waiting for UART TX EMPTY\n");
502
503out:
504 spin_unlock_irqrestore(&port->lock, flags);
505}
506
507#endif /* CONFIG_CONSOLE_POLL */
508
509static const struct uart_ops meson_uart_ops = {
510 .set_mctrl = meson_uart_set_mctrl,
511 .get_mctrl = meson_uart_get_mctrl,
512 .tx_empty = meson_uart_tx_empty,
513 .start_tx = meson_uart_start_tx,
514 .stop_tx = meson_uart_stop_tx,
515 .stop_rx = meson_uart_stop_rx,
516 .startup = meson_uart_startup,
517 .shutdown = meson_uart_shutdown,
518 .set_termios = meson_uart_set_termios,
519 .type = meson_uart_type,
520 .config_port = meson_uart_config_port,
521 .request_port = meson_uart_request_port,
522 .release_port = meson_uart_release_port,
523 .verify_port = meson_uart_verify_port,
524#ifdef CONFIG_CONSOLE_POLL
525 .poll_get_char = meson_uart_poll_get_char,
526 .poll_put_char = meson_uart_poll_put_char,
527#endif
528};
529
530#ifdef CONFIG_SERIAL_MESON_CONSOLE
531static void meson_uart_enable_tx_engine(struct uart_port *port)
532{
533 u32 val;
534
535 val = readl(port->membase + AML_UART_CONTROL);
536 val |= AML_UART_TX_EN;
537 writel(val, port->membase + AML_UART_CONTROL);
538}
539
540static void meson_console_putchar(struct uart_port *port, unsigned char ch)
541{
542 if (!port->membase)
543 return;
544
545 while (readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)
546 cpu_relax();
547 writel(ch, port->membase + AML_UART_WFIFO);
548}
549
550static void meson_serial_port_write(struct uart_port *port, const char *s,
551 u_int count)
552{
553 unsigned long flags;
554 int locked;
555 u32 val, tmp;
556
557 local_irq_save(flags);
558 if (port->sysrq) {
559 locked = 0;
560 } else if (oops_in_progress) {
561 locked = spin_trylock(&port->lock);
562 } else {
563 spin_lock(&port->lock);
564 locked = 1;
565 }
566
567 val = readl(port->membase + AML_UART_CONTROL);
568 tmp = val & ~(AML_UART_TX_INT_EN | AML_UART_RX_INT_EN);
569 writel(tmp, port->membase + AML_UART_CONTROL);
570
571 uart_console_write(port, s, count, meson_console_putchar);
572 writel(val, port->membase + AML_UART_CONTROL);
573
574 if (locked)
575 spin_unlock(&port->lock);
576 local_irq_restore(flags);
577}
578
579static void meson_serial_console_write(struct console *co, const char *s,
580 u_int count)
581{
582 struct uart_port *port;
583
584 port = meson_ports[co->index];
585 if (!port)
586 return;
587
588 meson_serial_port_write(port, s, count);
589}
590
591static int meson_serial_console_setup(struct console *co, char *options)
592{
593 struct uart_port *port;
594 int baud = 115200;
595 int bits = 8;
596 int parity = 'n';
597 int flow = 'n';
598
599 if (co->index < 0 || co->index >= AML_UART_PORT_NUM)
600 return -EINVAL;
601
602 port = meson_ports[co->index];
603 if (!port || !port->membase)
604 return -ENODEV;
605
606 meson_uart_enable_tx_engine(port);
607
608 if (options)
609 uart_parse_options(options, &baud, &parity, &bits, &flow);
610
611 return uart_set_options(port, co, baud, parity, bits, flow);
612}
613
614static struct console meson_serial_console = {
615 .name = AML_UART_DEV_NAME,
616 .write = meson_serial_console_write,
617 .device = uart_console_device,
618 .setup = meson_serial_console_setup,
619 .flags = CON_PRINTBUFFER,
620 .index = -1,
621 .data = &meson_uart_driver,
622};
623
624static int __init meson_serial_console_init(void)
625{
626 register_console(&meson_serial_console);
627 return 0;
628}
629
630static void meson_serial_early_console_write(struct console *co,
631 const char *s,
632 u_int count)
633{
634 struct earlycon_device *dev = co->data;
635
636 meson_serial_port_write(&dev->port, s, count);
637}
638
639static int __init
640meson_serial_early_console_setup(struct earlycon_device *device, const char *opt)
641{
642 if (!device->port.membase)
643 return -ENODEV;
644
645 meson_uart_enable_tx_engine(&device->port);
646 device->con->write = meson_serial_early_console_write;
647 return 0;
648}
649
650OF_EARLYCON_DECLARE(meson, "amlogic,meson-ao-uart",
651 meson_serial_early_console_setup);
652
653#define MESON_SERIAL_CONSOLE (&meson_serial_console)
654#else
655static int __init meson_serial_console_init(void) {
656 return 0;
657}
658#define MESON_SERIAL_CONSOLE NULL
659#endif
660
661static struct uart_driver meson_uart_driver = {
662 .owner = THIS_MODULE,
663 .driver_name = "meson_uart",
664 .dev_name = AML_UART_DEV_NAME,
665 .nr = AML_UART_PORT_NUM,
666 .cons = MESON_SERIAL_CONSOLE,
667};
668
669static int meson_uart_probe_clocks(struct platform_device *pdev,
670 struct uart_port *port)
671{
672 struct clk *clk_xtal = NULL;
673 struct clk *clk_pclk = NULL;
674 struct clk *clk_baud = NULL;
675
676 clk_pclk = devm_clk_get_enabled(&pdev->dev, "pclk");
677 if (IS_ERR(clk_pclk))
678 return PTR_ERR(clk_pclk);
679
680 clk_xtal = devm_clk_get_enabled(&pdev->dev, "xtal");
681 if (IS_ERR(clk_xtal))
682 return PTR_ERR(clk_xtal);
683
684 clk_baud = devm_clk_get_enabled(&pdev->dev, "baud");
685 if (IS_ERR(clk_baud))
686 return PTR_ERR(clk_baud);
687
688 port->uartclk = clk_get_rate(clk_baud);
689
690 return 0;
691}
692
693static int meson_uart_probe(struct platform_device *pdev)
694{
695 struct resource *res_mem;
696 struct uart_port *port;
697 u32 fifosize = 64; /* Default is 64, 128 for EE UART_0 */
698 int ret = 0;
699 int irq;
700
701 if (pdev->dev.of_node)
702 pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
703
704 if (pdev->id < 0) {
705 int id;
706
707 for (id = AML_UART_PORT_OFFSET; id < AML_UART_PORT_NUM; id++) {
708 if (!meson_ports[id]) {
709 pdev->id = id;
710 break;
711 }
712 }
713 }
714
715 if (pdev->id < 0 || pdev->id >= AML_UART_PORT_NUM)
716 return -EINVAL;
717
718 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
719 if (!res_mem)
720 return -ENODEV;
721
722 irq = platform_get_irq(pdev, 0);
723 if (irq < 0)
724 return irq;
725
726 of_property_read_u32(pdev->dev.of_node, "fifo-size", &fifosize);
727
728 if (meson_ports[pdev->id]) {
729 dev_err(&pdev->dev, "port %d already allocated\n", pdev->id);
730 return -EBUSY;
731 }
732
733 port = devm_kzalloc(&pdev->dev, sizeof(struct uart_port), GFP_KERNEL);
734 if (!port)
735 return -ENOMEM;
736
737 ret = meson_uart_probe_clocks(pdev, port);
738 if (ret)
739 return ret;
740
741 port->iotype = UPIO_MEM;
742 port->mapbase = res_mem->start;
743 port->mapsize = resource_size(res_mem);
744 port->irq = irq;
745 port->flags = UPF_BOOT_AUTOCONF | UPF_LOW_LATENCY;
746 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MESON_CONSOLE);
747 port->dev = &pdev->dev;
748 port->line = pdev->id;
749 port->type = PORT_MESON;
750 port->x_char = 0;
751 port->ops = &meson_uart_ops;
752 port->fifosize = fifosize;
753 port->private_data = (void *)device_get_match_data(&pdev->dev);
754
755 meson_ports[pdev->id] = port;
756 platform_set_drvdata(pdev, port);
757
758 /* reset port before registering (and possibly registering console) */
759 if (meson_uart_request_port(port) >= 0) {
760 meson_uart_reset(port);
761 meson_uart_release_port(port);
762 }
763
764 ret = uart_add_one_port(&meson_uart_driver, port);
765 if (ret)
766 meson_ports[pdev->id] = NULL;
767
768 return ret;
769}
770
771static int meson_uart_remove(struct platform_device *pdev)
772{
773 struct uart_port *port;
774
775 port = platform_get_drvdata(pdev);
776 uart_remove_one_port(&meson_uart_driver, port);
777 meson_ports[pdev->id] = NULL;
778
779 return 0;
780}
781
782static struct meson_uart_data s4_uart_data = {
783 .has_xtal_div2 = true,
784};
785
786static const struct of_device_id meson_uart_dt_match[] = {
787 { .compatible = "amlogic,meson6-uart" },
788 { .compatible = "amlogic,meson8-uart" },
789 { .compatible = "amlogic,meson8b-uart" },
790 { .compatible = "amlogic,meson-gx-uart" },
791 {
792 .compatible = "amlogic,meson-s4-uart",
793 .data = (void *)&s4_uart_data,
794 },
795 { /* sentinel */ },
796};
797MODULE_DEVICE_TABLE(of, meson_uart_dt_match);
798
799static struct platform_driver meson_uart_platform_driver = {
800 .probe = meson_uart_probe,
801 .remove = meson_uart_remove,
802 .driver = {
803 .name = "meson_uart",
804 .of_match_table = meson_uart_dt_match,
805 },
806};
807
808static int __init meson_uart_init(void)
809{
810 int ret;
811
812 ret = meson_serial_console_init();
813 if (ret)
814 return ret;
815
816 ret = uart_register_driver(&meson_uart_driver);
817 if (ret)
818 return ret;
819
820 ret = platform_driver_register(&meson_uart_platform_driver);
821 if (ret)
822 uart_unregister_driver(&meson_uart_driver);
823
824 return ret;
825}
826
827static void __exit meson_uart_exit(void)
828{
829 platform_driver_unregister(&meson_uart_platform_driver);
830 uart_unregister_driver(&meson_uart_driver);
831}
832
833module_init(meson_uart_init);
834module_exit(meson_uart_exit);
835
836MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
837MODULE_DESCRIPTION("Amlogic Meson serial port driver");
838MODULE_LICENSE("GPL v2");