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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Driver for CPM (SCC/SMC) serial ports
4 *
5 * Copyright (C) 2004 Freescale Semiconductor, Inc.
6 *
7 * 2006 (c) MontaVista Software, Inc.
8 * Vitaly Bordug <vbordug@ru.mvista.com>
9 */
10#ifndef CPM_UART_H
11#define CPM_UART_H
12
13#include <linux/platform_device.h>
14#include <linux/fs_uart_pd.h>
15
16#if defined(CONFIG_CPM2)
17#include "cpm_uart_cpm2.h"
18#elif defined(CONFIG_CPM1)
19#include "cpm_uart_cpm1.h"
20#endif
21
22#define SERIAL_CPM_MAJOR 204
23#define SERIAL_CPM_MINOR 46
24
25#define IS_SMC(pinfo) (pinfo->flags & FLAG_SMC)
26#define IS_DISCARDING(pinfo) (pinfo->flags & FLAG_DISCARDING)
27#define FLAG_DISCARDING 0x00000004 /* when set, don't discard */
28#define FLAG_SMC 0x00000002
29#define FLAG_CONSOLE 0x00000001
30
31#define UART_SMC1 fsid_smc1_uart
32#define UART_SMC2 fsid_smc2_uart
33#define UART_SCC1 fsid_scc1_uart
34#define UART_SCC2 fsid_scc2_uart
35#define UART_SCC3 fsid_scc3_uart
36#define UART_SCC4 fsid_scc4_uart
37
38#define UART_NR fs_uart_nr
39
40#define RX_NUM_FIFO 4
41#define RX_BUF_SIZE 32
42#define TX_NUM_FIFO 4
43#define TX_BUF_SIZE 32
44
45#define SCC_WAIT_CLOSING 100
46
47#define GPIO_CTS 0
48#define GPIO_RTS 1
49#define GPIO_DCD 2
50#define GPIO_DSR 3
51#define GPIO_DTR 4
52#define GPIO_RI 5
53
54#define NUM_GPIOS (GPIO_RI+1)
55
56struct uart_cpm_port {
57 struct uart_port port;
58 u16 rx_nrfifos;
59 u16 rx_fifosize;
60 u16 tx_nrfifos;
61 u16 tx_fifosize;
62 smc_t __iomem *smcp;
63 smc_uart_t __iomem *smcup;
64 scc_t __iomem *sccp;
65 scc_uart_t __iomem *sccup;
66 cbd_t __iomem *rx_bd_base;
67 cbd_t __iomem *rx_cur;
68 cbd_t __iomem *tx_bd_base;
69 cbd_t __iomem *tx_cur;
70 unsigned char *tx_buf;
71 unsigned char *rx_buf;
72 u32 flags;
73 struct clk *clk;
74 u8 brg;
75 uint dp_addr;
76 void *mem_addr;
77 dma_addr_t dma_addr;
78 u32 mem_size;
79 /* wait on close if needed */
80 int wait_closing;
81 /* value to combine with opcode to form cpm command */
82 u32 command;
83 int gpios[NUM_GPIOS];
84};
85
86extern int cpm_uart_nr;
87extern struct uart_cpm_port cpm_uart_ports[UART_NR];
88
89/* these are located in their respective files */
90void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd);
91void __iomem *cpm_uart_map_pram(struct uart_cpm_port *port,
92 struct device_node *np);
93void cpm_uart_unmap_pram(struct uart_cpm_port *port, void __iomem *pram);
94int cpm_uart_init_portdesc(void);
95int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con);
96void cpm_uart_freebuf(struct uart_cpm_port *pinfo);
97
98void smc1_lineif(struct uart_cpm_port *pinfo);
99void smc2_lineif(struct uart_cpm_port *pinfo);
100void scc1_lineif(struct uart_cpm_port *pinfo);
101void scc2_lineif(struct uart_cpm_port *pinfo);
102void scc3_lineif(struct uart_cpm_port *pinfo);
103void scc4_lineif(struct uart_cpm_port *pinfo);
104
105/*
106 virtual to phys transtalion
107*/
108static inline unsigned long cpu2cpm_addr(void *addr,
109 struct uart_cpm_port *pinfo)
110{
111 int offset;
112 u32 val = (u32)addr;
113 u32 mem = (u32)pinfo->mem_addr;
114 /* sane check */
115 if (likely(val >= mem && val < mem + pinfo->mem_size)) {
116 offset = val - mem;
117 return pinfo->dma_addr + offset;
118 }
119 /* something nasty happened */
120 BUG();
121 return 0;
122}
123
124static inline void *cpm2cpu_addr(unsigned long addr,
125 struct uart_cpm_port *pinfo)
126{
127 int offset;
128 u32 val = addr;
129 u32 dma = (u32)pinfo->dma_addr;
130 /* sane check */
131 if (likely(val >= dma && val < dma + pinfo->mem_size)) {
132 offset = val - dma;
133 return pinfo->mem_addr + offset;
134 }
135 /* something nasty happened */
136 BUG();
137 return NULL;
138}
139
140
141#endif /* CPM_UART_H */
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Driver for CPM (SCC/SMC) serial ports
4 *
5 * Copyright (C) 2004 Freescale Semiconductor, Inc.
6 *
7 * 2006 (c) MontaVista Software, Inc.
8 * Vitaly Bordug <vbordug@ru.mvista.com>
9 */
10#ifndef CPM_UART_H
11#define CPM_UART_H
12
13#include <linux/platform_device.h>
14#include <linux/fs_uart_pd.h>
15
16struct gpio_desc;
17
18#if defined(CONFIG_CPM2)
19#include "cpm_uart_cpm2.h"
20#elif defined(CONFIG_CPM1)
21#include "cpm_uart_cpm1.h"
22#elif defined(CONFIG_COMPILE_TEST)
23#include "cpm_uart_cpm2.h"
24#endif
25
26#define SERIAL_CPM_MAJOR 204
27#define SERIAL_CPM_MINOR 46
28
29#define IS_SMC(pinfo) (pinfo->flags & FLAG_SMC)
30#define IS_DISCARDING(pinfo) (pinfo->flags & FLAG_DISCARDING)
31#define FLAG_DISCARDING 0x00000004 /* when set, don't discard */
32#define FLAG_SMC 0x00000002
33#define FLAG_CONSOLE 0x00000001
34
35#define UART_SMC1 fsid_smc1_uart
36#define UART_SMC2 fsid_smc2_uart
37#define UART_SCC1 fsid_scc1_uart
38#define UART_SCC2 fsid_scc2_uart
39#define UART_SCC3 fsid_scc3_uart
40#define UART_SCC4 fsid_scc4_uart
41
42#define UART_NR fs_uart_nr
43
44#define RX_NUM_FIFO 4
45#define RX_BUF_SIZE 32
46#define TX_NUM_FIFO 4
47#define TX_BUF_SIZE 32
48
49#define SCC_WAIT_CLOSING 100
50
51#define GPIO_CTS 0
52#define GPIO_RTS 1
53#define GPIO_DCD 2
54#define GPIO_DSR 3
55#define GPIO_DTR 4
56#define GPIO_RI 5
57
58#define NUM_GPIOS (GPIO_RI+1)
59
60struct uart_cpm_port {
61 struct uart_port port;
62 u16 rx_nrfifos;
63 u16 rx_fifosize;
64 u16 tx_nrfifos;
65 u16 tx_fifosize;
66 smc_t __iomem *smcp;
67 smc_uart_t __iomem *smcup;
68 scc_t __iomem *sccp;
69 scc_uart_t __iomem *sccup;
70 cbd_t __iomem *rx_bd_base;
71 cbd_t __iomem *rx_cur;
72 cbd_t __iomem *tx_bd_base;
73 cbd_t __iomem *tx_cur;
74 unsigned char *tx_buf;
75 unsigned char *rx_buf;
76 u32 flags;
77 struct clk *clk;
78 u8 brg;
79 uint dp_addr;
80 void *mem_addr;
81 dma_addr_t dma_addr;
82 u32 mem_size;
83 /* wait on close if needed */
84 int wait_closing;
85 /* value to combine with opcode to form cpm command */
86 u32 command;
87 struct gpio_desc *gpios[NUM_GPIOS];
88};
89
90extern struct uart_cpm_port cpm_uart_ports[UART_NR];
91
92/* these are located in their respective files */
93void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd);
94void __iomem *cpm_uart_map_pram(struct uart_cpm_port *port,
95 struct device_node *np);
96void cpm_uart_unmap_pram(struct uart_cpm_port *port, void __iomem *pram);
97int cpm_uart_init_portdesc(void);
98int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con);
99void cpm_uart_freebuf(struct uart_cpm_port *pinfo);
100
101void smc1_lineif(struct uart_cpm_port *pinfo);
102void smc2_lineif(struct uart_cpm_port *pinfo);
103void scc1_lineif(struct uart_cpm_port *pinfo);
104void scc2_lineif(struct uart_cpm_port *pinfo);
105void scc3_lineif(struct uart_cpm_port *pinfo);
106void scc4_lineif(struct uart_cpm_port *pinfo);
107
108/*
109 virtual to phys transtalion
110*/
111static inline unsigned long cpu2cpm_addr(void *addr,
112 struct uart_cpm_port *pinfo)
113{
114 int offset;
115 u32 val = (u32)addr;
116 u32 mem = (u32)pinfo->mem_addr;
117 /* sane check */
118 if (likely(val >= mem && val < mem + pinfo->mem_size)) {
119 offset = val - mem;
120 return pinfo->dma_addr + offset;
121 }
122 /* something nasty happened */
123 BUG();
124 return 0;
125}
126
127static inline void *cpm2cpu_addr(unsigned long addr,
128 struct uart_cpm_port *pinfo)
129{
130 int offset;
131 u32 val = addr;
132 u32 dma = (u32)pinfo->dma_addr;
133 /* sane check */
134 if (likely(val >= dma && val < dma + pinfo->mem_size)) {
135 offset = val - dma;
136 return pinfo->mem_addr + offset;
137 }
138 /* something nasty happened */
139 BUG();
140 return NULL;
141}
142
143
144#endif /* CPM_UART_H */