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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * SPI controller driver for the Mikrotik RB4xx boards
4 *
5 * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2015 Bert Vermeulen <bert@biot.com>
7 *
8 * This file was based on the patches for Linux 2.6.27.39 published by
9 * MikroTik for their RouterBoard 4xx series devices.
10 */
11
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/clk.h>
16#include <linux/spi/spi.h>
17
18#include <asm/mach-ath79/ar71xx_regs.h>
19
20struct rb4xx_spi {
21 void __iomem *base;
22 struct clk *clk;
23};
24
25static inline u32 rb4xx_read(struct rb4xx_spi *rbspi, u32 reg)
26{
27 return __raw_readl(rbspi->base + reg);
28}
29
30static inline void rb4xx_write(struct rb4xx_spi *rbspi, u32 reg, u32 value)
31{
32 __raw_writel(value, rbspi->base + reg);
33}
34
35static inline void do_spi_clk(struct rb4xx_spi *rbspi, u32 spi_ioc, int value)
36{
37 u32 regval;
38
39 regval = spi_ioc;
40 if (value & BIT(0))
41 regval |= AR71XX_SPI_IOC_DO;
42
43 rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval);
44 rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval | AR71XX_SPI_IOC_CLK);
45}
46
47static void do_spi_byte(struct rb4xx_spi *rbspi, u32 spi_ioc, u8 byte)
48{
49 int i;
50
51 for (i = 7; i >= 0; i--)
52 do_spi_clk(rbspi, spi_ioc, byte >> i);
53}
54
55/* The CS2 pin is used to clock in a second bit per clock cycle. */
56static inline void do_spi_clk_two(struct rb4xx_spi *rbspi, u32 spi_ioc,
57 u8 value)
58{
59 u32 regval;
60
61 regval = spi_ioc;
62 if (value & BIT(1))
63 regval |= AR71XX_SPI_IOC_DO;
64 if (value & BIT(0))
65 regval |= AR71XX_SPI_IOC_CS2;
66
67 rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval);
68 rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval | AR71XX_SPI_IOC_CLK);
69}
70
71/* Two bits at a time, msb first */
72static void do_spi_byte_two(struct rb4xx_spi *rbspi, u32 spi_ioc, u8 byte)
73{
74 do_spi_clk_two(rbspi, spi_ioc, byte >> 6);
75 do_spi_clk_two(rbspi, spi_ioc, byte >> 4);
76 do_spi_clk_two(rbspi, spi_ioc, byte >> 2);
77 do_spi_clk_two(rbspi, spi_ioc, byte >> 0);
78}
79
80static void rb4xx_set_cs(struct spi_device *spi, bool enable)
81{
82 struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master);
83
84 /*
85 * Setting CS is done along with bitbanging the actual values,
86 * since it's all on the same hardware register. However the
87 * CPLD needs CS deselected after every command.
88 */
89 if (enable)
90 rb4xx_write(rbspi, AR71XX_SPI_REG_IOC,
91 AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1);
92}
93
94static int rb4xx_transfer_one(struct spi_master *master,
95 struct spi_device *spi, struct spi_transfer *t)
96{
97 struct rb4xx_spi *rbspi = spi_master_get_devdata(master);
98 int i;
99 u32 spi_ioc;
100 u8 *rx_buf;
101 const u8 *tx_buf;
102
103 /*
104 * Prime the SPI register with the SPI device selected. The m25p80 boot
105 * flash and CPLD share the CS0 pin. This works because the CPLD's
106 * command set was designed to almost not clash with that of the
107 * boot flash.
108 */
109 if (spi->chip_select == 2)
110 /* MMC */
111 spi_ioc = AR71XX_SPI_IOC_CS0;
112 else
113 /* Boot flash and CPLD */
114 spi_ioc = AR71XX_SPI_IOC_CS1;
115
116 tx_buf = t->tx_buf;
117 rx_buf = t->rx_buf;
118 for (i = 0; i < t->len; ++i) {
119 if (t->tx_nbits == SPI_NBITS_DUAL)
120 /* CPLD can use two-wire transfers */
121 do_spi_byte_two(rbspi, spi_ioc, tx_buf[i]);
122 else
123 do_spi_byte(rbspi, spi_ioc, tx_buf[i]);
124 if (!rx_buf)
125 continue;
126 rx_buf[i] = rb4xx_read(rbspi, AR71XX_SPI_REG_RDS);
127 }
128 spi_finalize_current_transfer(master);
129
130 return 0;
131}
132
133static int rb4xx_spi_probe(struct platform_device *pdev)
134{
135 struct spi_master *master;
136 struct clk *ahb_clk;
137 struct rb4xx_spi *rbspi;
138 int err;
139 void __iomem *spi_base;
140
141 spi_base = devm_platform_ioremap_resource(pdev, 0);
142 if (IS_ERR(spi_base))
143 return PTR_ERR(spi_base);
144
145 master = spi_alloc_master(&pdev->dev, sizeof(*rbspi));
146 if (!master)
147 return -ENOMEM;
148
149 ahb_clk = devm_clk_get(&pdev->dev, "ahb");
150 if (IS_ERR(ahb_clk))
151 return PTR_ERR(ahb_clk);
152
153 master->bus_num = 0;
154 master->num_chipselect = 3;
155 master->mode_bits = SPI_TX_DUAL;
156 master->bits_per_word_mask = SPI_BPW_MASK(8);
157 master->flags = SPI_MASTER_MUST_TX;
158 master->transfer_one = rb4xx_transfer_one;
159 master->set_cs = rb4xx_set_cs;
160
161 err = devm_spi_register_master(&pdev->dev, master);
162 if (err) {
163 dev_err(&pdev->dev, "failed to register SPI master\n");
164 return err;
165 }
166
167 err = clk_prepare_enable(ahb_clk);
168 if (err)
169 return err;
170
171 rbspi = spi_master_get_devdata(master);
172 rbspi->base = spi_base;
173 rbspi->clk = ahb_clk;
174 platform_set_drvdata(pdev, rbspi);
175
176 /* Enable SPI */
177 rb4xx_write(rbspi, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
178
179 return 0;
180}
181
182static int rb4xx_spi_remove(struct platform_device *pdev)
183{
184 struct rb4xx_spi *rbspi = platform_get_drvdata(pdev);
185
186 clk_disable_unprepare(rbspi->clk);
187
188 return 0;
189}
190
191static struct platform_driver rb4xx_spi_drv = {
192 .probe = rb4xx_spi_probe,
193 .remove = rb4xx_spi_remove,
194 .driver = {
195 .name = "rb4xx-spi",
196 },
197};
198
199module_platform_driver(rb4xx_spi_drv);
200
201MODULE_DESCRIPTION("Mikrotik RB4xx SPI controller driver");
202MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
203MODULE_AUTHOR("Bert Vermeulen <bert@biot.com>");
204MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * SPI controller driver for the Mikrotik RB4xx boards
4 *
5 * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2015 Bert Vermeulen <bert@biot.com>
7 *
8 * This file was based on the patches for Linux 2.6.27.39 published by
9 * MikroTik for their RouterBoard 4xx series devices.
10 */
11
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/clk.h>
16#include <linux/spi/spi.h>
17#include <linux/of.h>
18
19#include <asm/mach-ath79/ar71xx_regs.h>
20
21struct rb4xx_spi {
22 void __iomem *base;
23 struct clk *clk;
24};
25
26static inline u32 rb4xx_read(struct rb4xx_spi *rbspi, u32 reg)
27{
28 return __raw_readl(rbspi->base + reg);
29}
30
31static inline void rb4xx_write(struct rb4xx_spi *rbspi, u32 reg, u32 value)
32{
33 __raw_writel(value, rbspi->base + reg);
34}
35
36static inline void do_spi_clk(struct rb4xx_spi *rbspi, u32 spi_ioc, int value)
37{
38 u32 regval;
39
40 regval = spi_ioc;
41 if (value & BIT(0))
42 regval |= AR71XX_SPI_IOC_DO;
43
44 rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval);
45 rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval | AR71XX_SPI_IOC_CLK);
46}
47
48static void do_spi_byte(struct rb4xx_spi *rbspi, u32 spi_ioc, u8 byte)
49{
50 int i;
51
52 for (i = 7; i >= 0; i--)
53 do_spi_clk(rbspi, spi_ioc, byte >> i);
54}
55
56/* The CS2 pin is used to clock in a second bit per clock cycle. */
57static inline void do_spi_clk_two(struct rb4xx_spi *rbspi, u32 spi_ioc,
58 u8 value)
59{
60 u32 regval;
61
62 regval = spi_ioc;
63 if (value & BIT(1))
64 regval |= AR71XX_SPI_IOC_DO;
65 if (value & BIT(0))
66 regval |= AR71XX_SPI_IOC_CS2;
67
68 rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval);
69 rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval | AR71XX_SPI_IOC_CLK);
70}
71
72/* Two bits at a time, msb first */
73static void do_spi_byte_two(struct rb4xx_spi *rbspi, u32 spi_ioc, u8 byte)
74{
75 do_spi_clk_two(rbspi, spi_ioc, byte >> 6);
76 do_spi_clk_two(rbspi, spi_ioc, byte >> 4);
77 do_spi_clk_two(rbspi, spi_ioc, byte >> 2);
78 do_spi_clk_two(rbspi, spi_ioc, byte >> 0);
79}
80
81static void rb4xx_set_cs(struct spi_device *spi, bool enable)
82{
83 struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master);
84
85 /*
86 * Setting CS is done along with bitbanging the actual values,
87 * since it's all on the same hardware register. However the
88 * CPLD needs CS deselected after every command.
89 */
90 if (enable)
91 rb4xx_write(rbspi, AR71XX_SPI_REG_IOC,
92 AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1);
93}
94
95static int rb4xx_transfer_one(struct spi_master *master,
96 struct spi_device *spi, struct spi_transfer *t)
97{
98 struct rb4xx_spi *rbspi = spi_master_get_devdata(master);
99 int i;
100 u32 spi_ioc;
101 u8 *rx_buf;
102 const u8 *tx_buf;
103
104 /*
105 * Prime the SPI register with the SPI device selected. The m25p80 boot
106 * flash and CPLD share the CS0 pin. This works because the CPLD's
107 * command set was designed to almost not clash with that of the
108 * boot flash.
109 */
110 if (spi->chip_select == 2)
111 /* MMC */
112 spi_ioc = AR71XX_SPI_IOC_CS0;
113 else
114 /* Boot flash and CPLD */
115 spi_ioc = AR71XX_SPI_IOC_CS1;
116
117 tx_buf = t->tx_buf;
118 rx_buf = t->rx_buf;
119 for (i = 0; i < t->len; ++i) {
120 if (t->tx_nbits == SPI_NBITS_DUAL)
121 /* CPLD can use two-wire transfers */
122 do_spi_byte_two(rbspi, spi_ioc, tx_buf[i]);
123 else
124 do_spi_byte(rbspi, spi_ioc, tx_buf[i]);
125 if (!rx_buf)
126 continue;
127 rx_buf[i] = rb4xx_read(rbspi, AR71XX_SPI_REG_RDS);
128 }
129 spi_finalize_current_transfer(master);
130
131 return 0;
132}
133
134static int rb4xx_spi_probe(struct platform_device *pdev)
135{
136 struct spi_master *master;
137 struct clk *ahb_clk;
138 struct rb4xx_spi *rbspi;
139 int err;
140 void __iomem *spi_base;
141
142 spi_base = devm_platform_ioremap_resource(pdev, 0);
143 if (IS_ERR(spi_base))
144 return PTR_ERR(spi_base);
145
146 master = devm_spi_alloc_master(&pdev->dev, sizeof(*rbspi));
147 if (!master)
148 return -ENOMEM;
149
150 ahb_clk = devm_clk_get(&pdev->dev, "ahb");
151 if (IS_ERR(ahb_clk))
152 return PTR_ERR(ahb_clk);
153
154 master->dev.of_node = pdev->dev.of_node;
155 master->bus_num = 0;
156 master->num_chipselect = 3;
157 master->mode_bits = SPI_TX_DUAL;
158 master->bits_per_word_mask = SPI_BPW_MASK(8);
159 master->flags = SPI_MASTER_MUST_TX;
160 master->transfer_one = rb4xx_transfer_one;
161 master->set_cs = rb4xx_set_cs;
162
163 rbspi = spi_master_get_devdata(master);
164 rbspi->base = spi_base;
165 rbspi->clk = ahb_clk;
166 platform_set_drvdata(pdev, rbspi);
167
168 err = devm_spi_register_master(&pdev->dev, master);
169 if (err) {
170 dev_err(&pdev->dev, "failed to register SPI master\n");
171 return err;
172 }
173
174 err = clk_prepare_enable(ahb_clk);
175 if (err)
176 return err;
177
178 /* Enable SPI */
179 rb4xx_write(rbspi, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
180
181 return 0;
182}
183
184static int rb4xx_spi_remove(struct platform_device *pdev)
185{
186 struct rb4xx_spi *rbspi = platform_get_drvdata(pdev);
187
188 clk_disable_unprepare(rbspi->clk);
189
190 return 0;
191}
192
193static const struct of_device_id rb4xx_spi_dt_match[] = {
194 { .compatible = "mikrotik,rb4xx-spi" },
195 { },
196};
197MODULE_DEVICE_TABLE(of, rb4xx_spi_dt_match);
198
199static struct platform_driver rb4xx_spi_drv = {
200 .probe = rb4xx_spi_probe,
201 .remove = rb4xx_spi_remove,
202 .driver = {
203 .name = "rb4xx-spi",
204 .of_match_table = of_match_ptr(rb4xx_spi_dt_match),
205 },
206};
207
208module_platform_driver(rb4xx_spi_drv);
209
210MODULE_DESCRIPTION("Mikrotik RB4xx SPI controller driver");
211MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
212MODULE_AUTHOR("Bert Vermeulen <bert@biot.com>");
213MODULE_LICENSE("GPL v2");