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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * An RTC driver for the NVIDIA Tegra 200 series internal RTC.
4 *
5 * Copyright (c) 2010-2019, NVIDIA Corporation.
6 */
7
8#include <linux/clk.h>
9#include <linux/delay.h>
10#include <linux/init.h>
11#include <linux/io.h>
12#include <linux/irq.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/mod_devicetable.h>
16#include <linux/platform_device.h>
17#include <linux/pm.h>
18#include <linux/rtc.h>
19#include <linux/slab.h>
20
21/* Set to 1 = busy every eight 32 kHz clocks during copy of sec+msec to AHB. */
22#define TEGRA_RTC_REG_BUSY 0x004
23#define TEGRA_RTC_REG_SECONDS 0x008
24/* When msec is read, the seconds are buffered into shadow seconds. */
25#define TEGRA_RTC_REG_SHADOW_SECONDS 0x00c
26#define TEGRA_RTC_REG_MILLI_SECONDS 0x010
27#define TEGRA_RTC_REG_SECONDS_ALARM0 0x014
28#define TEGRA_RTC_REG_SECONDS_ALARM1 0x018
29#define TEGRA_RTC_REG_MILLI_SECONDS_ALARM0 0x01c
30#define TEGRA_RTC_REG_INTR_MASK 0x028
31/* write 1 bits to clear status bits */
32#define TEGRA_RTC_REG_INTR_STATUS 0x02c
33
34/* bits in INTR_MASK */
35#define TEGRA_RTC_INTR_MASK_MSEC_CDN_ALARM (1<<4)
36#define TEGRA_RTC_INTR_MASK_SEC_CDN_ALARM (1<<3)
37#define TEGRA_RTC_INTR_MASK_MSEC_ALARM (1<<2)
38#define TEGRA_RTC_INTR_MASK_SEC_ALARM1 (1<<1)
39#define TEGRA_RTC_INTR_MASK_SEC_ALARM0 (1<<0)
40
41/* bits in INTR_STATUS */
42#define TEGRA_RTC_INTR_STATUS_MSEC_CDN_ALARM (1<<4)
43#define TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM (1<<3)
44#define TEGRA_RTC_INTR_STATUS_MSEC_ALARM (1<<2)
45#define TEGRA_RTC_INTR_STATUS_SEC_ALARM1 (1<<1)
46#define TEGRA_RTC_INTR_STATUS_SEC_ALARM0 (1<<0)
47
48struct tegra_rtc_info {
49 struct platform_device *pdev;
50 struct rtc_device *rtc;
51 void __iomem *base; /* NULL if not initialized */
52 struct clk *clk;
53 int irq; /* alarm and periodic IRQ */
54 spinlock_t lock;
55};
56
57/*
58 * RTC hardware is busy when it is updating its values over AHB once every
59 * eight 32 kHz clocks (~250 us). Outside of these updates the CPU is free to
60 * write. CPU is always free to read.
61 */
62static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info)
63{
64 return readl(info->base + TEGRA_RTC_REG_BUSY) & 1;
65}
66
67/*
68 * Wait for hardware to be ready for writing. This function tries to maximize
69 * the amount of time before the next update. It does this by waiting for the
70 * RTC to become busy with its periodic update, then returning once the RTC
71 * first becomes not busy.
72 *
73 * This periodic update (where the seconds and milliseconds are copied to the
74 * AHB side) occurs every eight 32 kHz clocks (~250 us). The behavior of this
75 * function allows us to make some assumptions without introducing a race,
76 * because 250 us is plenty of time to read/write a value.
77 */
78static int tegra_rtc_wait_while_busy(struct device *dev)
79{
80 struct tegra_rtc_info *info = dev_get_drvdata(dev);
81 int retries = 500; /* ~490 us is the worst case, ~250 us is best */
82
83 /*
84 * First wait for the RTC to become busy. This is when it posts its
85 * updated seconds+msec registers to AHB side.
86 */
87 while (tegra_rtc_check_busy(info)) {
88 if (!retries--)
89 goto retry_failed;
90
91 udelay(1);
92 }
93
94 /* now we have about 250 us to manipulate registers */
95 return 0;
96
97retry_failed:
98 dev_err(dev, "write failed: retry count exceeded\n");
99 return -ETIMEDOUT;
100}
101
102static int tegra_rtc_read_time(struct device *dev, struct rtc_time *tm)
103{
104 struct tegra_rtc_info *info = dev_get_drvdata(dev);
105 unsigned long flags;
106 u32 sec, msec;
107
108 /*
109 * RTC hardware copies seconds to shadow seconds when a read of
110 * milliseconds occurs. use a lock to keep other threads out.
111 */
112 spin_lock_irqsave(&info->lock, flags);
113
114 msec = readl(info->base + TEGRA_RTC_REG_MILLI_SECONDS);
115 sec = readl(info->base + TEGRA_RTC_REG_SHADOW_SECONDS);
116
117 spin_unlock_irqrestore(&info->lock, flags);
118
119 rtc_time64_to_tm(sec, tm);
120
121 dev_vdbg(dev, "time read as %u, %ptR\n", sec, tm);
122
123 return 0;
124}
125
126static int tegra_rtc_set_time(struct device *dev, struct rtc_time *tm)
127{
128 struct tegra_rtc_info *info = dev_get_drvdata(dev);
129 u32 sec;
130 int ret;
131
132 /* convert tm to seconds */
133 sec = rtc_tm_to_time64(tm);
134
135 dev_vdbg(dev, "time set to %u, %ptR\n", sec, tm);
136
137 /* seconds only written if wait succeeded */
138 ret = tegra_rtc_wait_while_busy(dev);
139 if (!ret)
140 writel(sec, info->base + TEGRA_RTC_REG_SECONDS);
141
142 dev_vdbg(dev, "time read back as %d\n",
143 readl(info->base + TEGRA_RTC_REG_SECONDS));
144
145 return ret;
146}
147
148static int tegra_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
149{
150 struct tegra_rtc_info *info = dev_get_drvdata(dev);
151 u32 sec, value;
152
153 sec = readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
154
155 if (sec == 0) {
156 /* alarm is disabled */
157 alarm->enabled = 0;
158 } else {
159 /* alarm is enabled */
160 alarm->enabled = 1;
161 rtc_time64_to_tm(sec, &alarm->time);
162 }
163
164 value = readl(info->base + TEGRA_RTC_REG_INTR_STATUS);
165 alarm->pending = (value & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0;
166
167 return 0;
168}
169
170static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
171{
172 struct tegra_rtc_info *info = dev_get_drvdata(dev);
173 unsigned long flags;
174 u32 status;
175
176 tegra_rtc_wait_while_busy(dev);
177 spin_lock_irqsave(&info->lock, flags);
178
179 /* read the original value, and OR in the flag */
180 status = readl(info->base + TEGRA_RTC_REG_INTR_MASK);
181 if (enabled)
182 status |= TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* set it */
183 else
184 status &= ~TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* clear it */
185
186 writel(status, info->base + TEGRA_RTC_REG_INTR_MASK);
187
188 spin_unlock_irqrestore(&info->lock, flags);
189
190 return 0;
191}
192
193static int tegra_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
194{
195 struct tegra_rtc_info *info = dev_get_drvdata(dev);
196 u32 sec;
197
198 if (alarm->enabled)
199 sec = rtc_tm_to_time64(&alarm->time);
200 else
201 sec = 0;
202
203 tegra_rtc_wait_while_busy(dev);
204 writel(sec, info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
205 dev_vdbg(dev, "alarm read back as %d\n",
206 readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0));
207
208 /* if successfully written and alarm is enabled ... */
209 if (sec) {
210 tegra_rtc_alarm_irq_enable(dev, 1);
211 dev_vdbg(dev, "alarm set as %u, %ptR\n", sec, &alarm->time);
212 } else {
213 /* disable alarm if 0 or write error */
214 dev_vdbg(dev, "alarm disabled\n");
215 tegra_rtc_alarm_irq_enable(dev, 0);
216 }
217
218 return 0;
219}
220
221static int tegra_rtc_proc(struct device *dev, struct seq_file *seq)
222{
223 if (!dev || !dev->driver)
224 return 0;
225
226 seq_printf(seq, "name\t\t: %s\n", dev_name(dev));
227
228 return 0;
229}
230
231static irqreturn_t tegra_rtc_irq_handler(int irq, void *data)
232{
233 struct device *dev = data;
234 struct tegra_rtc_info *info = dev_get_drvdata(dev);
235 unsigned long events = 0, flags;
236 u32 status;
237
238 status = readl(info->base + TEGRA_RTC_REG_INTR_STATUS);
239 if (status) {
240 /* clear the interrupt masks and status on any IRQ */
241 tegra_rtc_wait_while_busy(dev);
242
243 spin_lock_irqsave(&info->lock, flags);
244 writel(0, info->base + TEGRA_RTC_REG_INTR_MASK);
245 writel(status, info->base + TEGRA_RTC_REG_INTR_STATUS);
246 spin_unlock_irqrestore(&info->lock, flags);
247 }
248
249 /* check if alarm */
250 if (status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0)
251 events |= RTC_IRQF | RTC_AF;
252
253 /* check if periodic */
254 if (status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM)
255 events |= RTC_IRQF | RTC_PF;
256
257 rtc_update_irq(info->rtc, 1, events);
258
259 return IRQ_HANDLED;
260}
261
262static const struct rtc_class_ops tegra_rtc_ops = {
263 .read_time = tegra_rtc_read_time,
264 .set_time = tegra_rtc_set_time,
265 .read_alarm = tegra_rtc_read_alarm,
266 .set_alarm = tegra_rtc_set_alarm,
267 .proc = tegra_rtc_proc,
268 .alarm_irq_enable = tegra_rtc_alarm_irq_enable,
269};
270
271static const struct of_device_id tegra_rtc_dt_match[] = {
272 { .compatible = "nvidia,tegra20-rtc", },
273 {}
274};
275MODULE_DEVICE_TABLE(of, tegra_rtc_dt_match);
276
277static int tegra_rtc_probe(struct platform_device *pdev)
278{
279 struct tegra_rtc_info *info;
280 struct resource *res;
281 int ret;
282
283 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
284 if (!info)
285 return -ENOMEM;
286
287 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
288 info->base = devm_ioremap_resource(&pdev->dev, res);
289 if (IS_ERR(info->base))
290 return PTR_ERR(info->base);
291
292 ret = platform_get_irq(pdev, 0);
293 if (ret <= 0)
294 return ret;
295
296 info->irq = ret;
297
298 info->rtc = devm_rtc_allocate_device(&pdev->dev);
299 if (IS_ERR(info->rtc))
300 return PTR_ERR(info->rtc);
301
302 info->rtc->ops = &tegra_rtc_ops;
303 info->rtc->range_max = U32_MAX;
304
305 info->clk = devm_clk_get(&pdev->dev, NULL);
306 if (IS_ERR(info->clk))
307 return PTR_ERR(info->clk);
308
309 ret = clk_prepare_enable(info->clk);
310 if (ret < 0)
311 return ret;
312
313 /* set context info */
314 info->pdev = pdev;
315 spin_lock_init(&info->lock);
316
317 platform_set_drvdata(pdev, info);
318
319 /* clear out the hardware */
320 writel(0, info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
321 writel(0xffffffff, info->base + TEGRA_RTC_REG_INTR_STATUS);
322 writel(0, info->base + TEGRA_RTC_REG_INTR_MASK);
323
324 device_init_wakeup(&pdev->dev, 1);
325
326 ret = devm_request_irq(&pdev->dev, info->irq, tegra_rtc_irq_handler,
327 IRQF_TRIGGER_HIGH, dev_name(&pdev->dev),
328 &pdev->dev);
329 if (ret) {
330 dev_err(&pdev->dev, "failed to request interrupt: %d\n", ret);
331 goto disable_clk;
332 }
333
334 ret = rtc_register_device(info->rtc);
335 if (ret)
336 goto disable_clk;
337
338 dev_notice(&pdev->dev, "Tegra internal Real Time Clock\n");
339
340 return 0;
341
342disable_clk:
343 clk_disable_unprepare(info->clk);
344 return ret;
345}
346
347static int tegra_rtc_remove(struct platform_device *pdev)
348{
349 struct tegra_rtc_info *info = platform_get_drvdata(pdev);
350
351 clk_disable_unprepare(info->clk);
352
353 return 0;
354}
355
356#ifdef CONFIG_PM_SLEEP
357static int tegra_rtc_suspend(struct device *dev)
358{
359 struct tegra_rtc_info *info = dev_get_drvdata(dev);
360
361 tegra_rtc_wait_while_busy(dev);
362
363 /* only use ALARM0 as a wake source */
364 writel(0xffffffff, info->base + TEGRA_RTC_REG_INTR_STATUS);
365 writel(TEGRA_RTC_INTR_STATUS_SEC_ALARM0,
366 info->base + TEGRA_RTC_REG_INTR_MASK);
367
368 dev_vdbg(dev, "alarm sec = %d\n",
369 readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0));
370
371 dev_vdbg(dev, "Suspend (device_may_wakeup=%d) IRQ:%d\n",
372 device_may_wakeup(dev), info->irq);
373
374 /* leave the alarms on as a wake source */
375 if (device_may_wakeup(dev))
376 enable_irq_wake(info->irq);
377
378 return 0;
379}
380
381static int tegra_rtc_resume(struct device *dev)
382{
383 struct tegra_rtc_info *info = dev_get_drvdata(dev);
384
385 dev_vdbg(dev, "Resume (device_may_wakeup=%d)\n",
386 device_may_wakeup(dev));
387
388 /* alarms were left on as a wake source, turn them off */
389 if (device_may_wakeup(dev))
390 disable_irq_wake(info->irq);
391
392 return 0;
393}
394#endif
395
396static SIMPLE_DEV_PM_OPS(tegra_rtc_pm_ops, tegra_rtc_suspend, tegra_rtc_resume);
397
398static void tegra_rtc_shutdown(struct platform_device *pdev)
399{
400 dev_vdbg(&pdev->dev, "disabling interrupts\n");
401 tegra_rtc_alarm_irq_enable(&pdev->dev, 0);
402}
403
404static struct platform_driver tegra_rtc_driver = {
405 .probe = tegra_rtc_probe,
406 .remove = tegra_rtc_remove,
407 .shutdown = tegra_rtc_shutdown,
408 .driver = {
409 .name = "tegra_rtc",
410 .of_match_table = tegra_rtc_dt_match,
411 .pm = &tegra_rtc_pm_ops,
412 },
413};
414module_platform_driver(tegra_rtc_driver);
415
416MODULE_AUTHOR("Jon Mayo <jmayo@nvidia.com>");
417MODULE_DESCRIPTION("driver for Tegra internal RTC");
418MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * An RTC driver for the NVIDIA Tegra 200 series internal RTC.
4 *
5 * Copyright (c) 2010-2019, NVIDIA Corporation.
6 */
7
8#include <linux/clk.h>
9#include <linux/delay.h>
10#include <linux/init.h>
11#include <linux/io.h>
12#include <linux/irq.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/mod_devicetable.h>
16#include <linux/platform_device.h>
17#include <linux/pm.h>
18#include <linux/rtc.h>
19#include <linux/slab.h>
20
21/* Set to 1 = busy every eight 32 kHz clocks during copy of sec+msec to AHB. */
22#define TEGRA_RTC_REG_BUSY 0x004
23#define TEGRA_RTC_REG_SECONDS 0x008
24/* When msec is read, the seconds are buffered into shadow seconds. */
25#define TEGRA_RTC_REG_SHADOW_SECONDS 0x00c
26#define TEGRA_RTC_REG_MILLI_SECONDS 0x010
27#define TEGRA_RTC_REG_SECONDS_ALARM0 0x014
28#define TEGRA_RTC_REG_SECONDS_ALARM1 0x018
29#define TEGRA_RTC_REG_MILLI_SECONDS_ALARM0 0x01c
30#define TEGRA_RTC_REG_INTR_MASK 0x028
31/* write 1 bits to clear status bits */
32#define TEGRA_RTC_REG_INTR_STATUS 0x02c
33
34/* bits in INTR_MASK */
35#define TEGRA_RTC_INTR_MASK_MSEC_CDN_ALARM (1<<4)
36#define TEGRA_RTC_INTR_MASK_SEC_CDN_ALARM (1<<3)
37#define TEGRA_RTC_INTR_MASK_MSEC_ALARM (1<<2)
38#define TEGRA_RTC_INTR_MASK_SEC_ALARM1 (1<<1)
39#define TEGRA_RTC_INTR_MASK_SEC_ALARM0 (1<<0)
40
41/* bits in INTR_STATUS */
42#define TEGRA_RTC_INTR_STATUS_MSEC_CDN_ALARM (1<<4)
43#define TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM (1<<3)
44#define TEGRA_RTC_INTR_STATUS_MSEC_ALARM (1<<2)
45#define TEGRA_RTC_INTR_STATUS_SEC_ALARM1 (1<<1)
46#define TEGRA_RTC_INTR_STATUS_SEC_ALARM0 (1<<0)
47
48struct tegra_rtc_info {
49 struct platform_device *pdev;
50 struct rtc_device *rtc;
51 void __iomem *base; /* NULL if not initialized */
52 struct clk *clk;
53 int irq; /* alarm and periodic IRQ */
54 spinlock_t lock;
55};
56
57/*
58 * RTC hardware is busy when it is updating its values over AHB once every
59 * eight 32 kHz clocks (~250 us). Outside of these updates the CPU is free to
60 * write. CPU is always free to read.
61 */
62static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info)
63{
64 return readl(info->base + TEGRA_RTC_REG_BUSY) & 1;
65}
66
67/*
68 * Wait for hardware to be ready for writing. This function tries to maximize
69 * the amount of time before the next update. It does this by waiting for the
70 * RTC to become busy with its periodic update, then returning once the RTC
71 * first becomes not busy.
72 *
73 * This periodic update (where the seconds and milliseconds are copied to the
74 * AHB side) occurs every eight 32 kHz clocks (~250 us). The behavior of this
75 * function allows us to make some assumptions without introducing a race,
76 * because 250 us is plenty of time to read/write a value.
77 */
78static int tegra_rtc_wait_while_busy(struct device *dev)
79{
80 struct tegra_rtc_info *info = dev_get_drvdata(dev);
81 int retries = 500; /* ~490 us is the worst case, ~250 us is best */
82
83 /*
84 * First wait for the RTC to become busy. This is when it posts its
85 * updated seconds+msec registers to AHB side.
86 */
87 while (tegra_rtc_check_busy(info)) {
88 if (!retries--)
89 goto retry_failed;
90
91 udelay(1);
92 }
93
94 /* now we have about 250 us to manipulate registers */
95 return 0;
96
97retry_failed:
98 dev_err(dev, "write failed: retry count exceeded\n");
99 return -ETIMEDOUT;
100}
101
102static int tegra_rtc_read_time(struct device *dev, struct rtc_time *tm)
103{
104 struct tegra_rtc_info *info = dev_get_drvdata(dev);
105 unsigned long flags;
106 u32 sec;
107
108 /*
109 * RTC hardware copies seconds to shadow seconds when a read of
110 * milliseconds occurs. use a lock to keep other threads out.
111 */
112 spin_lock_irqsave(&info->lock, flags);
113
114 readl(info->base + TEGRA_RTC_REG_MILLI_SECONDS);
115 sec = readl(info->base + TEGRA_RTC_REG_SHADOW_SECONDS);
116
117 spin_unlock_irqrestore(&info->lock, flags);
118
119 rtc_time64_to_tm(sec, tm);
120
121 dev_vdbg(dev, "time read as %u, %ptR\n", sec, tm);
122
123 return 0;
124}
125
126static int tegra_rtc_set_time(struct device *dev, struct rtc_time *tm)
127{
128 struct tegra_rtc_info *info = dev_get_drvdata(dev);
129 u32 sec;
130 int ret;
131
132 /* convert tm to seconds */
133 sec = rtc_tm_to_time64(tm);
134
135 dev_vdbg(dev, "time set to %u, %ptR\n", sec, tm);
136
137 /* seconds only written if wait succeeded */
138 ret = tegra_rtc_wait_while_busy(dev);
139 if (!ret)
140 writel(sec, info->base + TEGRA_RTC_REG_SECONDS);
141
142 dev_vdbg(dev, "time read back as %d\n",
143 readl(info->base + TEGRA_RTC_REG_SECONDS));
144
145 return ret;
146}
147
148static int tegra_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
149{
150 struct tegra_rtc_info *info = dev_get_drvdata(dev);
151 u32 sec, value;
152
153 sec = readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
154
155 if (sec == 0) {
156 /* alarm is disabled */
157 alarm->enabled = 0;
158 } else {
159 /* alarm is enabled */
160 alarm->enabled = 1;
161 rtc_time64_to_tm(sec, &alarm->time);
162 }
163
164 value = readl(info->base + TEGRA_RTC_REG_INTR_STATUS);
165 alarm->pending = (value & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0;
166
167 return 0;
168}
169
170static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
171{
172 struct tegra_rtc_info *info = dev_get_drvdata(dev);
173 unsigned long flags;
174 u32 status;
175
176 tegra_rtc_wait_while_busy(dev);
177 spin_lock_irqsave(&info->lock, flags);
178
179 /* read the original value, and OR in the flag */
180 status = readl(info->base + TEGRA_RTC_REG_INTR_MASK);
181 if (enabled)
182 status |= TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* set it */
183 else
184 status &= ~TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* clear it */
185
186 writel(status, info->base + TEGRA_RTC_REG_INTR_MASK);
187
188 spin_unlock_irqrestore(&info->lock, flags);
189
190 return 0;
191}
192
193static int tegra_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
194{
195 struct tegra_rtc_info *info = dev_get_drvdata(dev);
196 u32 sec;
197
198 if (alarm->enabled)
199 sec = rtc_tm_to_time64(&alarm->time);
200 else
201 sec = 0;
202
203 tegra_rtc_wait_while_busy(dev);
204 writel(sec, info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
205 dev_vdbg(dev, "alarm read back as %d\n",
206 readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0));
207
208 /* if successfully written and alarm is enabled ... */
209 if (sec) {
210 tegra_rtc_alarm_irq_enable(dev, 1);
211 dev_vdbg(dev, "alarm set as %u, %ptR\n", sec, &alarm->time);
212 } else {
213 /* disable alarm if 0 or write error */
214 dev_vdbg(dev, "alarm disabled\n");
215 tegra_rtc_alarm_irq_enable(dev, 0);
216 }
217
218 return 0;
219}
220
221static int tegra_rtc_proc(struct device *dev, struct seq_file *seq)
222{
223 if (!dev || !dev->driver)
224 return 0;
225
226 seq_printf(seq, "name\t\t: %s\n", dev_name(dev));
227
228 return 0;
229}
230
231static irqreturn_t tegra_rtc_irq_handler(int irq, void *data)
232{
233 struct device *dev = data;
234 struct tegra_rtc_info *info = dev_get_drvdata(dev);
235 unsigned long events = 0;
236 u32 status;
237
238 status = readl(info->base + TEGRA_RTC_REG_INTR_STATUS);
239 if (status) {
240 /* clear the interrupt masks and status on any IRQ */
241 tegra_rtc_wait_while_busy(dev);
242
243 spin_lock(&info->lock);
244 writel(0, info->base + TEGRA_RTC_REG_INTR_MASK);
245 writel(status, info->base + TEGRA_RTC_REG_INTR_STATUS);
246 spin_unlock(&info->lock);
247 }
248
249 /* check if alarm */
250 if (status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0)
251 events |= RTC_IRQF | RTC_AF;
252
253 /* check if periodic */
254 if (status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM)
255 events |= RTC_IRQF | RTC_PF;
256
257 rtc_update_irq(info->rtc, 1, events);
258
259 return IRQ_HANDLED;
260}
261
262static const struct rtc_class_ops tegra_rtc_ops = {
263 .read_time = tegra_rtc_read_time,
264 .set_time = tegra_rtc_set_time,
265 .read_alarm = tegra_rtc_read_alarm,
266 .set_alarm = tegra_rtc_set_alarm,
267 .proc = tegra_rtc_proc,
268 .alarm_irq_enable = tegra_rtc_alarm_irq_enable,
269};
270
271static const struct of_device_id tegra_rtc_dt_match[] = {
272 { .compatible = "nvidia,tegra20-rtc", },
273 {}
274};
275MODULE_DEVICE_TABLE(of, tegra_rtc_dt_match);
276
277static int tegra_rtc_probe(struct platform_device *pdev)
278{
279 struct tegra_rtc_info *info;
280 int ret;
281
282 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
283 if (!info)
284 return -ENOMEM;
285
286 info->base = devm_platform_ioremap_resource(pdev, 0);
287 if (IS_ERR(info->base))
288 return PTR_ERR(info->base);
289
290 ret = platform_get_irq(pdev, 0);
291 if (ret <= 0)
292 return ret;
293
294 info->irq = ret;
295
296 info->rtc = devm_rtc_allocate_device(&pdev->dev);
297 if (IS_ERR(info->rtc))
298 return PTR_ERR(info->rtc);
299
300 info->rtc->ops = &tegra_rtc_ops;
301 info->rtc->range_max = U32_MAX;
302
303 info->clk = devm_clk_get(&pdev->dev, NULL);
304 if (IS_ERR(info->clk))
305 return PTR_ERR(info->clk);
306
307 ret = clk_prepare_enable(info->clk);
308 if (ret < 0)
309 return ret;
310
311 /* set context info */
312 info->pdev = pdev;
313 spin_lock_init(&info->lock);
314
315 platform_set_drvdata(pdev, info);
316
317 /* clear out the hardware */
318 writel(0, info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
319 writel(0xffffffff, info->base + TEGRA_RTC_REG_INTR_STATUS);
320 writel(0, info->base + TEGRA_RTC_REG_INTR_MASK);
321
322 device_init_wakeup(&pdev->dev, 1);
323
324 ret = devm_request_irq(&pdev->dev, info->irq, tegra_rtc_irq_handler,
325 IRQF_TRIGGER_HIGH, dev_name(&pdev->dev),
326 &pdev->dev);
327 if (ret) {
328 dev_err(&pdev->dev, "failed to request interrupt: %d\n", ret);
329 goto disable_clk;
330 }
331
332 ret = devm_rtc_register_device(info->rtc);
333 if (ret)
334 goto disable_clk;
335
336 dev_notice(&pdev->dev, "Tegra internal Real Time Clock\n");
337
338 return 0;
339
340disable_clk:
341 clk_disable_unprepare(info->clk);
342 return ret;
343}
344
345static int tegra_rtc_remove(struct platform_device *pdev)
346{
347 struct tegra_rtc_info *info = platform_get_drvdata(pdev);
348
349 clk_disable_unprepare(info->clk);
350
351 return 0;
352}
353
354#ifdef CONFIG_PM_SLEEP
355static int tegra_rtc_suspend(struct device *dev)
356{
357 struct tegra_rtc_info *info = dev_get_drvdata(dev);
358
359 tegra_rtc_wait_while_busy(dev);
360
361 /* only use ALARM0 as a wake source */
362 writel(0xffffffff, info->base + TEGRA_RTC_REG_INTR_STATUS);
363 writel(TEGRA_RTC_INTR_STATUS_SEC_ALARM0,
364 info->base + TEGRA_RTC_REG_INTR_MASK);
365
366 dev_vdbg(dev, "alarm sec = %d\n",
367 readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0));
368
369 dev_vdbg(dev, "Suspend (device_may_wakeup=%d) IRQ:%d\n",
370 device_may_wakeup(dev), info->irq);
371
372 /* leave the alarms on as a wake source */
373 if (device_may_wakeup(dev))
374 enable_irq_wake(info->irq);
375
376 return 0;
377}
378
379static int tegra_rtc_resume(struct device *dev)
380{
381 struct tegra_rtc_info *info = dev_get_drvdata(dev);
382
383 dev_vdbg(dev, "Resume (device_may_wakeup=%d)\n",
384 device_may_wakeup(dev));
385
386 /* alarms were left on as a wake source, turn them off */
387 if (device_may_wakeup(dev))
388 disable_irq_wake(info->irq);
389
390 return 0;
391}
392#endif
393
394static SIMPLE_DEV_PM_OPS(tegra_rtc_pm_ops, tegra_rtc_suspend, tegra_rtc_resume);
395
396static void tegra_rtc_shutdown(struct platform_device *pdev)
397{
398 dev_vdbg(&pdev->dev, "disabling interrupts\n");
399 tegra_rtc_alarm_irq_enable(&pdev->dev, 0);
400}
401
402static struct platform_driver tegra_rtc_driver = {
403 .probe = tegra_rtc_probe,
404 .remove = tegra_rtc_remove,
405 .shutdown = tegra_rtc_shutdown,
406 .driver = {
407 .name = "tegra_rtc",
408 .of_match_table = tegra_rtc_dt_match,
409 .pm = &tegra_rtc_pm_ops,
410 },
411};
412module_platform_driver(tegra_rtc_driver);
413
414MODULE_AUTHOR("Jon Mayo <jmayo@nvidia.com>");
415MODULE_DESCRIPTION("driver for Tegra internal RTC");
416MODULE_LICENSE("GPL");