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1/*
2 * Copyright (C) 2015 Red Hat, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26#include <drm/drm_atomic_helper.h>
27#include <drm/drm_fourcc.h>
28#include <drm/drm_plane_helper.h>
29
30#include "virtgpu_drv.h"
31
32static const uint32_t virtio_gpu_formats[] = {
33 DRM_FORMAT_HOST_XRGB8888,
34};
35
36static const uint32_t virtio_gpu_cursor_formats[] = {
37 DRM_FORMAT_HOST_ARGB8888,
38};
39
40uint32_t virtio_gpu_translate_format(uint32_t drm_fourcc)
41{
42 uint32_t format;
43
44 switch (drm_fourcc) {
45 case DRM_FORMAT_XRGB8888:
46 format = VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM;
47 break;
48 case DRM_FORMAT_ARGB8888:
49 format = VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM;
50 break;
51 case DRM_FORMAT_BGRX8888:
52 format = VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM;
53 break;
54 case DRM_FORMAT_BGRA8888:
55 format = VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM;
56 break;
57 default:
58 /*
59 * This should not happen, we handle everything listed
60 * in virtio_gpu_formats[].
61 */
62 format = 0;
63 break;
64 }
65 WARN_ON(format == 0);
66 return format;
67}
68
69static void virtio_gpu_plane_destroy(struct drm_plane *plane)
70{
71 drm_plane_cleanup(plane);
72 kfree(plane);
73}
74
75static const struct drm_plane_funcs virtio_gpu_plane_funcs = {
76 .update_plane = drm_atomic_helper_update_plane,
77 .disable_plane = drm_atomic_helper_disable_plane,
78 .destroy = virtio_gpu_plane_destroy,
79 .reset = drm_atomic_helper_plane_reset,
80 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
81 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
82};
83
84static int virtio_gpu_plane_atomic_check(struct drm_plane *plane,
85 struct drm_plane_state *state)
86{
87 return 0;
88}
89
90static void virtio_gpu_primary_plane_update(struct drm_plane *plane,
91 struct drm_plane_state *old_state)
92{
93 struct drm_device *dev = plane->dev;
94 struct virtio_gpu_device *vgdev = dev->dev_private;
95 struct virtio_gpu_output *output = NULL;
96 struct virtio_gpu_framebuffer *vgfb;
97 struct virtio_gpu_object *bo;
98 uint32_t handle;
99
100 if (plane->state->crtc)
101 output = drm_crtc_to_virtio_gpu_output(plane->state->crtc);
102 if (old_state->crtc)
103 output = drm_crtc_to_virtio_gpu_output(old_state->crtc);
104 if (WARN_ON(!output))
105 return;
106
107 if (plane->state->fb && output->enabled) {
108 vgfb = to_virtio_gpu_framebuffer(plane->state->fb);
109 bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]);
110 handle = bo->hw_res_handle;
111 if (bo->dumb) {
112 virtio_gpu_cmd_transfer_to_host_2d
113 (vgdev, bo, 0,
114 cpu_to_le32(plane->state->src_w >> 16),
115 cpu_to_le32(plane->state->src_h >> 16),
116 cpu_to_le32(plane->state->src_x >> 16),
117 cpu_to_le32(plane->state->src_y >> 16), NULL);
118 }
119 } else {
120 handle = 0;
121 }
122
123 DRM_DEBUG("handle 0x%x, crtc %dx%d+%d+%d, src %dx%d+%d+%d\n", handle,
124 plane->state->crtc_w, plane->state->crtc_h,
125 plane->state->crtc_x, plane->state->crtc_y,
126 plane->state->src_w >> 16,
127 plane->state->src_h >> 16,
128 plane->state->src_x >> 16,
129 plane->state->src_y >> 16);
130 virtio_gpu_cmd_set_scanout(vgdev, output->index, handle,
131 plane->state->src_w >> 16,
132 plane->state->src_h >> 16,
133 plane->state->src_x >> 16,
134 plane->state->src_y >> 16);
135 if (handle)
136 virtio_gpu_cmd_resource_flush(vgdev, handle,
137 plane->state->src_x >> 16,
138 plane->state->src_y >> 16,
139 plane->state->src_w >> 16,
140 plane->state->src_h >> 16);
141}
142
143static int virtio_gpu_cursor_prepare_fb(struct drm_plane *plane,
144 struct drm_plane_state *new_state)
145{
146 struct drm_device *dev = plane->dev;
147 struct virtio_gpu_device *vgdev = dev->dev_private;
148 struct virtio_gpu_framebuffer *vgfb;
149 struct virtio_gpu_object *bo;
150
151 if (!new_state->fb)
152 return 0;
153
154 vgfb = to_virtio_gpu_framebuffer(new_state->fb);
155 bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]);
156 if (bo && bo->dumb && (plane->state->fb != new_state->fb)) {
157 vgfb->fence = virtio_gpu_fence_alloc(vgdev);
158 if (!vgfb->fence)
159 return -ENOMEM;
160 }
161
162 return 0;
163}
164
165static void virtio_gpu_cursor_cleanup_fb(struct drm_plane *plane,
166 struct drm_plane_state *old_state)
167{
168 struct virtio_gpu_framebuffer *vgfb;
169
170 if (!plane->state->fb)
171 return;
172
173 vgfb = to_virtio_gpu_framebuffer(plane->state->fb);
174 if (vgfb->fence) {
175 dma_fence_put(&vgfb->fence->f);
176 vgfb->fence = NULL;
177 }
178}
179
180static void virtio_gpu_cursor_plane_update(struct drm_plane *plane,
181 struct drm_plane_state *old_state)
182{
183 struct drm_device *dev = plane->dev;
184 struct virtio_gpu_device *vgdev = dev->dev_private;
185 struct virtio_gpu_output *output = NULL;
186 struct virtio_gpu_framebuffer *vgfb;
187 struct virtio_gpu_object *bo = NULL;
188 uint32_t handle;
189 int ret = 0;
190
191 if (plane->state->crtc)
192 output = drm_crtc_to_virtio_gpu_output(plane->state->crtc);
193 if (old_state->crtc)
194 output = drm_crtc_to_virtio_gpu_output(old_state->crtc);
195 if (WARN_ON(!output))
196 return;
197
198 if (plane->state->fb) {
199 vgfb = to_virtio_gpu_framebuffer(plane->state->fb);
200 bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]);
201 handle = bo->hw_res_handle;
202 } else {
203 handle = 0;
204 }
205
206 if (bo && bo->dumb && (plane->state->fb != old_state->fb)) {
207 /* new cursor -- update & wait */
208 virtio_gpu_cmd_transfer_to_host_2d
209 (vgdev, bo, 0,
210 cpu_to_le32(plane->state->crtc_w),
211 cpu_to_le32(plane->state->crtc_h),
212 0, 0, vgfb->fence);
213 ret = virtio_gpu_object_reserve(bo, false);
214 if (!ret) {
215 dma_resv_add_excl_fence(bo->tbo.base.resv,
216 &vgfb->fence->f);
217 dma_fence_put(&vgfb->fence->f);
218 vgfb->fence = NULL;
219 virtio_gpu_object_unreserve(bo);
220 virtio_gpu_object_wait(bo, false);
221 }
222 }
223
224 if (plane->state->fb != old_state->fb) {
225 DRM_DEBUG("update, handle %d, pos +%d+%d, hot %d,%d\n", handle,
226 plane->state->crtc_x,
227 plane->state->crtc_y,
228 plane->state->fb ? plane->state->fb->hot_x : 0,
229 plane->state->fb ? plane->state->fb->hot_y : 0);
230 output->cursor.hdr.type =
231 cpu_to_le32(VIRTIO_GPU_CMD_UPDATE_CURSOR);
232 output->cursor.resource_id = cpu_to_le32(handle);
233 if (plane->state->fb) {
234 output->cursor.hot_x =
235 cpu_to_le32(plane->state->fb->hot_x);
236 output->cursor.hot_y =
237 cpu_to_le32(plane->state->fb->hot_y);
238 } else {
239 output->cursor.hot_x = cpu_to_le32(0);
240 output->cursor.hot_y = cpu_to_le32(0);
241 }
242 } else {
243 DRM_DEBUG("move +%d+%d\n",
244 plane->state->crtc_x,
245 plane->state->crtc_y);
246 output->cursor.hdr.type =
247 cpu_to_le32(VIRTIO_GPU_CMD_MOVE_CURSOR);
248 }
249 output->cursor.pos.x = cpu_to_le32(plane->state->crtc_x);
250 output->cursor.pos.y = cpu_to_le32(plane->state->crtc_y);
251 virtio_gpu_cursor_ping(vgdev, output);
252}
253
254static const struct drm_plane_helper_funcs virtio_gpu_primary_helper_funcs = {
255 .atomic_check = virtio_gpu_plane_atomic_check,
256 .atomic_update = virtio_gpu_primary_plane_update,
257};
258
259static const struct drm_plane_helper_funcs virtio_gpu_cursor_helper_funcs = {
260 .prepare_fb = virtio_gpu_cursor_prepare_fb,
261 .cleanup_fb = virtio_gpu_cursor_cleanup_fb,
262 .atomic_check = virtio_gpu_plane_atomic_check,
263 .atomic_update = virtio_gpu_cursor_plane_update,
264};
265
266struct drm_plane *virtio_gpu_plane_init(struct virtio_gpu_device *vgdev,
267 enum drm_plane_type type,
268 int index)
269{
270 struct drm_device *dev = vgdev->ddev;
271 const struct drm_plane_helper_funcs *funcs;
272 struct drm_plane *plane;
273 const uint32_t *formats;
274 int ret, nformats;
275
276 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
277 if (!plane)
278 return ERR_PTR(-ENOMEM);
279
280 if (type == DRM_PLANE_TYPE_CURSOR) {
281 formats = virtio_gpu_cursor_formats;
282 nformats = ARRAY_SIZE(virtio_gpu_cursor_formats);
283 funcs = &virtio_gpu_cursor_helper_funcs;
284 } else {
285 formats = virtio_gpu_formats;
286 nformats = ARRAY_SIZE(virtio_gpu_formats);
287 funcs = &virtio_gpu_primary_helper_funcs;
288 }
289 ret = drm_universal_plane_init(dev, plane, 1 << index,
290 &virtio_gpu_plane_funcs,
291 formats, nformats,
292 NULL, type, NULL);
293 if (ret)
294 goto err_plane_init;
295
296 drm_plane_helper_add(plane, funcs);
297 return plane;
298
299err_plane_init:
300 kfree(plane);
301 return ERR_PTR(ret);
302}
1/*
2 * Copyright (C) 2015 Red Hat, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26#include <drm/drm_atomic_helper.h>
27#include <drm/drm_damage_helper.h>
28#include <drm/drm_fourcc.h>
29
30#include "virtgpu_drv.h"
31
32static const uint32_t virtio_gpu_formats[] = {
33 DRM_FORMAT_HOST_XRGB8888,
34};
35
36static const uint32_t virtio_gpu_cursor_formats[] = {
37 DRM_FORMAT_HOST_ARGB8888,
38};
39
40uint32_t virtio_gpu_translate_format(uint32_t drm_fourcc)
41{
42 uint32_t format;
43
44 switch (drm_fourcc) {
45 case DRM_FORMAT_XRGB8888:
46 format = VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM;
47 break;
48 case DRM_FORMAT_ARGB8888:
49 format = VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM;
50 break;
51 case DRM_FORMAT_BGRX8888:
52 format = VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM;
53 break;
54 case DRM_FORMAT_BGRA8888:
55 format = VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM;
56 break;
57 default:
58 /*
59 * This should not happen, we handle everything listed
60 * in virtio_gpu_formats[].
61 */
62 format = 0;
63 break;
64 }
65 WARN_ON(format == 0);
66 return format;
67}
68
69static const struct drm_plane_funcs virtio_gpu_plane_funcs = {
70 .update_plane = drm_atomic_helper_update_plane,
71 .disable_plane = drm_atomic_helper_disable_plane,
72 .reset = drm_atomic_helper_plane_reset,
73 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
74 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
75};
76
77static int virtio_gpu_plane_atomic_check(struct drm_plane *plane,
78 struct drm_atomic_state *state)
79{
80 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
81 plane);
82 bool is_cursor = plane->type == DRM_PLANE_TYPE_CURSOR;
83 struct drm_crtc_state *crtc_state;
84 int ret;
85
86 if (!new_plane_state->fb || WARN_ON(!new_plane_state->crtc))
87 return 0;
88
89 crtc_state = drm_atomic_get_crtc_state(state,
90 new_plane_state->crtc);
91 if (IS_ERR(crtc_state))
92 return PTR_ERR(crtc_state);
93
94 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
95 DRM_PLANE_NO_SCALING,
96 DRM_PLANE_NO_SCALING,
97 is_cursor, true);
98 return ret;
99}
100
101static void virtio_gpu_update_dumb_bo(struct virtio_gpu_device *vgdev,
102 struct drm_plane_state *state,
103 struct drm_rect *rect)
104{
105 struct virtio_gpu_object *bo =
106 gem_to_virtio_gpu_obj(state->fb->obj[0]);
107 struct virtio_gpu_object_array *objs;
108 uint32_t w = rect->x2 - rect->x1;
109 uint32_t h = rect->y2 - rect->y1;
110 uint32_t x = rect->x1;
111 uint32_t y = rect->y1;
112 uint32_t off = x * state->fb->format->cpp[0] +
113 y * state->fb->pitches[0];
114
115 objs = virtio_gpu_array_alloc(1);
116 if (!objs)
117 return;
118 virtio_gpu_array_add_obj(objs, &bo->base.base);
119
120 virtio_gpu_cmd_transfer_to_host_2d(vgdev, off, w, h, x, y,
121 objs, NULL);
122}
123
124static void virtio_gpu_resource_flush(struct drm_plane *plane,
125 uint32_t x, uint32_t y,
126 uint32_t width, uint32_t height)
127{
128 struct drm_device *dev = plane->dev;
129 struct virtio_gpu_device *vgdev = dev->dev_private;
130 struct virtio_gpu_framebuffer *vgfb;
131 struct virtio_gpu_object *bo;
132
133 vgfb = to_virtio_gpu_framebuffer(plane->state->fb);
134 bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]);
135 if (vgfb->fence) {
136 struct virtio_gpu_object_array *objs;
137
138 objs = virtio_gpu_array_alloc(1);
139 if (!objs)
140 return;
141 virtio_gpu_array_add_obj(objs, vgfb->base.obj[0]);
142 virtio_gpu_array_lock_resv(objs);
143 virtio_gpu_cmd_resource_flush(vgdev, bo->hw_res_handle, x, y,
144 width, height, objs, vgfb->fence);
145 virtio_gpu_notify(vgdev);
146
147 dma_fence_wait_timeout(&vgfb->fence->f, true,
148 msecs_to_jiffies(50));
149 dma_fence_put(&vgfb->fence->f);
150 vgfb->fence = NULL;
151 } else {
152 virtio_gpu_cmd_resource_flush(vgdev, bo->hw_res_handle, x, y,
153 width, height, NULL, NULL);
154 virtio_gpu_notify(vgdev);
155 }
156}
157
158static void virtio_gpu_primary_plane_update(struct drm_plane *plane,
159 struct drm_atomic_state *state)
160{
161 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
162 plane);
163 struct drm_device *dev = plane->dev;
164 struct virtio_gpu_device *vgdev = dev->dev_private;
165 struct virtio_gpu_output *output = NULL;
166 struct virtio_gpu_object *bo;
167 struct drm_rect rect;
168
169 if (plane->state->crtc)
170 output = drm_crtc_to_virtio_gpu_output(plane->state->crtc);
171 if (old_state->crtc)
172 output = drm_crtc_to_virtio_gpu_output(old_state->crtc);
173 if (WARN_ON(!output))
174 return;
175
176 if (!plane->state->fb || !output->crtc.state->active) {
177 DRM_DEBUG("nofb\n");
178 virtio_gpu_cmd_set_scanout(vgdev, output->index, 0,
179 plane->state->src_w >> 16,
180 plane->state->src_h >> 16,
181 0, 0);
182 virtio_gpu_notify(vgdev);
183 return;
184 }
185
186 if (!drm_atomic_helper_damage_merged(old_state, plane->state, &rect))
187 return;
188
189 bo = gem_to_virtio_gpu_obj(plane->state->fb->obj[0]);
190 if (bo->dumb)
191 virtio_gpu_update_dumb_bo(vgdev, plane->state, &rect);
192
193 if (plane->state->fb != old_state->fb ||
194 plane->state->src_w != old_state->src_w ||
195 plane->state->src_h != old_state->src_h ||
196 plane->state->src_x != old_state->src_x ||
197 plane->state->src_y != old_state->src_y ||
198 output->needs_modeset) {
199 output->needs_modeset = false;
200 DRM_DEBUG("handle 0x%x, crtc %dx%d+%d+%d, src %dx%d+%d+%d\n",
201 bo->hw_res_handle,
202 plane->state->crtc_w, plane->state->crtc_h,
203 plane->state->crtc_x, plane->state->crtc_y,
204 plane->state->src_w >> 16,
205 plane->state->src_h >> 16,
206 plane->state->src_x >> 16,
207 plane->state->src_y >> 16);
208
209 if (bo->host3d_blob || bo->guest_blob) {
210 virtio_gpu_cmd_set_scanout_blob
211 (vgdev, output->index, bo,
212 plane->state->fb,
213 plane->state->src_w >> 16,
214 plane->state->src_h >> 16,
215 plane->state->src_x >> 16,
216 plane->state->src_y >> 16);
217 } else {
218 virtio_gpu_cmd_set_scanout(vgdev, output->index,
219 bo->hw_res_handle,
220 plane->state->src_w >> 16,
221 plane->state->src_h >> 16,
222 plane->state->src_x >> 16,
223 plane->state->src_y >> 16);
224 }
225 }
226
227 virtio_gpu_resource_flush(plane,
228 rect.x1,
229 rect.y1,
230 rect.x2 - rect.x1,
231 rect.y2 - rect.y1);
232}
233
234static int virtio_gpu_plane_prepare_fb(struct drm_plane *plane,
235 struct drm_plane_state *new_state)
236{
237 struct drm_device *dev = plane->dev;
238 struct virtio_gpu_device *vgdev = dev->dev_private;
239 struct virtio_gpu_framebuffer *vgfb;
240 struct virtio_gpu_object *bo;
241
242 if (!new_state->fb)
243 return 0;
244
245 vgfb = to_virtio_gpu_framebuffer(new_state->fb);
246 bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]);
247 if (!bo || (plane->type == DRM_PLANE_TYPE_PRIMARY && !bo->guest_blob))
248 return 0;
249
250 if (bo->dumb && (plane->state->fb != new_state->fb)) {
251 vgfb->fence = virtio_gpu_fence_alloc(vgdev, vgdev->fence_drv.context,
252 0);
253 if (!vgfb->fence)
254 return -ENOMEM;
255 }
256
257 return 0;
258}
259
260static void virtio_gpu_plane_cleanup_fb(struct drm_plane *plane,
261 struct drm_plane_state *state)
262{
263 struct virtio_gpu_framebuffer *vgfb;
264
265 if (!state->fb)
266 return;
267
268 vgfb = to_virtio_gpu_framebuffer(state->fb);
269 if (vgfb->fence) {
270 dma_fence_put(&vgfb->fence->f);
271 vgfb->fence = NULL;
272 }
273}
274
275static void virtio_gpu_cursor_plane_update(struct drm_plane *plane,
276 struct drm_atomic_state *state)
277{
278 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
279 plane);
280 struct drm_device *dev = plane->dev;
281 struct virtio_gpu_device *vgdev = dev->dev_private;
282 struct virtio_gpu_output *output = NULL;
283 struct virtio_gpu_framebuffer *vgfb;
284 struct virtio_gpu_object *bo = NULL;
285 uint32_t handle;
286
287 if (plane->state->crtc)
288 output = drm_crtc_to_virtio_gpu_output(plane->state->crtc);
289 if (old_state->crtc)
290 output = drm_crtc_to_virtio_gpu_output(old_state->crtc);
291 if (WARN_ON(!output))
292 return;
293
294 if (plane->state->fb) {
295 vgfb = to_virtio_gpu_framebuffer(plane->state->fb);
296 bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]);
297 handle = bo->hw_res_handle;
298 } else {
299 handle = 0;
300 }
301
302 if (bo && bo->dumb && (plane->state->fb != old_state->fb)) {
303 /* new cursor -- update & wait */
304 struct virtio_gpu_object_array *objs;
305
306 objs = virtio_gpu_array_alloc(1);
307 if (!objs)
308 return;
309 virtio_gpu_array_add_obj(objs, vgfb->base.obj[0]);
310 virtio_gpu_array_lock_resv(objs);
311 virtio_gpu_cmd_transfer_to_host_2d
312 (vgdev, 0,
313 plane->state->crtc_w,
314 plane->state->crtc_h,
315 0, 0, objs, vgfb->fence);
316 virtio_gpu_notify(vgdev);
317 dma_fence_wait(&vgfb->fence->f, true);
318 dma_fence_put(&vgfb->fence->f);
319 vgfb->fence = NULL;
320 }
321
322 if (plane->state->fb != old_state->fb) {
323 DRM_DEBUG("update, handle %d, pos +%d+%d, hot %d,%d\n", handle,
324 plane->state->crtc_x,
325 plane->state->crtc_y,
326 plane->state->fb ? plane->state->fb->hot_x : 0,
327 plane->state->fb ? plane->state->fb->hot_y : 0);
328 output->cursor.hdr.type =
329 cpu_to_le32(VIRTIO_GPU_CMD_UPDATE_CURSOR);
330 output->cursor.resource_id = cpu_to_le32(handle);
331 if (plane->state->fb) {
332 output->cursor.hot_x =
333 cpu_to_le32(plane->state->fb->hot_x);
334 output->cursor.hot_y =
335 cpu_to_le32(plane->state->fb->hot_y);
336 } else {
337 output->cursor.hot_x = cpu_to_le32(0);
338 output->cursor.hot_y = cpu_to_le32(0);
339 }
340 } else {
341 DRM_DEBUG("move +%d+%d\n",
342 plane->state->crtc_x,
343 plane->state->crtc_y);
344 output->cursor.hdr.type =
345 cpu_to_le32(VIRTIO_GPU_CMD_MOVE_CURSOR);
346 }
347 output->cursor.pos.x = cpu_to_le32(plane->state->crtc_x);
348 output->cursor.pos.y = cpu_to_le32(plane->state->crtc_y);
349 virtio_gpu_cursor_ping(vgdev, output);
350}
351
352static const struct drm_plane_helper_funcs virtio_gpu_primary_helper_funcs = {
353 .prepare_fb = virtio_gpu_plane_prepare_fb,
354 .cleanup_fb = virtio_gpu_plane_cleanup_fb,
355 .atomic_check = virtio_gpu_plane_atomic_check,
356 .atomic_update = virtio_gpu_primary_plane_update,
357};
358
359static const struct drm_plane_helper_funcs virtio_gpu_cursor_helper_funcs = {
360 .prepare_fb = virtio_gpu_plane_prepare_fb,
361 .cleanup_fb = virtio_gpu_plane_cleanup_fb,
362 .atomic_check = virtio_gpu_plane_atomic_check,
363 .atomic_update = virtio_gpu_cursor_plane_update,
364};
365
366struct drm_plane *virtio_gpu_plane_init(struct virtio_gpu_device *vgdev,
367 enum drm_plane_type type,
368 int index)
369{
370 struct drm_device *dev = vgdev->ddev;
371 const struct drm_plane_helper_funcs *funcs;
372 struct drm_plane *plane;
373 const uint32_t *formats;
374 int nformats;
375
376 if (type == DRM_PLANE_TYPE_CURSOR) {
377 formats = virtio_gpu_cursor_formats;
378 nformats = ARRAY_SIZE(virtio_gpu_cursor_formats);
379 funcs = &virtio_gpu_cursor_helper_funcs;
380 } else {
381 formats = virtio_gpu_formats;
382 nformats = ARRAY_SIZE(virtio_gpu_formats);
383 funcs = &virtio_gpu_primary_helper_funcs;
384 }
385
386 plane = drmm_universal_plane_alloc(dev, struct drm_plane, dev,
387 1 << index, &virtio_gpu_plane_funcs,
388 formats, nformats, NULL, type, NULL);
389 if (IS_ERR(plane))
390 return plane;
391
392 drm_plane_helper_add(plane, funcs);
393 return plane;
394}