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1/*
2 * Copyright(c) 2011-2015 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24#include "i915_vgpu.h"
25
26/**
27 * DOC: Intel GVT-g guest support
28 *
29 * Intel GVT-g is a graphics virtualization technology which shares the
30 * GPU among multiple virtual machines on a time-sharing basis. Each
31 * virtual machine is presented a virtual GPU (vGPU), which has equivalent
32 * features as the underlying physical GPU (pGPU), so i915 driver can run
33 * seamlessly in a virtual machine. This file provides vGPU specific
34 * optimizations when running in a virtual machine, to reduce the complexity
35 * of vGPU emulation and to improve the overall performance.
36 *
37 * A primary function introduced here is so-called "address space ballooning"
38 * technique. Intel GVT-g partitions global graphics memory among multiple VMs,
39 * so each VM can directly access a portion of the memory without hypervisor's
40 * intervention, e.g. filling textures or queuing commands. However with the
41 * partitioning an unmodified i915 driver would assume a smaller graphics
42 * memory starting from address ZERO, then requires vGPU emulation module to
43 * translate the graphics address between 'guest view' and 'host view', for
44 * all registers and command opcodes which contain a graphics memory address.
45 * To reduce the complexity, Intel GVT-g introduces "address space ballooning",
46 * by telling the exact partitioning knowledge to each guest i915 driver, which
47 * then reserves and prevents non-allocated portions from allocation. Thus vGPU
48 * emulation module only needs to scan and validate graphics addresses without
49 * complexity of address translation.
50 *
51 */
52
53/**
54 * i915_detect_vgpu - detect virtual GPU
55 * @dev_priv: i915 device private
56 *
57 * This function is called at the initialization stage, to detect whether
58 * running on a vGPU.
59 */
60void i915_detect_vgpu(struct drm_i915_private *dev_priv)
61{
62 struct pci_dev *pdev = dev_priv->drm.pdev;
63 u64 magic;
64 u16 version_major;
65 void __iomem *shared_area;
66
67 BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
68
69 /*
70 * This is called before we setup the main MMIO BAR mappings used via
71 * the uncore structure, so we need to access the BAR directly. Since
72 * we do not support VGT on older gens, return early so we don't have
73 * to consider differently numbered or sized MMIO bars
74 */
75 if (INTEL_GEN(dev_priv) < 6)
76 return;
77
78 shared_area = pci_iomap_range(pdev, 0, VGT_PVINFO_PAGE, VGT_PVINFO_SIZE);
79 if (!shared_area) {
80 DRM_ERROR("failed to map MMIO bar to check for VGT\n");
81 return;
82 }
83
84 magic = readq(shared_area + vgtif_offset(magic));
85 if (magic != VGT_MAGIC)
86 goto out;
87
88 version_major = readw(shared_area + vgtif_offset(version_major));
89 if (version_major < VGT_VERSION_MAJOR) {
90 DRM_INFO("VGT interface version mismatch!\n");
91 goto out;
92 }
93
94 dev_priv->vgpu.caps = readl(shared_area + vgtif_offset(vgt_caps));
95
96 dev_priv->vgpu.active = true;
97 mutex_init(&dev_priv->vgpu.lock);
98 DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
99
100out:
101 pci_iounmap(pdev, shared_area);
102}
103
104bool intel_vgpu_has_full_ppgtt(struct drm_i915_private *dev_priv)
105{
106 return dev_priv->vgpu.caps & VGT_CAPS_FULL_PPGTT;
107}
108
109struct _balloon_info_ {
110 /*
111 * There are up to 2 regions per mappable/unmappable graphic
112 * memory that might be ballooned. Here, index 0/1 is for mappable
113 * graphic memory, 2/3 for unmappable graphic memory.
114 */
115 struct drm_mm_node space[4];
116};
117
118static struct _balloon_info_ bl_info;
119
120static void vgt_deballoon_space(struct i915_ggtt *ggtt,
121 struct drm_mm_node *node)
122{
123 if (!drm_mm_node_allocated(node))
124 return;
125
126 DRM_DEBUG_DRIVER("deballoon space: range [0x%llx - 0x%llx] %llu KiB.\n",
127 node->start,
128 node->start + node->size,
129 node->size / 1024);
130
131 ggtt->vm.reserved -= node->size;
132 drm_mm_remove_node(node);
133}
134
135/**
136 * intel_vgt_deballoon - deballoon reserved graphics address trunks
137 * @ggtt: the global GGTT from which we reserved earlier
138 *
139 * This function is called to deallocate the ballooned-out graphic memory, when
140 * driver is unloaded or when ballooning fails.
141 */
142void intel_vgt_deballoon(struct i915_ggtt *ggtt)
143{
144 int i;
145
146 if (!intel_vgpu_active(ggtt->vm.i915))
147 return;
148
149 DRM_DEBUG("VGT deballoon.\n");
150
151 for (i = 0; i < 4; i++)
152 vgt_deballoon_space(ggtt, &bl_info.space[i]);
153}
154
155static int vgt_balloon_space(struct i915_ggtt *ggtt,
156 struct drm_mm_node *node,
157 unsigned long start, unsigned long end)
158{
159 unsigned long size = end - start;
160 int ret;
161
162 if (start >= end)
163 return -EINVAL;
164
165 DRM_INFO("balloon space: range [ 0x%lx - 0x%lx ] %lu KiB.\n",
166 start, end, size / 1024);
167 ret = i915_gem_gtt_reserve(&ggtt->vm, node,
168 size, start, I915_COLOR_UNEVICTABLE,
169 0);
170 if (!ret)
171 ggtt->vm.reserved += size;
172
173 return ret;
174}
175
176/**
177 * intel_vgt_balloon - balloon out reserved graphics address trunks
178 * @ggtt: the global GGTT from which to reserve
179 *
180 * This function is called at the initialization stage, to balloon out the
181 * graphic address space allocated to other vGPUs, by marking these spaces as
182 * reserved. The ballooning related knowledge(starting address and size of
183 * the mappable/unmappable graphic memory) is described in the vgt_if structure
184 * in a reserved mmio range.
185 *
186 * To give an example, the drawing below depicts one typical scenario after
187 * ballooning. Here the vGPU1 has 2 pieces of graphic address spaces ballooned
188 * out each for the mappable and the non-mappable part. From the vGPU1 point of
189 * view, the total size is the same as the physical one, with the start address
190 * of its graphic space being zero. Yet there are some portions ballooned out(
191 * the shadow part, which are marked as reserved by drm allocator). From the
192 * host point of view, the graphic address space is partitioned by multiple
193 * vGPUs in different VMs. ::
194 *
195 * vGPU1 view Host view
196 * 0 ------> +-----------+ +-----------+
197 * ^ |###########| | vGPU3 |
198 * | |###########| +-----------+
199 * | |###########| | vGPU2 |
200 * | +-----------+ +-----------+
201 * mappable GM | available | ==> | vGPU1 |
202 * | +-----------+ +-----------+
203 * | |###########| | |
204 * v |###########| | Host |
205 * +=======+===========+ +===========+
206 * ^ |###########| | vGPU3 |
207 * | |###########| +-----------+
208 * | |###########| | vGPU2 |
209 * | +-----------+ +-----------+
210 * unmappable GM | available | ==> | vGPU1 |
211 * | +-----------+ +-----------+
212 * | |###########| | |
213 * | |###########| | Host |
214 * v |###########| | |
215 * total GM size ------> +-----------+ +-----------+
216 *
217 * Returns:
218 * zero on success, non-zero if configuration invalid or ballooning failed
219 */
220int intel_vgt_balloon(struct i915_ggtt *ggtt)
221{
222 struct intel_uncore *uncore = &ggtt->vm.i915->uncore;
223 unsigned long ggtt_end = ggtt->vm.total;
224
225 unsigned long mappable_base, mappable_size, mappable_end;
226 unsigned long unmappable_base, unmappable_size, unmappable_end;
227 int ret;
228
229 if (!intel_vgpu_active(ggtt->vm.i915))
230 return 0;
231
232 mappable_base =
233 intel_uncore_read(uncore, vgtif_reg(avail_rs.mappable_gmadr.base));
234 mappable_size =
235 intel_uncore_read(uncore, vgtif_reg(avail_rs.mappable_gmadr.size));
236 unmappable_base =
237 intel_uncore_read(uncore, vgtif_reg(avail_rs.nonmappable_gmadr.base));
238 unmappable_size =
239 intel_uncore_read(uncore, vgtif_reg(avail_rs.nonmappable_gmadr.size));
240
241 mappable_end = mappable_base + mappable_size;
242 unmappable_end = unmappable_base + unmappable_size;
243
244 DRM_INFO("VGT ballooning configuration:\n");
245 DRM_INFO("Mappable graphic memory: base 0x%lx size %ldKiB\n",
246 mappable_base, mappable_size / 1024);
247 DRM_INFO("Unmappable graphic memory: base 0x%lx size %ldKiB\n",
248 unmappable_base, unmappable_size / 1024);
249
250 if (mappable_end > ggtt->mappable_end ||
251 unmappable_base < ggtt->mappable_end ||
252 unmappable_end > ggtt_end) {
253 DRM_ERROR("Invalid ballooning configuration!\n");
254 return -EINVAL;
255 }
256
257 /* Unmappable graphic memory ballooning */
258 if (unmappable_base > ggtt->mappable_end) {
259 ret = vgt_balloon_space(ggtt, &bl_info.space[2],
260 ggtt->mappable_end, unmappable_base);
261
262 if (ret)
263 goto err;
264 }
265
266 if (unmappable_end < ggtt_end) {
267 ret = vgt_balloon_space(ggtt, &bl_info.space[3],
268 unmappable_end, ggtt_end);
269 if (ret)
270 goto err_upon_mappable;
271 }
272
273 /* Mappable graphic memory ballooning */
274 if (mappable_base) {
275 ret = vgt_balloon_space(ggtt, &bl_info.space[0],
276 0, mappable_base);
277
278 if (ret)
279 goto err_upon_unmappable;
280 }
281
282 if (mappable_end < ggtt->mappable_end) {
283 ret = vgt_balloon_space(ggtt, &bl_info.space[1],
284 mappable_end, ggtt->mappable_end);
285
286 if (ret)
287 goto err_below_mappable;
288 }
289
290 DRM_INFO("VGT balloon successfully\n");
291 return 0;
292
293err_below_mappable:
294 vgt_deballoon_space(ggtt, &bl_info.space[0]);
295err_upon_unmappable:
296 vgt_deballoon_space(ggtt, &bl_info.space[3]);
297err_upon_mappable:
298 vgt_deballoon_space(ggtt, &bl_info.space[2]);
299err:
300 DRM_ERROR("VGT balloon fail\n");
301 return ret;
302}
1/*
2 * Copyright(c) 2011-2015 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24#include "i915_drv.h"
25#include "i915_pvinfo.h"
26#include "i915_vgpu.h"
27
28/**
29 * DOC: Intel GVT-g guest support
30 *
31 * Intel GVT-g is a graphics virtualization technology which shares the
32 * GPU among multiple virtual machines on a time-sharing basis. Each
33 * virtual machine is presented a virtual GPU (vGPU), which has equivalent
34 * features as the underlying physical GPU (pGPU), so i915 driver can run
35 * seamlessly in a virtual machine. This file provides vGPU specific
36 * optimizations when running in a virtual machine, to reduce the complexity
37 * of vGPU emulation and to improve the overall performance.
38 *
39 * A primary function introduced here is so-called "address space ballooning"
40 * technique. Intel GVT-g partitions global graphics memory among multiple VMs,
41 * so each VM can directly access a portion of the memory without hypervisor's
42 * intervention, e.g. filling textures or queuing commands. However with the
43 * partitioning an unmodified i915 driver would assume a smaller graphics
44 * memory starting from address ZERO, then requires vGPU emulation module to
45 * translate the graphics address between 'guest view' and 'host view', for
46 * all registers and command opcodes which contain a graphics memory address.
47 * To reduce the complexity, Intel GVT-g introduces "address space ballooning",
48 * by telling the exact partitioning knowledge to each guest i915 driver, which
49 * then reserves and prevents non-allocated portions from allocation. Thus vGPU
50 * emulation module only needs to scan and validate graphics addresses without
51 * complexity of address translation.
52 *
53 */
54
55/**
56 * intel_vgpu_detect - detect virtual GPU
57 * @dev_priv: i915 device private
58 *
59 * This function is called at the initialization stage, to detect whether
60 * running on a vGPU.
61 */
62void intel_vgpu_detect(struct drm_i915_private *dev_priv)
63{
64 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
65 u64 magic;
66 u16 version_major;
67 void __iomem *shared_area;
68
69 BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
70
71 /*
72 * This is called before we setup the main MMIO BAR mappings used via
73 * the uncore structure, so we need to access the BAR directly. Since
74 * we do not support VGT on older gens, return early so we don't have
75 * to consider differently numbered or sized MMIO bars
76 */
77 if (GRAPHICS_VER(dev_priv) < 6)
78 return;
79
80 shared_area = pci_iomap_range(pdev, 0, VGT_PVINFO_PAGE, VGT_PVINFO_SIZE);
81 if (!shared_area) {
82 drm_err(&dev_priv->drm,
83 "failed to map MMIO bar to check for VGT\n");
84 return;
85 }
86
87 magic = readq(shared_area + vgtif_offset(magic));
88 if (magic != VGT_MAGIC)
89 goto out;
90
91 version_major = readw(shared_area + vgtif_offset(version_major));
92 if (version_major < VGT_VERSION_MAJOR) {
93 drm_info(&dev_priv->drm, "VGT interface version mismatch!\n");
94 goto out;
95 }
96
97 dev_priv->vgpu.caps = readl(shared_area + vgtif_offset(vgt_caps));
98
99 dev_priv->vgpu.active = true;
100 mutex_init(&dev_priv->vgpu.lock);
101 drm_info(&dev_priv->drm, "Virtual GPU for Intel GVT-g detected.\n");
102
103out:
104 pci_iounmap(pdev, shared_area);
105}
106
107void intel_vgpu_register(struct drm_i915_private *i915)
108{
109 /*
110 * Notify a valid surface after modesetting, when running inside a VM.
111 */
112 if (intel_vgpu_active(i915))
113 intel_uncore_write(&i915->uncore, vgtif_reg(display_ready),
114 VGT_DRV_DISPLAY_READY);
115}
116
117bool intel_vgpu_active(struct drm_i915_private *dev_priv)
118{
119 return dev_priv->vgpu.active;
120}
121
122bool intel_vgpu_has_full_ppgtt(struct drm_i915_private *dev_priv)
123{
124 return dev_priv->vgpu.caps & VGT_CAPS_FULL_PPGTT;
125}
126
127bool intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)
128{
129 return dev_priv->vgpu.caps & VGT_CAPS_HWSP_EMULATION;
130}
131
132bool intel_vgpu_has_huge_gtt(struct drm_i915_private *dev_priv)
133{
134 return dev_priv->vgpu.caps & VGT_CAPS_HUGE_GTT;
135}
136
137struct _balloon_info_ {
138 /*
139 * There are up to 2 regions per mappable/unmappable graphic
140 * memory that might be ballooned. Here, index 0/1 is for mappable
141 * graphic memory, 2/3 for unmappable graphic memory.
142 */
143 struct drm_mm_node space[4];
144};
145
146static struct _balloon_info_ bl_info;
147
148static void vgt_deballoon_space(struct i915_ggtt *ggtt,
149 struct drm_mm_node *node)
150{
151 struct drm_i915_private *dev_priv = ggtt->vm.i915;
152 if (!drm_mm_node_allocated(node))
153 return;
154
155 drm_dbg(&dev_priv->drm,
156 "deballoon space: range [0x%llx - 0x%llx] %llu KiB.\n",
157 node->start,
158 node->start + node->size,
159 node->size / 1024);
160
161 ggtt->vm.reserved -= node->size;
162 drm_mm_remove_node(node);
163}
164
165/**
166 * intel_vgt_deballoon - deballoon reserved graphics address trunks
167 * @ggtt: the global GGTT from which we reserved earlier
168 *
169 * This function is called to deallocate the ballooned-out graphic memory, when
170 * driver is unloaded or when ballooning fails.
171 */
172void intel_vgt_deballoon(struct i915_ggtt *ggtt)
173{
174 struct drm_i915_private *dev_priv = ggtt->vm.i915;
175 int i;
176
177 if (!intel_vgpu_active(ggtt->vm.i915))
178 return;
179
180 drm_dbg(&dev_priv->drm, "VGT deballoon.\n");
181
182 for (i = 0; i < 4; i++)
183 vgt_deballoon_space(ggtt, &bl_info.space[i]);
184}
185
186static int vgt_balloon_space(struct i915_ggtt *ggtt,
187 struct drm_mm_node *node,
188 unsigned long start, unsigned long end)
189{
190 struct drm_i915_private *dev_priv = ggtt->vm.i915;
191 unsigned long size = end - start;
192 int ret;
193
194 if (start >= end)
195 return -EINVAL;
196
197 drm_info(&dev_priv->drm,
198 "balloon space: range [ 0x%lx - 0x%lx ] %lu KiB.\n",
199 start, end, size / 1024);
200 ret = i915_gem_gtt_reserve(&ggtt->vm, NULL, node,
201 size, start, I915_COLOR_UNEVICTABLE,
202 0);
203 if (!ret)
204 ggtt->vm.reserved += size;
205
206 return ret;
207}
208
209/**
210 * intel_vgt_balloon - balloon out reserved graphics address trunks
211 * @ggtt: the global GGTT from which to reserve
212 *
213 * This function is called at the initialization stage, to balloon out the
214 * graphic address space allocated to other vGPUs, by marking these spaces as
215 * reserved. The ballooning related knowledge(starting address and size of
216 * the mappable/unmappable graphic memory) is described in the vgt_if structure
217 * in a reserved mmio range.
218 *
219 * To give an example, the drawing below depicts one typical scenario after
220 * ballooning. Here the vGPU1 has 2 pieces of graphic address spaces ballooned
221 * out each for the mappable and the non-mappable part. From the vGPU1 point of
222 * view, the total size is the same as the physical one, with the start address
223 * of its graphic space being zero. Yet there are some portions ballooned out(
224 * the shadow part, which are marked as reserved by drm allocator). From the
225 * host point of view, the graphic address space is partitioned by multiple
226 * vGPUs in different VMs. ::
227 *
228 * vGPU1 view Host view
229 * 0 ------> +-----------+ +-----------+
230 * ^ |###########| | vGPU3 |
231 * | |###########| +-----------+
232 * | |###########| | vGPU2 |
233 * | +-----------+ +-----------+
234 * mappable GM | available | ==> | vGPU1 |
235 * | +-----------+ +-----------+
236 * | |###########| | |
237 * v |###########| | Host |
238 * +=======+===========+ +===========+
239 * ^ |###########| | vGPU3 |
240 * | |###########| +-----------+
241 * | |###########| | vGPU2 |
242 * | +-----------+ +-----------+
243 * unmappable GM | available | ==> | vGPU1 |
244 * | +-----------+ +-----------+
245 * | |###########| | |
246 * | |###########| | Host |
247 * v |###########| | |
248 * total GM size ------> +-----------+ +-----------+
249 *
250 * Returns:
251 * zero on success, non-zero if configuration invalid or ballooning failed
252 */
253int intel_vgt_balloon(struct i915_ggtt *ggtt)
254{
255 struct drm_i915_private *dev_priv = ggtt->vm.i915;
256 struct intel_uncore *uncore = &dev_priv->uncore;
257 unsigned long ggtt_end = ggtt->vm.total;
258
259 unsigned long mappable_base, mappable_size, mappable_end;
260 unsigned long unmappable_base, unmappable_size, unmappable_end;
261 int ret;
262
263 if (!intel_vgpu_active(ggtt->vm.i915))
264 return 0;
265
266 mappable_base =
267 intel_uncore_read(uncore, vgtif_reg(avail_rs.mappable_gmadr.base));
268 mappable_size =
269 intel_uncore_read(uncore, vgtif_reg(avail_rs.mappable_gmadr.size));
270 unmappable_base =
271 intel_uncore_read(uncore, vgtif_reg(avail_rs.nonmappable_gmadr.base));
272 unmappable_size =
273 intel_uncore_read(uncore, vgtif_reg(avail_rs.nonmappable_gmadr.size));
274
275 mappable_end = mappable_base + mappable_size;
276 unmappable_end = unmappable_base + unmappable_size;
277
278 drm_info(&dev_priv->drm, "VGT ballooning configuration:\n");
279 drm_info(&dev_priv->drm,
280 "Mappable graphic memory: base 0x%lx size %ldKiB\n",
281 mappable_base, mappable_size / 1024);
282 drm_info(&dev_priv->drm,
283 "Unmappable graphic memory: base 0x%lx size %ldKiB\n",
284 unmappable_base, unmappable_size / 1024);
285
286 if (mappable_end > ggtt->mappable_end ||
287 unmappable_base < ggtt->mappable_end ||
288 unmappable_end > ggtt_end) {
289 drm_err(&dev_priv->drm, "Invalid ballooning configuration!\n");
290 return -EINVAL;
291 }
292
293 /* Unmappable graphic memory ballooning */
294 if (unmappable_base > ggtt->mappable_end) {
295 ret = vgt_balloon_space(ggtt, &bl_info.space[2],
296 ggtt->mappable_end, unmappable_base);
297
298 if (ret)
299 goto err;
300 }
301
302 if (unmappable_end < ggtt_end) {
303 ret = vgt_balloon_space(ggtt, &bl_info.space[3],
304 unmappable_end, ggtt_end);
305 if (ret)
306 goto err_upon_mappable;
307 }
308
309 /* Mappable graphic memory ballooning */
310 if (mappable_base) {
311 ret = vgt_balloon_space(ggtt, &bl_info.space[0],
312 0, mappable_base);
313
314 if (ret)
315 goto err_upon_unmappable;
316 }
317
318 if (mappable_end < ggtt->mappable_end) {
319 ret = vgt_balloon_space(ggtt, &bl_info.space[1],
320 mappable_end, ggtt->mappable_end);
321
322 if (ret)
323 goto err_below_mappable;
324 }
325
326 drm_info(&dev_priv->drm, "VGT balloon successfully\n");
327 return 0;
328
329err_below_mappable:
330 vgt_deballoon_space(ggtt, &bl_info.space[0]);
331err_upon_unmappable:
332 vgt_deballoon_space(ggtt, &bl_info.space[3]);
333err_upon_mappable:
334 vgt_deballoon_space(ggtt, &bl_info.space[2]);
335err:
336 drm_err(&dev_priv->drm, "VGT balloon fail\n");
337 return ret;
338}