1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (C) 2012 Texas Instruments
   4 * Author: Rob Clark <robdclark@gmail.com>
   5 */
   6
   7#include <linux/component.h>
   8#include <linux/gpio/consumer.h>
   9#include <linux/hdmi.h>
 
  10#include <linux/module.h>
  11#include <linux/platform_data/tda9950.h>
  12#include <linux/irq.h>
  13#include <sound/asoundef.h>
  14#include <sound/hdmi-codec.h>
  15
  16#include <drm/drm_atomic_helper.h>
 
  17#include <drm/drm_edid.h>
  18#include <drm/drm_of.h>
  19#include <drm/drm_print.h>
  20#include <drm/drm_probe_helper.h>
 
  21#include <drm/i2c/tda998x.h>
  22
  23#include <media/cec-notifier.h>
  24
  25#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
  26
  27enum {
  28	AUDIO_ROUTE_I2S,
  29	AUDIO_ROUTE_SPDIF,
  30	AUDIO_ROUTE_NUM
  31};
  32
  33struct tda998x_audio_route {
  34	u8 ena_aclk;
  35	u8 mux_ap;
  36	u8 aip_clksel;
  37};
  38
  39struct tda998x_audio_settings {
  40	const struct tda998x_audio_route *route;
  41	struct hdmi_audio_infoframe cea;
  42	unsigned int sample_rate;
  43	u8 status[5];
  44	u8 ena_ap;
  45	u8 i2s_format;
  46	u8 cts_n;
  47};
  48
  49struct tda998x_priv {
  50	struct i2c_client *cec;
  51	struct i2c_client *hdmi;
  52	struct mutex mutex;
  53	u16 rev;
  54	u8 cec_addr;
  55	u8 current_page;
  56	bool is_on;
  57	bool supports_infoframes;
  58	bool sink_has_audio;
  59	enum hdmi_quantization_range rgb_quant_range;
  60	u8 vip_cntrl_0;
  61	u8 vip_cntrl_1;
  62	u8 vip_cntrl_2;
  63	unsigned long tmds_clock;
  64	struct tda998x_audio_settings audio;
  65
  66	struct platform_device *audio_pdev;
  67	struct mutex audio_mutex;
  68
  69	struct mutex edid_mutex;
  70	wait_queue_head_t wq_edid;
  71	volatile int wq_edid_wait;
  72
  73	struct work_struct detect_work;
  74	struct timer_list edid_delay_timer;
  75	wait_queue_head_t edid_delay_waitq;
  76	bool edid_delay_active;
  77
  78	struct drm_encoder encoder;
  79	struct drm_bridge bridge;
  80	struct drm_connector connector;
  81
  82	u8 audio_port_enable[AUDIO_ROUTE_NUM];
  83	struct tda9950_glue cec_glue;
  84	struct gpio_desc *calib;
  85	struct cec_notifier *cec_notify;
  86};
  87
  88#define conn_to_tda998x_priv(x) \
  89	container_of(x, struct tda998x_priv, connector)
  90#define enc_to_tda998x_priv(x) \
  91	container_of(x, struct tda998x_priv, encoder)
  92#define bridge_to_tda998x_priv(x) \
  93	container_of(x, struct tda998x_priv, bridge)
  94
  95/* The TDA9988 series of devices use a paged register scheme.. to simplify
  96 * things we encode the page # in upper bits of the register #.  To read/
  97 * write a given register, we need to make sure CURPAGE register is set
  98 * appropriately.  Which implies reads/writes are not atomic.  Fun!
  99 */
 100
 101#define REG(page, addr) (((page) << 8) | (addr))
 102#define REG2ADDR(reg)   ((reg) & 0xff)
 103#define REG2PAGE(reg)   (((reg) >> 8) & 0xff)
 104
 105#define REG_CURPAGE               0xff                /* write */
 106
 107
 108/* Page 00h: General Control */
 109#define REG_VERSION_LSB           REG(0x00, 0x00)     /* read */
 110#define REG_MAIN_CNTRL0           REG(0x00, 0x01)     /* read/write */
 111# define MAIN_CNTRL0_SR           (1 << 0)
 112# define MAIN_CNTRL0_DECS         (1 << 1)
 113# define MAIN_CNTRL0_DEHS         (1 << 2)
 114# define MAIN_CNTRL0_CECS         (1 << 3)
 115# define MAIN_CNTRL0_CEHS         (1 << 4)
 116# define MAIN_CNTRL0_SCALER       (1 << 7)
 117#define REG_VERSION_MSB           REG(0x00, 0x02)     /* read */
 118#define REG_SOFTRESET             REG(0x00, 0x0a)     /* write */
 119# define SOFTRESET_AUDIO          (1 << 0)
 120# define SOFTRESET_I2C_MASTER     (1 << 1)
 121#define REG_DDC_DISABLE           REG(0x00, 0x0b)     /* read/write */
 122#define REG_CCLK_ON               REG(0x00, 0x0c)     /* read/write */
 123#define REG_I2C_MASTER            REG(0x00, 0x0d)     /* read/write */
 124# define I2C_MASTER_DIS_MM        (1 << 0)
 125# define I2C_MASTER_DIS_FILT      (1 << 1)
 126# define I2C_MASTER_APP_STRT_LAT  (1 << 2)
 127#define REG_FEAT_POWERDOWN        REG(0x00, 0x0e)     /* read/write */
 128# define FEAT_POWERDOWN_PREFILT   BIT(0)
 129# define FEAT_POWERDOWN_CSC       BIT(1)
 130# define FEAT_POWERDOWN_SPDIF     (1 << 3)
 131#define REG_INT_FLAGS_0           REG(0x00, 0x0f)     /* read/write */
 132#define REG_INT_FLAGS_1           REG(0x00, 0x10)     /* read/write */
 133#define REG_INT_FLAGS_2           REG(0x00, 0x11)     /* read/write */
 134# define INT_FLAGS_2_EDID_BLK_RD  (1 << 1)
 135#define REG_ENA_ACLK              REG(0x00, 0x16)     /* read/write */
 136#define REG_ENA_VP_0              REG(0x00, 0x18)     /* read/write */
 137#define REG_ENA_VP_1              REG(0x00, 0x19)     /* read/write */
 138#define REG_ENA_VP_2              REG(0x00, 0x1a)     /* read/write */
 139#define REG_ENA_AP                REG(0x00, 0x1e)     /* read/write */
 140#define REG_VIP_CNTRL_0           REG(0x00, 0x20)     /* write */
 141# define VIP_CNTRL_0_MIRR_A       (1 << 7)
 142# define VIP_CNTRL_0_SWAP_A(x)    (((x) & 7) << 4)
 143# define VIP_CNTRL_0_MIRR_B       (1 << 3)
 144# define VIP_CNTRL_0_SWAP_B(x)    (((x) & 7) << 0)
 145#define REG_VIP_CNTRL_1           REG(0x00, 0x21)     /* write */
 146# define VIP_CNTRL_1_MIRR_C       (1 << 7)
 147# define VIP_CNTRL_1_SWAP_C(x)    (((x) & 7) << 4)
 148# define VIP_CNTRL_1_MIRR_D       (1 << 3)
 149# define VIP_CNTRL_1_SWAP_D(x)    (((x) & 7) << 0)
 150#define REG_VIP_CNTRL_2           REG(0x00, 0x22)     /* write */
 151# define VIP_CNTRL_2_MIRR_E       (1 << 7)
 152# define VIP_CNTRL_2_SWAP_E(x)    (((x) & 7) << 4)
 153# define VIP_CNTRL_2_MIRR_F       (1 << 3)
 154# define VIP_CNTRL_2_SWAP_F(x)    (((x) & 7) << 0)
 155#define REG_VIP_CNTRL_3           REG(0x00, 0x23)     /* write */
 156# define VIP_CNTRL_3_X_TGL        (1 << 0)
 157# define VIP_CNTRL_3_H_TGL        (1 << 1)
 158# define VIP_CNTRL_3_V_TGL        (1 << 2)
 159# define VIP_CNTRL_3_EMB          (1 << 3)
 160# define VIP_CNTRL_3_SYNC_DE      (1 << 4)
 161# define VIP_CNTRL_3_SYNC_HS      (1 << 5)
 162# define VIP_CNTRL_3_DE_INT       (1 << 6)
 163# define VIP_CNTRL_3_EDGE         (1 << 7)
 164#define REG_VIP_CNTRL_4           REG(0x00, 0x24)     /* write */
 165# define VIP_CNTRL_4_BLC(x)       (((x) & 3) << 0)
 166# define VIP_CNTRL_4_BLANKIT(x)   (((x) & 3) << 2)
 167# define VIP_CNTRL_4_CCIR656      (1 << 4)
 168# define VIP_CNTRL_4_656_ALT      (1 << 5)
 169# define VIP_CNTRL_4_TST_656      (1 << 6)
 170# define VIP_CNTRL_4_TST_PAT      (1 << 7)
 171#define REG_VIP_CNTRL_5           REG(0x00, 0x25)     /* write */
 172# define VIP_CNTRL_5_CKCASE       (1 << 0)
 173# define VIP_CNTRL_5_SP_CNT(x)    (((x) & 3) << 1)
 174#define REG_MUX_AP                REG(0x00, 0x26)     /* read/write */
 175# define MUX_AP_SELECT_I2S	  0x64
 176# define MUX_AP_SELECT_SPDIF	  0x40
 177#define REG_MUX_VP_VIP_OUT        REG(0x00, 0x27)     /* read/write */
 178#define REG_MAT_CONTRL            REG(0x00, 0x80)     /* write */
 179# define MAT_CONTRL_MAT_SC(x)     (((x) & 3) << 0)
 180# define MAT_CONTRL_MAT_BP        (1 << 2)
 181#define REG_VIDFORMAT             REG(0x00, 0xa0)     /* write */
 182#define REG_REFPIX_MSB            REG(0x00, 0xa1)     /* write */
 183#define REG_REFPIX_LSB            REG(0x00, 0xa2)     /* write */
 184#define REG_REFLINE_MSB           REG(0x00, 0xa3)     /* write */
 185#define REG_REFLINE_LSB           REG(0x00, 0xa4)     /* write */
 186#define REG_NPIX_MSB              REG(0x00, 0xa5)     /* write */
 187#define REG_NPIX_LSB              REG(0x00, 0xa6)     /* write */
 188#define REG_NLINE_MSB             REG(0x00, 0xa7)     /* write */
 189#define REG_NLINE_LSB             REG(0x00, 0xa8)     /* write */
 190#define REG_VS_LINE_STRT_1_MSB    REG(0x00, 0xa9)     /* write */
 191#define REG_VS_LINE_STRT_1_LSB    REG(0x00, 0xaa)     /* write */
 192#define REG_VS_PIX_STRT_1_MSB     REG(0x00, 0xab)     /* write */
 193#define REG_VS_PIX_STRT_1_LSB     REG(0x00, 0xac)     /* write */
 194#define REG_VS_LINE_END_1_MSB     REG(0x00, 0xad)     /* write */
 195#define REG_VS_LINE_END_1_LSB     REG(0x00, 0xae)     /* write */
 196#define REG_VS_PIX_END_1_MSB      REG(0x00, 0xaf)     /* write */
 197#define REG_VS_PIX_END_1_LSB      REG(0x00, 0xb0)     /* write */
 198#define REG_VS_LINE_STRT_2_MSB    REG(0x00, 0xb1)     /* write */
 199#define REG_VS_LINE_STRT_2_LSB    REG(0x00, 0xb2)     /* write */
 200#define REG_VS_PIX_STRT_2_MSB     REG(0x00, 0xb3)     /* write */
 201#define REG_VS_PIX_STRT_2_LSB     REG(0x00, 0xb4)     /* write */
 202#define REG_VS_LINE_END_2_MSB     REG(0x00, 0xb5)     /* write */
 203#define REG_VS_LINE_END_2_LSB     REG(0x00, 0xb6)     /* write */
 204#define REG_VS_PIX_END_2_MSB      REG(0x00, 0xb7)     /* write */
 205#define REG_VS_PIX_END_2_LSB      REG(0x00, 0xb8)     /* write */
 206#define REG_HS_PIX_START_MSB      REG(0x00, 0xb9)     /* write */
 207#define REG_HS_PIX_START_LSB      REG(0x00, 0xba)     /* write */
 208#define REG_HS_PIX_STOP_MSB       REG(0x00, 0xbb)     /* write */
 209#define REG_HS_PIX_STOP_LSB       REG(0x00, 0xbc)     /* write */
 210#define REG_VWIN_START_1_MSB      REG(0x00, 0xbd)     /* write */
 211#define REG_VWIN_START_1_LSB      REG(0x00, 0xbe)     /* write */
 212#define REG_VWIN_END_1_MSB        REG(0x00, 0xbf)     /* write */
 213#define REG_VWIN_END_1_LSB        REG(0x00, 0xc0)     /* write */
 214#define REG_VWIN_START_2_MSB      REG(0x00, 0xc1)     /* write */
 215#define REG_VWIN_START_2_LSB      REG(0x00, 0xc2)     /* write */
 216#define REG_VWIN_END_2_MSB        REG(0x00, 0xc3)     /* write */
 217#define REG_VWIN_END_2_LSB        REG(0x00, 0xc4)     /* write */
 218#define REG_DE_START_MSB          REG(0x00, 0xc5)     /* write */
 219#define REG_DE_START_LSB          REG(0x00, 0xc6)     /* write */
 220#define REG_DE_STOP_MSB           REG(0x00, 0xc7)     /* write */
 221#define REG_DE_STOP_LSB           REG(0x00, 0xc8)     /* write */
 222#define REG_TBG_CNTRL_0           REG(0x00, 0xca)     /* write */
 223# define TBG_CNTRL_0_TOP_TGL      (1 << 0)
 224# define TBG_CNTRL_0_TOP_SEL      (1 << 1)
 225# define TBG_CNTRL_0_DE_EXT       (1 << 2)
 226# define TBG_CNTRL_0_TOP_EXT      (1 << 3)
 227# define TBG_CNTRL_0_FRAME_DIS    (1 << 5)
 228# define TBG_CNTRL_0_SYNC_MTHD    (1 << 6)
 229# define TBG_CNTRL_0_SYNC_ONCE    (1 << 7)
 230#define REG_TBG_CNTRL_1           REG(0x00, 0xcb)     /* write */
 231# define TBG_CNTRL_1_H_TGL        (1 << 0)
 232# define TBG_CNTRL_1_V_TGL        (1 << 1)
 233# define TBG_CNTRL_1_TGL_EN       (1 << 2)
 234# define TBG_CNTRL_1_X_EXT        (1 << 3)
 235# define TBG_CNTRL_1_H_EXT        (1 << 4)
 236# define TBG_CNTRL_1_V_EXT        (1 << 5)
 237# define TBG_CNTRL_1_DWIN_DIS     (1 << 6)
 238#define REG_ENABLE_SPACE          REG(0x00, 0xd6)     /* write */
 239#define REG_HVF_CNTRL_0           REG(0x00, 0xe4)     /* write */
 240# define HVF_CNTRL_0_SM           (1 << 7)
 241# define HVF_CNTRL_0_RWB          (1 << 6)
 242# define HVF_CNTRL_0_PREFIL(x)    (((x) & 3) << 2)
 243# define HVF_CNTRL_0_INTPOL(x)    (((x) & 3) << 0)
 244#define REG_HVF_CNTRL_1           REG(0x00, 0xe5)     /* write */
 245# define HVF_CNTRL_1_FOR          (1 << 0)
 246# define HVF_CNTRL_1_YUVBLK       (1 << 1)
 247# define HVF_CNTRL_1_VQR(x)       (((x) & 3) << 2)
 248# define HVF_CNTRL_1_PAD(x)       (((x) & 3) << 4)
 249# define HVF_CNTRL_1_SEMI_PLANAR  (1 << 6)
 250#define REG_RPT_CNTRL             REG(0x00, 0xf0)     /* write */
 251# define RPT_CNTRL_REPEAT(x)      ((x) & 15)
 252#define REG_I2S_FORMAT            REG(0x00, 0xfc)     /* read/write */
 253# define I2S_FORMAT_PHILIPS       (0 << 0)
 254# define I2S_FORMAT_LEFT_J        (2 << 0)
 255# define I2S_FORMAT_RIGHT_J       (3 << 0)
 256#define REG_AIP_CLKSEL            REG(0x00, 0xfd)     /* write */
 257# define AIP_CLKSEL_AIP_SPDIF	  (0 << 3)
 258# define AIP_CLKSEL_AIP_I2S	  (1 << 3)
 259# define AIP_CLKSEL_FS_ACLK	  (0 << 0)
 260# define AIP_CLKSEL_FS_MCLK	  (1 << 0)
 261# define AIP_CLKSEL_FS_FS64SPDIF  (2 << 0)
 262
 263/* Page 02h: PLL settings */
 264#define REG_PLL_SERIAL_1          REG(0x02, 0x00)     /* read/write */
 265# define PLL_SERIAL_1_SRL_FDN     (1 << 0)
 266# define PLL_SERIAL_1_SRL_IZ(x)   (((x) & 3) << 1)
 267# define PLL_SERIAL_1_SRL_MAN_IZ  (1 << 6)
 268#define REG_PLL_SERIAL_2          REG(0x02, 0x01)     /* read/write */
 269# define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
 270# define PLL_SERIAL_2_SRL_PR(x)   (((x) & 0xf) << 4)
 271#define REG_PLL_SERIAL_3          REG(0x02, 0x02)     /* read/write */
 272# define PLL_SERIAL_3_SRL_CCIR    (1 << 0)
 273# define PLL_SERIAL_3_SRL_DE      (1 << 2)
 274# define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
 275#define REG_SERIALIZER            REG(0x02, 0x03)     /* read/write */
 276#define REG_BUFFER_OUT            REG(0x02, 0x04)     /* read/write */
 277#define REG_PLL_SCG1              REG(0x02, 0x05)     /* read/write */
 278#define REG_PLL_SCG2              REG(0x02, 0x06)     /* read/write */
 279#define REG_PLL_SCGN1             REG(0x02, 0x07)     /* read/write */
 280#define REG_PLL_SCGN2             REG(0x02, 0x08)     /* read/write */
 281#define REG_PLL_SCGR1             REG(0x02, 0x09)     /* read/write */
 282#define REG_PLL_SCGR2             REG(0x02, 0x0a)     /* read/write */
 283#define REG_AUDIO_DIV             REG(0x02, 0x0e)     /* read/write */
 284# define AUDIO_DIV_SERCLK_1       0
 285# define AUDIO_DIV_SERCLK_2       1
 286# define AUDIO_DIV_SERCLK_4       2
 287# define AUDIO_DIV_SERCLK_8       3
 288# define AUDIO_DIV_SERCLK_16      4
 289# define AUDIO_DIV_SERCLK_32      5
 290#define REG_SEL_CLK               REG(0x02, 0x11)     /* read/write */
 291# define SEL_CLK_SEL_CLK1         (1 << 0)
 292# define SEL_CLK_SEL_VRF_CLK(x)   (((x) & 3) << 1)
 293# define SEL_CLK_ENA_SC_CLK       (1 << 3)
 294#define REG_ANA_GENERAL           REG(0x02, 0x12)     /* read/write */
 295
 296
 297/* Page 09h: EDID Control */
 298#define REG_EDID_DATA_0           REG(0x09, 0x00)     /* read */
 299/* next 127 successive registers are the EDID block */
 300#define REG_EDID_CTRL             REG(0x09, 0xfa)     /* read/write */
 301#define REG_DDC_ADDR              REG(0x09, 0xfb)     /* read/write */
 302#define REG_DDC_OFFS              REG(0x09, 0xfc)     /* read/write */
 303#define REG_DDC_SEGM_ADDR         REG(0x09, 0xfd)     /* read/write */
 304#define REG_DDC_SEGM              REG(0x09, 0xfe)     /* read/write */
 305
 306
 307/* Page 10h: information frames and packets */
 308#define REG_IF1_HB0               REG(0x10, 0x20)     /* read/write */
 309#define REG_IF2_HB0               REG(0x10, 0x40)     /* read/write */
 310#define REG_IF3_HB0               REG(0x10, 0x60)     /* read/write */
 311#define REG_IF4_HB0               REG(0x10, 0x80)     /* read/write */
 312#define REG_IF5_HB0               REG(0x10, 0xa0)     /* read/write */
 313
 314
 315/* Page 11h: audio settings and content info packets */
 316#define REG_AIP_CNTRL_0           REG(0x11, 0x00)     /* read/write */
 317# define AIP_CNTRL_0_RST_FIFO     (1 << 0)
 318# define AIP_CNTRL_0_SWAP         (1 << 1)
 319# define AIP_CNTRL_0_LAYOUT       (1 << 2)
 320# define AIP_CNTRL_0_ACR_MAN      (1 << 5)
 321# define AIP_CNTRL_0_RST_CTS      (1 << 6)
 322#define REG_CA_I2S                REG(0x11, 0x01)     /* read/write */
 323# define CA_I2S_CA_I2S(x)         (((x) & 31) << 0)
 324# define CA_I2S_HBR_CHSTAT        (1 << 6)
 325#define REG_LATENCY_RD            REG(0x11, 0x04)     /* read/write */
 326#define REG_ACR_CTS_0             REG(0x11, 0x05)     /* read/write */
 327#define REG_ACR_CTS_1             REG(0x11, 0x06)     /* read/write */
 328#define REG_ACR_CTS_2             REG(0x11, 0x07)     /* read/write */
 329#define REG_ACR_N_0               REG(0x11, 0x08)     /* read/write */
 330#define REG_ACR_N_1               REG(0x11, 0x09)     /* read/write */
 331#define REG_ACR_N_2               REG(0x11, 0x0a)     /* read/write */
 332#define REG_CTS_N                 REG(0x11, 0x0c)     /* read/write */
 333# define CTS_N_K(x)               (((x) & 7) << 0)
 334# define CTS_N_M(x)               (((x) & 3) << 4)
 335#define REG_ENC_CNTRL             REG(0x11, 0x0d)     /* read/write */
 336# define ENC_CNTRL_RST_ENC        (1 << 0)
 337# define ENC_CNTRL_RST_SEL        (1 << 1)
 338# define ENC_CNTRL_CTL_CODE(x)    (((x) & 3) << 2)
 339#define REG_DIP_FLAGS             REG(0x11, 0x0e)     /* read/write */
 340# define DIP_FLAGS_ACR            (1 << 0)
 341# define DIP_FLAGS_GC             (1 << 1)
 342#define REG_DIP_IF_FLAGS          REG(0x11, 0x0f)     /* read/write */
 343# define DIP_IF_FLAGS_IF1         (1 << 1)
 344# define DIP_IF_FLAGS_IF2         (1 << 2)
 345# define DIP_IF_FLAGS_IF3         (1 << 3)
 346# define DIP_IF_FLAGS_IF4         (1 << 4)
 347# define DIP_IF_FLAGS_IF5         (1 << 5)
 348#define REG_CH_STAT_B(x)          REG(0x11, 0x14 + (x)) /* read/write */
 349
 350
 351/* Page 12h: HDCP and OTP */
 352#define REG_TX3                   REG(0x12, 0x9a)     /* read/write */
 353#define REG_TX4                   REG(0x12, 0x9b)     /* read/write */
 354# define TX4_PD_RAM               (1 << 1)
 355#define REG_TX33                  REG(0x12, 0xb8)     /* read/write */
 356# define TX33_HDMI                (1 << 1)
 357
 358
 359/* Page 13h: Gamut related metadata packets */
 360
 361
 362
 363/* CEC registers: (not paged)
 364 */
 365#define REG_CEC_INTSTATUS	  0xee		      /* read */
 366# define CEC_INTSTATUS_CEC	  (1 << 0)
 367# define CEC_INTSTATUS_HDMI	  (1 << 1)
 368#define REG_CEC_CAL_XOSC_CTRL1    0xf2
 369# define CEC_CAL_XOSC_CTRL1_ENA_CAL	BIT(0)
 370#define REG_CEC_DES_FREQ2         0xf5
 371# define CEC_DES_FREQ2_DIS_AUTOCAL BIT(7)
 372#define REG_CEC_CLK               0xf6
 373# define CEC_CLK_FRO              0x11
 374#define REG_CEC_FRO_IM_CLK_CTRL   0xfb                /* read/write */
 375# define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
 376# define CEC_FRO_IM_CLK_CTRL_ENA_OTP   (1 << 6)
 377# define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
 378# define CEC_FRO_IM_CLK_CTRL_FRO_DIV   (1 << 0)
 379#define REG_CEC_RXSHPDINTENA	  0xfc		      /* read/write */
 380#define REG_CEC_RXSHPDINT	  0xfd		      /* read */
 381# define CEC_RXSHPDINT_RXSENS     BIT(0)
 382# define CEC_RXSHPDINT_HPD        BIT(1)
 383#define REG_CEC_RXSHPDLEV         0xfe                /* read */
 384# define CEC_RXSHPDLEV_RXSENS     (1 << 0)
 385# define CEC_RXSHPDLEV_HPD        (1 << 1)
 386
 387#define REG_CEC_ENAMODS           0xff                /* read/write */
 388# define CEC_ENAMODS_EN_CEC_CLK   (1 << 7)
 389# define CEC_ENAMODS_DIS_FRO      (1 << 6)
 390# define CEC_ENAMODS_DIS_CCLK     (1 << 5)
 391# define CEC_ENAMODS_EN_RXSENS    (1 << 2)
 392# define CEC_ENAMODS_EN_HDMI      (1 << 1)
 393# define CEC_ENAMODS_EN_CEC       (1 << 0)
 394
 395
 396/* Device versions: */
 397#define TDA9989N2                 0x0101
 398#define TDA19989                  0x0201
 399#define TDA19989N2                0x0202
 400#define TDA19988                  0x0301
 401
 402static void
 403cec_write(struct tda998x_priv *priv, u16 addr, u8 val)
 404{
 405	u8 buf[] = {addr, val};
 406	struct i2c_msg msg = {
 407		.addr = priv->cec_addr,
 408		.len = 2,
 409		.buf = buf,
 410	};
 411	int ret;
 412
 413	ret = i2c_transfer(priv->hdmi->adapter, &msg, 1);
 414	if (ret < 0)
 415		dev_err(&priv->hdmi->dev, "Error %d writing to cec:0x%x\n",
 416			ret, addr);
 417}
 418
 419static u8
 420cec_read(struct tda998x_priv *priv, u8 addr)
 421{
 422	u8 val;
 423	struct i2c_msg msg[2] = {
 424		{
 425			.addr = priv->cec_addr,
 426			.len = 1,
 427			.buf = &addr,
 428		}, {
 429			.addr = priv->cec_addr,
 430			.flags = I2C_M_RD,
 431			.len = 1,
 432			.buf = &val,
 433		},
 434	};
 435	int ret;
 436
 437	ret = i2c_transfer(priv->hdmi->adapter, msg, ARRAY_SIZE(msg));
 438	if (ret < 0) {
 439		dev_err(&priv->hdmi->dev, "Error %d reading from cec:0x%x\n",
 440			ret, addr);
 441		val = 0;
 442	}
 443
 444	return val;
 445}
 446
 447static void cec_enamods(struct tda998x_priv *priv, u8 mods, bool enable)
 448{
 449	int val = cec_read(priv, REG_CEC_ENAMODS);
 450
 451	if (val < 0)
 452		return;
 453
 454	if (enable)
 455		val |= mods;
 456	else
 457		val &= ~mods;
 458
 459	cec_write(priv, REG_CEC_ENAMODS, val);
 460}
 461
 462static void tda998x_cec_set_calibration(struct tda998x_priv *priv, bool enable)
 463{
 464	if (enable) {
 465		u8 val;
 466
 467		cec_write(priv, 0xf3, 0xc0);
 468		cec_write(priv, 0xf4, 0xd4);
 469
 470		/* Enable automatic calibration mode */
 471		val = cec_read(priv, REG_CEC_DES_FREQ2);
 472		val &= ~CEC_DES_FREQ2_DIS_AUTOCAL;
 473		cec_write(priv, REG_CEC_DES_FREQ2, val);
 474
 475		/* Enable free running oscillator */
 476		cec_write(priv, REG_CEC_CLK, CEC_CLK_FRO);
 477		cec_enamods(priv, CEC_ENAMODS_DIS_FRO, false);
 478
 479		cec_write(priv, REG_CEC_CAL_XOSC_CTRL1,
 480			  CEC_CAL_XOSC_CTRL1_ENA_CAL);
 481	} else {
 482		cec_write(priv, REG_CEC_CAL_XOSC_CTRL1, 0);
 483	}
 484}
 485
 486/*
 487 * Calibration for the internal oscillator: we need to set calibration mode,
 488 * and then pulse the IRQ line low for a 10ms ± 1% period.
 489 */
 490static void tda998x_cec_calibration(struct tda998x_priv *priv)
 491{
 492	struct gpio_desc *calib = priv->calib;
 493
 494	mutex_lock(&priv->edid_mutex);
 495	if (priv->hdmi->irq > 0)
 496		disable_irq(priv->hdmi->irq);
 497	gpiod_direction_output(calib, 1);
 498	tda998x_cec_set_calibration(priv, true);
 499
 500	local_irq_disable();
 501	gpiod_set_value(calib, 0);
 502	mdelay(10);
 503	gpiod_set_value(calib, 1);
 504	local_irq_enable();
 505
 506	tda998x_cec_set_calibration(priv, false);
 507	gpiod_direction_input(calib);
 508	if (priv->hdmi->irq > 0)
 509		enable_irq(priv->hdmi->irq);
 510	mutex_unlock(&priv->edid_mutex);
 511}
 512
 513static int tda998x_cec_hook_init(void *data)
 514{
 515	struct tda998x_priv *priv = data;
 516	struct gpio_desc *calib;
 517
 518	calib = gpiod_get(&priv->hdmi->dev, "nxp,calib", GPIOD_ASIS);
 519	if (IS_ERR(calib)) {
 520		dev_warn(&priv->hdmi->dev, "failed to get calibration gpio: %ld\n",
 521			 PTR_ERR(calib));
 522		return PTR_ERR(calib);
 523	}
 524
 525	priv->calib = calib;
 526
 527	return 0;
 528}
 529
 530static void tda998x_cec_hook_exit(void *data)
 531{
 532	struct tda998x_priv *priv = data;
 533
 534	gpiod_put(priv->calib);
 535	priv->calib = NULL;
 536}
 537
 538static int tda998x_cec_hook_open(void *data)
 539{
 540	struct tda998x_priv *priv = data;
 541
 542	cec_enamods(priv, CEC_ENAMODS_EN_CEC_CLK | CEC_ENAMODS_EN_CEC, true);
 543	tda998x_cec_calibration(priv);
 544
 545	return 0;
 546}
 547
 548static void tda998x_cec_hook_release(void *data)
 549{
 550	struct tda998x_priv *priv = data;
 551
 552	cec_enamods(priv, CEC_ENAMODS_EN_CEC_CLK | CEC_ENAMODS_EN_CEC, false);
 553}
 554
 555static int
 556set_page(struct tda998x_priv *priv, u16 reg)
 557{
 558	if (REG2PAGE(reg) != priv->current_page) {
 559		struct i2c_client *client = priv->hdmi;
 560		u8 buf[] = {
 561				REG_CURPAGE, REG2PAGE(reg)
 562		};
 563		int ret = i2c_master_send(client, buf, sizeof(buf));
 564		if (ret < 0) {
 565			dev_err(&client->dev, "%s %04x err %d\n", __func__,
 566					reg, ret);
 567			return ret;
 568		}
 569
 570		priv->current_page = REG2PAGE(reg);
 571	}
 572	return 0;
 573}
 574
 575static int
 576reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt)
 577{
 578	struct i2c_client *client = priv->hdmi;
 579	u8 addr = REG2ADDR(reg);
 580	int ret;
 581
 582	mutex_lock(&priv->mutex);
 583	ret = set_page(priv, reg);
 584	if (ret < 0)
 585		goto out;
 586
 587	ret = i2c_master_send(client, &addr, sizeof(addr));
 588	if (ret < 0)
 589		goto fail;
 590
 591	ret = i2c_master_recv(client, buf, cnt);
 592	if (ret < 0)
 593		goto fail;
 594
 595	goto out;
 596
 597fail:
 598	dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
 599out:
 600	mutex_unlock(&priv->mutex);
 601	return ret;
 602}
 603
 604#define MAX_WRITE_RANGE_BUF 32
 605
 606static void
 607reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt)
 608{
 609	struct i2c_client *client = priv->hdmi;
 610	/* This is the maximum size of the buffer passed in */
 611	u8 buf[MAX_WRITE_RANGE_BUF + 1];
 612	int ret;
 613
 614	if (cnt > MAX_WRITE_RANGE_BUF) {
 615		dev_err(&client->dev, "Fixed write buffer too small (%d)\n",
 616				MAX_WRITE_RANGE_BUF);
 617		return;
 618	}
 619
 620	buf[0] = REG2ADDR(reg);
 621	memcpy(&buf[1], p, cnt);
 622
 623	mutex_lock(&priv->mutex);
 624	ret = set_page(priv, reg);
 625	if (ret < 0)
 626		goto out;
 627
 628	ret = i2c_master_send(client, buf, cnt + 1);
 629	if (ret < 0)
 630		dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 631out:
 632	mutex_unlock(&priv->mutex);
 633}
 634
 635static int
 636reg_read(struct tda998x_priv *priv, u16 reg)
 637{
 638	u8 val = 0;
 639	int ret;
 640
 641	ret = reg_read_range(priv, reg, &val, sizeof(val));
 642	if (ret < 0)
 643		return ret;
 644	return val;
 645}
 646
 647static void
 648reg_write(struct tda998x_priv *priv, u16 reg, u8 val)
 649{
 650	struct i2c_client *client = priv->hdmi;
 651	u8 buf[] = {REG2ADDR(reg), val};
 652	int ret;
 653
 654	mutex_lock(&priv->mutex);
 655	ret = set_page(priv, reg);
 656	if (ret < 0)
 657		goto out;
 658
 659	ret = i2c_master_send(client, buf, sizeof(buf));
 660	if (ret < 0)
 661		dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 662out:
 663	mutex_unlock(&priv->mutex);
 664}
 665
 666static void
 667reg_write16(struct tda998x_priv *priv, u16 reg, u16 val)
 668{
 669	struct i2c_client *client = priv->hdmi;
 670	u8 buf[] = {REG2ADDR(reg), val >> 8, val};
 671	int ret;
 672
 673	mutex_lock(&priv->mutex);
 674	ret = set_page(priv, reg);
 675	if (ret < 0)
 676		goto out;
 677
 678	ret = i2c_master_send(client, buf, sizeof(buf));
 679	if (ret < 0)
 680		dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 681out:
 682	mutex_unlock(&priv->mutex);
 683}
 684
 685static void
 686reg_set(struct tda998x_priv *priv, u16 reg, u8 val)
 687{
 688	int old_val;
 689
 690	old_val = reg_read(priv, reg);
 691	if (old_val >= 0)
 692		reg_write(priv, reg, old_val | val);
 693}
 694
 695static void
 696reg_clear(struct tda998x_priv *priv, u16 reg, u8 val)
 697{
 698	int old_val;
 699
 700	old_val = reg_read(priv, reg);
 701	if (old_val >= 0)
 702		reg_write(priv, reg, old_val & ~val);
 703}
 704
 705static void
 706tda998x_reset(struct tda998x_priv *priv)
 707{
 708	/* reset audio and i2c master: */
 709	reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
 710	msleep(50);
 711	reg_write(priv, REG_SOFTRESET, 0);
 712	msleep(50);
 713
 714	/* reset transmitter: */
 715	reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
 716	reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
 717
 718	/* PLL registers common configuration */
 719	reg_write(priv, REG_PLL_SERIAL_1, 0x00);
 720	reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
 721	reg_write(priv, REG_PLL_SERIAL_3, 0x00);
 722	reg_write(priv, REG_SERIALIZER,   0x00);
 723	reg_write(priv, REG_BUFFER_OUT,   0x00);
 724	reg_write(priv, REG_PLL_SCG1,     0x00);
 725	reg_write(priv, REG_AUDIO_DIV,    AUDIO_DIV_SERCLK_8);
 726	reg_write(priv, REG_SEL_CLK,      SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
 727	reg_write(priv, REG_PLL_SCGN1,    0xfa);
 728	reg_write(priv, REG_PLL_SCGN2,    0x00);
 729	reg_write(priv, REG_PLL_SCGR1,    0x5b);
 730	reg_write(priv, REG_PLL_SCGR2,    0x00);
 731	reg_write(priv, REG_PLL_SCG2,     0x10);
 732
 733	/* Write the default value MUX register */
 734	reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
 735}
 736
 737/*
 738 * The TDA998x has a problem when trying to read the EDID close to a
 739 * HPD assertion: it needs a delay of 100ms to avoid timing out while
 740 * trying to read EDID data.
 741 *
 742 * However, tda998x_connector_get_modes() may be called at any moment
 743 * after tda998x_connector_detect() indicates that we are connected, so
 744 * we need to delay probing modes in tda998x_connector_get_modes() after
 745 * we have seen a HPD inactive->active transition.  This code implements
 746 * that delay.
 747 */
 748static void tda998x_edid_delay_done(struct timer_list *t)
 749{
 750	struct tda998x_priv *priv = from_timer(priv, t, edid_delay_timer);
 751
 752	priv->edid_delay_active = false;
 753	wake_up(&priv->edid_delay_waitq);
 754	schedule_work(&priv->detect_work);
 755}
 756
 757static void tda998x_edid_delay_start(struct tda998x_priv *priv)
 758{
 759	priv->edid_delay_active = true;
 760	mod_timer(&priv->edid_delay_timer, jiffies + HZ/10);
 761}
 762
 763static int tda998x_edid_delay_wait(struct tda998x_priv *priv)
 764{
 765	return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active);
 766}
 767
 768/*
 769 * We need to run the KMS hotplug event helper outside of our threaded
 770 * interrupt routine as this can call back into our get_modes method,
 771 * which will want to make use of interrupts.
 772 */
 773static void tda998x_detect_work(struct work_struct *work)
 774{
 775	struct tda998x_priv *priv =
 776		container_of(work, struct tda998x_priv, detect_work);
 777	struct drm_device *dev = priv->connector.dev;
 778
 779	if (dev)
 780		drm_kms_helper_hotplug_event(dev);
 781}
 782
 783/*
 784 * only 2 interrupts may occur: screen plug/unplug and EDID read
 785 */
 786static irqreturn_t tda998x_irq_thread(int irq, void *data)
 787{
 788	struct tda998x_priv *priv = data;
 789	u8 sta, cec, lvl, flag0, flag1, flag2;
 790	bool handled = false;
 791
 792	sta = cec_read(priv, REG_CEC_INTSTATUS);
 793	if (sta & CEC_INTSTATUS_HDMI) {
 794		cec = cec_read(priv, REG_CEC_RXSHPDINT);
 795		lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
 796		flag0 = reg_read(priv, REG_INT_FLAGS_0);
 797		flag1 = reg_read(priv, REG_INT_FLAGS_1);
 798		flag2 = reg_read(priv, REG_INT_FLAGS_2);
 799		DRM_DEBUG_DRIVER(
 800			"tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
 801			sta, cec, lvl, flag0, flag1, flag2);
 802
 803		if (cec & CEC_RXSHPDINT_HPD) {
 804			if (lvl & CEC_RXSHPDLEV_HPD) {
 805				tda998x_edid_delay_start(priv);
 806			} else {
 807				schedule_work(&priv->detect_work);
 808				cec_notifier_set_phys_addr(priv->cec_notify,
 809						   CEC_PHYS_ADDR_INVALID);
 810			}
 811
 812			handled = true;
 813		}
 814
 815		if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
 816			priv->wq_edid_wait = 0;
 817			wake_up(&priv->wq_edid);
 818			handled = true;
 819		}
 820	}
 821
 822	return IRQ_RETVAL(handled);
 823}
 824
 825static void
 826tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr,
 827		 union hdmi_infoframe *frame)
 828{
 829	u8 buf[MAX_WRITE_RANGE_BUF];
 830	ssize_t len;
 831
 832	len = hdmi_infoframe_pack(frame, buf, sizeof(buf));
 833	if (len < 0) {
 834		dev_err(&priv->hdmi->dev,
 835			"hdmi_infoframe_pack() type=0x%02x failed: %zd\n",
 836			frame->any.type, len);
 837		return;
 838	}
 839
 840	reg_clear(priv, REG_DIP_IF_FLAGS, bit);
 841	reg_write_range(priv, addr, buf, len);
 842	reg_set(priv, REG_DIP_IF_FLAGS, bit);
 843}
 844
 845static void tda998x_write_aif(struct tda998x_priv *priv,
 846			      const struct hdmi_audio_infoframe *cea)
 847{
 848	union hdmi_infoframe frame;
 849
 850	frame.audio = *cea;
 851
 852	tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame);
 853}
 854
 855static void
 856tda998x_write_avi(struct tda998x_priv *priv, const struct drm_display_mode *mode)
 857{
 858	union hdmi_infoframe frame;
 859
 860	drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 861						 &priv->connector, mode);
 862	frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;
 863	drm_hdmi_avi_infoframe_quant_range(&frame.avi, &priv->connector, mode,
 864					   priv->rgb_quant_range);
 865
 866	tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame);
 867}
 868
 869static void tda998x_write_vsi(struct tda998x_priv *priv,
 870			      const struct drm_display_mode *mode)
 871{
 872	union hdmi_infoframe frame;
 873
 874	if (drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 875							&priv->connector,
 876							mode))
 877		reg_clear(priv, REG_DIP_IF_FLAGS, DIP_IF_FLAGS_IF1);
 878	else
 879		tda998x_write_if(priv, DIP_IF_FLAGS_IF1, REG_IF1_HB0, &frame);
 880}
 881
 882/* Audio support */
 883
 884static const struct tda998x_audio_route tda998x_audio_route[AUDIO_ROUTE_NUM] = {
 885	[AUDIO_ROUTE_I2S] = {
 886		.ena_aclk = 1,
 887		.mux_ap = MUX_AP_SELECT_I2S,
 888		.aip_clksel = AIP_CLKSEL_AIP_I2S | AIP_CLKSEL_FS_ACLK,
 889	},
 890	[AUDIO_ROUTE_SPDIF] = {
 891		.ena_aclk = 0,
 892		.mux_ap = MUX_AP_SELECT_SPDIF,
 893		.aip_clksel = AIP_CLKSEL_AIP_SPDIF | AIP_CLKSEL_FS_FS64SPDIF,
 894	},
 895};
 896
 897/* Configure the TDA998x audio data and clock routing. */
 898static int tda998x_derive_routing(struct tda998x_priv *priv,
 899				  struct tda998x_audio_settings *s,
 900				  unsigned int route)
 901{
 902	s->route = &tda998x_audio_route[route];
 903	s->ena_ap = priv->audio_port_enable[route];
 904	if (s->ena_ap == 0) {
 905		dev_err(&priv->hdmi->dev, "no audio configuration found\n");
 906		return -EINVAL;
 907	}
 908
 909	return 0;
 910}
 911
 912/*
 913 * The audio clock divisor register controls a divider producing Audio_Clk_Out
 914 * from SERclk by dividing it by 2^n where 0 <= n <= 5.  We don't know what
 915 * Audio_Clk_Out or SERclk are. We guess SERclk is the same as TMDS clock.
 916 *
 917 * It seems that Audio_Clk_Out must be the smallest value that is greater
 918 * than 128*fs, otherwise audio does not function. There is some suggestion
 919 * that 126*fs is a better value.
 920 */
 921static u8 tda998x_get_adiv(struct tda998x_priv *priv, unsigned int fs)
 922{
 923	unsigned long min_audio_clk = fs * 128;
 924	unsigned long ser_clk = priv->tmds_clock * 1000;
 925	u8 adiv;
 926
 927	for (adiv = AUDIO_DIV_SERCLK_32; adiv != AUDIO_DIV_SERCLK_1; adiv--)
 928		if (ser_clk > min_audio_clk << adiv)
 929			break;
 930
 931	dev_dbg(&priv->hdmi->dev,
 932		"ser_clk=%luHz fs=%uHz min_aclk=%luHz adiv=%d\n",
 933		ser_clk, fs, min_audio_clk, adiv);
 934
 935	return adiv;
 936}
 937
 938/*
 939 * In auto-CTS mode, the TDA998x uses a "measured time stamp" counter to
 940 * generate the CTS value.  It appears that the "measured time stamp" is
 941 * the number of TDMS clock cycles within a number of audio input clock
 942 * cycles defined by the k and N parameters defined below, in a similar
 943 * way to that which is set out in the CTS generation in the HDMI spec.
 944 *
 945 *  tmdsclk ----> mts -> /m ---> CTS
 946 *                 ^
 947 *  sclk -> /k -> /N
 948 *
 949 * CTS = mts / m, where m is 2^M.
 950 * /k is a divider based on the K value below, K+1 for K < 4, or 8 for K >= 4
 951 * /N is a divider based on the HDMI specified N value.
 952 *
 953 * This produces the following equation:
 954 *  CTS = tmds_clock * k * N / (sclk * m)
 955 *
 956 * When combined with the sink-side equation, and realising that sclk is
 957 * bclk_ratio * fs, we end up with:
 958 *  k = m * bclk_ratio / 128.
 959 *
 960 * Note: S/PDIF always uses a bclk_ratio of 64.
 961 */
 962static int tda998x_derive_cts_n(struct tda998x_priv *priv,
 963				struct tda998x_audio_settings *settings,
 964				unsigned int ratio)
 965{
 966	switch (ratio) {
 967	case 16:
 968		settings->cts_n = CTS_N_M(3) | CTS_N_K(0);
 969		break;
 970	case 32:
 971		settings->cts_n = CTS_N_M(3) | CTS_N_K(1);
 972		break;
 973	case 48:
 974		settings->cts_n = CTS_N_M(3) | CTS_N_K(2);
 975		break;
 976	case 64:
 977		settings->cts_n = CTS_N_M(3) | CTS_N_K(3);
 978		break;
 979	case 128:
 980		settings->cts_n = CTS_N_M(0) | CTS_N_K(0);
 981		break;
 982	default:
 983		dev_err(&priv->hdmi->dev, "unsupported bclk ratio %ufs\n",
 984			ratio);
 985		return -EINVAL;
 986	}
 987	return 0;
 988}
 989
 990static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
 991{
 992	if (on) {
 993		reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
 994		reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
 995		reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
 996	} else {
 997		reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
 998	}
 999}
1000
1001static void tda998x_configure_audio(struct tda998x_priv *priv)
1002{
1003	const struct tda998x_audio_settings *settings = &priv->audio;
1004	u8 buf[6], adiv;
1005	u32 n;
1006
1007	/* If audio is not configured, there is nothing to do. */
1008	if (settings->ena_ap == 0)
1009		return;
1010
1011	adiv = tda998x_get_adiv(priv, settings->sample_rate);
1012
1013	/* Enable audio ports */
1014	reg_write(priv, REG_ENA_AP, settings->ena_ap);
1015	reg_write(priv, REG_ENA_ACLK, settings->route->ena_aclk);
1016	reg_write(priv, REG_MUX_AP, settings->route->mux_ap);
1017	reg_write(priv, REG_I2S_FORMAT, settings->i2s_format);
1018	reg_write(priv, REG_AIP_CLKSEL, settings->route->aip_clksel);
1019	reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
1020					AIP_CNTRL_0_ACR_MAN);	/* auto CTS */
1021	reg_write(priv, REG_CTS_N, settings->cts_n);
1022	reg_write(priv, REG_AUDIO_DIV, adiv);
1023
1024	/*
1025	 * This is the approximate value of N, which happens to be
1026	 * the recommended values for non-coherent clocks.
1027	 */
1028	n = 128 * settings->sample_rate / 1000;
1029
1030	/* Write the CTS and N values */
1031	buf[0] = 0x44;
1032	buf[1] = 0x42;
1033	buf[2] = 0x01;
1034	buf[3] = n;
1035	buf[4] = n >> 8;
1036	buf[5] = n >> 16;
1037	reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
1038
1039	/* Reset CTS generator */
1040	reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
1041	reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
1042
1043	/* Write the channel status
1044	 * The REG_CH_STAT_B-registers skip IEC958 AES2 byte, because
1045	 * there is a separate register for each I2S wire.
1046	 */
1047	buf[0] = settings->status[0];
1048	buf[1] = settings->status[1];
1049	buf[2] = settings->status[3];
1050	buf[3] = settings->status[4];
1051	reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
1052
1053	tda998x_audio_mute(priv, true);
1054	msleep(20);
1055	tda998x_audio_mute(priv, false);
1056
1057	tda998x_write_aif(priv, &settings->cea);
1058}
1059
1060static int tda998x_audio_hw_params(struct device *dev, void *data,
1061				   struct hdmi_codec_daifmt *daifmt,
1062				   struct hdmi_codec_params *params)
1063{
1064	struct tda998x_priv *priv = dev_get_drvdata(dev);
1065	unsigned int bclk_ratio;
1066	bool spdif = daifmt->fmt == HDMI_SPDIF;
1067	int ret;
1068	struct tda998x_audio_settings audio = {
1069		.sample_rate = params->sample_rate,
1070		.cea = params->cea,
1071	};
1072
1073	memcpy(audio.status, params->iec.status,
1074	       min(sizeof(audio.status), sizeof(params->iec.status)));
1075
1076	switch (daifmt->fmt) {
1077	case HDMI_I2S:
1078		audio.i2s_format = I2S_FORMAT_PHILIPS;
1079		break;
1080	case HDMI_LEFT_J:
1081		audio.i2s_format = I2S_FORMAT_LEFT_J;
1082		break;
1083	case HDMI_RIGHT_J:
1084		audio.i2s_format = I2S_FORMAT_RIGHT_J;
1085		break;
1086	case HDMI_SPDIF:
1087		audio.i2s_format = 0;
1088		break;
1089	default:
1090		dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt);
1091		return -EINVAL;
1092	}
1093
1094	if (!spdif &&
1095	    (daifmt->bit_clk_inv || daifmt->frame_clk_inv ||
1096	     daifmt->bit_clk_master || daifmt->frame_clk_master)) {
1097		dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__,
1098			daifmt->bit_clk_inv, daifmt->frame_clk_inv,
1099			daifmt->bit_clk_master,
1100			daifmt->frame_clk_master);
1101		return -EINVAL;
1102	}
1103
1104	ret = tda998x_derive_routing(priv, &audio, AUDIO_ROUTE_I2S + spdif);
1105	if (ret < 0)
1106		return ret;
1107
1108	bclk_ratio = spdif ? 64 : params->sample_width * 2;
1109	ret = tda998x_derive_cts_n(priv, &audio, bclk_ratio);
1110	if (ret < 0)
1111		return ret;
1112
1113	mutex_lock(&priv->audio_mutex);
1114	priv->audio = audio;
1115	if (priv->supports_infoframes && priv->sink_has_audio)
1116		tda998x_configure_audio(priv);
1117	mutex_unlock(&priv->audio_mutex);
1118
1119	return 0;
1120}
1121
1122static void tda998x_audio_shutdown(struct device *dev, void *data)
1123{
1124	struct tda998x_priv *priv = dev_get_drvdata(dev);
1125
1126	mutex_lock(&priv->audio_mutex);
1127
1128	reg_write(priv, REG_ENA_AP, 0);
1129	priv->audio.ena_ap = 0;
1130
1131	mutex_unlock(&priv->audio_mutex);
1132}
1133
1134int tda998x_audio_digital_mute(struct device *dev, void *data, bool enable)
 
1135{
1136	struct tda998x_priv *priv = dev_get_drvdata(dev);
1137
1138	mutex_lock(&priv->audio_mutex);
1139
1140	tda998x_audio_mute(priv, enable);
1141
1142	mutex_unlock(&priv->audio_mutex);
1143	return 0;
1144}
1145
1146static int tda998x_audio_get_eld(struct device *dev, void *data,
1147				 uint8_t *buf, size_t len)
1148{
1149	struct tda998x_priv *priv = dev_get_drvdata(dev);
1150
1151	mutex_lock(&priv->audio_mutex);
1152	memcpy(buf, priv->connector.eld,
1153	       min(sizeof(priv->connector.eld), len));
1154	mutex_unlock(&priv->audio_mutex);
1155
1156	return 0;
1157}
1158
1159static const struct hdmi_codec_ops audio_codec_ops = {
1160	.hw_params = tda998x_audio_hw_params,
1161	.audio_shutdown = tda998x_audio_shutdown,
1162	.digital_mute = tda998x_audio_digital_mute,
1163	.get_eld = tda998x_audio_get_eld,
 
1164};
1165
1166static int tda998x_audio_codec_init(struct tda998x_priv *priv,
1167				    struct device *dev)
1168{
1169	struct hdmi_codec_pdata codec_data = {
1170		.ops = &audio_codec_ops,
1171		.max_i2s_channels = 2,
 
 
1172	};
1173
1174	if (priv->audio_port_enable[AUDIO_ROUTE_I2S])
1175		codec_data.i2s = 1;
1176	if (priv->audio_port_enable[AUDIO_ROUTE_SPDIF])
1177		codec_data.spdif = 1;
1178
1179	priv->audio_pdev = platform_device_register_data(
1180		dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
1181		&codec_data, sizeof(codec_data));
1182
1183	return PTR_ERR_OR_ZERO(priv->audio_pdev);
1184}
1185
1186/* DRM connector functions */
1187
1188static enum drm_connector_status
1189tda998x_connector_detect(struct drm_connector *connector, bool force)
1190{
1191	struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1192	u8 val = cec_read(priv, REG_CEC_RXSHPDLEV);
1193
1194	return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
1195			connector_status_disconnected;
1196}
1197
1198static void tda998x_connector_destroy(struct drm_connector *connector)
1199{
1200	drm_connector_cleanup(connector);
1201}
1202
1203static const struct drm_connector_funcs tda998x_connector_funcs = {
1204	.reset = drm_atomic_helper_connector_reset,
1205	.fill_modes = drm_helper_probe_single_connector_modes,
1206	.detect = tda998x_connector_detect,
1207	.destroy = tda998x_connector_destroy,
1208	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1209	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1210};
1211
1212static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length)
1213{
1214	struct tda998x_priv *priv = data;
1215	u8 offset, segptr;
1216	int ret, i;
1217
1218	offset = (blk & 1) ? 128 : 0;
1219	segptr = blk / 2;
1220
1221	mutex_lock(&priv->edid_mutex);
1222
1223	reg_write(priv, REG_DDC_ADDR, 0xa0);
1224	reg_write(priv, REG_DDC_OFFS, offset);
1225	reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1226	reg_write(priv, REG_DDC_SEGM, segptr);
1227
1228	/* enable reading EDID: */
1229	priv->wq_edid_wait = 1;
1230	reg_write(priv, REG_EDID_CTRL, 0x1);
1231
1232	/* flag must be cleared by sw: */
1233	reg_write(priv, REG_EDID_CTRL, 0x0);
1234
1235	/* wait for block read to complete: */
1236	if (priv->hdmi->irq) {
1237		i = wait_event_timeout(priv->wq_edid,
1238					!priv->wq_edid_wait,
1239					msecs_to_jiffies(100));
1240		if (i < 0) {
1241			dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
1242			ret = i;
1243			goto failed;
1244		}
1245	} else {
1246		for (i = 100; i > 0; i--) {
1247			msleep(1);
1248			ret = reg_read(priv, REG_INT_FLAGS_2);
1249			if (ret < 0)
1250				goto failed;
1251			if (ret & INT_FLAGS_2_EDID_BLK_RD)
1252				break;
1253		}
1254	}
1255
1256	if (i == 0) {
1257		dev_err(&priv->hdmi->dev, "read edid timeout\n");
1258		ret = -ETIMEDOUT;
1259		goto failed;
1260	}
1261
1262	ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length);
1263	if (ret != length) {
1264		dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1265			blk, ret);
1266		goto failed;
1267	}
1268
1269	ret = 0;
1270
1271 failed:
1272	mutex_unlock(&priv->edid_mutex);
1273	return ret;
1274}
1275
1276static int tda998x_connector_get_modes(struct drm_connector *connector)
1277{
1278	struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1279	struct edid *edid;
1280	int n;
1281
1282	/*
1283	 * If we get killed while waiting for the HPD timeout, return
1284	 * no modes found: we are not in a restartable path, so we
1285	 * can't handle signals gracefully.
1286	 */
1287	if (tda998x_edid_delay_wait(priv))
1288		return 0;
1289
1290	if (priv->rev == TDA19988)
1291		reg_clear(priv, REG_TX4, TX4_PD_RAM);
1292
1293	edid = drm_do_get_edid(connector, read_edid_block, priv);
1294
1295	if (priv->rev == TDA19988)
1296		reg_set(priv, REG_TX4, TX4_PD_RAM);
1297
1298	if (!edid) {
1299		dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
1300		return 0;
1301	}
1302
1303	drm_connector_update_edid_property(connector, edid);
1304	cec_notifier_set_phys_addr_from_edid(priv->cec_notify, edid);
1305
1306	mutex_lock(&priv->audio_mutex);
1307	n = drm_add_edid_modes(connector, edid);
1308	priv->sink_has_audio = drm_detect_monitor_audio(edid);
1309	mutex_unlock(&priv->audio_mutex);
1310
1311	kfree(edid);
1312
1313	return n;
1314}
1315
1316static struct drm_encoder *
1317tda998x_connector_best_encoder(struct drm_connector *connector)
1318{
1319	struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1320
1321	return priv->bridge.encoder;
1322}
1323
1324static
1325const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = {
1326	.get_modes = tda998x_connector_get_modes,
1327	.best_encoder = tda998x_connector_best_encoder,
1328};
1329
1330static int tda998x_connector_init(struct tda998x_priv *priv,
1331				  struct drm_device *drm)
1332{
1333	struct drm_connector *connector = &priv->connector;
1334	int ret;
1335
1336	connector->interlace_allowed = 1;
1337
1338	if (priv->hdmi->irq)
1339		connector->polled = DRM_CONNECTOR_POLL_HPD;
1340	else
1341		connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1342			DRM_CONNECTOR_POLL_DISCONNECT;
1343
1344	drm_connector_helper_add(connector, &tda998x_connector_helper_funcs);
1345	ret = drm_connector_init(drm, connector, &tda998x_connector_funcs,
1346				 DRM_MODE_CONNECTOR_HDMIA);
1347	if (ret)
1348		return ret;
1349
1350	drm_connector_attach_encoder(&priv->connector,
1351				     priv->bridge.encoder);
1352
1353	return 0;
1354}
1355
1356/* DRM bridge functions */
1357
1358static int tda998x_bridge_attach(struct drm_bridge *bridge)
 
1359{
1360	struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1361
 
 
 
 
 
1362	return tda998x_connector_init(priv, bridge->dev);
1363}
1364
1365static void tda998x_bridge_detach(struct drm_bridge *bridge)
1366{
1367	struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1368
1369	drm_connector_cleanup(&priv->connector);
1370}
1371
1372static enum drm_mode_status tda998x_bridge_mode_valid(struct drm_bridge *bridge,
 
1373				     const struct drm_display_mode *mode)
1374{
1375	/* TDA19988 dotclock can go up to 165MHz */
1376	struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1377
1378	if (mode->clock > ((priv->rev == TDA19988) ? 165000 : 150000))
1379		return MODE_CLOCK_HIGH;
1380	if (mode->htotal >= BIT(13))
1381		return MODE_BAD_HVALUE;
1382	if (mode->vtotal >= BIT(11))
1383		return MODE_BAD_VVALUE;
1384	return MODE_OK;
1385}
1386
1387static void tda998x_bridge_enable(struct drm_bridge *bridge)
1388{
1389	struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1390
1391	if (!priv->is_on) {
1392		/* enable video ports, audio will be enabled later */
1393		reg_write(priv, REG_ENA_VP_0, 0xff);
1394		reg_write(priv, REG_ENA_VP_1, 0xff);
1395		reg_write(priv, REG_ENA_VP_2, 0xff);
1396		/* set muxing after enabling ports: */
1397		reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
1398		reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
1399		reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
1400
1401		priv->is_on = true;
1402	}
1403}
1404
1405static void tda998x_bridge_disable(struct drm_bridge *bridge)
1406{
1407	struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1408
1409	if (priv->is_on) {
1410		/* disable video ports */
1411		reg_write(priv, REG_ENA_VP_0, 0x00);
1412		reg_write(priv, REG_ENA_VP_1, 0x00);
1413		reg_write(priv, REG_ENA_VP_2, 0x00);
1414
1415		priv->is_on = false;
1416	}
1417}
1418
1419static void tda998x_bridge_mode_set(struct drm_bridge *bridge,
1420				    const struct drm_display_mode *mode,
1421				    const struct drm_display_mode *adjusted_mode)
1422{
1423	struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1424	unsigned long tmds_clock;
1425	u16 ref_pix, ref_line, n_pix, n_line;
1426	u16 hs_pix_s, hs_pix_e;
1427	u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
1428	u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
1429	u16 vwin1_line_s, vwin1_line_e;
1430	u16 vwin2_line_s, vwin2_line_e;
1431	u16 de_pix_s, de_pix_e;
1432	u8 reg, div, rep, sel_clk;
1433
1434	/*
1435	 * Since we are "computer" like, our source invariably produces
1436	 * full-range RGB.  If the monitor supports full-range, then use
1437	 * it, otherwise reduce to limited-range.
1438	 */
1439	priv->rgb_quant_range =
1440		priv->connector.display_info.rgb_quant_range_selectable ?
1441		HDMI_QUANTIZATION_RANGE_FULL :
1442		drm_default_rgb_quant_range(adjusted_mode);
1443
1444	/*
1445	 * Internally TDA998x is using ITU-R BT.656 style sync but
1446	 * we get VESA style sync. TDA998x is using a reference pixel
1447	 * relative to ITU to sync to the input frame and for output
1448	 * sync generation. Currently, we are using reference detection
1449	 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
1450	 * which is position of rising VS with coincident rising HS.
1451	 *
1452	 * Now there is some issues to take care of:
1453	 * - HDMI data islands require sync-before-active
1454	 * - TDA998x register values must be > 0 to be enabled
1455	 * - REFLINE needs an additional offset of +1
1456	 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
1457	 *
1458	 * So we add +1 to all horizontal and vertical register values,
1459	 * plus an additional +3 for REFPIX as we are using RGB input only.
1460	 */
1461	n_pix        = mode->htotal;
1462	n_line       = mode->vtotal;
1463
1464	hs_pix_e     = mode->hsync_end - mode->hdisplay;
1465	hs_pix_s     = mode->hsync_start - mode->hdisplay;
1466	de_pix_e     = mode->htotal;
1467	de_pix_s     = mode->htotal - mode->hdisplay;
1468	ref_pix      = 3 + hs_pix_s;
1469
1470	/*
1471	 * Attached LCD controllers may generate broken sync. Allow
1472	 * those to adjust the position of the rising VS edge by adding
1473	 * HSKEW to ref_pix.
1474	 */
1475	if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
1476		ref_pix += adjusted_mode->hskew;
1477
1478	if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
1479		ref_line     = 1 + mode->vsync_start - mode->vdisplay;
1480		vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
1481		vwin1_line_e = vwin1_line_s + mode->vdisplay;
1482		vs1_pix_s    = vs1_pix_e = hs_pix_s;
1483		vs1_line_s   = mode->vsync_start - mode->vdisplay;
1484		vs1_line_e   = vs1_line_s +
1485			       mode->vsync_end - mode->vsync_start;
1486		vwin2_line_s = vwin2_line_e = 0;
1487		vs2_pix_s    = vs2_pix_e  = 0;
1488		vs2_line_s   = vs2_line_e = 0;
1489	} else {
1490		ref_line     = 1 + (mode->vsync_start - mode->vdisplay)/2;
1491		vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
1492		vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
1493		vs1_pix_s    = vs1_pix_e = hs_pix_s;
1494		vs1_line_s   = (mode->vsync_start - mode->vdisplay)/2;
1495		vs1_line_e   = vs1_line_s +
1496			       (mode->vsync_end - mode->vsync_start)/2;
1497		vwin2_line_s = vwin1_line_s + mode->vtotal/2;
1498		vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
1499		vs2_pix_s    = vs2_pix_e = hs_pix_s + mode->htotal/2;
1500		vs2_line_s   = vs1_line_s + mode->vtotal/2 ;
1501		vs2_line_e   = vs2_line_s +
1502			       (mode->vsync_end - mode->vsync_start)/2;
1503	}
1504
1505	/*
1506	 * Select pixel repeat depending on the double-clock flag
1507	 * (which means we have to repeat each pixel once.)
1508	 */
1509	rep = mode->flags & DRM_MODE_FLAG_DBLCLK ? 1 : 0;
1510	sel_clk = SEL_CLK_ENA_SC_CLK | SEL_CLK_SEL_CLK1 |
1511		  SEL_CLK_SEL_VRF_CLK(rep ? 2 : 0);
1512
1513	/* the TMDS clock is scaled up by the pixel repeat */
1514	tmds_clock = mode->clock * (1 + rep);
1515
1516	/*
1517	 * The divisor is power-of-2. The TDA9983B datasheet gives
1518	 * this as ranges of Msample/s, which is 10x the TMDS clock:
1519	 *   0 - 800 to 1500 Msample/s
1520	 *   1 - 400 to 800 Msample/s
1521	 *   2 - 200 to 400 Msample/s
1522	 *   3 - as 2 above
1523	 */
1524	for (div = 0; div < 3; div++)
1525		if (80000 >> div <= tmds_clock)
1526			break;
1527
1528	mutex_lock(&priv->audio_mutex);
1529
1530	priv->tmds_clock = tmds_clock;
1531
1532	/* mute the audio FIFO: */
1533	reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
1534
1535	/* set HDMI HDCP mode off: */
1536	reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
1537	reg_clear(priv, REG_TX33, TX33_HDMI);
1538	reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
1539
1540	/* no pre-filter or interpolator: */
1541	reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
1542			HVF_CNTRL_0_INTPOL(0));
1543	reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_PREFILT);
1544	reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
1545	reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
1546			VIP_CNTRL_4_BLC(0));
1547
1548	reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
1549	reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
1550					  PLL_SERIAL_3_SRL_DE);
1551	reg_write(priv, REG_SERIALIZER, 0);
1552	reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
1553
1554	reg_write(priv, REG_RPT_CNTRL, RPT_CNTRL_REPEAT(rep));
1555	reg_write(priv, REG_SEL_CLK, sel_clk);
1556	reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
1557			PLL_SERIAL_2_SRL_PR(rep));
1558
1559	/* set color matrix according to output rgb quant range */
1560	if (priv->rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) {
1561		static u8 tda998x_full_to_limited_range[] = {
1562			MAT_CONTRL_MAT_SC(2),
1563			0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1564			0x03, 0x6f, 0x00, 0x00, 0x00, 0x00,
1565			0x00, 0x00, 0x03, 0x6f, 0x00, 0x00,
1566			0x00, 0x00, 0x00, 0x00, 0x03, 0x6f,
1567			0x00, 0x40, 0x00, 0x40, 0x00, 0x40
1568		};
1569		reg_clear(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC);
1570		reg_write_range(priv, REG_MAT_CONTRL,
1571				tda998x_full_to_limited_range,
1572				sizeof(tda998x_full_to_limited_range));
1573	} else {
1574		reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
1575					MAT_CONTRL_MAT_SC(1));
1576		reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC);
1577	}
1578
1579	/* set BIAS tmds value: */
1580	reg_write(priv, REG_ANA_GENERAL, 0x09);
1581
1582	/*
1583	 * Sync on rising HSYNC/VSYNC
1584	 */
1585	reg = VIP_CNTRL_3_SYNC_HS;
1586
1587	/*
1588	 * TDA19988 requires high-active sync at input stage,
1589	 * so invert low-active sync provided by master encoder here
1590	 */
1591	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1592		reg |= VIP_CNTRL_3_H_TGL;
1593	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1594		reg |= VIP_CNTRL_3_V_TGL;
1595	reg_write(priv, REG_VIP_CNTRL_3, reg);
1596
1597	reg_write(priv, REG_VIDFORMAT, 0x00);
1598	reg_write16(priv, REG_REFPIX_MSB, ref_pix);
1599	reg_write16(priv, REG_REFLINE_MSB, ref_line);
1600	reg_write16(priv, REG_NPIX_MSB, n_pix);
1601	reg_write16(priv, REG_NLINE_MSB, n_line);
1602	reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
1603	reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
1604	reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
1605	reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
1606	reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
1607	reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
1608	reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
1609	reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
1610	reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
1611	reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
1612	reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
1613	reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
1614	reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
1615	reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
1616	reg_write16(priv, REG_DE_START_MSB, de_pix_s);
1617	reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
1618
1619	if (priv->rev == TDA19988) {
1620		/* let incoming pixels fill the active space (if any) */
1621		reg_write(priv, REG_ENABLE_SPACE, 0x00);
1622	}
1623
1624	/*
1625	 * Always generate sync polarity relative to input sync and
1626	 * revert input stage toggled sync at output stage
1627	 */
1628	reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
1629	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1630		reg |= TBG_CNTRL_1_H_TGL;
1631	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1632		reg |= TBG_CNTRL_1_V_TGL;
1633	reg_write(priv, REG_TBG_CNTRL_1, reg);
1634
1635	/* must be last register set: */
1636	reg_write(priv, REG_TBG_CNTRL_0, 0);
1637
1638	/* CEA-861B section 6 says that:
1639	 * CEA version 1 (CEA-861) has no support for infoframes.
1640	 * CEA version 2 (CEA-861A) supports version 1 AVI infoframes,
1641	 * and optional basic audio.
1642	 * CEA version 3 (CEA-861B) supports version 1 and 2 AVI infoframes,
1643	 * and optional digital audio, with audio infoframes.
1644	 *
1645	 * Since we only support generation of version 2 AVI infoframes,
1646	 * ignore CEA version 2 and below (iow, behave as if we're a
1647	 * CEA-861 source.)
1648	 */
1649	priv->supports_infoframes = priv->connector.display_info.cea_rev >= 3;
1650
1651	if (priv->supports_infoframes) {
1652		/* We need to turn HDMI HDCP stuff on to get audio through */
1653		reg &= ~TBG_CNTRL_1_DWIN_DIS;
1654		reg_write(priv, REG_TBG_CNTRL_1, reg);
1655		reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
1656		reg_set(priv, REG_TX33, TX33_HDMI);
1657
1658		tda998x_write_avi(priv, adjusted_mode);
1659		tda998x_write_vsi(priv, adjusted_mode);
1660
1661		if (priv->sink_has_audio)
1662			tda998x_configure_audio(priv);
1663	}
1664
1665	mutex_unlock(&priv->audio_mutex);
1666}
1667
1668static const struct drm_bridge_funcs tda998x_bridge_funcs = {
1669	.attach = tda998x_bridge_attach,
1670	.detach = tda998x_bridge_detach,
1671	.mode_valid = tda998x_bridge_mode_valid,
1672	.disable = tda998x_bridge_disable,
1673	.mode_set = tda998x_bridge_mode_set,
1674	.enable = tda998x_bridge_enable,
1675};
1676
1677/* I2C driver functions */
1678
1679static int tda998x_get_audio_ports(struct tda998x_priv *priv,
1680				   struct device_node *np)
1681{
1682	const u32 *port_data;
1683	u32 size;
1684	int i;
1685
1686	port_data = of_get_property(np, "audio-ports", &size);
1687	if (!port_data)
1688		return 0;
1689
1690	size /= sizeof(u32);
1691	if (size > 2 * ARRAY_SIZE(priv->audio_port_enable) || size % 2 != 0) {
1692		dev_err(&priv->hdmi->dev,
1693			"Bad number of elements in audio-ports dt-property\n");
1694		return -EINVAL;
1695	}
1696
1697	size /= 2;
1698
1699	for (i = 0; i < size; i++) {
1700		unsigned int route;
1701		u8 afmt = be32_to_cpup(&port_data[2*i]);
1702		u8 ena_ap = be32_to_cpup(&port_data[2*i+1]);
1703
1704		switch (afmt) {
1705		case AFMT_I2S:
1706			route = AUDIO_ROUTE_I2S;
1707			break;
1708		case AFMT_SPDIF:
1709			route = AUDIO_ROUTE_SPDIF;
1710			break;
1711		default:
1712			dev_err(&priv->hdmi->dev,
1713				"Bad audio format %u\n", afmt);
1714			return -EINVAL;
1715		}
1716
1717		if (!ena_ap) {
1718			dev_err(&priv->hdmi->dev, "invalid zero port config\n");
1719			continue;
1720		}
1721
1722		if (priv->audio_port_enable[route]) {
1723			dev_err(&priv->hdmi->dev,
1724				"%s format already configured\n",
1725				route == AUDIO_ROUTE_SPDIF ? "SPDIF" : "I2S");
1726			return -EINVAL;
1727		}
1728
1729		priv->audio_port_enable[route] = ena_ap;
1730	}
1731	return 0;
1732}
1733
1734static int tda998x_set_config(struct tda998x_priv *priv,
1735			      const struct tda998x_encoder_params *p)
1736{
1737	priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
1738			    (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
1739			    VIP_CNTRL_0_SWAP_B(p->swap_b) |
1740			    (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
1741	priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
1742			    (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
1743			    VIP_CNTRL_1_SWAP_D(p->swap_d) |
1744			    (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
1745	priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
1746			    (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
1747			    VIP_CNTRL_2_SWAP_F(p->swap_f) |
1748			    (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
1749
1750	if (p->audio_params.format != AFMT_UNUSED) {
1751		unsigned int ratio, route;
1752		bool spdif = p->audio_params.format == AFMT_SPDIF;
1753
1754		route = AUDIO_ROUTE_I2S + spdif;
1755
1756		priv->audio.route = &tda998x_audio_route[route];
1757		priv->audio.cea = p->audio_params.cea;
1758		priv->audio.sample_rate = p->audio_params.sample_rate;
1759		memcpy(priv->audio.status, p->audio_params.status,
1760		       min(sizeof(priv->audio.status),
1761			   sizeof(p->audio_params.status)));
1762		priv->audio.ena_ap = p->audio_params.config;
1763		priv->audio.i2s_format = I2S_FORMAT_PHILIPS;
1764
1765		ratio = spdif ? 64 : p->audio_params.sample_width * 2;
1766		return tda998x_derive_cts_n(priv, &priv->audio, ratio);
1767	}
1768
1769	return 0;
1770}
1771
1772static void tda998x_destroy(struct device *dev)
1773{
1774	struct tda998x_priv *priv = dev_get_drvdata(dev);
1775
1776	drm_bridge_remove(&priv->bridge);
1777
1778	/* disable all IRQs and free the IRQ handler */
1779	cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1780	reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1781
1782	if (priv->audio_pdev)
1783		platform_device_unregister(priv->audio_pdev);
1784
1785	if (priv->hdmi->irq)
1786		free_irq(priv->hdmi->irq, priv);
1787
1788	del_timer_sync(&priv->edid_delay_timer);
1789	cancel_work_sync(&priv->detect_work);
1790
1791	i2c_unregister_device(priv->cec);
1792
1793	if (priv->cec_notify)
1794		cec_notifier_put(priv->cec_notify);
1795}
1796
1797static int tda998x_create(struct device *dev)
1798{
1799	struct i2c_client *client = to_i2c_client(dev);
1800	struct device_node *np = client->dev.of_node;
1801	struct i2c_board_info cec_info;
1802	struct tda998x_priv *priv;
1803	u32 video;
1804	int rev_lo, rev_hi, ret;
1805
1806	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1807	if (!priv)
1808		return -ENOMEM;
1809
1810	dev_set_drvdata(dev, priv);
1811
1812	mutex_init(&priv->mutex);	/* protect the page access */
1813	mutex_init(&priv->audio_mutex); /* protect access from audio thread */
1814	mutex_init(&priv->edid_mutex);
1815	INIT_LIST_HEAD(&priv->bridge.list);
1816	init_waitqueue_head(&priv->edid_delay_waitq);
1817	timer_setup(&priv->edid_delay_timer, tda998x_edid_delay_done, 0);
1818	INIT_WORK(&priv->detect_work, tda998x_detect_work);
1819
1820	priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1821	priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1822	priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1823
1824	/* CEC I2C address bound to TDA998x I2C addr by configuration pins */
1825	priv->cec_addr = 0x34 + (client->addr & 0x03);
1826	priv->current_page = 0xff;
1827	priv->hdmi = client;
1828
1829	/* wake up the device: */
1830	cec_write(priv, REG_CEC_ENAMODS,
1831			CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1832
1833	tda998x_reset(priv);
1834
1835	/* read version: */
1836	rev_lo = reg_read(priv, REG_VERSION_LSB);
1837	if (rev_lo < 0) {
1838		dev_err(dev, "failed to read version: %d\n", rev_lo);
1839		return rev_lo;
1840	}
1841
1842	rev_hi = reg_read(priv, REG_VERSION_MSB);
1843	if (rev_hi < 0) {
1844		dev_err(dev, "failed to read version: %d\n", rev_hi);
1845		return rev_hi;
1846	}
1847
1848	priv->rev = rev_lo | rev_hi << 8;
1849
1850	/* mask off feature bits: */
1851	priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1852
1853	switch (priv->rev) {
1854	case TDA9989N2:
1855		dev_info(dev, "found TDA9989 n2");
1856		break;
1857	case TDA19989:
1858		dev_info(dev, "found TDA19989");
1859		break;
1860	case TDA19989N2:
1861		dev_info(dev, "found TDA19989 n2");
1862		break;
1863	case TDA19988:
1864		dev_info(dev, "found TDA19988");
1865		break;
1866	default:
1867		dev_err(dev, "found unsupported device: %04x\n", priv->rev);
1868		return -ENXIO;
1869	}
1870
1871	/* after reset, enable DDC: */
1872	reg_write(priv, REG_DDC_DISABLE, 0x00);
1873
1874	/* set clock on DDC channel: */
1875	reg_write(priv, REG_TX3, 39);
1876
1877	/* if necessary, disable multi-master: */
1878	if (priv->rev == TDA19989)
1879		reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
1880
1881	cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
1882			CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1883
1884	/* ensure interrupts are disabled */
1885	cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1886
1887	/* clear pending interrupts */
1888	cec_read(priv, REG_CEC_RXSHPDINT);
1889	reg_read(priv, REG_INT_FLAGS_0);
1890	reg_read(priv, REG_INT_FLAGS_1);
1891	reg_read(priv, REG_INT_FLAGS_2);
1892
1893	/* initialize the optional IRQ */
1894	if (client->irq) {
1895		unsigned long irq_flags;
1896
1897		/* init read EDID waitqueue and HDP work */
1898		init_waitqueue_head(&priv->wq_edid);
1899
1900		irq_flags =
1901			irqd_get_trigger_type(irq_get_irq_data(client->irq));
1902
1903		priv->cec_glue.irq_flags = irq_flags;
1904
1905		irq_flags |= IRQF_SHARED | IRQF_ONESHOT;
1906		ret = request_threaded_irq(client->irq, NULL,
1907					   tda998x_irq_thread, irq_flags,
1908					   "tda998x", priv);
1909		if (ret) {
1910			dev_err(dev, "failed to request IRQ#%u: %d\n",
1911				client->irq, ret);
1912			goto err_irq;
1913		}
1914
1915		/* enable HPD irq */
1916		cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1917	}
1918
1919	priv->cec_notify = cec_notifier_get(dev);
1920	if (!priv->cec_notify) {
1921		ret = -ENOMEM;
1922		goto fail;
1923	}
1924
1925	priv->cec_glue.parent = dev;
1926	priv->cec_glue.data = priv;
1927	priv->cec_glue.init = tda998x_cec_hook_init;
1928	priv->cec_glue.exit = tda998x_cec_hook_exit;
1929	priv->cec_glue.open = tda998x_cec_hook_open;
1930	priv->cec_glue.release = tda998x_cec_hook_release;
1931
1932	/*
1933	 * Some TDA998x are actually two I2C devices merged onto one piece
1934	 * of silicon: TDA9989 and TDA19989 combine the HDMI transmitter
1935	 * with a slightly modified TDA9950 CEC device.  The CEC device
1936	 * is at the TDA9950 address, with the address pins strapped across
1937	 * to the TDA998x address pins.  Hence, it always has the same
1938	 * offset.
1939	 */
1940	memset(&cec_info, 0, sizeof(cec_info));
1941	strlcpy(cec_info.type, "tda9950", sizeof(cec_info.type));
1942	cec_info.addr = priv->cec_addr;
1943	cec_info.platform_data = &priv->cec_glue;
1944	cec_info.irq = client->irq;
1945
1946	priv->cec = i2c_new_device(client->adapter, &cec_info);
1947	if (!priv->cec) {
1948		ret = -ENODEV;
1949		goto fail;
1950	}
1951
1952	/* enable EDID read irq: */
1953	reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1954
1955	if (np) {
1956		/* get the device tree parameters */
1957		ret = of_property_read_u32(np, "video-ports", &video);
1958		if (ret == 0) {
1959			priv->vip_cntrl_0 = video >> 16;
1960			priv->vip_cntrl_1 = video >> 8;
1961			priv->vip_cntrl_2 = video;
1962		}
1963
1964		ret = tda998x_get_audio_ports(priv, np);
1965		if (ret)
1966			goto fail;
1967
1968		if (priv->audio_port_enable[AUDIO_ROUTE_I2S] ||
1969		    priv->audio_port_enable[AUDIO_ROUTE_SPDIF])
1970			tda998x_audio_codec_init(priv, &client->dev);
1971	} else if (dev->platform_data) {
1972		ret = tda998x_set_config(priv, dev->platform_data);
1973		if (ret)
1974			goto fail;
1975	}
1976
1977	priv->bridge.funcs = &tda998x_bridge_funcs;
1978#ifdef CONFIG_OF
1979	priv->bridge.of_node = dev->of_node;
1980#endif
1981
1982	drm_bridge_add(&priv->bridge);
1983
1984	return 0;
1985
1986fail:
1987	tda998x_destroy(dev);
1988err_irq:
1989	return ret;
1990}
1991
1992/* DRM encoder functions */
1993
1994static void tda998x_encoder_destroy(struct drm_encoder *encoder)
1995{
1996	drm_encoder_cleanup(encoder);
1997}
1998
1999static const struct drm_encoder_funcs tda998x_encoder_funcs = {
2000	.destroy = tda998x_encoder_destroy,
2001};
2002
2003static int tda998x_encoder_init(struct device *dev, struct drm_device *drm)
2004{
2005	struct tda998x_priv *priv = dev_get_drvdata(dev);
2006	u32 crtcs = 0;
2007	int ret;
2008
2009	if (dev->of_node)
2010		crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
2011
2012	/* If no CRTCs were found, fall back to our old behaviour */
2013	if (crtcs == 0) {
2014		dev_warn(dev, "Falling back to first CRTC\n");
2015		crtcs = 1 << 0;
2016	}
2017
2018	priv->encoder.possible_crtcs = crtcs;
2019
2020	ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs,
2021			       DRM_MODE_ENCODER_TMDS, NULL);
2022	if (ret)
2023		goto err_encoder;
2024
2025	ret = drm_bridge_attach(&priv->encoder, &priv->bridge, NULL);
2026	if (ret)
2027		goto err_bridge;
2028
2029	return 0;
2030
2031err_bridge:
2032	drm_encoder_cleanup(&priv->encoder);
2033err_encoder:
2034	return ret;
2035}
2036
2037static int tda998x_bind(struct device *dev, struct device *master, void *data)
2038{
2039	struct drm_device *drm = data;
2040
2041	return tda998x_encoder_init(dev, drm);
2042}
2043
2044static void tda998x_unbind(struct device *dev, struct device *master,
2045			   void *data)
2046{
2047	struct tda998x_priv *priv = dev_get_drvdata(dev);
2048
2049	drm_encoder_cleanup(&priv->encoder);
2050}
2051
2052static const struct component_ops tda998x_ops = {
2053	.bind = tda998x_bind,
2054	.unbind = tda998x_unbind,
2055};
2056
2057static int
2058tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
2059{
2060	int ret;
2061
2062	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
2063		dev_warn(&client->dev, "adapter does not support I2C\n");
2064		return -EIO;
2065	}
2066
2067	ret = tda998x_create(&client->dev);
2068	if (ret)
2069		return ret;
2070
2071	ret = component_add(&client->dev, &tda998x_ops);
2072	if (ret)
2073		tda998x_destroy(&client->dev);
2074	return ret;
2075}
2076
2077static int tda998x_remove(struct i2c_client *client)
2078{
2079	component_del(&client->dev, &tda998x_ops);
2080	tda998x_destroy(&client->dev);
2081	return 0;
2082}
2083
2084#ifdef CONFIG_OF
2085static const struct of_device_id tda998x_dt_ids[] = {
2086	{ .compatible = "nxp,tda998x", },
2087	{ }
2088};
2089MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
2090#endif
2091
2092static const struct i2c_device_id tda998x_ids[] = {
2093	{ "tda998x", 0 },
2094	{ }
2095};
2096MODULE_DEVICE_TABLE(i2c, tda998x_ids);
2097
2098static struct i2c_driver tda998x_driver = {
2099	.probe = tda998x_probe,
2100	.remove = tda998x_remove,
2101	.driver = {
2102		.name = "tda998x",
2103		.of_match_table = of_match_ptr(tda998x_dt_ids),
2104	},
2105	.id_table = tda998x_ids,
2106};
2107
2108module_i2c_driver(tda998x_driver);
2109
2110MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
2111MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
2112MODULE_LICENSE("GPL");