Loading...
1/* Copyright 2012-15 Advanced Micro Devices, Inc.
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice shall be included in
11 * all copies or substantial portions of the Software.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
19 * OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * Authors: AMD
22 *
23 */
24
25#ifndef __DC_CLOCK_SOURCE_DCE_H__
26#define __DC_CLOCK_SOURCE_DCE_H__
27
28#include "../inc/clock_source.h"
29
30#define TO_DCE110_CLK_SRC(clk_src)\
31 container_of(clk_src, struct dce110_clk_src, base)
32
33#define CS_COMMON_REG_LIST_DCE_100_110(id) \
34 SRI(RESYNC_CNTL, PIXCLK, id), \
35 SRI(PLL_CNTL, BPHYC_PLL, id)
36
37#define CS_COMMON_REG_LIST_DCE_80(id) \
38 SRI(RESYNC_CNTL, PIXCLK, id), \
39 SRI(PLL_CNTL, DCCG_PLL, id)
40
41#define CS_COMMON_REG_LIST_DCE_112(id) \
42 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, id)
43
44
45#define CS_SF(reg_name, field_name, post_fix)\
46 .field_name = reg_name ## __ ## field_name ## post_fix
47
48#define CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\
49 CS_SF(PLL_CNTL, PLL_REF_DIV_SRC, mask_sh),\
50 CS_SF(PIXCLK1_RESYNC_CNTL, DCCG_DEEP_COLOR_CNTL1, mask_sh),\
51 CS_SF(PLL_POST_DIV, PLL_POST_DIV_PIXCLK, mask_sh),\
52 CS_SF(PLL_REF_DIV, PLL_REF_DIV, mask_sh)
53
54#define CS_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\
55 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
56 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh)
57
58#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
59#define CS_COMMON_REG_LIST_DCN2_0(index, pllid) \
60 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
61 SRII(PHASE, DP_DTO, 0),\
62 SRII(PHASE, DP_DTO, 1),\
63 SRII(PHASE, DP_DTO, 2),\
64 SRII(PHASE, DP_DTO, 3),\
65 SRII(PHASE, DP_DTO, 4),\
66 SRII(PHASE, DP_DTO, 5),\
67 SRII(MODULO, DP_DTO, 0),\
68 SRII(MODULO, DP_DTO, 1),\
69 SRII(MODULO, DP_DTO, 2),\
70 SRII(MODULO, DP_DTO, 3),\
71 SRII(MODULO, DP_DTO, 4),\
72 SRII(MODULO, DP_DTO, 5),\
73 SRII(PIXEL_RATE_CNTL, OTG, 0),\
74 SRII(PIXEL_RATE_CNTL, OTG, 1),\
75 SRII(PIXEL_RATE_CNTL, OTG, 2),\
76 SRII(PIXEL_RATE_CNTL, OTG, 3),\
77 SRII(PIXEL_RATE_CNTL, OTG, 4),\
78 SRII(PIXEL_RATE_CNTL, OTG, 5)
79#endif
80
81#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
82#define CS_COMMON_REG_LIST_DCN2_1(index, pllid) \
83 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
84 SRII(PHASE, DP_DTO, 0),\
85 SRII(PHASE, DP_DTO, 1),\
86 SRII(PHASE, DP_DTO, 2),\
87 SRII(PHASE, DP_DTO, 3),\
88 SRII(MODULO, DP_DTO, 0),\
89 SRII(MODULO, DP_DTO, 1),\
90 SRII(MODULO, DP_DTO, 2),\
91 SRII(MODULO, DP_DTO, 3),\
92 SRII(PIXEL_RATE_CNTL, OTG, 0),\
93 SRII(PIXEL_RATE_CNTL, OTG, 1),\
94 SRII(PIXEL_RATE_CNTL, OTG, 2),\
95 SRII(PIXEL_RATE_CNTL, OTG, 3)
96#endif
97
98#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
99#define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\
100 CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\
101 CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\
102 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
103 CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
104#endif
105
106#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
107
108#define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \
109 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
110 SRII(PHASE, DP_DTO, 0),\
111 SRII(PHASE, DP_DTO, 1),\
112 SRII(PHASE, DP_DTO, 2),\
113 SRII(PHASE, DP_DTO, 3),\
114 SRII(MODULO, DP_DTO, 0),\
115 SRII(MODULO, DP_DTO, 1),\
116 SRII(MODULO, DP_DTO, 2),\
117 SRII(MODULO, DP_DTO, 3),\
118 SRII(PIXEL_RATE_CNTL, OTG, 0), \
119 SRII(PIXEL_RATE_CNTL, OTG, 1), \
120 SRII(PIXEL_RATE_CNTL, OTG, 2), \
121 SRII(PIXEL_RATE_CNTL, OTG, 3)
122
123#define CS_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
124 CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\
125 CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\
126 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
127 CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
128
129#endif
130
131#define CS_REG_FIELD_LIST(type) \
132 type PLL_REF_DIV_SRC; \
133 type DCCG_DEEP_COLOR_CNTL1; \
134 type PHYPLLA_DCCG_DEEP_COLOR_CNTL; \
135 type PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE; \
136 type PLL_POST_DIV_PIXCLK; \
137 type PLL_REF_DIV; \
138 type DP_DTO0_PHASE; \
139 type DP_DTO0_MODULO; \
140 type DP_DTO0_ENABLE;
141
142struct dce110_clk_src_shift {
143 CS_REG_FIELD_LIST(uint8_t)
144};
145
146struct dce110_clk_src_mask{
147 CS_REG_FIELD_LIST(uint32_t)
148};
149
150struct dce110_clk_src_regs {
151 uint32_t RESYNC_CNTL;
152 uint32_t PIXCLK_RESYNC_CNTL;
153 uint32_t PLL_CNTL;
154
155 /* below are for DTO.
156 * todo: should probably use different struct to not waste space
157 */
158 uint32_t PHASE[MAX_PIPES];
159 uint32_t MODULO[MAX_PIPES];
160 uint32_t PIXEL_RATE_CNTL[MAX_PIPES];
161};
162
163struct dce110_clk_src {
164 struct clock_source base;
165 const struct dce110_clk_src_regs *regs;
166 const struct dce110_clk_src_mask *cs_mask;
167 const struct dce110_clk_src_shift *cs_shift;
168 struct dc_bios *bios;
169
170 struct spread_spectrum_data *dp_ss_params;
171 uint32_t dp_ss_params_cnt;
172 struct spread_spectrum_data *hdmi_ss_params;
173 uint32_t hdmi_ss_params_cnt;
174 struct spread_spectrum_data *dvi_ss_params;
175 uint32_t dvi_ss_params_cnt;
176 struct spread_spectrum_data *lvds_ss_params;
177 uint32_t lvds_ss_params_cnt;
178
179 uint32_t ext_clk_khz;
180 uint32_t ref_freq_khz;
181
182 struct calc_pll_clock_source calc_pll;
183 struct calc_pll_clock_source calc_pll_hdmi;
184};
185
186bool dce110_clk_src_construct(
187 struct dce110_clk_src *clk_src,
188 struct dc_context *ctx,
189 struct dc_bios *bios,
190 enum clock_source_id,
191 const struct dce110_clk_src_regs *regs,
192 const struct dce110_clk_src_shift *cs_shift,
193 const struct dce110_clk_src_mask *cs_mask);
194
195bool dce112_clk_src_construct(
196 struct dce110_clk_src *clk_src,
197 struct dc_context *ctx,
198 struct dc_bios *bios,
199 enum clock_source_id id,
200 const struct dce110_clk_src_regs *regs,
201 const struct dce110_clk_src_shift *cs_shift,
202 const struct dce110_clk_src_mask *cs_mask);
203
204#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
205bool dcn20_clk_src_construct(
206 struct dce110_clk_src *clk_src,
207 struct dc_context *ctx,
208 struct dc_bios *bios,
209 enum clock_source_id id,
210 const struct dce110_clk_src_regs *regs,
211 const struct dce110_clk_src_shift *cs_shift,
212 const struct dce110_clk_src_mask *cs_mask);
213#endif
214
215#endif
1/* Copyright 2012-15 Advanced Micro Devices, Inc.
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice shall be included in
11 * all copies or substantial portions of the Software.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
19 * OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * Authors: AMD
22 *
23 */
24
25#ifndef __DC_CLOCK_SOURCE_DCE_H__
26#define __DC_CLOCK_SOURCE_DCE_H__
27
28#include "../inc/clock_source.h"
29
30#define TO_DCE110_CLK_SRC(clk_src)\
31 container_of(clk_src, struct dce110_clk_src, base)
32
33#define CS_COMMON_REG_LIST_DCE_100_110(id) \
34 SRI(RESYNC_CNTL, PIXCLK, id), \
35 SRI(PLL_CNTL, BPHYC_PLL, id)
36
37#define CS_COMMON_REG_LIST_DCE_80(id) \
38 SRI(RESYNC_CNTL, PIXCLK, id), \
39 SRI(PLL_CNTL, DCCG_PLL, id)
40
41#define CS_COMMON_REG_LIST_DCE_112(id) \
42 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, id)
43
44
45#define CS_SF(reg_name, field_name, post_fix)\
46 .field_name = reg_name ## __ ## field_name ## post_fix
47
48#define CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\
49 CS_SF(PLL_CNTL, PLL_REF_DIV_SRC, mask_sh),\
50 CS_SF(PIXCLK1_RESYNC_CNTL, DCCG_DEEP_COLOR_CNTL1, mask_sh),\
51 CS_SF(PLL_POST_DIV, PLL_POST_DIV_PIXCLK, mask_sh),\
52 CS_SF(PLL_REF_DIV, PLL_REF_DIV, mask_sh)
53
54#define CS_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\
55 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
56 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh)
57
58#define CS_COMMON_REG_LIST_DCN2_0(index, pllid) \
59 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
60 SRII(PHASE, DP_DTO, 0),\
61 SRII(PHASE, DP_DTO, 1),\
62 SRII(PHASE, DP_DTO, 2),\
63 SRII(PHASE, DP_DTO, 3),\
64 SRII(PHASE, DP_DTO, 4),\
65 SRII(PHASE, DP_DTO, 5),\
66 SRII(MODULO, DP_DTO, 0),\
67 SRII(MODULO, DP_DTO, 1),\
68 SRII(MODULO, DP_DTO, 2),\
69 SRII(MODULO, DP_DTO, 3),\
70 SRII(MODULO, DP_DTO, 4),\
71 SRII(MODULO, DP_DTO, 5),\
72 SRII(PIXEL_RATE_CNTL, OTG, 0),\
73 SRII(PIXEL_RATE_CNTL, OTG, 1),\
74 SRII(PIXEL_RATE_CNTL, OTG, 2),\
75 SRII(PIXEL_RATE_CNTL, OTG, 3),\
76 SRII(PIXEL_RATE_CNTL, OTG, 4),\
77 SRII(PIXEL_RATE_CNTL, OTG, 5)
78
79#define CS_COMMON_REG_LIST_DCN201(index, pllid) \
80 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
81 SRII(PHASE, DP_DTO, 0),\
82 SRII(PHASE, DP_DTO, 1),\
83 SRII(MODULO, DP_DTO, 0),\
84 SRII(MODULO, DP_DTO, 1),\
85 SRII(PIXEL_RATE_CNTL, OTG, 0),\
86 SRII(PIXEL_RATE_CNTL, OTG, 1)
87
88#define CS_COMMON_REG_LIST_DCN2_1(index, pllid) \
89 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
90 SRII(PHASE, DP_DTO, 0),\
91 SRII(PHASE, DP_DTO, 1),\
92 SRII(PHASE, DP_DTO, 2),\
93 SRII(PHASE, DP_DTO, 3),\
94 SRII(MODULO, DP_DTO, 0),\
95 SRII(MODULO, DP_DTO, 1),\
96 SRII(MODULO, DP_DTO, 2),\
97 SRII(MODULO, DP_DTO, 3),\
98 SRII(PIXEL_RATE_CNTL, OTG, 0),\
99 SRII(PIXEL_RATE_CNTL, OTG, 1),\
100 SRII(PIXEL_RATE_CNTL, OTG, 2),\
101 SRII(PIXEL_RATE_CNTL, OTG, 3)
102
103#define CS_COMMON_REG_LIST_DCN3_0(index, pllid) \
104 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
105 SRII(PHASE, DP_DTO, 0),\
106 SRII(PHASE, DP_DTO, 1),\
107 SRII(PHASE, DP_DTO, 2),\
108 SRII(PHASE, DP_DTO, 3),\
109 SRII(MODULO, DP_DTO, 0),\
110 SRII(MODULO, DP_DTO, 1),\
111 SRII(MODULO, DP_DTO, 2),\
112 SRII(MODULO, DP_DTO, 3),\
113 SRII(PIXEL_RATE_CNTL, OTG, 0),\
114 SRII(PIXEL_RATE_CNTL, OTG, 1),\
115 SRII(PIXEL_RATE_CNTL, OTG, 2),\
116 SRII(PIXEL_RATE_CNTL, OTG, 3)
117
118#define CS_COMMON_REG_LIST_DCN3_01(index, pllid) \
119 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
120 SRII(PHASE, DP_DTO, 0),\
121 SRII(PHASE, DP_DTO, 1),\
122 SRII(PHASE, DP_DTO, 2),\
123 SRII(PHASE, DP_DTO, 3),\
124 SRII(MODULO, DP_DTO, 0),\
125 SRII(MODULO, DP_DTO, 1),\
126 SRII(MODULO, DP_DTO, 2),\
127 SRII(MODULO, DP_DTO, 3),\
128 SRII(PIXEL_RATE_CNTL, OTG, 0),\
129 SRII(PIXEL_RATE_CNTL, OTG, 1),\
130 SRII(PIXEL_RATE_CNTL, OTG, 2),\
131 SRII(PIXEL_RATE_CNTL, OTG, 3)
132
133#define CS_COMMON_REG_LIST_DCN3_02(index, pllid) \
134 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
135 SRII(PHASE, DP_DTO, 0),\
136 SRII(PHASE, DP_DTO, 1),\
137 SRII(PHASE, DP_DTO, 2),\
138 SRII(PHASE, DP_DTO, 3),\
139 SRII(PHASE, DP_DTO, 4),\
140 SRII(MODULO, DP_DTO, 0),\
141 SRII(MODULO, DP_DTO, 1),\
142 SRII(MODULO, DP_DTO, 2),\
143 SRII(MODULO, DP_DTO, 3),\
144 SRII(MODULO, DP_DTO, 4),\
145 SRII(PIXEL_RATE_CNTL, OTG, 0),\
146 SRII(PIXEL_RATE_CNTL, OTG, 1),\
147 SRII(PIXEL_RATE_CNTL, OTG, 2),\
148 SRII(PIXEL_RATE_CNTL, OTG, 3),\
149 SRII(PIXEL_RATE_CNTL, OTG, 4)
150
151#define CS_COMMON_REG_LIST_DCN3_03(index, pllid) \
152 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
153 SRII(PHASE, DP_DTO, 0),\
154 SRII(PHASE, DP_DTO, 1),\
155 SRII(MODULO, DP_DTO, 0),\
156 SRII(MODULO, DP_DTO, 1),\
157 SRII(PIXEL_RATE_CNTL, OTG, 0),\
158 SRII(PIXEL_RATE_CNTL, OTG, 1)
159
160#define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\
161 CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\
162 CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\
163 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
164 CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
165
166#define CS_COMMON_MASK_SH_LIST_DCN3_1_4(mask_sh)\
167 CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh),\
168 CS_SF(OTG0_PIXEL_RATE_CNTL, PIPE0_DTO_SRC_SEL, mask_sh),
169
170#define CS_COMMON_MASK_SH_LIST_DCN3_2(mask_sh)\
171 CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh),\
172 CS_SF(OTG0_PIXEL_RATE_CNTL, PIPE0_DTO_SRC_SEL, mask_sh)
173
174#define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \
175 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
176 SRII(PHASE, DP_DTO, 0),\
177 SRII(PHASE, DP_DTO, 1),\
178 SRII(PHASE, DP_DTO, 2),\
179 SRII(PHASE, DP_DTO, 3),\
180 SRII(MODULO, DP_DTO, 0),\
181 SRII(MODULO, DP_DTO, 1),\
182 SRII(MODULO, DP_DTO, 2),\
183 SRII(MODULO, DP_DTO, 3),\
184 SRII(PIXEL_RATE_CNTL, OTG, 0), \
185 SRII(PIXEL_RATE_CNTL, OTG, 1), \
186 SRII(PIXEL_RATE_CNTL, OTG, 2), \
187 SRII(PIXEL_RATE_CNTL, OTG, 3)
188
189#define CS_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
190 CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\
191 CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\
192 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
193 CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
194
195
196#define CS_REG_FIELD_LIST(type) \
197 type PLL_REF_DIV_SRC; \
198 type DCCG_DEEP_COLOR_CNTL1; \
199 type PHYPLLA_DCCG_DEEP_COLOR_CNTL; \
200 type PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE; \
201 type PLL_POST_DIV_PIXCLK; \
202 type PLL_REF_DIV; \
203 type DP_DTO0_PHASE; \
204 type DP_DTO0_MODULO; \
205 type DP_DTO0_ENABLE;
206
207#if defined(CONFIG_DRM_AMD_DC_DCN)
208#define CS_REG_FIELD_LIST_DCN32(type) \
209 type PIPE0_DTO_SRC_SEL;
210#endif
211
212struct dce110_clk_src_shift {
213 CS_REG_FIELD_LIST(uint8_t)
214#if defined(CONFIG_DRM_AMD_DC_DCN)
215 CS_REG_FIELD_LIST_DCN32(uint8_t)
216#endif
217};
218
219struct dce110_clk_src_mask{
220 CS_REG_FIELD_LIST(uint32_t)
221#if defined(CONFIG_DRM_AMD_DC_DCN)
222 CS_REG_FIELD_LIST_DCN32(uint32_t)
223#endif
224};
225
226struct dce110_clk_src_regs {
227 uint32_t RESYNC_CNTL;
228 uint32_t PIXCLK_RESYNC_CNTL;
229 uint32_t PLL_CNTL;
230
231 /* below are for DTO.
232 * todo: should probably use different struct to not waste space
233 */
234 uint32_t PHASE[MAX_PIPES];
235 uint32_t MODULO[MAX_PIPES];
236 uint32_t PIXEL_RATE_CNTL[MAX_PIPES];
237};
238
239struct dce110_clk_src {
240 struct clock_source base;
241 const struct dce110_clk_src_regs *regs;
242 const struct dce110_clk_src_mask *cs_mask;
243 const struct dce110_clk_src_shift *cs_shift;
244 struct dc_bios *bios;
245
246 struct spread_spectrum_data *dp_ss_params;
247 uint32_t dp_ss_params_cnt;
248 struct spread_spectrum_data *hdmi_ss_params;
249 uint32_t hdmi_ss_params_cnt;
250 struct spread_spectrum_data *dvi_ss_params;
251 uint32_t dvi_ss_params_cnt;
252 struct spread_spectrum_data *lvds_ss_params;
253 uint32_t lvds_ss_params_cnt;
254
255 uint32_t ext_clk_khz;
256 uint32_t ref_freq_khz;
257
258 struct calc_pll_clock_source calc_pll;
259 struct calc_pll_clock_source calc_pll_hdmi;
260};
261
262bool dce110_clk_src_construct(
263 struct dce110_clk_src *clk_src,
264 struct dc_context *ctx,
265 struct dc_bios *bios,
266 enum clock_source_id,
267 const struct dce110_clk_src_regs *regs,
268 const struct dce110_clk_src_shift *cs_shift,
269 const struct dce110_clk_src_mask *cs_mask);
270
271bool dce112_clk_src_construct(
272 struct dce110_clk_src *clk_src,
273 struct dc_context *ctx,
274 struct dc_bios *bios,
275 enum clock_source_id id,
276 const struct dce110_clk_src_regs *regs,
277 const struct dce110_clk_src_shift *cs_shift,
278 const struct dce110_clk_src_mask *cs_mask);
279
280bool dcn20_clk_src_construct(
281 struct dce110_clk_src *clk_src,
282 struct dc_context *ctx,
283 struct dc_bios *bios,
284 enum clock_source_id id,
285 const struct dce110_clk_src_regs *regs,
286 const struct dce110_clk_src_shift *cs_shift,
287 const struct dce110_clk_src_mask *cs_mask);
288
289bool dcn3_clk_src_construct(
290 struct dce110_clk_src *clk_src,
291 struct dc_context *ctx,
292 struct dc_bios *bios,
293 enum clock_source_id id,
294 const struct dce110_clk_src_regs *regs,
295 const struct dce110_clk_src_shift *cs_shift,
296 const struct dce110_clk_src_mask *cs_mask);
297
298bool dcn301_clk_src_construct(
299 struct dce110_clk_src *clk_src,
300 struct dc_context *ctx,
301 struct dc_bios *bios,
302 enum clock_source_id id,
303 const struct dce110_clk_src_regs *regs,
304 const struct dce110_clk_src_shift *cs_shift,
305 const struct dce110_clk_src_mask *cs_mask);
306
307bool dcn31_clk_src_construct(
308 struct dce110_clk_src *clk_src,
309 struct dc_context *ctx,
310 struct dc_bios *bios,
311 enum clock_source_id id,
312 const struct dce110_clk_src_regs *regs,
313 const struct dce110_clk_src_shift *cs_shift,
314 const struct dce110_clk_src_mask *cs_mask);
315
316/* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */
317struct pixel_rate_range_table_entry {
318 unsigned int range_min_khz;
319 unsigned int range_max_khz;
320 unsigned int target_pixel_rate_khz;
321 unsigned short mult_factor;
322 unsigned short div_factor;
323};
324
325extern const struct pixel_rate_range_table_entry video_optimized_pixel_rates[];
326const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb(
327 unsigned int pixel_rate_khz);
328
329#endif