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1/*
2 * SATA glue for Cavium Octeon III SOCs.
3 *
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 *
9 * Copyright (C) 2010-2015 Cavium Networks
10 *
11 */
12
13#include <linux/module.h>
14#include <linux/dma-mapping.h>
15#include <linux/platform_device.h>
16#include <linux/of_platform.h>
17
18#include <asm/octeon/octeon.h>
19#include <asm/bitfield.h>
20
21#define CVMX_SATA_UCTL_SHIM_CFG 0xE8
22
23#define SATA_UCTL_ENDIAN_MODE_BIG 1
24#define SATA_UCTL_ENDIAN_MODE_LITTLE 0
25#define SATA_UCTL_ENDIAN_MODE_MASK 3
26
27#define SATA_UCTL_DMA_ENDIAN_MODE_SHIFT 8
28#define SATA_UCTL_CSR_ENDIAN_MODE_SHIFT 0
29#define SATA_UCTL_DMA_READ_CMD_SHIFT 12
30
31static int ahci_octeon_probe(struct platform_device *pdev)
32{
33 struct device *dev = &pdev->dev;
34 struct device_node *node = dev->of_node;
35 struct resource *res;
36 void __iomem *base;
37 u64 cfg;
38 int ret;
39
40 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
41 base = devm_ioremap_resource(&pdev->dev, res);
42 if (IS_ERR(base))
43 return PTR_ERR(base);
44
45 cfg = cvmx_readq_csr(base + CVMX_SATA_UCTL_SHIM_CFG);
46
47 cfg &= ~(SATA_UCTL_ENDIAN_MODE_MASK << SATA_UCTL_DMA_ENDIAN_MODE_SHIFT);
48 cfg &= ~(SATA_UCTL_ENDIAN_MODE_MASK << SATA_UCTL_CSR_ENDIAN_MODE_SHIFT);
49
50#ifdef __BIG_ENDIAN
51 cfg |= SATA_UCTL_ENDIAN_MODE_BIG << SATA_UCTL_DMA_ENDIAN_MODE_SHIFT;
52 cfg |= SATA_UCTL_ENDIAN_MODE_BIG << SATA_UCTL_CSR_ENDIAN_MODE_SHIFT;
53#else
54 cfg |= SATA_UCTL_ENDIAN_MODE_LITTLE << SATA_UCTL_DMA_ENDIAN_MODE_SHIFT;
55 cfg |= SATA_UCTL_ENDIAN_MODE_LITTLE << SATA_UCTL_CSR_ENDIAN_MODE_SHIFT;
56#endif
57
58 cfg |= 1 << SATA_UCTL_DMA_READ_CMD_SHIFT;
59
60 cvmx_writeq_csr(base + CVMX_SATA_UCTL_SHIM_CFG, cfg);
61
62 if (!node) {
63 dev_err(dev, "no device node, failed to add octeon sata\n");
64 return -ENODEV;
65 }
66
67 ret = of_platform_populate(node, NULL, NULL, dev);
68 if (ret) {
69 dev_err(dev, "failed to add ahci-platform core\n");
70 return ret;
71 }
72
73 return 0;
74}
75
76static int ahci_octeon_remove(struct platform_device *pdev)
77{
78 return 0;
79}
80
81static const struct of_device_id octeon_ahci_match[] = {
82 { .compatible = "cavium,octeon-7130-sata-uctl", },
83 {},
84};
85MODULE_DEVICE_TABLE(of, octeon_ahci_match);
86
87static struct platform_driver ahci_octeon_driver = {
88 .probe = ahci_octeon_probe,
89 .remove = ahci_octeon_remove,
90 .driver = {
91 .name = "octeon-ahci",
92 .of_match_table = octeon_ahci_match,
93 },
94};
95
96module_platform_driver(ahci_octeon_driver);
97
98MODULE_LICENSE("GPL");
99MODULE_AUTHOR("Cavium, Inc. <support@cavium.com>");
100MODULE_DESCRIPTION("Cavium Inc. sata config.");
1/*
2 * SATA glue for Cavium Octeon III SOCs.
3 *
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 *
9 * Copyright (C) 2010-2015 Cavium Networks
10 *
11 */
12
13#include <linux/module.h>
14#include <linux/dma-mapping.h>
15#include <linux/platform_device.h>
16#include <linux/of_platform.h>
17
18#include <asm/octeon/octeon.h>
19#include <asm/bitfield.h>
20
21#define CVMX_SATA_UCTL_SHIM_CFG 0xE8
22
23#define SATA_UCTL_ENDIAN_MODE_BIG 1
24#define SATA_UCTL_ENDIAN_MODE_LITTLE 0
25#define SATA_UCTL_ENDIAN_MODE_MASK 3
26
27#define SATA_UCTL_DMA_ENDIAN_MODE_SHIFT 8
28#define SATA_UCTL_CSR_ENDIAN_MODE_SHIFT 0
29#define SATA_UCTL_DMA_READ_CMD_SHIFT 12
30
31static int ahci_octeon_probe(struct platform_device *pdev)
32{
33 struct device *dev = &pdev->dev;
34 struct device_node *node = dev->of_node;
35 struct resource *res;
36 void __iomem *base;
37 u64 cfg;
38 int ret;
39
40 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
41 base = devm_ioremap_resource(&pdev->dev, res);
42 if (IS_ERR(base))
43 return PTR_ERR(base);
44
45 cfg = cvmx_readq_csr(base + CVMX_SATA_UCTL_SHIM_CFG);
46
47 cfg &= ~(SATA_UCTL_ENDIAN_MODE_MASK << SATA_UCTL_DMA_ENDIAN_MODE_SHIFT);
48 cfg &= ~(SATA_UCTL_ENDIAN_MODE_MASK << SATA_UCTL_CSR_ENDIAN_MODE_SHIFT);
49
50#ifdef __BIG_ENDIAN
51 cfg |= SATA_UCTL_ENDIAN_MODE_BIG << SATA_UCTL_DMA_ENDIAN_MODE_SHIFT;
52 cfg |= SATA_UCTL_ENDIAN_MODE_BIG << SATA_UCTL_CSR_ENDIAN_MODE_SHIFT;
53#else
54 cfg |= SATA_UCTL_ENDIAN_MODE_LITTLE << SATA_UCTL_DMA_ENDIAN_MODE_SHIFT;
55 cfg |= SATA_UCTL_ENDIAN_MODE_LITTLE << SATA_UCTL_CSR_ENDIAN_MODE_SHIFT;
56#endif
57
58 cfg |= 1 << SATA_UCTL_DMA_READ_CMD_SHIFT;
59
60 cvmx_writeq_csr(base + CVMX_SATA_UCTL_SHIM_CFG, cfg);
61
62 if (!node) {
63 dev_err(dev, "no device node, failed to add octeon sata\n");
64 return -ENODEV;
65 }
66
67 ret = of_platform_populate(node, NULL, NULL, dev);
68 if (ret) {
69 dev_err(dev, "failed to add ahci-platform core\n");
70 return ret;
71 }
72
73 return 0;
74}
75
76static int ahci_octeon_remove(struct platform_device *pdev)
77{
78 return 0;
79}
80
81static const struct of_device_id octeon_ahci_match[] = {
82 { .compatible = "cavium,octeon-7130-sata-uctl", },
83 { /* sentinel */ }
84};
85MODULE_DEVICE_TABLE(of, octeon_ahci_match);
86
87static struct platform_driver ahci_octeon_driver = {
88 .probe = ahci_octeon_probe,
89 .remove = ahci_octeon_remove,
90 .driver = {
91 .name = "octeon-ahci",
92 .of_match_table = octeon_ahci_match,
93 },
94};
95
96module_platform_driver(ahci_octeon_driver);
97
98MODULE_LICENSE("GPL");
99MODULE_AUTHOR("Cavium, Inc. <support@cavium.com>");
100MODULE_DESCRIPTION("Cavium Inc. sata config.");