1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * arch/sh/kernel/cpu/irq/intc-sh5.c
  4 *
  5 * Interrupt Controller support for SH5 INTC.
  6 *
  7 * Copyright (C) 2000, 2001  Paolo Alberelli
  8 * Copyright (C) 2003  Paul Mundt
  9 *
 10 * Per-interrupt selective. IRLM=0 (Fixed priority) is not
 11 * supported being useless without a cascaded interrupt
 12 * controller.
 13 */
 14#include <linux/init.h>
 15#include <linux/interrupt.h>
 16#include <linux/irq.h>
 17#include <linux/io.h>
 18#include <linux/kernel.h>
 19#include <linux/bitops.h>
 20#include <cpu/irq.h>
 21#include <asm/page.h>
 22
 23/*
 24 * Maybe the generic Peripheral block could move to a more
 25 * generic include file. INTC Block will be defined here
 26 * and only here to make INTC self-contained in a single
 27 * file.
 28 */
 29#define	INTC_BLOCK_OFFSET	0x01000000
 30
 31/* Base */
 32#define INTC_BASE		PHYS_PERIPHERAL_BLOCK + \
 33				INTC_BLOCK_OFFSET
 34
 35/* Address */
 36#define INTC_ICR_SET		(intc_virt + 0x0)
 37#define INTC_ICR_CLEAR		(intc_virt + 0x8)
 38#define INTC_INTPRI_0		(intc_virt + 0x10)
 39#define INTC_INTSRC_0		(intc_virt + 0x50)
 40#define INTC_INTSRC_1		(intc_virt + 0x58)
 41#define INTC_INTREQ_0		(intc_virt + 0x60)
 42#define INTC_INTREQ_1		(intc_virt + 0x68)
 43#define INTC_INTENB_0		(intc_virt + 0x70)
 44#define INTC_INTENB_1		(intc_virt + 0x78)
 45#define INTC_INTDSB_0		(intc_virt + 0x80)
 46#define INTC_INTDSB_1		(intc_virt + 0x88)
 47
 48#define INTC_ICR_IRLM		0x1
 49#define	INTC_INTPRI_PREGS	8		/* 8 Priority Registers */
 50#define	INTC_INTPRI_PPREG	8		/* 8 Priorities per Register */
 51
 52
 53/*
 54 * Mapper between the vector ordinal and the IRQ number
 55 * passed to kernel/device drivers.
 56 */
 57int intc_evt_to_irq[(0xE20/0x20)+1] = {
 58	-1, -1, -1, -1, -1, -1, -1, -1,	/* 0x000 - 0x0E0 */
 59	-1, -1, -1, -1, -1, -1, -1, -1,	/* 0x100 - 0x1E0 */
 60	 0,  0,  0,  0,  0,  1,  0,  0,	/* 0x200 - 0x2E0 */
 61	 2,  0,  0,  3,  0,  0,  0, -1,	/* 0x300 - 0x3E0 */
 62	32, 33, 34, 35, 36, 37, 38, -1,	/* 0x400 - 0x4E0 */
 63	-1, -1, -1, 63, -1, -1, -1, -1,	/* 0x500 - 0x5E0 */
 64	-1, -1, 18, 19, 20, 21, 22, -1,	/* 0x600 - 0x6E0 */
 65	39, 40, 41, 42, -1, -1, -1, -1,	/* 0x700 - 0x7E0 */
 66	 4,  5,  6,  7, -1, -1, -1, -1,	/* 0x800 - 0x8E0 */
 67	-1, -1, -1, -1, -1, -1, -1, -1,	/* 0x900 - 0x9E0 */
 68	12, 13, 14, 15, 16, 17, -1, -1,	/* 0xA00 - 0xAE0 */
 69	-1, -1, -1, -1, -1, -1, -1, -1,	/* 0xB00 - 0xBE0 */
 70	-1, -1, -1, -1, -1, -1, -1, -1,	/* 0xC00 - 0xCE0 */
 71	-1, -1, -1, -1, -1, -1, -1, -1,	/* 0xD00 - 0xDE0 */
 72	-1, -1				/* 0xE00 - 0xE20 */
 73};
 74
 75static unsigned long intc_virt;
 76static int irlm;		/* IRL mode */
 77
 78static void enable_intc_irq(struct irq_data *data)
 79{
 80	unsigned int irq = data->irq;
 81	unsigned long reg;
 82	unsigned long bitmask;
 83
 84	if ((irq <= IRQ_IRL3) && (irlm == NO_PRIORITY))
 85		printk("Trying to use straight IRL0-3 with an encoding platform.\n");
 86
 87	if (irq < 32) {
 88		reg = INTC_INTENB_0;
 89		bitmask = 1 << irq;
 90	} else {
 91		reg = INTC_INTENB_1;
 92		bitmask = 1 << (irq - 32);
 93	}
 94
 95	__raw_writel(bitmask, reg);
 96}
 97
 98static void disable_intc_irq(struct irq_data *data)
 99{
100	unsigned int irq = data->irq;
101	unsigned long reg;
102	unsigned long bitmask;
103
104	if (irq < 32) {
105		reg = INTC_INTDSB_0;
106		bitmask = 1 << irq;
107	} else {
108		reg = INTC_INTDSB_1;
109		bitmask = 1 << (irq - 32);
110	}
111
112	__raw_writel(bitmask, reg);
113}
114
115static struct irq_chip intc_irq_type = {
116	.name = "INTC",
117	.irq_enable = enable_intc_irq,
118	.irq_disable = disable_intc_irq,
119};
120
121void __init plat_irq_setup(void)
122{
123	unsigned long long __dummy0, __dummy1=~0x00000000100000f0;
124	unsigned long reg;
125	int i;
126
127	intc_virt = (unsigned long)ioremap_nocache(INTC_BASE, 1024);
128	if (!intc_virt) {
129		panic("Unable to remap INTC\n");
130	}
131
132
133	/* Set default: per-line enable/disable, priority driven ack/eoi */
134	for (i = 0; i < NR_INTC_IRQS; i++)
135		irq_set_chip_and_handler(i, &intc_irq_type, handle_level_irq);
136
137
138	/* Disable all interrupts and set all priorities to 0 to avoid trouble */
139	__raw_writel(-1, INTC_INTDSB_0);
140	__raw_writel(-1, INTC_INTDSB_1);
141
142	for (reg = INTC_INTPRI_0, i = 0; i < INTC_INTPRI_PREGS; i++, reg += 8)
143		__raw_writel( NO_PRIORITY, reg);
144
145
146#ifdef CONFIG_SH_CAYMAN
147	{
148		unsigned long data;
149
150		/* Set IRLM */
151		/* If all the priorities are set to 'no priority', then
152		 * assume we are using encoded mode.
153		 */
154		irlm = platform_int_priority[IRQ_IRL0] +
155		       platform_int_priority[IRQ_IRL1] +
156		       platform_int_priority[IRQ_IRL2] +
157		       platform_int_priority[IRQ_IRL3];
158		if (irlm == NO_PRIORITY) {
159			/* IRLM = 0 */
160			reg = INTC_ICR_CLEAR;
161			i = IRQ_INTA;
162			printk("Trying to use encoded IRL0-3. IRLs unsupported.\n");
163		} else {
164			/* IRLM = 1 */
165			reg = INTC_ICR_SET;
166			i = IRQ_IRL0;
167		}
168		__raw_writel(INTC_ICR_IRLM, reg);
169
170		/* Set interrupt priorities according to platform description */
171		for (data = 0, reg = INTC_INTPRI_0; i < NR_INTC_IRQS; i++) {
172			data |= platform_int_priority[i] <<
173				((i % INTC_INTPRI_PPREG) * 4);
174			if ((i % INTC_INTPRI_PPREG) == (INTC_INTPRI_PPREG - 1)) {
175				/* Upon the 7th, set Priority Register */
176				__raw_writel(data, reg);
177				data = 0;
178				reg += 8;
179			}
180		}
181	}
182#endif
183
184	/*
185	 * And now let interrupts come in.
186	 * sti() is not enough, we need to
187	 * lower priority, too.
188	 */
189        __asm__ __volatile__("getcon    " __SR ", %0\n\t"
190                             "and       %0, %1, %0\n\t"
191                             "putcon    %0, " __SR "\n\t"
192                             : "=&r" (__dummy0)
193                             : "r" (__dummy1));
194}