1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2/*
  3 *  pci-vr41xx.h, Include file for PCI Control Unit of the NEC VR4100 series.
  4 *
  5 *  Copyright (C) 2002	MontaVista Software Inc.
  6 *    Author: Yoichi Yuasa <source@mvista.com>
  7 *  Copyright (C) 2004-2005  Yoichi Yuasa <yuasa@linux-mips.org>
  8 */
  9#ifndef __PCI_VR41XX_H
 10#define __PCI_VR41XX_H
 11
 12#define PCIU_BASE		0x0f000c00UL
 13#define PCIU_SIZE		0x200UL
 14
 15#define PCIMMAW1REG		0x00
 16#define PCIMMAW2REG		0x04
 17#define PCITAW1REG		0x08
 18#define PCITAW2REG		0x0c
 19#define PCIMIOAWREG		0x10
 20 #define IBA(addr)		((addr) & 0xff000000U)
 21 #define MASTER_MSK(mask)	(((mask) >> 11) & 0x000fe000U)
 22 #define PCIA(addr)		(((addr) >> 24) & 0x000000ffU)
 23 #define TARGET_MSK(mask)	(((mask) >> 8) & 0x000fe000U)
 24 #define ITA(addr)		(((addr) >> 24) & 0x000000ffU)
 25 #define PCIIA(addr)		(((addr) >> 24) & 0x000000ffU)
 26 #define WINEN			0x1000U
 27#define PCICONFDREG		0x14
 28#define PCICONFAREG		0x18
 29#define PCIMAILREG		0x1c
 30#define BUSERRADREG		0x24
 31 #define EA(reg)		((reg) &0xfffffffc)
 32
 33#define INTCNTSTAREG		0x28
 34 #define MABTCLR		0x80000000U
 35 #define TRDYCLR		0x40000000U
 36 #define PARCLR			0x20000000U
 37 #define MBCLR			0x10000000U
 38 #define SERRCLR		0x08000000U
 39 #define RTYCLR			0x04000000U
 40 #define MABCLR			0x02000000U
 41 #define TABCLR			0x01000000U
 42 /* RFU */
 43 #define MABTMSK		0x00008000U
 44 #define TRDYMSK		0x00004000U
 45 #define PARMSK			0x00002000U
 46 #define MBMSK			0x00001000U
 47 #define SERRMSK		0x00000800U
 48 #define RTYMSK			0x00000400U
 49 #define MABMSK			0x00000200U
 50 #define TABMSK			0x00000100U
 51 #define IBAMABT		0x00000080U
 52 #define TRDYRCH		0x00000040U
 53 #define PAR			0x00000020U
 54 #define MB			0x00000010U
 55 #define PCISERR		0x00000008U
 56 #define RTYRCH			0x00000004U
 57 #define MABORT			0x00000002U
 58 #define TABORT			0x00000001U
 59
 60#define PCIEXACCREG		0x2c
 61 #define UNLOCK			0x2U
 62 #define EAREQ			0x1U
 63#define PCIRECONTREG		0x30
 64 #define RTRYCNT(reg)		((reg) & 0x000000ffU)
 65#define PCIENREG		0x34
 66 #define PCIU_CONFIG_DONE	0x4U
 67#define PCICLKSELREG		0x38
 68 #define EQUAL_VTCLOCK		0x2U
 69 #define HALF_VTCLOCK		0x0U
 70 #define ONE_THIRD_VTCLOCK	0x3U
 71 #define QUARTER_VTCLOCK	0x1U
 72#define PCITRDYVREG		0x3c
 73 #define TRDYV(val)		((uint32_t)(val) & 0xffU)
 74#define PCICLKRUNREG		0x60
 75
 76#define VENDORIDREG		0x100
 77#define DEVICEIDREG		0x100
 78#define COMMANDREG		0x104
 79#define STATUSREG		0x104
 80#define REVIDREG		0x108
 81#define CLASSREG		0x108
 82#define CACHELSREG		0x10c
 83#define LATTIMEREG		0x10c
 84 #define MLTIM(val)		(((uint32_t)(val) << 7) & 0xff00U)
 85#define MAILBAREG		0x110
 86#define PCIMBA1REG		0x114
 87#define PCIMBA2REG		0x118
 88 #define MBADD(base)		((base) & 0xfffff800U)
 89 #define PMBA(base)		((base) & 0xffe00000U)
 90 #define PREF			0x8U
 91 #define PREF_APPROVAL		0x8U
 92 #define PREF_DISAPPROVAL	0x0U
 93 #define TYPE			0x6U
 94 #define TYPE_32BITSPACE	0x0U
 95 #define MSI			0x1U
 96 #define MSI_MEMORY		0x0U
 97#define INTLINEREG		0x13c
 98#define INTPINREG		0x13c
 99#define RETVALREG		0x140
100#define PCIAPCNTREG		0x140
101 #define TKYGNT			0x04000000U
102 #define TKYGNT_ENABLE		0x04000000U
103 #define TKYGNT_DISABLE		0x00000000U
104 #define PAPC			0x03000000U
105 #define PAPC_ALTERNATE_B	0x02000000U
106 #define PAPC_ALTERNATE_0	0x01000000U
107 #define PAPC_FAIR		0x00000000U
108 #define RTYVAL(val)		(((uint32_t)(val) << 7) & 0xff00U)
109 #define RTYVAL_MASK		0xff00U
110
111#define PCI_CLOCK_MAX		33333333U
112
113/*
114 * Default setup
115 */
116#define PCI_MASTER_MEM1_BUS_BASE_ADDRESS	0x10000000U
117#define PCI_MASTER_MEM1_ADDRESS_MASK		0x7c000000U
118#define PCI_MASTER_MEM1_PCI_BASE_ADDRESS	0x10000000U
119
120#define PCI_TARGET_MEM1_ADDRESS_MASK		0x08000000U
121#define PCI_TARGET_MEM1_BUS_BASE_ADDRESS	0x00000000U
122
123#define PCI_MASTER_IO_BUS_BASE_ADDRESS		0x16000000U
124#define PCI_MASTER_IO_ADDRESS_MASK		0x7e000000U
125#define PCI_MASTER_IO_PCI_BASE_ADDRESS		0x00000000U
126
127#define PCI_MAILBOX_BASE_ADDRESS		0x00000000U
128
129#define PCI_TARGET_WINDOW1_BASE_ADDRESS		0x00000000U
130
131#define IO_PORT_BASE		KSEG1ADDR(PCI_MASTER_IO_BUS_BASE_ADDRESS)
132#define IO_PORT_RESOURCE_START	PCI_MASTER_IO_PCI_BASE_ADDRESS
133#define IO_PORT_RESOURCE_END	(~PCI_MASTER_IO_ADDRESS_MASK & PCI_MASTER_ADDRESS_MASK)
134
135#define PCI_IO_RESOURCE_START	0x01000000UL
136#define PCI_IO_RESOURCE_END	0x01ffffffUL
137
138#define PCI_MEM_RESOURCE_START	0x11000000UL
139#define PCI_MEM_RESOURCE_END	0x13ffffffUL
140
141#endif /* __PCI_VR41XX_H */