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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 */
4
5/**
6 * Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA
7 * and interrupt. PCI interface supports MMIO access method, but does not
8 * seem to support I/O ports.
9 *
10 * Read/write operation in the region 0x80000000-0xBFFFFFFF causes
11 * a memory read/write command on the PCI bus. 30 LSBs of address on
12 * the bus are taken from memory read/write request and 2 MSBs are
13 * determined by PCI unit configuration.
14 *
15 * To work with the configuration space instead of memory is necessary set
16 * the CFG_SEL bit in the PCI_MISC_CONFIG register.
17 *
18 * Devices on the bus can perform DMA requests via chip BAR1. PCI host
19 * controller BARs are programmend as if an external device is programmed.
20 * Which means that during configuration, IDSEL pin of the chip should be
21 * asserted.
22 *
23 * We know (and support) only one board that uses the PCI interface -
24 * Fonera 2.0g (FON2202). It has a USB EHCI controller connected to the
25 * AR2315 PCI bus. IDSEL pin of USB controller is connected to AD[13] line
26 * and IDSEL pin of AR2315 is connected to AD[16] line.
27 */
28
29#include <linux/types.h>
30#include <linux/pci.h>
31#include <linux/platform_device.h>
32#include <linux/kernel.h>
33#include <linux/init.h>
34#include <linux/mm.h>
35#include <linux/delay.h>
36#include <linux/bitops.h>
37#include <linux/irq.h>
38#include <linux/irqdomain.h>
39#include <linux/io.h>
40#include <asm/paccess.h>
41
42/*
43 * PCI Bus Interface Registers
44 */
45#define AR2315_PCI_1MS_REG 0x0008
46
47#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
48
49#define AR2315_PCI_MISC_CONFIG 0x000c
50
51#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
52#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* Mem or Config cycles */
53#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
54#define AR2315_PCIMISC_RST_MODE 0x00000030
55#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
56#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
57#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
58#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
59#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
60#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
61#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
62#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
63 * disable */
64
65#define AR2315_PCI_OUT_TSTAMP 0x0010
66
67#define AR2315_PCI_UNCACHE_CFG 0x0014
68
69#define AR2315_PCI_IN_EN 0x0100
70
71#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
72#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
73#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
74#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
75
76#define AR2315_PCI_IN_DIS 0x0104
77
78#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
79#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
80#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
81#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
82
83#define AR2315_PCI_IN_PTR 0x0200
84
85#define AR2315_PCI_OUT_EN 0x0400
86
87#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
88
89#define AR2315_PCI_OUT_DIS 0x0404
90
91#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
92
93#define AR2315_PCI_OUT_PTR 0x0408
94
95/* PCI interrupt status (write one to clear) */
96#define AR2315_PCI_ISR 0x0500
97
98#define AR2315_PCI_INT_TX 0x00000001 /* Desc In Completed */
99#define AR2315_PCI_INT_TXOK 0x00000002 /* Desc In OK */
100#define AR2315_PCI_INT_TXERR 0x00000004 /* Desc In ERR */
101#define AR2315_PCI_INT_TXEOL 0x00000008 /* Desc In End-of-List */
102#define AR2315_PCI_INT_RX 0x00000010 /* Desc Out Completed */
103#define AR2315_PCI_INT_RXOK 0x00000020 /* Desc Out OK */
104#define AR2315_PCI_INT_RXERR 0x00000040 /* Desc Out ERR */
105#define AR2315_PCI_INT_RXEOL 0x00000080 /* Desc Out EOL */
106#define AR2315_PCI_INT_TXOOD 0x00000200 /* Desc In Out-of-Desc */
107#define AR2315_PCI_INT_DESCMASK 0x0000FFFF /* Desc Mask */
108#define AR2315_PCI_INT_EXT 0x02000000 /* Extern PCI INTA */
109#define AR2315_PCI_INT_ABORT 0x04000000 /* PCI bus abort event */
110
111/* PCI interrupt mask */
112#define AR2315_PCI_IMR 0x0504
113
114/* Global PCI interrupt enable */
115#define AR2315_PCI_IER 0x0508
116
117#define AR2315_PCI_IER_DISABLE 0x00 /* disable pci interrupts */
118#define AR2315_PCI_IER_ENABLE 0x01 /* enable pci interrupts */
119
120#define AR2315_PCI_HOST_IN_EN 0x0800
121#define AR2315_PCI_HOST_IN_DIS 0x0804
122#define AR2315_PCI_HOST_IN_PTR 0x0810
123#define AR2315_PCI_HOST_OUT_EN 0x0900
124#define AR2315_PCI_HOST_OUT_DIS 0x0904
125#define AR2315_PCI_HOST_OUT_PTR 0x0908
126
127/*
128 * PCI interrupts, which share IP5
129 * Keep ordered according to AR2315_PCI_INT_XXX bits
130 */
131#define AR2315_PCI_IRQ_EXT 25
132#define AR2315_PCI_IRQ_ABORT 26
133#define AR2315_PCI_IRQ_COUNT 27
134
135/* Arbitrary size of memory region to access the configuration space */
136#define AR2315_PCI_CFG_SIZE 0x00100000
137
138#define AR2315_PCI_HOST_SLOT 3
139#define AR2315_PCI_HOST_DEVID ((0xff18 << 16) | PCI_VENDOR_ID_ATHEROS)
140
141/*
142 * We need some arbitrary non-zero value to be programmed to the BAR1 register
143 * of PCI host controller to enable DMA. The same value should be used as the
144 * offset to calculate the physical address of DMA buffer for PCI devices.
145 */
146#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
147
148/* ??? access BAR */
149#define AR2315_PCI_HOST_MBAR0 0x10000000
150/* RAM access BAR */
151#define AR2315_PCI_HOST_MBAR1 AR2315_PCI_HOST_SDRAM_BASEADDR
152/* ??? access BAR */
153#define AR2315_PCI_HOST_MBAR2 0x30000000
154
155struct ar2315_pci_ctrl {
156 void __iomem *cfg_mem;
157 void __iomem *mmr_mem;
158 unsigned irq;
159 unsigned irq_ext;
160 struct irq_domain *domain;
161 struct pci_controller pci_ctrl;
162 struct resource mem_res;
163 struct resource io_res;
164};
165
166static inline dma_addr_t ar2315_dev_offset(struct device *dev)
167{
168 if (dev && dev_is_pci(dev))
169 return AR2315_PCI_HOST_SDRAM_BASEADDR;
170 return 0;
171}
172
173dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
174{
175 return paddr + ar2315_dev_offset(dev);
176}
177
178phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dma_addr)
179{
180 return dma_addr - ar2315_dev_offset(dev);
181}
182
183static inline struct ar2315_pci_ctrl *ar2315_pci_bus_to_apc(struct pci_bus *bus)
184{
185 struct pci_controller *hose = bus->sysdata;
186
187 return container_of(hose, struct ar2315_pci_ctrl, pci_ctrl);
188}
189
190static inline u32 ar2315_pci_reg_read(struct ar2315_pci_ctrl *apc, u32 reg)
191{
192 return __raw_readl(apc->mmr_mem + reg);
193}
194
195static inline void ar2315_pci_reg_write(struct ar2315_pci_ctrl *apc, u32 reg,
196 u32 val)
197{
198 __raw_writel(val, apc->mmr_mem + reg);
199}
200
201static inline void ar2315_pci_reg_mask(struct ar2315_pci_ctrl *apc, u32 reg,
202 u32 mask, u32 val)
203{
204 u32 ret = ar2315_pci_reg_read(apc, reg);
205
206 ret &= ~mask;
207 ret |= val;
208 ar2315_pci_reg_write(apc, reg, ret);
209}
210
211static int ar2315_pci_cfg_access(struct ar2315_pci_ctrl *apc, unsigned devfn,
212 int where, int size, u32 *ptr, bool write)
213{
214 int func = PCI_FUNC(devfn);
215 int dev = PCI_SLOT(devfn);
216 u32 addr = (1 << (13 + dev)) | (func << 8) | (where & ~3);
217 u32 mask = 0xffffffff >> 8 * (4 - size);
218 u32 sh = (where & 3) * 8;
219 u32 value, isr;
220
221 /* Prevent access past the remapped area */
222 if (addr >= AR2315_PCI_CFG_SIZE || dev > 18)
223 return PCIBIOS_DEVICE_NOT_FOUND;
224
225 /* Clear pending errors */
226 ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
227 /* Select Configuration access */
228 ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, 0,
229 AR2315_PCIMISC_CFG_SEL);
230
231 mb(); /* PCI must see space change before we begin */
232
233 value = __raw_readl(apc->cfg_mem + addr);
234
235 isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR);
236
237 if (isr & AR2315_PCI_INT_ABORT)
238 goto exit_err;
239
240 if (write) {
241 value = (value & ~(mask << sh)) | *ptr << sh;
242 __raw_writel(value, apc->cfg_mem + addr);
243 isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR);
244 if (isr & AR2315_PCI_INT_ABORT)
245 goto exit_err;
246 } else {
247 *ptr = (value >> sh) & mask;
248 }
249
250 goto exit;
251
252exit_err:
253 ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
254 if (!write)
255 *ptr = 0xffffffff;
256
257exit:
258 /* Select Memory access */
259 ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL,
260 0);
261
262 return isr & AR2315_PCI_INT_ABORT ? PCIBIOS_DEVICE_NOT_FOUND :
263 PCIBIOS_SUCCESSFUL;
264}
265
266static inline int ar2315_pci_local_cfg_rd(struct ar2315_pci_ctrl *apc,
267 unsigned devfn, int where, u32 *val)
268{
269 return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), val,
270 false);
271}
272
273static inline int ar2315_pci_local_cfg_wr(struct ar2315_pci_ctrl *apc,
274 unsigned devfn, int where, u32 val)
275{
276 return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), &val,
277 true);
278}
279
280static int ar2315_pci_cfg_read(struct pci_bus *bus, unsigned devfn, int where,
281 int size, u32 *value)
282{
283 struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
284
285 if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
286 return PCIBIOS_DEVICE_NOT_FOUND;
287
288 return ar2315_pci_cfg_access(apc, devfn, where, size, value, false);
289}
290
291static int ar2315_pci_cfg_write(struct pci_bus *bus, unsigned devfn, int where,
292 int size, u32 value)
293{
294 struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
295
296 if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
297 return PCIBIOS_DEVICE_NOT_FOUND;
298
299 return ar2315_pci_cfg_access(apc, devfn, where, size, &value, true);
300}
301
302static struct pci_ops ar2315_pci_ops = {
303 .read = ar2315_pci_cfg_read,
304 .write = ar2315_pci_cfg_write,
305};
306
307static int ar2315_pci_host_setup(struct ar2315_pci_ctrl *apc)
308{
309 unsigned devfn = PCI_DEVFN(AR2315_PCI_HOST_SLOT, 0);
310 int res;
311 u32 id;
312
313 res = ar2315_pci_local_cfg_rd(apc, devfn, PCI_VENDOR_ID, &id);
314 if (res != PCIBIOS_SUCCESSFUL || id != AR2315_PCI_HOST_DEVID)
315 return -ENODEV;
316
317 /* Program MBARs */
318 ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_0,
319 AR2315_PCI_HOST_MBAR0);
320 ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_1,
321 AR2315_PCI_HOST_MBAR1);
322 ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_2,
323 AR2315_PCI_HOST_MBAR2);
324
325 /* Run */
326 ar2315_pci_local_cfg_wr(apc, devfn, PCI_COMMAND, PCI_COMMAND_MEMORY |
327 PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
328 PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
329 PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
330
331 return 0;
332}
333
334static void ar2315_pci_irq_handler(struct irq_desc *desc)
335{
336 struct ar2315_pci_ctrl *apc = irq_desc_get_handler_data(desc);
337 u32 pending = ar2315_pci_reg_read(apc, AR2315_PCI_ISR) &
338 ar2315_pci_reg_read(apc, AR2315_PCI_IMR);
339 unsigned pci_irq = 0;
340
341 if (pending)
342 pci_irq = irq_find_mapping(apc->domain, __ffs(pending));
343
344 if (pci_irq)
345 generic_handle_irq(pci_irq);
346 else
347 spurious_interrupt();
348}
349
350static void ar2315_pci_irq_mask(struct irq_data *d)
351{
352 struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
353
354 ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, BIT(d->hwirq), 0);
355}
356
357static void ar2315_pci_irq_mask_ack(struct irq_data *d)
358{
359 struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
360 u32 m = BIT(d->hwirq);
361
362 ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, m, 0);
363 ar2315_pci_reg_write(apc, AR2315_PCI_ISR, m);
364}
365
366static void ar2315_pci_irq_unmask(struct irq_data *d)
367{
368 struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
369
370 ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, 0, BIT(d->hwirq));
371}
372
373static struct irq_chip ar2315_pci_irq_chip = {
374 .name = "AR2315-PCI",
375 .irq_mask = ar2315_pci_irq_mask,
376 .irq_mask_ack = ar2315_pci_irq_mask_ack,
377 .irq_unmask = ar2315_pci_irq_unmask,
378};
379
380static int ar2315_pci_irq_map(struct irq_domain *d, unsigned irq,
381 irq_hw_number_t hw)
382{
383 irq_set_chip_and_handler(irq, &ar2315_pci_irq_chip, handle_level_irq);
384 irq_set_chip_data(irq, d->host_data);
385 return 0;
386}
387
388static struct irq_domain_ops ar2315_pci_irq_domain_ops = {
389 .map = ar2315_pci_irq_map,
390};
391
392static void ar2315_pci_irq_init(struct ar2315_pci_ctrl *apc)
393{
394 ar2315_pci_reg_mask(apc, AR2315_PCI_IER, AR2315_PCI_IER_ENABLE, 0);
395 ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, (AR2315_PCI_INT_ABORT |
396 AR2315_PCI_INT_EXT), 0);
397
398 apc->irq_ext = irq_create_mapping(apc->domain, AR2315_PCI_IRQ_EXT);
399
400 irq_set_chained_handler_and_data(apc->irq, ar2315_pci_irq_handler,
401 apc);
402
403 /* Clear any pending Abort or external Interrupts
404 * and enable interrupt processing */
405 ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT |
406 AR2315_PCI_INT_EXT);
407 ar2315_pci_reg_mask(apc, AR2315_PCI_IER, 0, AR2315_PCI_IER_ENABLE);
408}
409
410static int ar2315_pci_probe(struct platform_device *pdev)
411{
412 struct ar2315_pci_ctrl *apc;
413 struct device *dev = &pdev->dev;
414 struct resource *res;
415 int irq, err;
416
417 apc = devm_kzalloc(dev, sizeof(*apc), GFP_KERNEL);
418 if (!apc)
419 return -ENOMEM;
420
421 irq = platform_get_irq(pdev, 0);
422 if (irq < 0)
423 return -EINVAL;
424 apc->irq = irq;
425
426 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
427 "ar2315-pci-ctrl");
428 apc->mmr_mem = devm_ioremap_resource(dev, res);
429 if (IS_ERR(apc->mmr_mem))
430 return PTR_ERR(apc->mmr_mem);
431
432 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
433 "ar2315-pci-ext");
434 if (!res)
435 return -EINVAL;
436
437 apc->mem_res.name = "AR2315 PCI mem space";
438 apc->mem_res.parent = res;
439 apc->mem_res.start = res->start;
440 apc->mem_res.end = res->end;
441 apc->mem_res.flags = IORESOURCE_MEM;
442
443 /* Remap PCI config space */
444 apc->cfg_mem = devm_ioremap_nocache(dev, res->start,
445 AR2315_PCI_CFG_SIZE);
446 if (!apc->cfg_mem) {
447 dev_err(dev, "failed to remap PCI config space\n");
448 return -ENOMEM;
449 }
450
451 /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
452 ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG,
453 AR2315_PCIMISC_RST_MODE,
454 AR2315_PCIRST_LOW);
455 msleep(100);
456
457 /* Bring the PCI out of reset */
458 ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG,
459 AR2315_PCIMISC_RST_MODE,
460 AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
461
462 ar2315_pci_reg_write(apc, AR2315_PCI_UNCACHE_CFG,
463 0x1E | /* 1GB uncached */
464 (1 << 5) | /* Enable uncached */
465 (0x2 << 30) /* Base: 0x80000000 */);
466 ar2315_pci_reg_read(apc, AR2315_PCI_UNCACHE_CFG);
467
468 msleep(500);
469
470 err = ar2315_pci_host_setup(apc);
471 if (err)
472 return err;
473
474 apc->domain = irq_domain_add_linear(NULL, AR2315_PCI_IRQ_COUNT,
475 &ar2315_pci_irq_domain_ops, apc);
476 if (!apc->domain) {
477 dev_err(dev, "failed to add IRQ domain\n");
478 return -ENOMEM;
479 }
480
481 ar2315_pci_irq_init(apc);
482
483 /* PCI controller does not support I/O ports */
484 apc->io_res.name = "AR2315 IO space";
485 apc->io_res.start = 0;
486 apc->io_res.end = 0;
487 apc->io_res.flags = IORESOURCE_IO,
488
489 apc->pci_ctrl.pci_ops = &ar2315_pci_ops;
490 apc->pci_ctrl.mem_resource = &apc->mem_res,
491 apc->pci_ctrl.io_resource = &apc->io_res,
492
493 register_pci_controller(&apc->pci_ctrl);
494
495 dev_info(dev, "register PCI controller\n");
496
497 return 0;
498}
499
500static struct platform_driver ar2315_pci_driver = {
501 .probe = ar2315_pci_probe,
502 .driver = {
503 .name = "ar2315-pci",
504 },
505};
506
507static int __init ar2315_pci_init(void)
508{
509 return platform_driver_register(&ar2315_pci_driver);
510}
511arch_initcall(ar2315_pci_init);
512
513int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
514{
515 struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(dev->bus);
516
517 return slot ? 0 : apc->irq_ext;
518}
519
520int pcibios_plat_dev_init(struct pci_dev *dev)
521{
522 return 0;
523}
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 */
4
5/*
6 * Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA
7 * and interrupt. PCI interface supports MMIO access method, but does not
8 * seem to support I/O ports.
9 *
10 * Read/write operation in the region 0x80000000-0xBFFFFFFF causes
11 * a memory read/write command on the PCI bus. 30 LSBs of address on
12 * the bus are taken from memory read/write request and 2 MSBs are
13 * determined by PCI unit configuration.
14 *
15 * To work with the configuration space instead of memory is necessary set
16 * the CFG_SEL bit in the PCI_MISC_CONFIG register.
17 *
18 * Devices on the bus can perform DMA requests via chip BAR1. PCI host
19 * controller BARs are programmend as if an external device is programmed.
20 * Which means that during configuration, IDSEL pin of the chip should be
21 * asserted.
22 *
23 * We know (and support) only one board that uses the PCI interface -
24 * Fonera 2.0g (FON2202). It has a USB EHCI controller connected to the
25 * AR2315 PCI bus. IDSEL pin of USB controller is connected to AD[13] line
26 * and IDSEL pin of AR2315 is connected to AD[16] line.
27 */
28
29#include <linux/types.h>
30#include <linux/pci.h>
31#include <linux/platform_device.h>
32#include <linux/kernel.h>
33#include <linux/init.h>
34#include <linux/dma-direct.h>
35#include <linux/mm.h>
36#include <linux/delay.h>
37#include <linux/bitops.h>
38#include <linux/irq.h>
39#include <linux/irqdomain.h>
40#include <linux/io.h>
41#include <asm/paccess.h>
42
43/*
44 * PCI Bus Interface Registers
45 */
46#define AR2315_PCI_1MS_REG 0x0008
47
48#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
49
50#define AR2315_PCI_MISC_CONFIG 0x000c
51
52#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
53#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* Mem or Config cycles */
54#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
55#define AR2315_PCIMISC_RST_MODE 0x00000030
56#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
57#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
58#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
59#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
60#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
61#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
62#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
63#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
64 * disable */
65
66#define AR2315_PCI_OUT_TSTAMP 0x0010
67
68#define AR2315_PCI_UNCACHE_CFG 0x0014
69
70#define AR2315_PCI_IN_EN 0x0100
71
72#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
73#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
74#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
75#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
76
77#define AR2315_PCI_IN_DIS 0x0104
78
79#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
80#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
81#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
82#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
83
84#define AR2315_PCI_IN_PTR 0x0200
85
86#define AR2315_PCI_OUT_EN 0x0400
87
88#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
89
90#define AR2315_PCI_OUT_DIS 0x0404
91
92#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
93
94#define AR2315_PCI_OUT_PTR 0x0408
95
96/* PCI interrupt status (write one to clear) */
97#define AR2315_PCI_ISR 0x0500
98
99#define AR2315_PCI_INT_TX 0x00000001 /* Desc In Completed */
100#define AR2315_PCI_INT_TXOK 0x00000002 /* Desc In OK */
101#define AR2315_PCI_INT_TXERR 0x00000004 /* Desc In ERR */
102#define AR2315_PCI_INT_TXEOL 0x00000008 /* Desc In End-of-List */
103#define AR2315_PCI_INT_RX 0x00000010 /* Desc Out Completed */
104#define AR2315_PCI_INT_RXOK 0x00000020 /* Desc Out OK */
105#define AR2315_PCI_INT_RXERR 0x00000040 /* Desc Out ERR */
106#define AR2315_PCI_INT_RXEOL 0x00000080 /* Desc Out EOL */
107#define AR2315_PCI_INT_TXOOD 0x00000200 /* Desc In Out-of-Desc */
108#define AR2315_PCI_INT_DESCMASK 0x0000FFFF /* Desc Mask */
109#define AR2315_PCI_INT_EXT 0x02000000 /* Extern PCI INTA */
110#define AR2315_PCI_INT_ABORT 0x04000000 /* PCI bus abort event */
111
112/* PCI interrupt mask */
113#define AR2315_PCI_IMR 0x0504
114
115/* Global PCI interrupt enable */
116#define AR2315_PCI_IER 0x0508
117
118#define AR2315_PCI_IER_DISABLE 0x00 /* disable pci interrupts */
119#define AR2315_PCI_IER_ENABLE 0x01 /* enable pci interrupts */
120
121#define AR2315_PCI_HOST_IN_EN 0x0800
122#define AR2315_PCI_HOST_IN_DIS 0x0804
123#define AR2315_PCI_HOST_IN_PTR 0x0810
124#define AR2315_PCI_HOST_OUT_EN 0x0900
125#define AR2315_PCI_HOST_OUT_DIS 0x0904
126#define AR2315_PCI_HOST_OUT_PTR 0x0908
127
128/*
129 * PCI interrupts, which share IP5
130 * Keep ordered according to AR2315_PCI_INT_XXX bits
131 */
132#define AR2315_PCI_IRQ_EXT 25
133#define AR2315_PCI_IRQ_ABORT 26
134#define AR2315_PCI_IRQ_COUNT 27
135
136/* Arbitrary size of memory region to access the configuration space */
137#define AR2315_PCI_CFG_SIZE 0x00100000
138
139#define AR2315_PCI_HOST_SLOT 3
140#define AR2315_PCI_HOST_DEVID ((0xff18 << 16) | PCI_VENDOR_ID_ATHEROS)
141
142/*
143 * We need some arbitrary non-zero value to be programmed to the BAR1 register
144 * of PCI host controller to enable DMA. The same value should be used as the
145 * offset to calculate the physical address of DMA buffer for PCI devices.
146 */
147#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
148
149/* ??? access BAR */
150#define AR2315_PCI_HOST_MBAR0 0x10000000
151/* RAM access BAR */
152#define AR2315_PCI_HOST_MBAR1 AR2315_PCI_HOST_SDRAM_BASEADDR
153/* ??? access BAR */
154#define AR2315_PCI_HOST_MBAR2 0x30000000
155
156struct ar2315_pci_ctrl {
157 void __iomem *cfg_mem;
158 void __iomem *mmr_mem;
159 unsigned irq;
160 unsigned irq_ext;
161 struct irq_domain *domain;
162 struct pci_controller pci_ctrl;
163 struct resource mem_res;
164 struct resource io_res;
165};
166
167static inline dma_addr_t ar2315_dev_offset(struct device *dev)
168{
169 if (dev && dev_is_pci(dev))
170 return AR2315_PCI_HOST_SDRAM_BASEADDR;
171 return 0;
172}
173
174dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
175{
176 return paddr + ar2315_dev_offset(dev);
177}
178
179phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dma_addr)
180{
181 return dma_addr - ar2315_dev_offset(dev);
182}
183
184static inline struct ar2315_pci_ctrl *ar2315_pci_bus_to_apc(struct pci_bus *bus)
185{
186 struct pci_controller *hose = bus->sysdata;
187
188 return container_of(hose, struct ar2315_pci_ctrl, pci_ctrl);
189}
190
191static inline u32 ar2315_pci_reg_read(struct ar2315_pci_ctrl *apc, u32 reg)
192{
193 return __raw_readl(apc->mmr_mem + reg);
194}
195
196static inline void ar2315_pci_reg_write(struct ar2315_pci_ctrl *apc, u32 reg,
197 u32 val)
198{
199 __raw_writel(val, apc->mmr_mem + reg);
200}
201
202static inline void ar2315_pci_reg_mask(struct ar2315_pci_ctrl *apc, u32 reg,
203 u32 mask, u32 val)
204{
205 u32 ret = ar2315_pci_reg_read(apc, reg);
206
207 ret &= ~mask;
208 ret |= val;
209 ar2315_pci_reg_write(apc, reg, ret);
210}
211
212static int ar2315_pci_cfg_access(struct ar2315_pci_ctrl *apc, unsigned devfn,
213 int where, int size, u32 *ptr, bool write)
214{
215 int func = PCI_FUNC(devfn);
216 int dev = PCI_SLOT(devfn);
217 u32 addr = (1 << (13 + dev)) | (func << 8) | (where & ~3);
218 u32 mask = 0xffffffff >> 8 * (4 - size);
219 u32 sh = (where & 3) * 8;
220 u32 value, isr;
221
222 /* Prevent access past the remapped area */
223 if (addr >= AR2315_PCI_CFG_SIZE || dev > 18)
224 return PCIBIOS_DEVICE_NOT_FOUND;
225
226 /* Clear pending errors */
227 ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
228 /* Select Configuration access */
229 ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, 0,
230 AR2315_PCIMISC_CFG_SEL);
231
232 mb(); /* PCI must see space change before we begin */
233
234 value = __raw_readl(apc->cfg_mem + addr);
235
236 isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR);
237
238 if (isr & AR2315_PCI_INT_ABORT)
239 goto exit_err;
240
241 if (write) {
242 value = (value & ~(mask << sh)) | *ptr << sh;
243 __raw_writel(value, apc->cfg_mem + addr);
244 isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR);
245 if (isr & AR2315_PCI_INT_ABORT)
246 goto exit_err;
247 } else {
248 *ptr = (value >> sh) & mask;
249 }
250
251 goto exit;
252
253exit_err:
254 ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
255 if (!write)
256 *ptr = 0xffffffff;
257
258exit:
259 /* Select Memory access */
260 ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL,
261 0);
262
263 return isr & AR2315_PCI_INT_ABORT ? PCIBIOS_DEVICE_NOT_FOUND :
264 PCIBIOS_SUCCESSFUL;
265}
266
267static inline int ar2315_pci_local_cfg_rd(struct ar2315_pci_ctrl *apc,
268 unsigned devfn, int where, u32 *val)
269{
270 return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), val,
271 false);
272}
273
274static inline int ar2315_pci_local_cfg_wr(struct ar2315_pci_ctrl *apc,
275 unsigned devfn, int where, u32 val)
276{
277 return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), &val,
278 true);
279}
280
281static int ar2315_pci_cfg_read(struct pci_bus *bus, unsigned devfn, int where,
282 int size, u32 *value)
283{
284 struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
285
286 if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
287 return PCIBIOS_DEVICE_NOT_FOUND;
288
289 return ar2315_pci_cfg_access(apc, devfn, where, size, value, false);
290}
291
292static int ar2315_pci_cfg_write(struct pci_bus *bus, unsigned devfn, int where,
293 int size, u32 value)
294{
295 struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
296
297 if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
298 return PCIBIOS_DEVICE_NOT_FOUND;
299
300 return ar2315_pci_cfg_access(apc, devfn, where, size, &value, true);
301}
302
303static struct pci_ops ar2315_pci_ops = {
304 .read = ar2315_pci_cfg_read,
305 .write = ar2315_pci_cfg_write,
306};
307
308static int ar2315_pci_host_setup(struct ar2315_pci_ctrl *apc)
309{
310 unsigned devfn = PCI_DEVFN(AR2315_PCI_HOST_SLOT, 0);
311 int res;
312 u32 id;
313
314 res = ar2315_pci_local_cfg_rd(apc, devfn, PCI_VENDOR_ID, &id);
315 if (res != PCIBIOS_SUCCESSFUL || id != AR2315_PCI_HOST_DEVID)
316 return -ENODEV;
317
318 /* Program MBARs */
319 ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_0,
320 AR2315_PCI_HOST_MBAR0);
321 ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_1,
322 AR2315_PCI_HOST_MBAR1);
323 ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_2,
324 AR2315_PCI_HOST_MBAR2);
325
326 /* Run */
327 ar2315_pci_local_cfg_wr(apc, devfn, PCI_COMMAND, PCI_COMMAND_MEMORY |
328 PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
329 PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
330 PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
331
332 return 0;
333}
334
335static void ar2315_pci_irq_handler(struct irq_desc *desc)
336{
337 struct ar2315_pci_ctrl *apc = irq_desc_get_handler_data(desc);
338 u32 pending = ar2315_pci_reg_read(apc, AR2315_PCI_ISR) &
339 ar2315_pci_reg_read(apc, AR2315_PCI_IMR);
340 int ret = 0;
341
342 if (pending)
343 ret = generic_handle_domain_irq(apc->domain, __ffs(pending));
344
345 if (!pending || ret)
346 spurious_interrupt();
347}
348
349static void ar2315_pci_irq_mask(struct irq_data *d)
350{
351 struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
352
353 ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, BIT(d->hwirq), 0);
354}
355
356static void ar2315_pci_irq_mask_ack(struct irq_data *d)
357{
358 struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
359 u32 m = BIT(d->hwirq);
360
361 ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, m, 0);
362 ar2315_pci_reg_write(apc, AR2315_PCI_ISR, m);
363}
364
365static void ar2315_pci_irq_unmask(struct irq_data *d)
366{
367 struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
368
369 ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, 0, BIT(d->hwirq));
370}
371
372static struct irq_chip ar2315_pci_irq_chip = {
373 .name = "AR2315-PCI",
374 .irq_mask = ar2315_pci_irq_mask,
375 .irq_mask_ack = ar2315_pci_irq_mask_ack,
376 .irq_unmask = ar2315_pci_irq_unmask,
377};
378
379static int ar2315_pci_irq_map(struct irq_domain *d, unsigned irq,
380 irq_hw_number_t hw)
381{
382 irq_set_chip_and_handler(irq, &ar2315_pci_irq_chip, handle_level_irq);
383 irq_set_chip_data(irq, d->host_data);
384 return 0;
385}
386
387static const struct irq_domain_ops ar2315_pci_irq_domain_ops = {
388 .map = ar2315_pci_irq_map,
389};
390
391static void ar2315_pci_irq_init(struct ar2315_pci_ctrl *apc)
392{
393 ar2315_pci_reg_mask(apc, AR2315_PCI_IER, AR2315_PCI_IER_ENABLE, 0);
394 ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, (AR2315_PCI_INT_ABORT |
395 AR2315_PCI_INT_EXT), 0);
396
397 apc->irq_ext = irq_create_mapping(apc->domain, AR2315_PCI_IRQ_EXT);
398
399 irq_set_chained_handler_and_data(apc->irq, ar2315_pci_irq_handler,
400 apc);
401
402 /* Clear any pending Abort or external Interrupts
403 * and enable interrupt processing */
404 ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT |
405 AR2315_PCI_INT_EXT);
406 ar2315_pci_reg_mask(apc, AR2315_PCI_IER, 0, AR2315_PCI_IER_ENABLE);
407}
408
409static int ar2315_pci_probe(struct platform_device *pdev)
410{
411 struct ar2315_pci_ctrl *apc;
412 struct device *dev = &pdev->dev;
413 struct resource *res;
414 int irq, err;
415
416 apc = devm_kzalloc(dev, sizeof(*apc), GFP_KERNEL);
417 if (!apc)
418 return -ENOMEM;
419
420 irq = platform_get_irq(pdev, 0);
421 if (irq < 0)
422 return -EINVAL;
423 apc->irq = irq;
424
425 apc->mmr_mem = devm_platform_ioremap_resource_byname(pdev,
426 "ar2315-pci-ctrl");
427 if (IS_ERR(apc->mmr_mem))
428 return PTR_ERR(apc->mmr_mem);
429
430 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
431 "ar2315-pci-ext");
432 if (!res)
433 return -EINVAL;
434
435 apc->mem_res.name = "AR2315 PCI mem space";
436 apc->mem_res.parent = res;
437 apc->mem_res.start = res->start;
438 apc->mem_res.end = res->end;
439 apc->mem_res.flags = IORESOURCE_MEM;
440
441 /* Remap PCI config space */
442 apc->cfg_mem = devm_ioremap(dev, res->start,
443 AR2315_PCI_CFG_SIZE);
444 if (!apc->cfg_mem) {
445 dev_err(dev, "failed to remap PCI config space\n");
446 return -ENOMEM;
447 }
448
449 /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
450 ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG,
451 AR2315_PCIMISC_RST_MODE,
452 AR2315_PCIRST_LOW);
453 msleep(100);
454
455 /* Bring the PCI out of reset */
456 ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG,
457 AR2315_PCIMISC_RST_MODE,
458 AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
459
460 ar2315_pci_reg_write(apc, AR2315_PCI_UNCACHE_CFG,
461 0x1E | /* 1GB uncached */
462 (1 << 5) | /* Enable uncached */
463 (0x2 << 30) /* Base: 0x80000000 */);
464 ar2315_pci_reg_read(apc, AR2315_PCI_UNCACHE_CFG);
465
466 msleep(500);
467
468 err = ar2315_pci_host_setup(apc);
469 if (err)
470 return err;
471
472 apc->domain = irq_domain_add_linear(NULL, AR2315_PCI_IRQ_COUNT,
473 &ar2315_pci_irq_domain_ops, apc);
474 if (!apc->domain) {
475 dev_err(dev, "failed to add IRQ domain\n");
476 return -ENOMEM;
477 }
478
479 ar2315_pci_irq_init(apc);
480
481 /* PCI controller does not support I/O ports */
482 apc->io_res.name = "AR2315 IO space";
483 apc->io_res.start = 0;
484 apc->io_res.end = 0;
485 apc->io_res.flags = IORESOURCE_IO;
486
487 apc->pci_ctrl.pci_ops = &ar2315_pci_ops;
488 apc->pci_ctrl.mem_resource = &apc->mem_res;
489 apc->pci_ctrl.io_resource = &apc->io_res;
490
491 register_pci_controller(&apc->pci_ctrl);
492
493 dev_info(dev, "register PCI controller\n");
494
495 return 0;
496}
497
498static struct platform_driver ar2315_pci_driver = {
499 .probe = ar2315_pci_probe,
500 .driver = {
501 .name = "ar2315-pci",
502 },
503};
504
505static int __init ar2315_pci_init(void)
506{
507 return platform_driver_register(&ar2315_pci_driver);
508}
509arch_initcall(ar2315_pci_init);
510
511int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
512{
513 struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(dev->bus);
514
515 return slot ? 0 : apc->irq_ext;
516}
517
518int pcibios_plat_dev_init(struct pci_dev *dev)
519{
520 return 0;
521}