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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * PMC-Sierra MSP board specific pci_ops
4 *
5 * Copyright 2001 MontaVista Software Inc.
6 * Copyright 2005-2007 PMC-Sierra, Inc
7 *
8 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
9 *
10 * Much of the code is derived from the original DDB5074 port by
11 * Geert Uytterhoeven <geert@linux-m68k.org>
12 */
13
14#define PCI_COUNTERS 1
15
16#include <linux/types.h>
17#include <linux/pci.h>
18#include <linux/interrupt.h>
19
20#if defined(CONFIG_PROC_FS) && defined(PCI_COUNTERS)
21#include <linux/proc_fs.h>
22#include <linux/seq_file.h>
23#endif /* CONFIG_PROC_FS && PCI_COUNTERS */
24
25#include <linux/kernel.h>
26#include <linux/init.h>
27
28#include <asm/byteorder.h>
29#if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL)
30#include <asm/mipsmtregs.h>
31#endif
32
33#include <msp_prom.h>
34#include <msp_cic_int.h>
35#include <msp_pci.h>
36#include <msp_regs.h>
37#include <msp_regops.h>
38
39#define PCI_ACCESS_READ 0
40#define PCI_ACCESS_WRITE 1
41
42#if defined(CONFIG_PROC_FS) && defined(PCI_COUNTERS)
43static char proc_init;
44extern struct proc_dir_entry *proc_bus_pci_dir;
45unsigned int pci_int_count[32];
46
47static void pci_proc_init(void);
48
49/*****************************************************************************
50 *
51 * FUNCTION: show_msp_pci_counts
52 * _________________________________________________________________________
53 *
54 * DESCRIPTION: Prints the count of how many times each PCI
55 * interrupt has asserted. Can be invoked by the
56 * /proc filesystem.
57 *
58 * INPUTS: m - synthetic file construction data
59 * v - iterator
60 *
61 * RETURNS: 0 or error
62 *
63 ****************************************************************************/
64static int show_msp_pci_counts(struct seq_file *m, void *v)
65{
66 int i;
67 unsigned int intcount, total = 0;
68
69 for (i = 0; i < 32; ++i) {
70 intcount = pci_int_count[i];
71 if (intcount != 0) {
72 seq_printf(m, "[%d] = %u\n", i, intcount);
73 total += intcount;
74 }
75 }
76
77 seq_printf(m, "total = %u\n", total);
78 return 0;
79}
80
81/*****************************************************************************
82 *
83 * FUNCTION: gen_pci_cfg_wr_show
84 * _________________________________________________________________________
85 *
86 * DESCRIPTION: Generates a configuration write cycle for debug purposes.
87 * The IDSEL line asserted and location and data written are
88 * immaterial. Just want to be able to prove that a
89 * configuration write can be correctly generated on the
90 * PCI bus. Intent is that this function by invocable from
91 * the /proc filesystem.
92 *
93 * INPUTS: m - synthetic file construction data
94 * v - iterator
95 *
96 * RETURNS: 0 or error
97 *
98 ****************************************************************************/
99static int gen_pci_cfg_wr_show(struct seq_file *m, void *v)
100{
101 unsigned char where = 0; /* Write to static Device/Vendor ID */
102 unsigned char bus_num = 0; /* Bus 0 */
103 unsigned char dev_fn = 0xF; /* Arbitrary device number */
104 u32 wr_data = 0xFF00AA00; /* Arbitrary data */
105 struct msp_pci_regs *preg = (void *)PCI_BASE_REG;
106 unsigned long value;
107 int intr;
108
109 seq_puts(m, "PMC MSP PCI: Beginning\n");
110
111 if (proc_init == 0) {
112 pci_proc_init();
113 proc_init = ~0;
114 }
115
116 seq_puts(m, "PMC MSP PCI: Before Cfg Wr\n");
117
118 /*
119 * Generate PCI Configuration Write Cycle
120 */
121
122 /* Clear cause register bits */
123 preg->if_status = ~(BPCI_IFSTATUS_BC0F | BPCI_IFSTATUS_BC1F);
124
125 /* Setup address that is to appear on PCI bus */
126 preg->config_addr = BPCI_CFGADDR_ENABLE |
127 (bus_num << BPCI_CFGADDR_BUSNUM_SHF) |
128 (dev_fn << BPCI_CFGADDR_FUNCTNUM_SHF) |
129 (where & 0xFC);
130
131 value = cpu_to_le32(wr_data);
132
133 /* Launch the PCI configuration write cycle */
134 *PCI_CONFIG_SPACE_REG = value;
135
136 /*
137 * Check if the PCI configuration cycle (rd or wr) succeeded, by
138 * checking the status bits for errors like master or target abort.
139 */
140 intr = preg->if_status;
141
142 seq_puts(m, "PMC MSP PCI: After Cfg Wr\n");
143 return 0;
144}
145
146/*****************************************************************************
147 *
148 * FUNCTION: pci_proc_init
149 * _________________________________________________________________________
150 *
151 * DESCRIPTION: Create entries in the /proc filesystem for debug access.
152 *
153 * INPUTS: none
154 *
155 * OUTPUTS: none
156 *
157 * RETURNS: none
158 *
159 ****************************************************************************/
160static void pci_proc_init(void)
161{
162 proc_create_single("pmc_msp_pci_rd_cnt", 0, NULL, show_msp_pci_counts);
163 proc_create_single("pmc_msp_pci_cfg_wr", 0, NULL, gen_pci_cfg_wr_show);
164}
165#endif /* CONFIG_PROC_FS && PCI_COUNTERS */
166
167/*****************************************************************************
168 *
169 * STRUCT: pci_io_resource
170 * _________________________________________________________________________
171 *
172 * DESCRIPTION: Defines the address range that pciauto() will use to
173 * assign to the I/O BARs of PCI devices.
174 *
175 * Use the start and end addresses of the MSP7120 PCI Host
176 * Controller I/O space, in the form that they appear on the
177 * PCI bus AFTER MSP7120 has performed address translation.
178 *
179 * For I/O accesses, MSP7120 ignores OATRAN and maps I/O
180 * accesses into the bottom 0xFFF region of address space,
181 * so that is the range to put into the pci_io_resource
182 * struct.
183 *
184 * In MSP4200, the start address was 0x04 instead of the
185 * expected 0x00. Will just assume there was a good reason
186 * for this!
187 *
188 * NOTES: Linux, by default, will assign I/O space to the lowest
189 * region of address space. Since MSP7120 and Linux,
190 * by default, have no offset in between how they map, the
191 * io_offset element of pci_controller struct should be set
192 * to zero.
193 * ELEMENTS:
194 * name - String used for a meaningful name.
195 *
196 * start - Start address of MSP7120's I/O space, as MSP7120 presents
197 * the address on the PCI bus.
198 *
199 * end - End address of MSP7120's I/O space, as MSP7120 presents
200 * the address on the PCI bus.
201 *
202 * flags - Attributes indicating the type of resource. In this case,
203 * indicate I/O space.
204 *
205 ****************************************************************************/
206static struct resource pci_io_resource = {
207 .name = "pci IO space",
208 .start = 0x04,
209 .end = 0x0FFF,
210 .flags = IORESOURCE_IO /* I/O space */
211};
212
213/*****************************************************************************
214 *
215 * STRUCT: pci_mem_resource
216 * _________________________________________________________________________
217 *
218 * DESCRIPTION: Defines the address range that pciauto() will use to
219 * assign to the memory BARs of PCI devices.
220 *
221 * The .start and .end values are dependent upon how address
222 * translation is performed by the OATRAN regiser.
223 *
224 * The values to use for .start and .end are the values
225 * in the form they appear on the PCI bus AFTER MSP7120 has
226 * performed OATRAN address translation.
227 *
228 * ELEMENTS:
229 * name - String used for a meaningful name.
230 *
231 * start - Start address of MSP7120's memory space, as MSP7120 presents
232 * the address on the PCI bus.
233 *
234 * end - End address of MSP7120's memory space, as MSP7120 presents
235 * the address on the PCI bus.
236 *
237 * flags - Attributes indicating the type of resource. In this case,
238 * indicate memory space.
239 *
240 ****************************************************************************/
241static struct resource pci_mem_resource = {
242 .name = "pci memory space",
243 .start = MSP_PCI_SPACE_BASE,
244 .end = MSP_PCI_SPACE_END,
245 .flags = IORESOURCE_MEM /* memory space */
246};
247
248/*****************************************************************************
249 *
250 * FUNCTION: bpci_interrupt
251 * _________________________________________________________________________
252 *
253 * DESCRIPTION: PCI status interrupt handler. Updates the count of how
254 * many times each status bit has been set, then clears
255 * the status bits. If the appropriate macros are defined,
256 * these counts can be viewed via the /proc filesystem.
257 *
258 * INPUTS: irq - unused
259 * dev_id - unused
260 * pt_regs - unused
261 *
262 * OUTPUTS: none
263 *
264 * RETURNS: PCIBIOS_SUCCESSFUL - success
265 *
266 ****************************************************************************/
267static irqreturn_t bpci_interrupt(int irq, void *dev_id)
268{
269 struct msp_pci_regs *preg = (void *)PCI_BASE_REG;
270 unsigned int stat = preg->if_status;
271
272#if defined(CONFIG_PROC_FS) && defined(PCI_COUNTERS)
273 int i;
274 for (i = 0; i < 32; ++i) {
275 if ((1 << i) & stat)
276 ++pci_int_count[i];
277 }
278#endif /* PROC_FS && PCI_COUNTERS */
279
280 /* printk("PCI ISR: Status=%08X\n", stat); */
281
282 /* write to clear all asserted interrupts */
283 preg->if_status = stat;
284
285 return IRQ_HANDLED;
286}
287
288/*****************************************************************************
289 *
290 * FUNCTION: msp_pcibios_config_access
291 * _________________________________________________________________________
292 *
293 * DESCRIPTION: Performs a PCI configuration access (rd or wr), then
294 * checks that the access succeeded by querying MSP7120's
295 * PCI status bits.
296 *
297 * INPUTS:
298 * access_type - kind of PCI configuration cycle to perform
299 * (read or write). Legal values are
300 * PCI_ACCESS_WRITE and PCI_ACCESS_READ.
301 *
302 * bus - pointer to the bus number of the device to
303 * be targeted for the configuration cycle.
304 * The only element of the pci_bus structure
305 * used is bus->number. This argument determines
306 * if the configuration access will be Type 0 or
307 * Type 1. Since MSP7120 assumes itself to be the
308 * PCI Host, any non-zero bus->number generates
309 * a Type 1 access.
310 *
311 * devfn - this is an 8-bit field. The lower three bits
312 * specify the function number of the device to
313 * be targeted for the configuration cycle, with
314 * all three-bit combinations being legal. The
315 * upper five bits specify the device number,
316 * with legal values being 10 to 31.
317 *
318 * where - address within the Configuration Header
319 * space to access.
320 *
321 * data - for write accesses, contains the data to
322 * write.
323 *
324 * OUTPUTS:
325 * data - for read accesses, contains the value read.
326 *
327 * RETURNS: PCIBIOS_SUCCESSFUL - success
328 * -1 - access failure
329 *
330 ****************************************************************************/
331int msp_pcibios_config_access(unsigned char access_type,
332 struct pci_bus *bus,
333 unsigned int devfn,
334 unsigned char where,
335 u32 *data)
336{
337 struct msp_pci_regs *preg = (void *)PCI_BASE_REG;
338 unsigned char bus_num = bus->number;
339 unsigned char dev_fn = (unsigned char)devfn;
340 unsigned long intr;
341 unsigned long value;
342 static char pciirqflag;
343 int ret;
344#if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL)
345 unsigned int vpe_status;
346#endif
347
348#if defined(CONFIG_PROC_FS) && defined(PCI_COUNTERS)
349 if (proc_init == 0) {
350 pci_proc_init();
351 proc_init = ~0;
352 }
353#endif /* CONFIG_PROC_FS && PCI_COUNTERS */
354
355 /*
356 * Just the first time this function invokes, allocate
357 * an interrupt line for PCI host status interrupts. The
358 * allocation assigns an interrupt handler to the interrupt.
359 */
360 if (pciirqflag == 0) {
361 ret = request_irq(MSP_INT_PCI,/* Hardcoded internal MSP7120 wiring */
362 bpci_interrupt,
363 IRQF_SHARED,
364 "PMC MSP PCI Host",
365 preg);
366 if (ret != 0)
367 return ret;
368 pciirqflag = ~0;
369 }
370
371#if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL)
372 vpe_status = dvpe();
373#endif
374
375 /*
376 * Clear PCI cause register bits.
377 *
378 * In Polo, the PCI Host had a dedicated DMA called the
379 * Block Copy (not to be confused with the general purpose Block
380 * Copy Engine block). There appear to have been special interrupts
381 * for this Block Copy, called Block Copy 0 Fault (BC0F) and
382 * Block Copy 1 Fault (BC1F). MSP4200 and MSP7120 don't have this
383 * dedicated Block Copy block, so these two interrupts are now
384 * marked reserved. In case the Block Copy is resurrected in a
385 * future design, maintain the code that treats these two interrupts
386 * specially.
387 *
388 * Write to clear all interrupts in the PCI status register, aside
389 * from BC0F and BC1F.
390 */
391 preg->if_status = ~(BPCI_IFSTATUS_BC0F | BPCI_IFSTATUS_BC1F);
392
393 /* Setup address that is to appear on PCI bus */
394 preg->config_addr = BPCI_CFGADDR_ENABLE |
395 (bus_num << BPCI_CFGADDR_BUSNUM_SHF) |
396 (dev_fn << BPCI_CFGADDR_FUNCTNUM_SHF) |
397 (where & 0xFC);
398
399 /* IF access is a PCI configuration write */
400 if (access_type == PCI_ACCESS_WRITE) {
401 value = cpu_to_le32(*data);
402 *PCI_CONFIG_SPACE_REG = value;
403 } else {
404 /* ELSE access is a PCI configuration read */
405 value = le32_to_cpu(*PCI_CONFIG_SPACE_REG);
406 *data = value;
407 }
408
409 /*
410 * Check if the PCI configuration cycle (rd or wr) succeeded, by
411 * checking the status bits for errors like master or target abort.
412 */
413 intr = preg->if_status;
414
415 /* Clear config access */
416 preg->config_addr = 0;
417
418 /* IF error occurred */
419 if (intr & ~(BPCI_IFSTATUS_BC0F | BPCI_IFSTATUS_BC1F)) {
420 /* Clear status bits */
421 preg->if_status = ~(BPCI_IFSTATUS_BC0F | BPCI_IFSTATUS_BC1F);
422
423#if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL)
424 evpe(vpe_status);
425#endif
426
427 return -1;
428 }
429
430#if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL)
431 evpe(vpe_status);
432#endif
433
434 return PCIBIOS_SUCCESSFUL;
435}
436
437/*****************************************************************************
438 *
439 * FUNCTION: msp_pcibios_read_config_byte
440 * _________________________________________________________________________
441 *
442 * DESCRIPTION: Read a byte from PCI configuration address spac
443 * Since the hardware can't address 8 bit chunks
444 * directly, read a 32-bit chunk, then mask off extraneous
445 * bits.
446 *
447 * INPUTS bus - structure containing attributes for the PCI bus
448 * that the read is destined for.
449 * devfn - device/function combination that the read is
450 * destined for.
451 * where - register within the Configuration Header space
452 * to access.
453 *
454 * OUTPUTS val - read data
455 *
456 * RETURNS: PCIBIOS_SUCCESSFUL - success
457 * -1 - read access failure
458 *
459 ****************************************************************************/
460static int
461msp_pcibios_read_config_byte(struct pci_bus *bus,
462 unsigned int devfn,
463 int where,
464 u32 *val)
465{
466 u32 data = 0;
467
468 /*
469 * If the config access did not complete normally (e.g., underwent
470 * master abort) do the PCI compliant thing, which is to supply an
471 * all ones value.
472 */
473 if (msp_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
474 where, &data)) {
475 *val = 0xFFFFFFFF;
476 return -1;
477 }
478
479 *val = (data >> ((where & 3) << 3)) & 0x0ff;
480
481 return PCIBIOS_SUCCESSFUL;
482}
483
484/*****************************************************************************
485 *
486 * FUNCTION: msp_pcibios_read_config_word
487 * _________________________________________________________________________
488 *
489 * DESCRIPTION: Read a word (16 bits) from PCI configuration address space.
490 * Since the hardware can't address 16 bit chunks
491 * directly, read a 32-bit chunk, then mask off extraneous
492 * bits.
493 *
494 * INPUTS bus - structure containing attributes for the PCI bus
495 * that the read is destined for.
496 * devfn - device/function combination that the read is
497 * destined for.
498 * where - register within the Configuration Header space
499 * to access.
500 *
501 * OUTPUTS val - read data
502 *
503 * RETURNS: PCIBIOS_SUCCESSFUL - success
504 * PCIBIOS_BAD_REGISTER_NUMBER - bad register address
505 * -1 - read access failure
506 *
507 ****************************************************************************/
508static int
509msp_pcibios_read_config_word(struct pci_bus *bus,
510 unsigned int devfn,
511 int where,
512 u32 *val)
513{
514 u32 data = 0;
515
516 /* if (where & 1) */ /* Commented out non-compliant code.
517 * Should allow word access to configuration
518 * registers, with only exception being when
519 * the word access would wrap around into
520 * the next dword.
521 */
522 if ((where & 3) == 3) {
523 *val = 0xFFFFFFFF;
524 return PCIBIOS_BAD_REGISTER_NUMBER;
525 }
526
527 /*
528 * If the config access did not complete normally (e.g., underwent
529 * master abort) do the PCI compliant thing, which is to supply an
530 * all ones value.
531 */
532 if (msp_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
533 where, &data)) {
534 *val = 0xFFFFFFFF;
535 return -1;
536 }
537
538 *val = (data >> ((where & 3) << 3)) & 0x0ffff;
539
540 return PCIBIOS_SUCCESSFUL;
541}
542
543/*****************************************************************************
544 *
545 * FUNCTION: msp_pcibios_read_config_dword
546 * _________________________________________________________________________
547 *
548 * DESCRIPTION: Read a double word (32 bits) from PCI configuration
549 * address space.
550 *
551 * INPUTS bus - structure containing attributes for the PCI bus
552 * that the read is destined for.
553 * devfn - device/function combination that the read is
554 * destined for.
555 * where - register within the Configuration Header space
556 * to access.
557 *
558 * OUTPUTS val - read data
559 *
560 * RETURNS: PCIBIOS_SUCCESSFUL - success
561 * PCIBIOS_BAD_REGISTER_NUMBER - bad register address
562 * -1 - read access failure
563 *
564 ****************************************************************************/
565static int
566msp_pcibios_read_config_dword(struct pci_bus *bus,
567 unsigned int devfn,
568 int where,
569 u32 *val)
570{
571 u32 data = 0;
572
573 /* Address must be dword aligned. */
574 if (where & 3) {
575 *val = 0xFFFFFFFF;
576 return PCIBIOS_BAD_REGISTER_NUMBER;
577 }
578
579 /*
580 * If the config access did not complete normally (e.g., underwent
581 * master abort) do the PCI compliant thing, which is to supply an
582 * all ones value.
583 */
584 if (msp_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
585 where, &data)) {
586 *val = 0xFFFFFFFF;
587 return -1;
588 }
589
590 *val = data;
591
592 return PCIBIOS_SUCCESSFUL;
593}
594
595/*****************************************************************************
596 *
597 * FUNCTION: msp_pcibios_write_config_byte
598 * _________________________________________________________________________
599 *
600 * DESCRIPTION: Write a byte to PCI configuration address space.
601 * Since the hardware can't address 8 bit chunks
602 * directly, a read-modify-write is performed.
603 *
604 * INPUTS bus - structure containing attributes for the PCI bus
605 * that the write is destined for.
606 * devfn - device/function combination that the write is
607 * destined for.
608 * where - register within the Configuration Header space
609 * to access.
610 * val - value to write
611 *
612 * OUTPUTS none
613 *
614 * RETURNS: PCIBIOS_SUCCESSFUL - success
615 * -1 - write access failure
616 *
617 ****************************************************************************/
618static int
619msp_pcibios_write_config_byte(struct pci_bus *bus,
620 unsigned int devfn,
621 int where,
622 u8 val)
623{
624 u32 data = 0;
625
626 /* read config space */
627 if (msp_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
628 where, &data))
629 return -1;
630
631 /* modify the byte within the dword */
632 data = (data & ~(0xff << ((where & 3) << 3))) |
633 (val << ((where & 3) << 3));
634
635 /* write back the full dword */
636 if (msp_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn,
637 where, &data))
638 return -1;
639
640 return PCIBIOS_SUCCESSFUL;
641}
642
643/*****************************************************************************
644 *
645 * FUNCTION: msp_pcibios_write_config_word
646 * _________________________________________________________________________
647 *
648 * DESCRIPTION: Write a word (16-bits) to PCI configuration address space.
649 * Since the hardware can't address 16 bit chunks
650 * directly, a read-modify-write is performed.
651 *
652 * INPUTS bus - structure containing attributes for the PCI bus
653 * that the write is destined for.
654 * devfn - device/function combination that the write is
655 * destined for.
656 * where - register within the Configuration Header space
657 * to access.
658 * val - value to write
659 *
660 * OUTPUTS none
661 *
662 * RETURNS: PCIBIOS_SUCCESSFUL - success
663 * PCIBIOS_BAD_REGISTER_NUMBER - bad register address
664 * -1 - write access failure
665 *
666 ****************************************************************************/
667static int
668msp_pcibios_write_config_word(struct pci_bus *bus,
669 unsigned int devfn,
670 int where,
671 u16 val)
672{
673 u32 data = 0;
674
675 /* Fixed non-compliance: if (where & 1) */
676 if ((where & 3) == 3)
677 return PCIBIOS_BAD_REGISTER_NUMBER;
678
679 /* read config space */
680 if (msp_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
681 where, &data))
682 return -1;
683
684 /* modify the word within the dword */
685 data = (data & ~(0xffff << ((where & 3) << 3))) |
686 (val << ((where & 3) << 3));
687
688 /* write back the full dword */
689 if (msp_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn,
690 where, &data))
691 return -1;
692
693 return PCIBIOS_SUCCESSFUL;
694}
695
696/*****************************************************************************
697 *
698 * FUNCTION: msp_pcibios_write_config_dword
699 * _________________________________________________________________________
700 *
701 * DESCRIPTION: Write a double word (32-bits) to PCI configuration address
702 * space.
703 *
704 * INPUTS bus - structure containing attributes for the PCI bus
705 * that the write is destined for.
706 * devfn - device/function combination that the write is
707 * destined for.
708 * where - register within the Configuration Header space
709 * to access.
710 * val - value to write
711 *
712 * OUTPUTS none
713 *
714 * RETURNS: PCIBIOS_SUCCESSFUL - success
715 * PCIBIOS_BAD_REGISTER_NUMBER - bad register address
716 * -1 - write access failure
717 *
718 ****************************************************************************/
719static int
720msp_pcibios_write_config_dword(struct pci_bus *bus,
721 unsigned int devfn,
722 int where,
723 u32 val)
724{
725 /* check that address is dword aligned */
726 if (where & 3)
727 return PCIBIOS_BAD_REGISTER_NUMBER;
728
729 /* perform write */
730 if (msp_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn,
731 where, &val))
732 return -1;
733
734 return PCIBIOS_SUCCESSFUL;
735}
736
737/*****************************************************************************
738 *
739 * FUNCTION: msp_pcibios_read_config
740 * _________________________________________________________________________
741 *
742 * DESCRIPTION: Interface the PCI configuration read request with
743 * the appropriate function, based on how many bytes
744 * the read request is.
745 *
746 * INPUTS bus - structure containing attributes for the PCI bus
747 * that the write is destined for.
748 * devfn - device/function combination that the write is
749 * destined for.
750 * where - register within the Configuration Header space
751 * to access.
752 * size - in units of bytes, should be 1, 2, or 4.
753 *
754 * OUTPUTS val - value read, with any extraneous bytes masked
755 * to zero.
756 *
757 * RETURNS: PCIBIOS_SUCCESSFUL - success
758 * -1 - failure
759 *
760 ****************************************************************************/
761int
762msp_pcibios_read_config(struct pci_bus *bus,
763 unsigned int devfn,
764 int where,
765 int size,
766 u32 *val)
767{
768 if (size == 1) {
769 if (msp_pcibios_read_config_byte(bus, devfn, where, val)) {
770 return -1;
771 }
772 } else if (size == 2) {
773 if (msp_pcibios_read_config_word(bus, devfn, where, val)) {
774 return -1;
775 }
776 } else if (size == 4) {
777 if (msp_pcibios_read_config_dword(bus, devfn, where, val)) {
778 return -1;
779 }
780 } else {
781 *val = 0xFFFFFFFF;
782 return -1;
783 }
784
785 return PCIBIOS_SUCCESSFUL;
786}
787
788/*****************************************************************************
789 *
790 * FUNCTION: msp_pcibios_write_config
791 * _________________________________________________________________________
792 *
793 * DESCRIPTION: Interface the PCI configuration write request with
794 * the appropriate function, based on how many bytes
795 * the read request is.
796 *
797 * INPUTS bus - structure containing attributes for the PCI bus
798 * that the write is destined for.
799 * devfn - device/function combination that the write is
800 * destined for.
801 * where - register within the Configuration Header space
802 * to access.
803 * size - in units of bytes, should be 1, 2, or 4.
804 * val - value to write
805 *
806 * OUTPUTS: none
807 *
808 * RETURNS: PCIBIOS_SUCCESSFUL - success
809 * -1 - failure
810 *
811 ****************************************************************************/
812int
813msp_pcibios_write_config(struct pci_bus *bus,
814 unsigned int devfn,
815 int where,
816 int size,
817 u32 val)
818{
819 if (size == 1) {
820 if (msp_pcibios_write_config_byte(bus, devfn,
821 where, (u8)(0xFF & val))) {
822 return -1;
823 }
824 } else if (size == 2) {
825 if (msp_pcibios_write_config_word(bus, devfn,
826 where, (u16)(0xFFFF & val))) {
827 return -1;
828 }
829 } else if (size == 4) {
830 if (msp_pcibios_write_config_dword(bus, devfn, where, val)) {
831 return -1;
832 }
833 } else {
834 return -1;
835 }
836
837 return PCIBIOS_SUCCESSFUL;
838}
839
840/*****************************************************************************
841 *
842 * STRUCTURE: msp_pci_ops
843 * _________________________________________________________________________
844 *
845 * DESCRIPTION: structure to abstract the hardware specific PCI
846 * configuration accesses.
847 *
848 * ELEMENTS:
849 * read - function for Linux to generate PCI Configuration reads.
850 * write - function for Linux to generate PCI Configuration writes.
851 *
852 ****************************************************************************/
853struct pci_ops msp_pci_ops = {
854 .read = msp_pcibios_read_config,
855 .write = msp_pcibios_write_config
856};
857
858/*****************************************************************************
859 *
860 * STRUCTURE: msp_pci_controller
861 * _________________________________________________________________________
862 *
863 * Describes the attributes of the MSP7120 PCI Host Controller
864 *
865 * ELEMENTS:
866 * pci_ops - abstracts the hardware specific PCI configuration
867 * accesses.
868 *
869 * mem_resource - address range pciauto() uses to assign to PCI device
870 * memory BARs.
871 *
872 * mem_offset - offset between how MSP7120 outbound PCI memory
873 * transaction addresses appear on the PCI bus and how Linux
874 * wants to configure memory BARs of the PCI devices.
875 * MSP7120 does nothing funky, so just set to zero.
876 *
877 * io_resource - address range pciauto() uses to assign to PCI device
878 * I/O BARs.
879 *
880 * io_offset - offset between how MSP7120 outbound PCI I/O
881 * transaction addresses appear on the PCI bus and how
882 * Linux defaults to configure I/O BARs of the PCI devices.
883 * MSP7120 maps outbound I/O accesses into the bottom
884 * bottom 4K of PCI address space (and ignores OATRAN).
885 * Since the Linux default is to configure I/O BARs to the
886 * bottom 4K, no special offset is needed. Just set to zero.
887 *
888 ****************************************************************************/
889static struct pci_controller msp_pci_controller = {
890 .pci_ops = &msp_pci_ops,
891 .mem_resource = &pci_mem_resource,
892 .mem_offset = 0,
893 .io_map_base = MSP_PCI_IOSPACE_BASE,
894 .io_resource = &pci_io_resource,
895 .io_offset = 0
896};
897
898/*****************************************************************************
899 *
900 * FUNCTION: msp_pci_init
901 * _________________________________________________________________________
902 *
903 * DESCRIPTION: Initialize the PCI Host Controller and register it with
904 * Linux so Linux can seize control of the PCI bus.
905 *
906 ****************************************************************************/
907void __init msp_pci_init(void)
908{
909 struct msp_pci_regs *preg = (void *)PCI_BASE_REG;
910 u32 id;
911
912 /* Extract Device ID */
913 id = read_reg32(PCI_JTAG_DEVID_REG, 0xFFFF) >> 12;
914
915 /* Check if JTAG ID identifies MSP7120 */
916 if (!MSP_HAS_PCI(id)) {
917 printk(KERN_WARNING "PCI: No PCI; id reads as %x\n", id);
918 goto no_pci;
919 }
920
921 /*
922 * Enable flushing of the PCI-SDRAM queue upon a read
923 * of the SDRAM's Memory Configuration Register.
924 */
925 *(unsigned long *)QFLUSH_REG_1 = 3;
926
927 /* Configure PCI Host Controller. */
928 preg->if_status = ~0; /* Clear cause register bits */
929 preg->config_addr = 0; /* Clear config access */
930 preg->oatran = MSP_PCI_OATRAN; /* PCI outbound addr translation */
931 preg->if_mask = 0xF8BF87C0; /* Enable all PCI status interrupts */
932
933 /* configure so inb(), outb(), and family are functional */
934 set_io_port_base(MSP_PCI_IOSPACE_BASE);
935
936 /* Tell Linux the details of the MSP7120 PCI Host Controller */
937 register_pci_controller(&msp_pci_controller);
938
939 return;
940
941no_pci:
942 /* Disable PCI channel */
943 printk(KERN_WARNING "PCI: no host PCI bus detected\n");
944}